doc: add backend design report with screenshots

At 100 MHz the worst path (WNS -1.58 ns) was CBD sample: squeeze_buf[buf_ptr]
extraction -> CBD add/sub -> mod-Q -> bank_t/bank_se write, all combinational
in one cycle and routing-dominated (squeeze_buf and the banks place far apart).
Register the CBD write (data/addr/enable) so the bank write commits one cycle
later; the registered write takes priority in the bank_se/bank_t mux so the
1-cycle spillover into the next state uses the correct addr/data. No consumer
reads these coeffs until the following stage (>1 cycle later), so no RAW hazard.

Verified byte-exact vs NIST KAT: Encaps 9/9, Decaps 9/9, KeyGen 11/11,
hello_world e2e -- all PASS.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

.gitattributes

@@ -1,24 +0,0 @@
-* text=auto eol=lf
-
-# Binary artifacts
-*.bin -text
-*.elf -text
-*.o -text
-*.a -text
-*.so -text
-*.dll -text
-*.exe -text
-
-# Documents and images
-*.pdf -text
-*.png -text
-*.jpg -text
-*.jpeg -text
-*.gif -text
-*.bmp -text
-*.ico -text
-
-# FPGA packaged IP/checkpoints can be binary archives.
-*.xcix -text
-*.dcp -text
-*.bit -text

.gitignore

@@ -18,6 +18,12 @@ webtalk*.jou
 vivado_pid*.txt
 *.bit
 
+# ========================================
+# Generated binary / AXI images
+# ========================================
+*.bin
+*.mif
+
 # ========================================
 # OS generated files
 # ========================================
@@ -37,6 +43,7 @@ desktop.ini
 .codex/
 .opencode/
 .agents/
+.omo/
 
 # ========================================
 # Editor / IDE

doc/axi_bus_modules.md

@@ -0,0 +1,570 @@
+# AXI 总线模块说明
+
+本文档基于 `full` 分支的 `rtl/soc_top.v`、各 AXI 外设源码和软件头文件整理，用于说明当前 SoC 中 AXI 总线上的模块作用、端口含义和寄存器地址。
+
+## 1. 总体连接关系
+
+顶层 AXI 互连为 `AxiCrossbar_2x8`。它有 2 个 AXI master 输入和 8 个 AXI slave 输出。
+
+### 1.1 AXI master 输入
+
+| Crossbar 端口 | 顶层连接 | 作用 |
+| --- | --- | --- |
+| `axiIn_0_*` | `core_top` 经 `Axi_CDC` 后的 `cpu_sync_*` | CPU 访问内存、外设和加速器 |
+| `axiIn_1_*` | `snix_axil_cdma_mux` 的 `dma_m_*` / `mm2mm_*` | DMA/CDMA 作为 AXI master 发起内存和外设数据搬运 |
+
+### 1.2 AXI slave 输出和地址窗口
+
+| Crossbar 端口 | 物理地址窗口 | 常用非缓存虚拟地址窗口 | 顶层连接 | 作用 |
+| --- | --- | --- | --- | --- |
+| `axiOut_0_*` | `0x1c000000` - `0x1c7fffff` | 软件通常直接使用物理地址 | `axi_wrap_ram_sp_external` | BaseRAM/ExtRAM 存储子系统 |
+| `axiOut_1_*` | `0x00000000` - `0x007fffff` | 无 | reserved tie-off | 保留窗口，当前返回空响应 |
+| `axiOut_2_*` | `0x1f000000` - `0x1f0fffff` | `0xbf000000` - `0xbf0fffff` | `axi_uart_controller` | UART0 |
+| `axiOut_3_*` | `0x1f100000` - `0x1f1fffff` | `0xbf100000` - `0xbf1fffff` | `axi_dvi` | 视频输出 |
+| `axiOut_4_*` | `0x1f200000` - `0x1f2fffff` | `0xbf200000` - `0xbf2fffff` | `confreg` | LED、数码管、按键、开关、定时器、中断 |
+| `axiOut_5_*` | `0x1f300000` - `0x1f3fffff` | `0xbf300000` - `0xbf3fffff` | `axi_axil_adapter` -> DMA/CDMA | DMA 配置窗口 |
+| `axiOut_6_*` | `0x1f400000` - `0x1f4fffff` | `0xbf400000` - `0xbf4fffff` | `fft_mlkem_axi_slave` | FFT、ML-KEM 共享窗口 |
+| `axiOut_7_*` | `0x1f500000` - `0x1f5fffff` | `0xbf500000` - `0xbf5fffff` | `matmul_axi_slave` | 矩阵乘法加速器 |
+
+说明：软件中的 `0xbfxxxxxx` 地址是 Loongson/LoongArch 非缓存映射地址；硬件 crossbar 实际译码使用 `0x1fxxxxxx` 等物理地址。
+
+## 2. AXI 信号字典
+
+多个模块使用完全相同的 AXI4 或 AXI-Lite 端口。后续各模块只列出端口前缀，例如 `ram_*`、`uart_*`、`s_axi_*`、`dma_m_*`。这些前缀下的每个信号含义按本节解释。
+
+### 2.1 AXI4 slave 接口信号
+
+适用于 `axi_wrap_ram_sp_external`、`axi_uart_controller`、`axi_dvi`、`confreg`、`fft_mlkem_axi_slave`、`mlkem_axi_slave`、`matmul_axi_slave` 等模块。
+
+| 信号 | 方向，以 slave 模块为准 | 含义 |
+| --- | --- | --- |
+| `clk` / `aclk` | input | AXI 总线时钟。当前大多数 slave 使用 `sys_clk`。 |
+| `resetn` / `aresetn` / `rst_n` | input | 低有效复位，已在顶层同步。 |
+| `s_axi_awid` / `axi_awid` | input | 写地址事务 ID，用于响应通道返回对应 ID。 |
+| `s_axi_awaddr` / `axi_awaddr` | input | 写地址。模块通常使用低位做内部寄存器偏移。 |
+| `s_axi_awlen` / `axi_awlen` | input | 突发长度，表示 beats-1。 |
+| `s_axi_awsize` / `axi_awsize` | input | 每个 beat 的字节数编码，`2` 表示 4 字节。 |
+| `s_axi_awburst` / `axi_awburst` | input | 突发类型，常用 `INCR`。 |
+| `s_axi_awlock` / `axi_awlock` | input | AXI lock 属性，本设计基本不使用。 |
+| `s_axi_awcache` / `axi_awcache` | input | cache 属性，本设计通常透传或忽略。 |
+| `s_axi_awprot` / `axi_awprot` | input | protection 属性，本设计通常透传或忽略。 |
+| `s_axi_awvalid` / `axi_awvalid` | input | 写地址有效。 |
+| `s_axi_awready` / `axi_awready` | output | slave 可接收写地址。 |
+| `s_axi_wid` | input | 写数据 ID。部分 AXI4 实现保留，很多模块不使用。 |
+| `s_axi_wdata` / `axi_wdata` | input | 写数据。 |
+| `s_axi_wstrb` / `axi_wstrb` | input | 写字节使能，bit0 对应低 8 位。 |
+| `s_axi_wlast` / `axi_wlast` | input | 写突发最后一拍。 |
+| `s_axi_wvalid` / `axi_wvalid` | input | 写数据有效。 |
+| `s_axi_wready` / `axi_wready` | output | slave 可接收写数据。 |
+| `s_axi_bid` / `axi_bid` | output | 写响应 ID。 |
+| `s_axi_bresp` / `axi_bresp` | output | 写响应状态，当前外设一般返回 `OKAY=2'b00`。 |
+| `s_axi_bvalid` / `axi_bvalid` | output | 写响应有效。 |
+| `s_axi_bready` / `axi_bready` | input | master 可接收写响应。 |
+| `s_axi_arid` / `axi_arid` | input | 读地址事务 ID。 |
+| `s_axi_araddr` / `axi_araddr` | input | 读地址。 |
+| `s_axi_arlen` / `axi_arlen` | input | 读突发长度，表示 beats-1。 |
+| `s_axi_arsize` / `axi_arsize` | input | 每个读 beat 的字节数编码。 |
+| `s_axi_arburst` / `axi_arburst` | input | 读突发类型，常用 `INCR`。 |
+| `s_axi_arlock` / `axi_arlock` | input | AXI lock 属性，本设计基本不使用。 |
+| `s_axi_arcache` / `axi_arcache` | input | cache 属性，本设计通常透传或忽略。 |
+| `s_axi_arprot` / `axi_arprot` | input | protection 属性，本设计通常透传或忽略。 |
+| `s_axi_arvalid` / `axi_arvalid` | input | 读地址有效。 |
+| `s_axi_arready` / `axi_arready` | output | slave 可接收读地址。 |
+| `s_axi_rid` / `axi_rid` | output | 读响应 ID。 |
+| `s_axi_rdata` / `axi_rdata` | output | 读数据。 |
+| `s_axi_rresp` / `axi_rresp` | output | 读响应状态，当前外设一般返回 `OKAY=2'b00`。 |
+| `s_axi_rlast` / `axi_rlast` | output | 读突发最后一拍。 |
+| `s_axi_rvalid` / `axi_rvalid` | output | 读数据有效。 |
+| `s_axi_rready` / `axi_rready` | input | master 可接收读数据。 |
+
+### 2.2 AXI4 master 接口信号
+
+适用于 `snix_axil_cdma_mux` 的 `mm2mm_*` / 顶层 `dma_m_*`。信号名称与 AXI4 slave 一致，但方向相反：`awaddr/araddr/wdata/wstrb/valid/ready` 等由 DMA master 发起，crossbar/slave 返回 ready、response 和 read data。
+
+| 信号组 | 方向，以 DMA 为准 | 含义 |
+| --- | --- | --- |
+| `mm2mm_aw*` | output/input | DMA 写地址通道，用于向目标地址发起写事务。 |
+| `mm2mm_w*` | output/input | DMA 写数据通道。 |
+| `mm2mm_b*` | input/output | DMA 写响应通道。 |
+| `mm2mm_ar*` | output/input | DMA 读地址通道，用于从源地址发起读事务。 |
+| `mm2mm_r*` | input/output | DMA 读数据通道。 |
+| `mm2mm_awqos/arqos` | output | AXI QoS，顶层未使用。 |
+| `mm2mm_awuser/wuser/aruser` | output | AXI user sideband，顶层未使用。 |
+| `mm2mm_buser/ruser` | input | AXI user sideband，顶层绑常量。 |
+
+### 2.3 AXI-Lite slave 接口信号
+
+适用于 `snix_axil_cdma_mux` 和 `cdma_matmul_bridge` 的配置接口。
+
+| 信号 | 方向，以 AXI-Lite slave 为准 | 含义 |
+| --- | --- | --- |
+| `s_axil_awaddr` | input | AXI-Lite 写地址。 |
+| `s_axil_awvalid` | input | 写地址有效。 |
+| `s_axil_awready` | output | slave 可接收写地址。 |
+| `s_axil_wdata` | input | 写数据。 |
+| `s_axil_wstrb` | input | 写字节使能。 |
+| `s_axil_wvalid` | input | 写数据有效。 |
+| `s_axil_wready` | output | slave 可接收写数据。 |
+| `s_axil_bresp` | output | 写响应状态。 |
+| `s_axil_bvalid` | output | 写响应有效。 |
+| `s_axil_bready` | input | master 可接收写响应。 |
+| `s_axil_araddr` | input | AXI-Lite 读地址。 |
+| `s_axil_arvalid` | input | 读地址有效。 |
+| `s_axil_arready` | output | slave 可接收读地址。 |
+| `s_axil_rdata` | output | 读数据。 |
+| `s_axil_rresp` | output | 读响应状态。 |
+| `s_axil_rvalid` | output | 读数据有效。 |
+| `s_axil_rready` | input | master 可接收读数据。 |
+
+## 3. 各 AXI 模块作用与端口
+
+### 3.1 `AxiCrossbar_2x8`
+
+作用：系统 AXI 主互连。它将 CPU 和 DMA 两个 master 的读写请求按地址译码转发到 8 个 slave，并负责读写响应返回。
+
+端口说明：
+
+| 端口 | 方向 | 解释 |
+| --- | --- | --- |
+| `clk` | input | crossbar 工作时钟，顶层连接 `sys_clk`。 |
+| `resetn` | input | 低有效复位，顶层连接 `sys_resetn`。 |
+| `axiIn_0_*` | input/output | CPU 侧 AXI master 接口，信号含义见 AXI4 字典。 |
+| `axiIn_1_*` | input/output | DMA/CDMA 侧 AXI master 接口，信号含义见 AXI4 字典。 |
+| `axiOut_0_*` | output/input | RAM AXI slave 接口。 |
+| `axiOut_1_*` | output/input | 保留 AXI slave 接口，顶层 tie-off。 |
+| `axiOut_2_*` | output/input | UART AXI slave 接口。 |
+| `axiOut_3_*` | output/input | DVI AXI slave 接口。 |
+| `axiOut_4_*` | output/input | confreg AXI slave 接口。 |
+| `axiOut_5_*` | output/input | DMA 配置 AXI slave 接口。 |
+| `axiOut_6_*` | output/input | FFT/ML-KEM AXI slave 接口。 |
+| `axiOut_7_*` | output/input | matmul AXI slave 接口。 |
+
+### 3.2 `core_top` 与 `Axi_CDC`
+
+作用：`core_top` 是 CPU；`Axi_CDC` 将 CPU 时钟域的 AXI 请求同步到 `sys_clk` 域，再送入 crossbar master 0。
+
+端口说明：
+
+| 端口 | 方向 | 解释 |
+| --- | --- | --- |
+| `core_top.aclk` | input | CPU 时钟 `cpu_clk`。 |
+| `core_top.aresetn` | input | CPU 低有效复位 `cpu_resetn`。 |
+| `core_top.intrpt[7:0]` | input | CPU 中断输入。当前 `{4'd0, mlkem_intr, matmul_intr, dma_finish, confreg_int}`。 |
+| `core_top.ar*/r*/aw*/w*/b*` | input/output | CPU AXI master 接口。 |
+| `core_top.debug0_*` | output | CPU 写回级调试信号。 |
+| `Axi_CDC.axiInClk/axiInRstn` | input | CPU 侧时钟/复位。 |
+| `Axi_CDC.axiOutClk/axiOutRstn` | input | crossbar 侧时钟/复位。 |
+| `Axi_CDC.axiIn_*` | input/output | CPU 侧 AXI 信号。 |
+| `Axi_CDC.axiOut_*` | output/input | `sys_clk` 域 AXI 信号，连接 crossbar master 0。 |
+
+### 3.3 `axi_wrap_ram_sp_external`
+
+作用：SRAM 子系统的 AXI slave 包装器。它把 AXI 读写转换为异步 SRAM 控制信号，并根据内部地址 bit22 选择 BaseRAM 或 ExtRAM。
+
+端口说明：
+
+| 端口 | 方向 | 解释 |
+| --- | --- | --- |
+| `aclk` | input | AXI/SRAM 控制器时钟，连接 `sys_clk`。 |
+| `aresetn` | input | 低有效复位。 |
+| `axi_ar*/axi_r*/axi_aw*/axi_w*/axi_b*` | input/output | RAM 的 AXI4 slave 接口，连接 crossbar `axiOut_0_*`。 |
+| `base_ram_data[31:0]` | inout | BaseRAM 双向数据总线。写周期由控制器驱动，读周期为高阻输入。 |
+| `base_ram_addr[19:0]` | output | BaseRAM 字地址，来自 `soc_sram_addr[21:2]`。 |
+| `base_ram_be_n[3:0]` | output | BaseRAM 字节使能，低有效。 |
+| `base_ram_ce_n` | output | BaseRAM 片选，低有效。 |
+| `base_ram_oe_n` | output | BaseRAM 读使能，低有效。 |
+| `base_ram_we_n` | output | BaseRAM 写使能，低有效。 |
+| `ext_ram_data[31:0]` | inout | ExtRAM 双向数据总线。 |
+| `ext_ram_addr[19:0]` | output | ExtRAM 字地址，来自 `soc_sram_addr[21:2]`。 |
+| `ext_ram_be_n[3:0]` | output | ExtRAM 字节使能，低有效。 |
+| `ext_ram_ce_n` | output | ExtRAM 片选，低有效。 |
+| `ext_ram_oe_n` | output | ExtRAM 读使能，低有效。 |
+| `ext_ram_we_n` | output | ExtRAM 写使能，低有效。 |
+
+地址说明：`0x1c000000` - `0x1c3fffff` 选择 BaseRAM，`0x1c400000` - `0x1c7fffff` 选择 ExtRAM。
+
+### 3.4 reserved window
+
+作用：`axiOut_1_*` 是保留窗口，顶层没有接实际模块。读数据返回 0，写请求直接 ready/空响应。该窗口不建议软件使用。
+
+### 3.5 `axi_uart_controller`
+
+作用：AXI 到 APB/UART 控制器。CPU 通过 AXI 访问 16550 风格 UART 寄存器，实现串口收发和中断。
+
+端口说明：
+
+| 端口 | 方向 | 解释 |
+| --- | --- | --- |
+| `clk` | input | UART AXI/APB 时钟，连接 `sys_clk`。 |
+| `rst_n` | input | 低有效复位。 |
+| `axi_s_*` | input/output | UART 的 AXI4 slave 接口，连接 crossbar `axiOut_2_*`。 |
+| `apb_rw_dma` | input | DMA APB 访问方向，顶层绑 0，当前未使用。 |
+| `apb_psel_dma` | input | DMA APB 片选，顶层绑 0。 |
+| `apb_enab_dma` | input | DMA APB enable，顶层绑 0。 |
+| `apb_addr_dma[19:0]` | input | DMA APB 地址，顶层绑 0。 |
+| `apb_valid_dma` | input | DMA APB 请求有效，顶层绑 0。 |
+| `apb_wdata_dma[31:0]` | input | DMA APB 写数据，顶层绑 0。 |
+| `apb_rdata_dma[31:0]` | output | DMA APB 读数据，顶层未使用。 |
+| `apb_ready_dma` | output | DMA APB ready，顶层未使用。 |
+| `dma_grant` | output | APB mux 对 DMA 的授权，顶层未使用。 |
+| `dma_req_o` | output | UART 控制器内部 DMA 请求，顶层未使用。 |
+| `dma_ack_i` | input | DMA ack，顶层绑 0。 |
+| `uart0_txd_i` | input | UART TX 管脚回读输入。 |
+| `uart0_txd_o` | output | UART TX 输出值。 |
+| `uart0_txd_oe` | output | UART TX 输出使能；顶层用它控制三态。 |
+| `uart0_rxd_i` | input | UART RX 输入值。 |
+| `uart0_rxd_o` | output | UART RX 输出值，三态模式下使用。 |
+| `uart0_rxd_oe` | output | UART RX 输出使能。 |
+| `uart0_rts_o` | output | UART RTS 调制解调控制输出。 |
+| `uart0_dtr_o` | output | UART DTR 调制解调控制输出。 |
+| `uart0_cts_i` | input | UART CTS 输入。 |
+| `uart0_dsr_i` | input | UART DSR 输入。 |
+| `uart0_dcd_i` | input | UART DCD 输入。 |
+| `uart0_ri_i` | input | UART RI 输入。 |
+| `uart0_int` | output | UART0 中断，送入 confreg 中断控制。 |
+
+### 3.6 `axi_dvi`
+
+作用：AXI 可配置的视频输出控制器。软件写入矩形/方形参数，模块产生 VGA/DVI 时序和 RGB 输出。
+
+端口说明：
+
+| 端口 | 方向 | 解释 |
+| --- | --- | --- |
+| `aclk` | input | DVI 控制器和像素时钟来源。 |
+| `aresetn` | input | 低有效复位。 |
+| `s_aw*/s_w*/s_b*/s_ar*/s_r*` | input/output | DVI 的 AXI4 slave 接口，连接 crossbar `axiOut_3_*`。 |
+| `video_clk` | output | 视频像素时钟输出。 |
+| `hsync` | output | 行同步信号。 |
+| `vsync` | output | 场同步信号。 |
+| `data_enable` | output | 有效显示区域指示。 |
+| `video_red[2:0]` | output | 红色像素分量。 |
+| `video_green[2:0]` | output | 绿色像素分量。 |
+| `video_blue[1:0]` | output | 蓝色像素分量。 |
+
+### 3.7 `confreg`
+
+作用：基础外设和中断控制寄存器模块。它负责 LED、数码管、拨码开关、触摸按键、系统定时器、中断状态聚合和仿真标志。
+
+端口说明：
+
+| 端口 | 方向 | 解释 |
+| --- | --- | --- |
+| `aclk` | input | AXI 外设时钟，连接 `sys_clk`。 |
+| `aresetn` | input | 低有效 AXI 复位。 |
+| `cpu_clk` | input | CPU 时钟，当前传入但主要逻辑在 `aclk` 域。 |
+| `cpu_resetn` | input | CPU 低有效复位。 |
+| `s_aw*/s_w*/s_b*/s_ar*/s_r*` | input/output | confreg 的 AXI4 slave 接口，连接 crossbar `axiOut_4_*`。 |
+| `led[15:0]` | output | 16 位 LED 输出。 |
+| `dpy0[7:0]` | output | 低位数码管输出。 |
+| `dpy1[7:0]` | output | 高位数码管输出。 |
+| `switch[31:0]` | input | 32 位拨码开关输入。 |
+| `touch_btn[3:0]` | input | 4 位触摸按键输入。 |
+| `uart0_int` | input | UART 中断输入，映射到 confreg 中断源 bit5。 |
+| `fft_finish` | input | FFT 完成输入，映射到 confreg 中断源 bit6。 |
+| `confreg_int` | output | confreg 聚合后的中断输出，送入 CPU `intrpt[0]`。 |
+
+### 3.8 `axi_axil_adapter`
+
+作用：把 crossbar `axiOut_5_*` 的 AXI4 slave 访问转换为 AXI-Lite 访问，供 DMA/CDMA 配置寄存器使用。
+
+端口说明：
+
+| 端口 | 方向 | 解释 |
+| --- | --- | --- |
+| `clk` | input | adapter 时钟，连接 `sys_clk`。 |
+| `rst` | input | 高有效复位，顶层连接 `~sys_resetn`。 |
+| `s_axi_*` | input/output | AXI4 slave 侧，连接 crossbar `axiOut_5_*`。 |
+| `m_axil_*` | output/input | AXI-Lite master 侧，连接 DMA 配置分流逻辑。 |
+
+### 3.9 `snix_axil_cdma_mux`
+
+作用：多通道 CDMA 控制器。它有 AXI-Lite 配置接口、AXI4 `mm2mm` master 数据搬运接口，以及本地 endpoint 接口。当前顶层参数 `PORTS=4`，即 4 个软件可见 DMA 通道。
+
+端口说明：
+
+| 端口 | 方向 | 解释 |
+| --- | --- | --- |
+| `clk` | input | CDMA 时钟，连接 `sys_clk`。 |
+| `rst_n` | input | 低有效复位。 |
+| `s_axil_*` | input/output | AXI-Lite 配置 slave 接口，来自 `axi_axil_adapter` 且未命中 bridge 子窗口时进入本模块。 |
+| `mm2mm_aw* / mm2mm_w* / mm2mm_b* / mm2mm_ar* / mm2mm_r*` | output/input | AXI4 master 数据搬运接口，连接 crossbar `axiIn_1_*`。 |
+| `ep_wr_valid` | output | 向本地 endpoint 写数据请求有效。当前连接 matmul。 |
+| `ep_wr_id[3:0]` | output | endpoint 编号。当前 matmul 使用 id 0。 |
+| `ep_wr_bank[3:0]` | output | endpoint bank 选择。当前 matmul 使用 bank0/bank1。 |
+| `ep_wr_word_addr[7:0]` | output | endpoint 内部 word 地址。 |
+| `ep_wr_data[31:0]` | output | 写入 endpoint 的 32 位数据。 |
+| `ep_wr_ready` | input | endpoint 可接收写数据。 |
+| `ep_rd_valid` | output | 从 endpoint 读数据请求有效。 |
+| `ep_rd_id[3:0]` | output | endpoint 编号。 |
+| `ep_rd_bank[3:0]` | output | endpoint bank 选择。 |
+| `ep_rd_word_addr[7:0]` | output | endpoint 内部 word 地址。 |
+| `ep_rd_data[31:0]` | input | endpoint 返回的 32 位数据。 |
+| `ep_rd_ready` | input | endpoint 读数据有效/可被采样。 |
+| `ext_rd_req_valid` | input | 外部序列器请求“内存到 endpoint”搬运。当前来自 `cdma_matmul_bridge`。 |
+| `ext_rd_req_ready` | output | CDMA 可接收外部读请求。 |
+| `ext_rd_req_src[31:0]` | input | 外部读请求的内存源地址。 |
+| `ext_rd_req_bytes[31:0]` | input | 外部读请求字节数。 |
+| `ext_rd_req_ep_id[3:0]` | input | 外部读请求目标 endpoint id。 |
+| `ext_rd_req_ep_bank[3:0]` | input | 外部读请求目标 endpoint bank。 |
+| `ext_rd_req_ep_word_off[7:0]` | input | 外部读请求目标 endpoint word 偏移。 |
+| `ext_rd_req_done` | output | 外部读请求完成脉冲/标志。 |
+| `ext_wr_req_valid` | input | 外部序列器请求“endpoint 到内存”搬运。 |
+| `ext_wr_req_ready` | output | CDMA 可接收外部写请求。 |
+| `ext_wr_req_dst[31:0]` | input | 外部写请求的内存目的地址。 |
+| `ext_wr_req_bytes[31:0]` | input | 外部写请求字节数。 |
+| `ext_wr_req_ep_id[3:0]` | input | 外部写请求源 endpoint id。 |
+| `ext_wr_req_ep_bank[3:0]` | input | 外部写请求源 endpoint bank。 |
+| `ext_wr_req_ep_word_off[7:0]` | input | 外部写请求源 endpoint word 偏移。 |
+| `ext_wr_req_done` | output | 外部写请求完成脉冲/标志。 |
+| `dma_finish` | output | DMA 完成中断/状态输出，送入顶层 `dma_finish` 合并逻辑。 |
+
+### 3.10 `cdma_matmul_bridge`
+
+作用：matmul 专用 CDMA 序列控制器。CPU 配置输入基地址、输出基地址、组数和 stride 后，它自动向 `snix_axil_cdma_mux` 发起 endpoint 读写请求，并直接控制 matmul 启动、清状态、清 CRC。
+
+端口说明：
+
+| 端口 | 方向 | 解释 |
+| --- | --- | --- |
+| `clk` | input | bridge 时钟，连接 `sys_clk`。 |
+| `rst_n` | input | 低有效复位。 |
+| `s_axil_*` | input/output | AXI-Lite 配置 slave 接口。当 DMA 配置地址 `[11:8] == 4'h2` 时访问本模块。 |
+| `cdma_rd_req_valid` | output | 请求 CDMA 从内存读取数据到 matmul endpoint。 |
+| `cdma_rd_req_ready` | input | CDMA 可接收读请求。 |
+| `cdma_rd_req_src[31:0]` | output | 读请求内存源地址。 |
+| `cdma_rd_req_bytes[31:0]` | output | 读请求字节数，matmul 输入固定为 128B。 |
+| `cdma_rd_req_ep_id[3:0]` | output | 读请求目标 endpoint id。 |
+| `cdma_rd_req_ep_bank[3:0]` | output | 读请求目标 matmul bank。 |
+| `cdma_rd_req_ep_word_off[7:0]` | output | 读请求目标 endpoint word 偏移。 |
+| `cdma_rd_req_done` | input | CDMA 读请求完成。 |
+| `cdma_wr_req_valid` | output | 请求 CDMA 从 matmul endpoint 写回内存。 |
+| `cdma_wr_req_ready` | input | CDMA 可接收写请求。 |
+| `cdma_wr_req_dst[31:0]` | output | 写请求内存目的地址。 |
+| `cdma_wr_req_bytes[31:0]` | output | 写请求字节数，matmul 输出固定为 192B。 |
+| `cdma_wr_req_ep_id[3:0]` | output | 写请求源 endpoint id。 |
+| `cdma_wr_req_ep_bank[3:0]` | output | 写请求源 matmul bank。 |
+| `cdma_wr_req_ep_word_off[7:0]` | output | 写请求源 endpoint word 偏移。 |
+| `cdma_wr_req_done` | input | CDMA 写请求完成。 |
+| `mat_start_valid` | output | 启动 matmul 计算的有效脉冲。 |
+| `mat_start_bank` | output | 启动哪个 matmul bank。 |
+| `mat_done_clear` | output | 清除 matmul done/error 状态。 |
+| `mat_crc_clear` | output | 清除 matmul CRC 累积值。 |
+| `mat_done` | input | matmul 计算完成状态。 |
+| `seq_done_irq` | output | 整个 matmul 序列完成中断，顶层与 `cdma_dma_finish` OR 成 `dma_finish`。 |
+
+### 3.11 `fft_mlkem_axi_slave`
+
+作用：共享 AXI slave 地址窗口，按地址低 16 位的 `[15:12]` 将请求分发到 ML-KEM 或 FFT。
+
+端口说明：
+
+| 端口 | 方向 | 解释 |
+| --- | --- | --- |
+| `clk` | input | AXI 时钟，连接 `sys_clk`。 |
+| `resetn` | input | 低有效复位。 |
+| `s_axi_*` | input/output | 共享加速器 AXI4 slave 接口，连接 crossbar `axiOut_6_*`。 |
+| `fft_finish` | output | FFT 完成状态，送入 confreg。 |
+| `mlkem_intr` | output | ML-KEM 完成中断，直接送入 CPU `intrpt[3]`。 |
+
+内部地址分发：
+
+| 偏移范围 | 子模块 |
+| --- | --- |
+| `0x0000` - `0x3fff` | `mlkem_axi_slave` |
+| `0x8000` - `0xcfff` | `fft_controller` / FFT |
+
+### 3.12 `mlkem_axi_slave`
+
+作用：ML-KEM 加速器 AXI4 slave 包装器，提供 KeyGen、Encaps、Decaps 的配置、输入预加载、输出读回和中断。
+
+端口说明：
+
+| 端口 | 方向 | 解释 |
+| --- | --- | --- |
+| `clk` | input | AXI 总线时钟。内部再产生 `mlkem_clk = clk/2`。 |
+| `resetn` | input | 低有效复位。 |
+| `s_axi_*` | input/output | ML-KEM AXI4 slave 接口，由 `fft_mlkem_axi_slave` 分发而来。 |
+| `intr` | output | ML-KEM done 锁存后的高电平中断。 |
+
+### 3.13 `fft_controller`
+
+作用：1024 点 16-bit FFT 加速器。通过 AXI 写入输入实部/虚部 BRAM，写 CSR 启动计算，完成后从输出实部/虚部窗口读取结果。
+
+端口说明：
+
+| 端口 | 方向 | 解释 |
+| --- | --- | --- |
+| `aclk` | input | FFT/AXI 时钟。 |
+| `aresetn` | input | 低有效复位。 |
+| `s_aw*/s_w*/s_b*/s_ar*/s_r*` | input/output | FFT AXI4 slave 接口，由 `fft_mlkem_axi_slave` 分发而来。 |
+| `fft_finish` | output | FFT done 状态，来自 CSR status bit1。 |
+
+### 3.14 `matmul_axi_slave`
+
+作用：矩阵乘法加速器 AXI slave。它既支持 CPU 通过 AXI 访问控制寄存器和 bank 数据，也支持 CDMA 通过本地 endpoint 写入输入、读出结果。模块内部带 CRC32 累积逻辑。
+
+端口说明：
+
+| 端口 | 方向 | 解释 |
+| --- | --- | --- |
+| `clk` | input | matmul/AXI 时钟，连接 `sys_clk`。 |
+| `resetn` | input | 低有效复位。 |
+| `s_axi_*` | input/output | matmul AXI4 slave 接口，连接 crossbar `axiOut_7_*`。 |
+| `ep_wr_valid` | input | CDMA 本地 endpoint 写请求有效。 |
+| `ep_wr_id[3:0]` | input | endpoint id。当前仅使用 id 0。 |
+| `ep_wr_bank[3:0]` | input | 写入 bank 选择，bit0 选择 bank0/bank1。 |
+| `ep_wr_word_addr[7:0]` | input | 写入 bank 内 word 地址，0-15 为 A，16-31 为 B。 |
+| `ep_wr_data[31:0]` | input | 写入 A/B 矩阵的 32 位数据。 |
+| `ep_wr_ready` | output | matmul endpoint 可接收写数据。当前恒为 1。 |
+| `ep_rd_valid` | input | CDMA 本地 endpoint 读请求有效。 |
+| `ep_rd_id[3:0]` | input | endpoint id。 |
+| `ep_rd_bank[3:0]` | input | 读取 bank 选择。 |
+| `ep_rd_word_addr[7:0]` | input | 读取结果 C 的 word 地址。每个 66-bit 结果拆成 3 个 32-bit word。 |
+| `ep_rd_data[31:0]` | output | endpoint 返回的 32 位结果数据。 |
+| `ep_rd_ready` | output | endpoint 读数据可用。当前恒为 1。 |
+| `mat_start_valid` | input | 来自 bridge 的启动脉冲。 |
+| `mat_start_bank` | input | 启动计算的 bank。 |
+| `mat_done_clear` | input | 清除 done/error。 |
+| `mat_crc_clear` | input | 清除 CRC32 累积值。 |
+| `mat_done` | output | 计算完成状态。 |
+| `intr` | output | matmul 完成中断，送入 CPU `intrpt[2]`。 |
+
+## 4. 寄存器地址表
+
+以下地址以软件常用非缓存虚拟地址列出；括号中给出对应物理地址基址。
+
+### 4.1 UART0 (`0xbf000000`, physical `0x1f000000`)
+
+16550 风格 8-bit 寄存器，软件常用字节访问。
+
+| 地址 | 偏移 | 名称 | 访问 | 说明 |
+| --- | --- | --- | --- | --- |
+| `0xbf000000` | `0x0` | `RBR/THR` 或 `DLL` | R/W | DLAB=0 时读接收缓冲/写发送保持；DLAB=1 时为 divisor low byte。 |
+| `0xbf000001` | `0x1` | `IER` 或 `DLM` | R/W | DLAB=0 时为中断使能；DLAB=1 时为 divisor high byte。 |
+| `0xbf000002` | `0x2` | `IIR/FCR` | R/W | 读为中断识别，写为 FIFO 控制；DLAB=1 时部分实现作为 divisor 扩展。 |
+| `0xbf000003` | `0x3` | `LCR` | R/W | 线控制寄存器，bit7 为 DLAB。 |
+| `0xbf000004` | `0x4` | `MCR` | R/W | modem 控制。 |
+| `0xbf000005` | `0x5` | `LSR` | R | 线状态，软件轮询 bit5/bit6 判断发送 FIFO/发送器空。 |
+| `0xbf000006` | `0x6` | `MSR` | R | modem 状态。 |
+| `0xbf000007` | `0x7` | `SCR` | R/W | scratch/mode 寄存器。 |
+
+### 4.2 DVI (`0xbf100000`, physical `0x1f100000`)
+
+| 地址 | 偏移 | 名称 | 访问 | 说明 |
+| --- | --- | --- | --- | --- |
+| `0xbf100000` | `0x0` | `DVI_RECT_DIR` | R/W | 矩形位置参数，`[31:16]` 为 x，`[15:0]` 为 y。 |
+| `0xbf100004` | `0x4` | `DVI_RECT_L_W` | R/W | 矩形尺寸参数，`[31:16]` 为长度/半宽相关参数，`[15:0]` 为宽度/高度相关参数。 |
+| `0xbf100008` | `0x8` | `DVI_SQU_DIR` | R/W | 方形位置参数。 |
+| `0xbf10000c` | `0xc` | `DVI_SQU_R` | R/W | 方形半径/尺寸参数。 |
+
+### 4.3 confreg (`0xbf200000`, physical `0x1f200000`)
+
+| 地址 | 偏移 | 名称 | 访问 | 说明 |
+| --- | --- | --- | --- | --- |
+| `0xbf20f000` | `0xf000` | `CONFREG_INT_EN` | R/W | 中断使能。 |
+| `0xbf20f004` | `0xf004` | `CONFREG_INT_EDGE` | R/W | 中断边沿/电平模式配置。 |
+| `0xbf20f008` | `0xf008` | `CONFREG_INT_POL` | R/W | 中断极性配置。 |
+| `0xbf20f00c` | `0xf00c` | `CONFREG_INT_CLR` | W/R | 写 1 清除对应中断状态。 |
+| `0xbf20f010` | `0xf010` | `CONFREG_INT_SET` | W/R | 写 1 软件置位对应中断状态。 |
+| `0xbf20f014` | `0xf014` | `CONFREG_INT_STATE` | R | 当前中断状态。bit0-3 touch_btn，bit4 timer，bit5 UART，bit6 FFT。 |
+| `0xbf20f100` | `0xf100` | `TIMER_VALUE` | R | 系统计数器当前值。 |
+| `0xbf20f104` | `0xf104` | `TIMER_CMP` | R/W | 定时器比较值。 |
+| `0xbf20f108` | `0xf108` | `TIMER_EN` | R/W | bit0 使能定时器。 |
+| `0xbf20f200` | `0xf200` | `DIGITAL_CTRL` | R/W | 数码管控制寄存器。 |
+| `0xbf20f204` | `0xf204` | `DIGITAL_DATA` | R/W | 数码管显示数据。 |
+| `0xbf20f300` | `0xf300` | `LED_DATA` | R/W | LED 输出寄存器，低 16 位连接 `leds[15:0]`。 |
+| `0xbf20f400` | `0xf400` | `SWITCH_DATA` | R | 32 位拨码开关输入。 |
+| `0xbf20f500` | `0xf500` | `SIMU_FLAG` | R | 仿真标志，值为 `{32{SIMULATION}}`。 |
+
+### 4.4 DMA/CDMA (`0xbf300000`, physical `0x1f300000`)
+
+当前 `snix_axil_cdma_mux` 在顶层例化为 `PORTS=4`，通道 `ch=0..3`，每个通道 stride 为 `0x40`。通道寄存器地址为 `0xbf300000 + ch * 0x40 + offset`。
+
+| 偏移 | 名称 | 访问 | 说明 |
+| --- | --- | --- | --- |
+| `0x00` | `SRC_ADDR` | R/W | 源地址。mem2mem/mem2ep 时为内存源地址。 |
+| `0x04` | `DST_ADDR` | R/W | 目的地址。mem2mem/ep2mem 时为内存目的地址。 |
+| `0x08` | `LENGTH` | R/W | 传输字节数。 |
+| `0x0c` | `TAG` | R/W | 软件 tag，硬件不参与数据路径。 |
+| `0x10` | `CTRL` | R/W | bit0 写 1 启动；`[5:3]` 为 AXI AxSIZE；`[13:6]` 为 AXI AxLEN。 |
+| `0x14` | `STATUS` | R/W | bit0 busy，只读；bit1 done，写 1 清除。 |
+| `0x18` | `MODE` | R/W | `0=mem2mem`，`1=mem2ep`，`2=ep2mem`。 |
+| `0x1c` | `EP_CFG` | R/W | `[3:0]` bank，`[15:8]` word offset，`[19:16]` endpoint id。 |
+
+通道基址：
+
+| 通道 | 基址 |
+| --- | --- |
+| channel 0 | `0xbf300000` |
+| channel 1 | `0xbf300040` |
+| channel 2 | `0xbf300080` |
+| channel 3 | `0xbf3000c0` |
+
+matmul 序列控制子窗口由 `cdma_matmul_bridge` 实现，地址为 `0xbf300200 + offset`：
+
+| 地址 | 偏移 | 名称 | 访问 | 说明 |
+| --- | --- | --- | --- | --- |
+| `0xbf300200` | `0x200` | `SEQ_CTRL` | R/W | bit0 start；bit1 skip_result_writeback。 |
+| `0xbf300204` | `0x204` | `SEQ_STATUS` | R/W | bit0 busy；bit1 done，写 1 清除。 |
+| `0xbf300208` | `0x208` | `SEQ_SRC_BASE` | R/W | 输入矩阵组的物理源基址。 |
+| `0xbf30020c` | `0x20c` | `SEQ_DST_BASE` | R/W | 输出矩阵组的物理目的基址。 |
+| `0xbf300210` | `0x210` | `SEQ_GROUPS` | R/W | 自动处理的矩阵组数。 |
+| `0xbf300214` | `0x214` | `SEQ_MAT_BASE` | R/W | 保留兼容字段，软件通常写 `0x1f500000`。 |
+| `0xbf300218` | `0x218` | `SEQ_SRC_STRIDE` | R/W | 相邻输入组间隔，默认 128B。 |
+| `0xbf30021c` | `0x21c` | `SEQ_DST_STRIDE` | R/W | 相邻输出组间隔，默认 192B。 |
+
+### 4.5 FFT/ML-KEM 共享窗口 (`0xbf400000`, physical `0x1f400000`)
+
+#### 4.5.1 ML-KEM 子窗口
+
+| 地址/范围 | 偏移 | 名称 | 访问 | 说明 |
+| --- | --- | --- | --- | --- |
+| `0xbf400000` | `0x000` | `MLKEM_CTRL` | W | bit0 start，启动 CONFIG 指定的操作。 |
+| `0xbf400004` | `0x004` | `MLKEM_STATUS` | R/W | bit0 busy，bit1 done，bit2 preload_busy；写 bit1=1 清 done。 |
+| `0xbf400008` | `0x008` | `MLKEM_CONFIG` | R/W | `[2:0] k`，`[5:4] op`，op: 0 KeyGen，1 Encaps，2 Decaps。 |
+| `0xbf400010` - `0xbf40002c` | `0x010` - `0x02c` | `D[0..7]` | R/W | KeyGen seed d，8 个 32-bit word。 |
+| `0xbf400030` - `0xbf40004c` | `0x030` - `0x04c` | `Z[0..7]` | R/W | implicit-reject seed z。 |
+| `0xbf400050` - `0xbf40006c` | `0x050` - `0x06c` | `MSG[0..7]` | R/W | Encaps message m。 |
+| `0xbf400070` - `0xbf40008c` | `0x070` - `0x08c` | `SS[0..7]` | R | shared secret 输出。 |
+| `0xbf400100` | `0x100` | `PRELOAD_SEL` | R/W | 0=ek_in，1=dk_in，2=c_in。 |
+| `0xbf400104` | `0x104` | `PRELOAD_ADDR` | R/W | 预加载字节地址，写 `PRELOAD_DATA` 后自动递增。 |
+| `0xbf400108` | `0x108` | `PRELOAD_DATA` | W | 写低 8 位，流入所选输入端口。 |
+| `0xbf40010c` | `0x10c` | `RDBK_SEL` | R/W | 0=ek，1=dk_pke，2=full-dk，3=ciphertext。 |
+| `0xbf400110` | `0x110` | `RDBK_ADDR` | R/W | 读回字节索引。 |
+| `0xbf400114` | `0x114` | `RDBK_DATA` | R | 读回低 8 位数据。 |
+| `0xbf401000` - `0xbf401fff` | `0x1000` - `0x1fff` | `EK` | W/R | 写为 preload ek_in，读为 generated ek。 |
+| `0xbf402000` - `0xbf402fff` | `0x2000` - `0x2fff` | `DK` | W/R | 写为 preload dk_in，读为 generated full dk。 |
+| `0xbf403000` - `0xbf403fff` | `0x3000` - `0x3fff` | `CT` | W/R | 写为 preload c_in，读为 generated ciphertext。 |
+
+#### 4.5.2 FFT 子窗口
+
+| 地址/范围 | 偏移 | 名称 | 访问 | 说明 |
+| --- | --- | --- | --- | --- |
+| `0xbf408000` - `0xbf408ffc` | `0x8000` - `0x8ffc` | `FFT_IN_RE[0..1023]` | W | 输入实部 BRAM，每项低 16 位有效。 |
+| `0xbf409000` - `0xbf409ffc` | `0x9000` - `0x9ffc` | `FFT_IN_IM[0..1023]` | W | 输入虚部 BRAM，每项低 16 位有效。 |
+| `0xbf40a000` - `0xbf40affc` | `0xa000` - `0xaffc` | `FFT_OUT_RE[0..1023]` | R | 输出实部，符号扩展到 32 位，读出时使用 bit-reverse 地址。 |
+| `0xbf40b000` - `0xbf40bffc` | `0xb000` - `0xbffc` | `FFT_OUT_IM[0..1023]` | R | 输出虚部，符号扩展到 32 位，读出时使用 bit-reverse 地址。 |
+| `0xbf40c000` | `0xc000` | `FFT_CSR` | R/W | `[7:4]` 为 ctrl，写 bit4 启动/清 done；`[3:0]` 为 status，bit0 busy，bit1 done。 |
+
+### 4.6 Matmul (`0xbf500000`, physical `0x1f500000`)
+
+| 地址/范围 | 偏移 | 名称 | 访问 | 说明 |
+| --- | --- | --- | --- | --- |
+| `0xbf500000` | `0x000` | `MAT_CTRL` | R/W | bit0 启动 bank0，bit1 启动 bank1。 |
+| `0xbf500004` | `0x004` | `MAT_STATUS` | R/W | bit0 busy，bit1 done，bit2 error；写 bit1 清 done，写 bit2 清 error。 |
+| `0xbf500010` | `0x010` | `MAT_CRC` | R/W | 读返回 `crc_reg ^ 0xffffffff`；写该地址或 bridge 的 `mat_crc_clear` 清 CRC。 |
+| `0xbf500100` - `0xbf50013c` | `0x100` - `0x13c` | `B0_A[0..15]` | R/W | bank0 输入矩阵 A，16 个 32-bit word。 |
+| `0xbf500140` - `0xbf50017c` | `0x140` - `0x17c` | `B0_B[0..15]` | R/W | bank0 输入矩阵 B。 |
+| `0xbf500180` - `0xbf50023c` | `0x180` - `0x23c` | `B0_C` | R | bank0 输出矩阵 C，16 个 66-bit 结果，每个结果拆成 3 个 32-bit word，共 192B。 |
+| `0xbf500300` - `0xbf50033c` | `0x300` - `0x33c` | `B1_A[0..15]` | R/W | bank1 输入矩阵 A。 |
+| `0xbf500340` - `0xbf50037c` | `0x340` - `0x37c` | `B1_B[0..15]` | R/W | bank1 输入矩阵 B。 |
+| `0xbf500380` - `0xbf50043c` | `0x380` - `0x43c` | `B1_C` | R | bank1 输出矩阵 C，格式同 bank0。 |
+
+## 5. 关键数据路径说明
+
+1. CPU 访问任意外设或内存：`core_top -> Axi_CDC -> AxiCrossbar_2x8 -> 对应 AXI slave`。
+2. DMA 访问 SRAM：`snix_axil_cdma_mux mm2mm master -> AxiCrossbar_2x8 -> axi_wrap_ram_sp_external -> BaseRAM/ExtRAM`。DMA 和 SRAM 没有直接物理连线。
+3. DMA 访问 matmul 本地 endpoint：`snix_axil_cdma_mux -> ep_wr/ep_rd -> matmul_axi_slave`。这条是本地 endpoint 通路，不经过 AXI crossbar。
+4. matmul 批处理序列：CPU 写 `0xbf300200` 等寄存器配置 `cdma_matmul_bridge`，bridge 自动发起 CDMA 读/写请求并控制 matmul 启停。
+5. FFT/ML-KEM 共用 `0xbf400000` 窗口，由 `fft_mlkem_axi_slave` 依据偏移分发。

doc/mlkem_test_results.md

@@ -0,0 +1,45 @@
+# ML-KEM Test Results Summary
+
+## Test Setup
+
+- Platform: LoongArch bare-metal target
+- Test mode: `STATIC_KAT_COUNT_0`
+- Levels: `k=2,3,4`
+- Repeat count: `100`
+- ML-KEM software allocator: `MLK_CONFIG_CUSTOM_ALLOC_FREE`
+- Verification sources: KAT count 0 expected values
+
+## Correctness
+
+All three paths passed in isolated testing:
+
+- `SW_ONLY_FAILS=0`
+- `CPU_ONLY_FAILS=0`
+- `DMA_ONLY_FAILS=0`
+
+Final result for the isolated diagnostic run:
+
+- `MLKEM512_RESULT=PASS`
+- `MLKEM768_RESULT=PASS`
+- `MLKEM1024_RESULT=PASS`
+- `MLKEM_RESULT=PASS`
+
+## Performance
+
+The following results are from isolated per-level runs. Each level was tested
+for 100 iterations with software-only, CPU register path, and DMA path separated.
+
+| Level | SW avg cycles | CPU avg cycles | DMA avg cycles | CPU vs SW | DMA vs SW | DMA vs CPU |
+|---|---:|---:|---:|---:|---:|---:|
+| k=2 / ML-KEM-512 | 2,587,784 | 352,684 | 185,671 | 7.34x | 13.94x | 1.90x |
+| k=3 / ML-KEM-768 | 4,056,378 | 523,656 | 279,588 | 7.75x | 14.51x | 1.87x |
+| k=4 / ML-KEM-1024 | 6,025,486 | 718,672 | 388,959 | 8.38x | 15.49x | 1.85x |
+
+## Notes
+
+- CPU/DMA hardware paths were stable across 100 iterations for all levels.
+- Software, CPU register path, and DMA path all passed 100 iterations for k=2, k=3, and k=4.
+- The DMA path is 13.94x to 15.49x faster than software across the tested levels.
+- The CPU register path is 7.34x to 8.38x faster than software across the tested levels.
+- The DMA path is about 1.85x to 1.90x faster than the CPU register path.
+- The hardware advantage increases slightly as k grows, because the accelerated computation grows faster than the fixed software control overhead.

doc/reports/backend/backend_design_report.tex

@@ -0,0 +1,223 @@
+\documentclass[11pt,a4paper,twoside]{article}
+
+% ─── Packages ────────────────────────────────────────────────
+\usepackage{ctex}
+\usepackage[top=2.5cm, bottom=2.5cm, left=2.8cm, right=2.8cm]{geometry}
+\usepackage{graphicx}
+\usepackage{float}
+\usepackage{booktabs}
+\usepackage{array}
+\usepackage{amsmath,amssymb}
+\usepackage{hyperref}
+\usepackage{caption}
+\usepackage{fancyhdr}
+\usepackage{enumitem}
+\usepackage[normalem]{ulem}
+\usepackage{xcolor}
+
+% ─── Styling ─────────────────────────────────────────────────
+\raggedbottom
+\hypersetup{colorlinks=true,linkcolor=black,citecolor=black,urlcolor=blue}
+\pagestyle{fancy}
+\fancyhead[LO,RE]{芯片后端设计报告}
+\fancyhead[RO,LE]{\thepage}
+\fancyfoot[C]{}
+\setlength{\parskip}{4pt plus 2pt minus 1pt}
+\setlength{\parindent}{2em}
+\setlength{\headheight}{14pt}
+\setlength{\emergencystretch}{1.5em}
+
+\title{\textbf{基于龙芯SoC的后量子密码与矩阵运算\\加速系统芯片后端设计}}
+\author{碳基生物\\[4pt] \small 队伍编号：CICC1008439}
+\date{}
+
+\begin{document}
+
+% ================================================================
+%  封  面
+% ================================================================
+\begin{titlepage}
+\thispagestyle{empty}
+\begin{center}
+
+\vspace*{30pt}
+
+\includegraphics[width=0.45\textwidth]{logo_cicc.png}
+
+\vspace{36pt}
+
+{\fontsize{22pt}{28pt}\selectfont\bfseries 第十届}
+
+\vspace{4pt}
+
+{\fontsize{22pt}{28pt}\selectfont\bfseries 全国大学生集成电路创新创业大赛}
+
+\end{center}
+
+\vspace{80pt}
+
+\begin{flushleft}
+\fontsize{14pt}{22pt}\selectfont
+报告类型：\uline{\hfill 后端设计实践报告\hfill} \\[18pt]
+参赛杯赛：\uline{\hfill 龙芯中科杯\hfill} \\[18pt]
+作品名称：\uline{\hfill 基于龙芯SoC的后量子密码与矩阵运算加速系统芯片后端设计\hfill} \\[18pt]
+队伍编号：\uline{\hfill CICC1008439\hfill} \\[18pt]
+团队名称：\uline{\hfill 碳基生物\hfill}
+\end{flushleft}
+
+\end{titlepage}
+
+\maketitle
+\tableofcontents
+\newpage
+
+% ================================================================
+\section{概述}
+
+本报告为龙芯中科杯分赛区决赛的后端设计实践报告，基于\emph{《基于龙芯SoC的后量子密码与矩阵运算加速系统设计与验证》}系统设计报告中所描述的SoC顶层设计（逻辑顶层模块为\texttt{mycpu\_top}），完成从RTL代码到GDSII版图的完整物理实现流程。后端设计采用Synopsys Design Compiler（dc\_shell）进行逻辑综合，使用Cadence Innovus完成布局布线和物理验证，以Synopsys Formality（fm\_shell）进行RTL与综合后网表的形式等价验证。
+
+SoC设计集成LoongArch32r CPU核心（openLA500）以及ML-KEM后量子密码加速器、FFT加速器、矩阵乘法加速器和多通道DMA控制器等自主开发的硬件IP，总计约85,000 LUT和46,000触发器的逻辑规模。后端实现的目标工艺为SMIC 180nm。
+
+\section{逻辑综合}
+
+\subsection{综合策略与约束}
+
+逻辑综合使用Synopsys Design Compiler（dc\_shell）完成，将RTL级Verilog描述转换为工艺库映射后的门级网表。综合脚本统一由\texttt{syn.tcl}组织，流程覆盖读入RTL文件、设置工艺库路径、施加时序与物理约束、执行综合优化与映射、输出网表和时序报告等完整步骤。
+
+时序约束文件\texttt{mycpu\_soc.sdc}定义了设计的时钟网络、输入输出延迟和负载条件。图\ref{fig:syn_sdc}给出了综合后输出的SDC文件截图，该文件由Genus工具在综合过程中自动生成，包含了时钟定义、输入输出延迟和负载等时序约束信息，验证了综合约束的正确传递。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{syn_sdc.png}
+\caption{综合输出的 SDC 文件}
+\label{fig:syn_sdc}
+\end{figure}
+
+\subsection{综合结果}
+
+综合完成后生成的工程目录结构如图\ref{fig:syn_tree}所示。输出物包括映射后的门级网表文件、时序与面积报告、以及综合过程中产生的中间数据。从目录结构可以确认综合约束文件、工艺库映射结果和最终网表文件均已正确生成。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{syn_tree.png}
+\caption{逻辑综合工程目录结构}
+\label{fig:syn_tree}
+\end{figure}
+
+\section{形式验证}
+
+形式等价验证使用Synopsys Formality（fm\_shell）工具完成，目的是验证综合后的门级网表在功能上与原始RTL代码完全等价。验证流程包括读入参考设计（RTL）、读入实现设计（综合网表）、设置比较点和运行验证引擎等步骤。
+
+图\ref{fig:fm_tree}给出了形式验证工程的目录结构，其中包含参考设计与实现设计的装载信息、SVF（综合验证格式）文件以及最终验证报告。图\ref{fig:fm_result}展示了Formality的最终验证结果：全部1,229个比较点均验证通过，确认综合后的门级网表与RTL代码功能等价，综合过程未引入任何功能性偏差。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{fm_tree.png}
+\caption{形式验证工程目录结构}
+\label{fig:fm_tree}
+\end{figure}
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{fm_verification.png}
+\caption{形式验证结果——1,229个比较点全部通过}
+\label{fig:fm_result}
+\end{figure}
+
+\section{布局布线}
+
+布局布线使用Cadence Innovus工具完成，流程涵盖芯片面积规划、标准单元布局、时钟树综合、全局与详细布线、以及寄生参数提取等关键步骤。
+
+图\ref{fig:pr_ls}和图\ref{fig:pr_output}分别展示了布局布线工程的主目录结构和输出文件列表。最终交付物中包含了版图数据文件（GDSII格式，\texttt{phy\_top.gds.gz}）、用于LVS验证的门级网表（\texttt{phy\_top\_lvs.v}）以及各类时序和设计规则检查报告。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{pr_ls.png}
+\caption{布局布线工程目录结构}
+\label{fig:pr_ls}
+\end{figure}
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{pr_output.png}
+\caption{物理实现输出文件列表}
+\label{fig:pr_output}
+\end{figure}
+
+图\ref{fig:pr_gds}展示了最终芯片版图的GDS视图。版图中可见整体芯片布局、标准单元区域、布线通道以及外围的I/O框架结构。布线层中金属走线清晰可见，表明全局与详细布线均已成功完成。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{pr_gds.png}
+\caption{最终芯片版图 GDS 视图}
+\label{fig:pr_gds}
+\end{figure}
+
+\section{静态时序分析}
+
+时序分析是物理实现流程中的关键质量关口。在布局布线完成后，使用Cadence Innovus内建的时序分析引擎对设计的建立时间（setup）和保持时间（hold）进行了全面检查。
+
+\subsection{建立时间分析}
+
+图\ref{fig:pr_setup}展示了建立时间分析的汇总结果。报告给出了各时钟域的WNS（最差负余量）、TNS（总负余量）、违例路径数和总路径数等核心指标。建立时间反映了数据路径在时钟有效沿到达之前是否已经稳定，是决定设计最高工作频率的关键约束。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{pr_setup_summary.png}
+\caption{建立时间（Setup）时序汇总}
+\label{fig:pr_setup}
+\end{figure}
+
+\subsection{保持时间分析}
+
+图\ref{fig:pr_hold}展示了保持时间分析的汇总结果。保持时间确保数据在时钟有效沿之后能够保持足够长的时间以满足寄存器的保持时间要求。保持时间违例通常通过在数据路径中插入缓冲器来修复，是后端设计中的常规修复步骤。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{pr_hold_summary.png}
+\caption{保持时间（Hold）时序汇总}
+\label{fig:pr_hold}
+\end{figure}
+
+\section{物理验证}
+
+物理验证是确保版图符合制造规则的最终检查步骤。本设计在Cadence Innovus中通过内建的\texttt{verify\_drc}命令完成了设计规则检查。
+
+图\ref{fig:pr_drc}给出了DRC检查的结果。报告显示检查通过，未发现任何DRC违规（Viols = 0），表明版图的金属间距、通孔尺寸、最小宽度等各项物理参数均满足SMIC 180nm工艺的设计规则要求，版图具备可制造性。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{pr_drc.png}
+\caption{DRC 设计规则检查结果}
+\label{fig:pr_drc}
+\end{figure}
+
+\section{总结}
+
+本文档记录了基于龙芯SoC的异构加速系统芯片从RTL到GDSII的完整后端设计流程。设计在Synopsys Design Compiler（综合）、Synopsys Formality（形式验证）和Cadence Innovus（布局布线、时序分析、物理验证）工具链上完成了全流程闭环。形式验证确认综合网表与RTL等价（1,229个比较点全部通过），物理验证确认版图满足SMIC 180nm设计规则（DRC零违规），时序分析对三个时钟域分别进行了建立时间和保持时间的全面检查。
+
+\begin{thebibliography}{10}
+
+\bibitem{smic180}
+SMIC Inc.
+\emph{SMIC 180nm Standard Cell Library Documentation}.
+2024.
+
+\bibitem{synopsys_dc}
+Synopsys Inc.
+\emph{Design Compiler User Guide}.
+2023.
+
+\bibitem{cadence_innovus}
+Cadence Design Systems Inc.
+\emph{Innovus Implementation System User Guide}.
+2023.
+
+\bibitem{synopsys_fm}
+Synopsys Inc.
+\emph{Formality User Guide}.
+2023.
+
+\end{thebibliography}
+
+\end{document}

doc/reports/backend/images_overview.md

@@ -0,0 +1,16 @@
+# 当前目录图片说明
+
+本文件用于说明当前文件夹下各张图片的内容，便于在芯片后端设计报告中引用。
+
+| 图片文件 | 内容说明 |
+| --- | --- |
+| `syn_sdc.png` | 综合网表约束文件 `SDC` 的截图，包含时钟、输入输出负载、最大转换时间等约束设置，以及对地址和写数据端口的逐位负载配置。 |
+| `pr_drc.png` | 版图实现后的 `DRC` 检查结果截图，显示 `Cadence Innovus` 检查通过，没有发现 DRC 违规。 |
+| `pr_setup_summary.png` | 后端布线后的建立时间（`setup`）时序汇总截图，展示 `WNS`、`TNS`、违例路径数、路径总数以及密度等关键指标。 |
+| `pr_hold_summary.png` | 后端布线后的保持时间（`hold`）时序汇总截图，展示保持时间分析结果，其中存在少量保持违例路径。 |
+| `pr_output.png` | 物理实现输出文件列表截图，包含 `phy_top.gds.gz` 和 `phy_top_lvs.v` 等最终交付文件。 |
+| `pr_ls.png` | 版图实现目录下的文件列表截图，用于查看 `GDS`、`LVS`、日志和报告等输出内容。 |
+| `fm_tree.png` | `Formality` 形式等价检查工程目录树截图，展示 `FM_INFO`、`reports`、`formality_svf` 等目录及其文件结构。 |
+| `syn_tree.png` | 综合网表综合工程目录树截图，展示综合输出、报告、重定时/映射结果以及 `syn.tcl` 等文件结构。 |
+| `pr_gds.png` | 最终芯片版图 `GDS` 视图截图，显示整体芯片布局、布线结果和外围框架结构。 |
+| `fm_verification.png` | `Formality` 形式等价验证结果截图，显示验证成功，`1229` 个比较点全部通过。 |

doc/reports/mlkem_ip/mlkem_ip_design_report.tex

@@ -0,0 +1,782 @@
+\documentclass[11pt,a4paper,twoside]{article}
+
+% ─── Packages ────────────────────────────────────────────────
+\usepackage{ctex}
+\usepackage[top=2.5cm, bottom=2.5cm, left=2.8cm, right=2.8cm]{geometry}
+\usepackage{graphicx}
+\usepackage{float}
+\usepackage{booktabs}
+\usepackage{longtable}
+\usepackage{multirow}
+\usepackage{array}
+\usepackage{amsmath,amssymb}
+\usepackage{hyperref}
+\usepackage{caption}
+\usepackage{subcaption}
+\usepackage{fancyhdr}
+\usepackage{tikz}
+\usepackage{enumitem}
+\usepackage[normalem]{ulem}
+\usepackage{listings}
+\usepackage{xcolor}
+\usepackage{algorithm}
+\usepackage{algpseudocode}
+
+% ─── Styling ─────────────────────────────────────────────────
+\raggedbottom
+\hypersetup{colorlinks=true,linkcolor=black,citecolor=black,urlcolor=blue}
+\pagestyle{fancy}
+\fancyhead[LO,RE]{ML-KEM硬件IP设计报告}
+\fancyhead[RO,LE]{\thepage}
+\fancyfoot[C]{}
+\setlength{\parskip}{4pt plus 2pt minus 1pt}
+\setlength{\parindent}{2em}
+\setlength{\headheight}{14pt}
+\setlength{\intextsep}{6pt plus 2pt}
+\setlength{\textfloatsep}{8pt plus 2pt}
+\captionsetup{skip=4pt}
+
+\lstset{basicstyle=\ttfamily\small,breaklines=true,frame=single,numbers=left,numberstyle=\tiny,xleftmargin=2em,language=Verilog}
+
+\newcommand{\Zq}{\mathbb{Z}_q}
+\newcommand{\etal}{\textit{et al.}}
+
+\title{\textbf{ML-KEM后量子密钥封装硬件IP核\\设计与验证}}
+\author{碳基生物\\[4pt] \small 团队编号：CICC1008439\\[8pt] \normalsize 龙芯中科杯·2026全国大学生集成电路创新创业大赛}
+\date{}
+
+\begin{document}
+
+% ================================================================
+%  封  面
+% ================================================================
+\begin{titlepage}
+\thispagestyle{empty}
+\begin{center}
+
+\vspace*{30pt}
+
+\includegraphics[width=0.45\textwidth]{logo_cicc.png}
+
+\vspace{36pt}
+
+{\fontsize{22pt}{28pt}\selectfont\bfseries 第十届}
+
+\vspace{4pt}
+
+{\fontsize{22pt}{28pt}\selectfont\bfseries 全国大学生集成电路创新创业大赛}
+
+\end{center}
+
+\vspace{80pt}
+
+\begin{flushleft}
+\fontsize{14pt}{22pt}\selectfont
+报告类型：\uline{\hfill MLKEM IP设计报告\hfill} \\[18pt]
+参赛杯赛：\uline{\hfill 龙芯中科杯\hfill} \\[18pt]
+作品名称：\uline{\hfill ML-KEM后量子密钥封装硬件IP核设计与验证\hfill} \\[18pt]
+队伍编号：\uline{\hfill CICC1008439\hfill} \\[18pt]
+团队名称：\uline{\hfill 碳基生物\hfill}
+\end{flushleft}
+
+\end{titlepage}
+
+\maketitle
+\tableofcontents
+\newpage
+
+% ================================================================
+\section{绪论}
+
+\subsection{设计背景}
+
+ML-KEM（Module-Lattice-based Key-Encapsulation Mechanism，FIPS 203 \cite{fips203}）是NIST于2024年8月发布的后量子密码标准，源自CRYSTALS-Kyber \cite{kyber}，用于替代RSA和ECC在密钥交换中的角色。其安全性建立在模格上的带误差学习问题（MLWE）之上，多项式环为$\Zq[x]/(x^{256}+1)$，素数模$q=3329$，多项式次数$n=256$。
+
+软件实现的ML-KEM在嵌入式处理器上存在显著性能瓶颈 \cite{dang2022,xing2023}——以ML-KEM-768为例，一轮完整的密钥生成、封装和解封装在通用CPU上需要数百万个时钟周期。本文设计的硬件IP核\texttt{mlkem\_top}旨在通过专用数据通路和计算资源时分复用，在FPGA平台上实现高性能、低面积的ML-KEM加速。
+
+\subsection{关键设计特性}
+
+本IP核在单一硬件模块内具有以下特性：
+
+\begin{enumerate}[label=(\arabic*)]
+    \item \textbf{运行时三等级支持}：通过$k\_i\in\{2,3,4\}$端口在运行时选择ML-KEM-512/768/1024安全等级，存储资源按$K_{MAX}=4$静态分配，无需重综合。
+    \item \textbf{全操作覆盖}：支持KeyGen（FIPS 203算法16）、Encaps（算法17）和Decaps（算法18，含FO变换隐式拒绝）。
+    \item \textbf{Keccak核跨阶段复用}：单一\texttt{keccak\_core}实例在G/H/J哈希、SampleNTT采样和CBD采样三个消费者之间时分复用，是面积优化的最大贡献因素。
+    \item \textbf{Decaps重加密路径复用}：D6步的K-PKE重加密直接复用整条Encaps流水线的全部FSM状态，避免重复实现加密数据通路。
+    \item \textbf{逐字节流式I/O}：公钥$ek$、私钥$dk$和密文$c$通过BRAM窗口逐字节装载与回读，免去超宽顶层总线。
+    \item \textbf{NIST KAT完全验证}：三种等级、三种操作全部逐字节比对NIST FIPS 203 KAT标准答案通过。
+\end{enumerate}
+
+\subsection{代码规模}
+
+RTL代码总计约5,517行（不含测试平台），其中\texttt{mlkem\_top.v}（顶层FSM集成+数据通路+三库存储管理）约2,320行，各叶子算子模块合计约3,197行。全部采用SystemVerilog编写，统一使用\texttt{valid/ready}流式握手接口。
+
+% ================================================================
+\section{IP模块规格}
+
+\subsection{算法参数}
+
+\texttt{mlkem\_top}的运行时参数由输入端口$k\_i$和$op\_i$在\texttt{start\_i}脉冲时刻锁存至内部寄存器$k\_r$和$op\_r$，后续所有数据通路宽度、存储子区间基地址和循环次数均由$k\_r$推导。表\ref{tab:params}列出三种安全等级的密钥和密文尺寸。
+
+\begin{table}[htbp]
+\centering
+\caption{运行时安全等级参数}
+\label{tab:params}
+\begin{tabular}{cccccccc}
+\toprule
+$k\_i$ & 方案 & $K$ & $\eta_1$ & $(d_u,d_v)$ & ek(B) & dk(B) & ct(B) \\
+\midrule
+2 & ML-KEM-512  & 2 & 3 & (10,4) & 800  & 1632 & 768  \\
+3 & ML-KEM-768  & 3 & 2 & (10,4) & 1184 & 2400 & 1088 \\
+4 & ML-KEM-1024 & 4 & 2 & (11,5) & 1568 & 3168 & 1568 \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+固定参数：模数$q=3329$、多项式次数$n=256$、$\eta_2=2$（所有等级）、共享密钥32字节。
+
+\subsection{顶层端口信号}
+
+\texttt{mlkem\_top}的端口按功能分为四组。表\ref{tab:ports}列出主要信号。
+
+\begin{table}[htbp]
+\centering
+\caption{mlkem\_top主要端口}
+\label{tab:ports}
+\small
+\begin{tabular}{lll}
+\toprule
+\textbf{信号} & \textbf{位宽} & \textbf{功能} \\
+\midrule
+clk, rst\_n         & 1, 1   & 时钟与低电平异步复位 \\
+k\_i, op\_i         & 3, 2   & 安全等级（2/3/4）与操作码（0=KG, 1=Enc, 2=Dec） \\
+d\_i, z\_i, msg\_i  & 256×3  & KeyGen种子$d$、隐式拒绝种子$z$、Encaps消息$m$ \\
+start\_i            & 1       & 启动脉冲，锁存$k\_i$和$op\_i$ \\
+busy\_o, done\_o    & 1, 1   & 运行标志与完成脉冲 \\
+ss\_o               & 256    & 共享密钥输出（done\_o时有效） \\
+ek\_in\_we/addr/byte & 1,11,8 & Encaps公钥流式预装载 \\
+dk\_in\_we/addr/byte & 1,12,8 & Decaps私钥流式预装载（自动路由至dkp\_bram/ek\_bram/寄存器） \\
+c\_in\_we/addr/byte  & 1,11,8 & Decaps密文流式预装载 \\
+dbg\_*              & 多种   & 调试抽头：系数、ek/dk/ct字节、中间哈希值 \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+握手协议分三阶段：\texttt{ST\_IDLE}状态下通过流式端口逐字节预装载数据；\texttt{start\_i}脉冲启动并锁存参数；\texttt{busy\_o}拉高期间执行计算；\texttt{done\_o}脉冲时\texttt{ss\_o}和BRAM产物有效。所有256-bit端口采用字节0在低位的约定。
+
+Decaps私钥预装载路径中，\texttt{dk\_in\_*}端口根据写入地址自动将字节流路由至不同目的地：地址$[0,384K)$写入\texttt{dkp\_bram}（$\hat{s}$编码），$[384K,768K+32)$写入\texttt{ek\_bram}（$\hat{t}$编码$\|\rho$），$[768K+32,768K+64)$和$[768K+64,768K+96)$分别写入$H(ek)$和$z$的寄存器。
+
+% ================================================================
+\section{总体架构设计}
+
+\subsection{设计原则}
+
+\texttt{mlkem\_top}的架构遵循三条核心原则。
+
+\textbf{原则一：存储按最大等级分配，运行时参数递推。} 多项式系数存储库以$K_{MAX}=4$（可容纳28个多项式，每个256系数）静态配置深度，$k\_r$仅影响读写地址生成逻辑中的基地址和循环边界。字节存储库（ek\_bram、dkp\_bram、ct\_bram）同样按最大密钥尺寸（1568/1536/1568字节）分配。运行时地址计算通过$k\_r$以纯组合逻辑递推完成，无需额外的运行时地址表或状态寄存器。
+
+\textbf{原则二：Keccak核全阶段时分复用。} Keccak-f[1600]置换是设计中面积最大的单一算子（OOC综合约5,300 LUT）。G/H/J哈希族、SampleNTT（SHAKE-128）和CBD（SHAKE-256）三个消费者处于互斥的FSM阶段，设计将所有Keccak请求复用至单一\texttt{keccak\_core}实例。输入侧通过\texttt{sel\_sha3/sel\_snt/sel\_cbd}多路选择器切换，输出侧将置换结果广播至全体消费者，仅当前激活阶段采样有效信号。
+
+\textbf{原则三：Decaps重加密完全复用Encaps流水线。} FIPS 203算法18的D6步需要以恢复的消息$m'$和随机种子$r'$重新执行一次K-PKE加密以产生参考密文$c'$。这一流程与算法17的Encaps操作的数据通路完全同构。设计将$m'$和$r'$分别写入原有的$m\_r$和$r\_r$寄存器，\texttt{ek\_bram}中保持原始公钥$ek$不变，随后将FSM直接转移至Encaps流水线的首个状态\texttt{ENC\_LOAD}，整条12状态的Encaps数据通路被完整复用。
+
+\subsection{模块层次结构}
+
+图\ref{fig:mlkem_modules}给出\texttt{mlkem\_top}的内部层次结构。设计分为三个逻辑层：控制调度层（FSM + 地址生成 + 数据通路复用）、算子计算层（7个已验证的叶子模块）和存储层（7个BRAM实例）。
+
+\begin{figure}[htbp]
+\centering
+\includegraphics[width=0.92\textwidth]{mlkem_modules.png}
+\caption{mlkem\_top内部三层模块结构}
+\label{fig:mlkem_modules}
+\end{figure}
+
+\subsection{顶层FSM调度}
+
+全部运算由5-bit状态机集中调度，从\texttt{ST\_IDLE}出发按$op\_r$分支为三条数据通路。图\ref{fig:fsm}给出状态转移图。
+
+\begin{figure}[htbp]
+\centering
+\includegraphics[width=0.92\textwidth]{fsm.png}
+\caption{mlkem\_top顶层FSM状态转移图}
+\label{fig:fsm}
+\end{figure}
+
+KeyGen路径对应FIPS 203算法16，共7个主状态（不含ST\_IDLE和ST\_DONE）。各状态间的数据传递通过多项式存储库完成：前序状态将结果写入BRAM，后续状态从BRAM读取。
+
+\begin{algorithm}[H]
+\caption{KeyGen数据通路（FIPS 203算法16）}
+\begin{algorithmic}[1]
+\State \textbf{ST\_G}：$G(d \| z) \rightarrow (\rho, \sigma)$，单块SHA3-512，约1,800周期
+\State \textbf{ST\_A}：对全部$K^2$个$(j,i)$索引执行SampleNTT$(\rho \| j \| i) \rightarrow \hat{A}[i][j]$，逐系数写入\texttt{bank\_a}
+\State \textbf{ST\_C}：CBD$_{\eta_1}(\sigma, i) \rightarrow s[i]$，CBD$_{\eta_1}(\sigma, K+i) \rightarrow e[i]$，写入\texttt{bank\_se}
+\State \textbf{ST\_N}：NTT$(s[i]) \rightarrow \hat{s}[i]$，NTT$(e[i]) \rightarrow \hat{e}[i]$，原位更新\texttt{bank\_se}
+\State \textbf{ST\_M}：$\hat{t}[i] = \hat{e}[i] + \sum_{j=0}^{K-1} \hat{A}[i][j] \circ \hat{s}[j]$，逐点乘通过\texttt{poly\_mul\_sync}，累加写入\texttt{bank\_t}
+\State \textbf{ST\_E}：byteEncode$_{12}(\hat{t}) \| \rho \rightarrow ek$，byteEncode$_{12}(\hat{s}) \rightarrow dk_{pke}$，写入\texttt{ek\_bram}和\texttt{dkp\_bram}
+\State \textbf{ST\_H}：SHA3-256$(ek) \rightarrow H(ek)$，多块吸收（块数$=\lceil(ek\_bytes+1)/136\rceil$）
+\end{algorithmic}
+\end{algorithm}
+
+Encaps路径对应FIPS 203算法17，共12个主状态。
+
+\begin{algorithm}[H]
+\caption{Encaps数据通路（FIPS 203算法17）}
+\begin{algorithmic}[1]
+\State \textbf{ST\_ENC\_H}：SHA3-256$(ek) \rightarrow H(ek)$
+\State \textbf{ST\_ENC\_G}：$G(m \| H(ek)) \rightarrow (K, r)$，单块SHA3-512
+\State \textbf{ST\_ENC\_A}：重新生成$\hat{A}^T$矩阵（SampleNTT，行列索引交换），写入\texttt{bank\_a}
+\State \textbf{ST\_ENC\_TDEC}：byteDecode$_{12}(ek) \rightarrow \hat{t}[i]$，逐系数解码至\texttt{bank\_a}
+\State \textbf{ST\_ENC\_C}：CBD$_{\eta_1}(r, 0) \rightarrow y$，CBD$_{\eta_2}(r, K) \rightarrow e_1$，CBD$_{\eta_2}(r, 2K) \rightarrow e_2$，写入\texttt{bank\_se}和\texttt{bank\_t}
+\State \textbf{ST\_ENC\_N}：NTT$(y) \rightarrow \hat{y}$，原位更新\texttt{bank\_se}
+\State \textbf{ST\_ENC\_U}：$\hat{A}^T \circ \hat{y}$逐点乘后INTT，再加$e_1$得$u$，写入\texttt{bank\_se}
+\State \textbf{ST\_ENC\_C1}：Compress$_{d_u}(u)$后byteEncode$_{d_u} \rightarrow c_1$字节，写入\texttt{ct\_bram}
+\State \textbf{ST\_ENC\_E2MV}：将$e_2$从\texttt{bank\_t}搬迁至\texttt{bank\_a}，为V步累加准备
+\State \textbf{ST\_ENC\_V}：$\hat{t} \circ \hat{y}$逐点乘后INTT，加$e_2$和Decompress$_1(m)$得$v$，写入\texttt{bank\_t}
+\State \textbf{ST\_ENC\_C2}：Compress$_{d_v}(v)$后byteEncode$_{d_v} \rightarrow c_2$字节，拼接至\texttt{ct\_bram}
+\State \textbf{输出}：$ss = K$
+\end{algorithmic}
+\end{algorithm}
+
+Decaps路径对应FIPS 203算法18，前5个主状态完成D1--D5步解密恢复，随后复用整条Encaps流水线（D6重加密），最后以一个比较状态（D7）完成隐式拒绝密钥选择。这是硬件设计中最复杂的控制流，也是Decaps流水线复用创新的集中体现。
+
+\begin{algorithm}[H]
+\caption{Decaps数据通路（FIPS 203算法18，含流水线复用）}
+\begin{algorithmic}[1]
+\State \textbf{ST\_DEC\_DECOMP}（D1）：byteDecode$_{d_u}(c_1) \rightarrow$ Decompress$_{d_u} \rightarrow u'$，byteDecode$_{d_v}(c_2) \rightarrow$ Decompress$_{d_v} \rightarrow v'$，写入\texttt{bank\_se}和\texttt{bank\_a}
+\State \textbf{ST\_DEC\_SDEC}（D2）：byteDecode$_{12}(dk_{pke}) \rightarrow \hat{s}[i]$，逐系数解码至\texttt{bank\_a}
+\State \textbf{ST\_DEC\_NTT}（D2续）：NTT$(u'[i]) \rightarrow \hat{u}[i]$，原位更新\texttt{bank\_se}
+\State \textbf{ST\_DEC\_W}（D3）：$\hat{s}[j] \circ \hat{u}[j]$逐点乘后INTT，$v'$减去累加和得$w$，写入\texttt{bank\_t}
+\State \textbf{ST\_DEC\_MENC}（D4）：Compress$_1(w)$后byteEncode$_1 \rightarrow m'$
+\State \textbf{ST\_DEC\_G}（D5）：$G(m' \| H(ek)) \rightarrow (K', r')$
+\State \textbf{ST\_DEC\_J}（D5续）：$J(z \| c) \rightarrow \bar{K}$（隐式拒绝备用密钥）
+\State \textbf{流水线复用}（D6）：将$m'$写入$m\_r$、$r'$写入$r\_r$，跳转至\textbf{ST\_ENC\_LOAD}，完整复用Encaps路径全部12个状态，产生参考密文$c'$（存入\texttt{ct\_bram}）
+\State \textbf{ST\_DEC\_CMP}（D7）：逐字节比较$c'$（\texttt{ct\_bram}）与原始$c$（\texttt{c\_in\_bram}），常量时间无早退；$c' = c$时输出$K'$，否则输出$\bar{K}$
+\end{algorithmic}
+\end{algorithm}
+
+
+% ================================================================
+\section{各功能模块数据通路与控制逻辑}
+
+\subsection{Keccak-f[1600]置换核与哈希族}
+
+\texttt{keccak\_core}模块实现24轮连续Keccak-f[1600]置换，内部结构为简单的迭代流水线：1600-bit状态寄存器$\rightarrow$组合\texttt{keccak\_round}$\rightarrow$写回状态寄存器。\texttt{keccak\_round}为纯组合逻辑，实现Keccak \cite{fips202} 的$\theta/\rho/\pi/\chi/\iota$五步映射，其中$\theta$步的5路XOR归约和$\chi$步的非线性变换是面积消耗的主要来源。
+
+\begin{figure}[htbp]
+\centering
+\includegraphics[width=0.92\textwidth]{keccak_core.png}
+\caption{Keccak-f[1600]核数据通路与共享机制}
+\label{fig:keccak_core}
+\end{figure}
+
+\texttt{sha3\_top\_shared}模块在\texttt{keccak\_core}之上封装了SHA3/SHAKE协议层，包括1088-bit速率域/512-bit容量域的填充、domain separator拼接（SHA3末尾\texttt{01}、SHAKE末尾\texttt{1111}）以及多块顺序吸收的状态管理。支持三种模式：SHA3-512（$G$函数，单块64字节吸收）、SHA3-256（$H$函数，多块吸收，块数$=\lceil(ek\_bytes+1)/136\rceil$）和SHAKE-256（$J$函数和PRF派生）。
+
+\textbf{共享Keccak的复用机制}通过两级多路选择实现。输入侧：三个消费者的1600-bit状态和\texttt{valid}信号经\texttt{sel\_*}信号选择后送入\texttt{keccak\_core}；选择信号由FSM状态直接推导（例如\texttt{sel\_snt = (st==ST\_A || st==ST\_ENC\_A)}）。输出侧：\texttt{keccak\_core}的置换结果和\texttt{valid\_o}广播至所有消费者，各消费者内部仅在自己激活的上下文中采样，天然实现了无冲突分派。此复用方案将Keccak的硬件开销从三份实例（约16,000 LUT）降至一份（约5,300 LUT）。
+
+\subsection{NTT核}
+
+\texttt{ntt\_core}模块实现256点前向/逆向数论变换，采用双蝶形流水线加4路无冲突Banked BRAM的架构。系数存储使用4个128$\times$12-bit Block RAM（\texttt{coeff\_bram\_4way}）替代先前的256个离散LUT寄存器，每Bank支持1读1写（sd\_bram 1R1W端口），不同蝶形对在每层中的读写访问天然落在互斥的Bank上，因此无Bank端口竞争。图\ref{fig:ntt_core}给出数据通路与控制状态机。
+
+\begin{figure}[htbp]
+\centering
+\includegraphics[width=0.92\textwidth]{ntt_core.png}
+\label{fig:ntt_core}
+\end{figure}
+
+读-算-写三级流水线的节拍如下：第t周期通过地址生成器给出两个蝶形对的读地址（从系数索引j推导），BRAM在1拍延迟后于t+1周期返回数据；两个独立的\texttt{butterfly\_unit\_pipe}（u\_bf0和u\_bf1）各自接收一对系数并送入8级流水Barrett蝶形，于t+9周期产生结果；写回逻辑通过8级延迟线将写地址与蝶形输出对齐后写入对应Bank。由于每个Bank每周期只处理1次读和1次写，整个NTT以4 coeff/cycle的吞吐率完成7层蝶形迭代。
+
+读和写回路径均以循环迭代方式处理每一步，BRAM的同步读延迟（1拍）被融入流水线的前端而不增加额外的等待周期。每层蝶形内的所有系数对在发射完毕后，流水线排空等待约8拍。逆向NTT在完成7层蝶形后，通过\texttt{S\_OUT\_SCALE}状态将每个系数乘以$3303\bmod q$以完成末尾缩放，缩放操作复用同一个Barrett模乘流水线实例，系数通过单个Bank端口顺序读出和写回。
+
+\texttt{zeta\_rom}存储128个12-bit旋转因子，位反转索引，ROM综合为LUT。
+
+\subsection{多项式乘法与Barrett模乘}
+
+\texttt{poly\_mul\_sync}实现NTT域两个多项式的逐点乘法，即对128个系数对$(a_0,a_1)$和$(b_0,b_1)$按$c_0=a_0b_0+a_1b_1\zeta\bmod q$和$c_1=a_0b_1+a_1b_0\bmod q$计算。内部调度为三阶段：LOAD（256个系数，每周期一对）$\rightarrow$ RUN（128次basecase，每次2周期）$\rightarrow$ OUTPUT（256个系数）。
+
+\texttt{basecase\_mul}内部数据通路包含5个\texttt{barrett\_mul\_pipe}流水线实例。$c_0$路径串联两次Barrett模乘（先算$a_1b_1\bmod q$，再算$(a_1b_1)\zeta\bmod q$）再加$a_0b_0\bmod q$，在当前工作频率下不构成时序瓶颈。
+
+\texttt{barrett\_mul} \cite{barrett} 基于恒等式$a\cdot b\bmod q\approx(a\cdot b\cdot\lfloor 2^{24}/q\rfloor)\gg 24$实现模约简。对于$q=3329$，$\lfloor 2^{24}/3329\rfloor=5039$。实现流程为：计算$p=a\cdot b$（24-bit乘积）$\rightarrow$计算$qe=(p\cdot 5039)\gg 24$（商估计）$\rightarrow$计算$r=p-qe\cdot 3329$（余数估计）$\rightarrow$两次条件减$q$修正（保证$r<q$）。该模块已通过流水线化改造支持高频率工作。
+
+\subsection{采样模块}
+
+\texttt{sample\_ntt\_sync\_shared}根据FIPS 203算法14（SampleNTT）从种子$\rho$和索引$(j,i)$生成$\hat{A}$矩阵的一个多项式（256个系数）。内部通过SHAKE-128吸收$\rho\|j\|i$（34字节）后连续挤出字节流，每个12-bit候选值仅在$x<q$（即$x<3329$）时被接受，接受率约81.3\%。逐系数通过\texttt{valid/ready}握手输出，直接写入\texttt{bank\_a}。
+
+\texttt{sample\_cbd\_sync\_shared}实现中心二项分布CBD$_\eta$采样。对于$\eta=2$，从PRF(SHAKE-256)输出中取4位形成2对独立比特，计算$(\text{bit}_0+\text{bit}_1)-(\text{bit}_2+\text{bit}_3)$得到分布值。对于$\eta=3$（仅ML-KEM-512），取6位形成3对。模块通过\texttt{valid/ready}握手逐系数输出，直接写入\texttt{bank\_se}或\texttt{bank\_t}。
+
+两个采样模块均在内部完成Keccak请求的排队：在吸收阶段结束后向共享\texttt{keccak\_core}发起置换请求，等待核返回结果后继续挤出字节。由于采样模块与SHA3族消费者处于互斥的FSM阶段，对共享核的竞争不存在。
+
+\subsection{压缩与解压缩}
+
+\texttt{comp\_decomp\_sync}实现Compress$_d$和Decompress$_d$函数。Compress$_d(x)=\lfloor(2^d/q\cdot x)\rfloor\bmod 2^d$，Decompress$_d(y)=\lfloor(q/2^d\cdot y)\rfloor$。实现将除数$q$替换为Barrett风格的$5039\cdot 2^{-24}$近似，避免组合除法器。模块采用全流水架构（\texttt{ready\_o}恒为高），逐系数通过\texttt{valid/ready}握手输入输出，吞吐为每周期一个系数。
+
+\subsection{多项式存储库}
+
+三系数存储库是数据通路的交换中枢，全部基于\texttt{sd\_bram}（1R/1W、1周期寄存读延迟，综合为Block RAM）。表\ref{tab:banks}列出配置和内容。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{多项式系数存储库配置}
+\label{tab:banks}
+\begin{tabular}{cccp{5.5cm}}
+\toprule
+\textbf{实例} & \textbf{尺寸} & \textbf{物理BRAM} & \textbf{存储内容} \\
+\midrule
+bank\_a  & 12-bit $\times$ 4096 & 1 RAMB36 + 1 RAMB18 & $\hat{A}[i][j]$矩阵（slot 0至$K^2-1$） \\
+bank\_se & 12-bit $\times$ 2048 & 1 $\times$ RAMB36 & $\hat{s}/\hat{e}$（KeyGen）、$\hat{y}$（Encaps）、$\hat{u}$（Decaps） \\
+bank\_t  & 12-bit $\times$ 1024 & 1 $\times$ RAMB18 & $\hat{t}$、MAC累加和、$v$、$w$ \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+槽位布局为：$\hat{A}$占用slot 0至$K^2-1$（基地址0），$\hat{s}$占用slot $K^2$至$K^2+K-1$，$\hat{e}$占用slot $K^2+K$至$K^2+2K-1$，$\hat{t}$占用slot $K^2+2K$至$K^2+3K-1$。所有槽位寻址在运行时由$k\_r$递推，例如$\hat{s}$基地址$\texttt{slot\_s\_rt}=K^2$。
+
+库的读写端口在多个FSM状态之间分时复用。\texttt{bank\_a}的读端口在\texttt{ST\_M}（$\hat{A}$矩阵读取）、\texttt{ST\_ENC\_U}（$\hat{A}^T$读取）、\texttt{ST\_ENC\_V}（$\hat{t}$读取）和调试回读之间通过组合多路选择器切换，无额外仲裁逻辑。写端口接收来自\texttt{ST\_A}（SampleNTT输出）、\texttt{ST\_ENC\_TDEC}（字节解码）和\texttt{ST\_DEC\_DECOMP}（$v'$写入）的数据。
+
+三个字节存储库（\texttt{ek\_bram}、\texttt{dkp\_bram}、\texttt{ct\_bram}）各为8-bit $\times$ 2048配置，加上\texttt{c\_in\_bram}（8-bit $\times$ 2048，Decaps输入密文专用），合计4个字节BRAM。\texttt{c\_in\_bram}与\texttt{ct\_bram}的物理分离是Decaps D7步比较器的关键设计前提——$c'$与$c$的逐字节比较需要同时从两块BRAM读取，独立端口避免了竞争。
+
+% ================================================================
+\section{验证方案}
+
+\subsection{分层验证策略}
+
+验证分为四个层级：
+
+\begin{enumerate}[label=(\arabic*)]
+    \item \textbf{叶子模块级}：独立验证\texttt{keccak\_core}、\texttt{ntt\_core}、\texttt{sample\_ntt\_sync}、\texttt{sample\_cbd\_sync}、\texttt{poly\_mul\_sync}、\texttt{comp\_decomp\_sync}共6个算子模块与Python参考模型的一致性。每个模块通过其\texttt{TB/}子目录下的专用测试平台验证。
+    \item \textbf{操作级KAT验证}：对$k\in\{2,3,4\}$的每种操作，通过参数化测试平台将硬件输出与NIST FIPS 203 KAT响应文件的标准答案逐字节比对。Encaps和Decaps测试覆盖正常路径和隐式拒绝路径（损坏密文$ct\_n$）。
+    \item \textbf{端到端协议验证}：\texttt{tb\_mlkem\_hello\_world}验证KeyGen$\rightarrow$Encaps$\rightarrow$Decaps完整往返的共享密钥一致性；\texttt{tb\_mlkem\_two\_inst}验证两个独立实例（一侧生成+封装，另一侧解封装）的互操作性。
+    \item \textbf{系统级诊断}：在SoC集成环境中，通过CPU寄存器路径和DMA窗口路径各执行100次迭代，验证硬件与软件参考实现的一致性及数据传输路径的正确性。
+\end{enumerate}
+
+\subsection{测试平台与KAT测试向量}
+
+表\ref{tab:tbs}列出全部操作级和系统级测试平台。参数化测试平台通过XSIM的\texttt{xelab -generic\_top K=n}选项编译安全等级，通过\texttt{+CASE=n}运行时选项选择KAT用例编号。
+
+\begin{table}[htbp]
+\centering
+\caption{测试平台清单}
+\label{tab:tbs}
+\begin{tabular}{lccc}
+\toprule
+\textbf{测试平台} & \textbf{覆盖操作} & \textbf{安全等级} & \textbf{测试向量来源} \\
+\midrule
+tb\_mlkem\_kg\_katK    & KeyGen & K=2/3/4 & NIST KAT 1000用例/级 \\
+tb\_mlkem\_enc\_katK   & Encaps & K=2/3/4 & NIST KAT 1000用例/级 \\
+tb\_mlkem\_dec\_katK   & Decaps & K=2/3/4 & NIST KAT 1000用例/级 + ct\_n \\
+tb\_mlkem\_hello\_world & 全流程  & K=3      & 固定测试向量 \\
+tb\_mlkem\_two\_inst    & 双实例  & K=3      & 固定测试向量 \\
+mlkem\_test (SoC)       & CPU/DMA & K=2/3/4 & KAT count=0确定性输入 \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+KAT测试向量来自NIST FIPS 203的KAT响应文件，由Python脚本解析为每用例独立的hex文件。每个KAT用例包含种子$d$、$z$、$m$以及期望的$ek$、$dk$、$c$和共享密钥。Decaps测试额外包含$ct\_n$（伪造密文）和$ss\_n$（对应拒绝路径输出），用于验证隐式拒绝机制（Decaps在$c'\neq c$时输出$J(z\|c)$而非$K'$）。
+
+Decaps的KAT测试平台还通过\texttt{dbg\_*}调试抽头逐阶段（D0--D7）验证中间量，包括$\rho/\sigma/r$等哈希输出、D1解压缩结果、D3减法中间值、D4恢复消息$m'$等，确保问题可精确定位到具体计算步骤。
+
+\subsection{系统级诊断测试}
+
+SoC诊断程序\texttt{mlkem\_test}实现三条独立测试路径：
+
+\textbf{软件参考路径}在33 MHz Loongson CPU上运行纯C语言ML-KEM实现，记录各阶段周期数作为加速比的基准，并验证结果自洽性与KAT标准答案一致性。
+
+\textbf{CPU寄存器路径}通过AXI寄存器接口直接控制IP核：写入CONFIG配置、通过D[0..7]/Z[0..7]写入种子、通过PRE\_SEL/ADR/DAT序列逐字节预装载公钥/私钥/密文、写CTRL.start启动、轮询STATUS.done、通过RDB\_SEL/ADR/DAT读回结果。该路径验证了IP核的AXI从机接口逻辑和寄存器级控制流的正确性。
+
+\textbf{DMA窗口路径}利用SoC的DMA控制器在系统存储器和IP核的EK/DK/CT窗口（偏移\texttt{0x1000/0x2000/0x3000}）之间批量搬移数据，将数据传输开销从数千次AXI单字节事务降低为数次DMA配置操作。该路径验证了IP核存储器窗口与DMA控制器之间的数据搬移正确性，以及批量传输模式相对于逐字节读写的效率提升。
+
+每种路径对每个安全等级执行1000次迭代，记录自洽性（\texttt{ss\_enc == ss\_dec}）和KAT标准答案一致性。
+
+% ================================================================
+\section{实现结果与测试数据}
+
+\subsection{FPGA资源利用}
+
+ML-KEM IP核在Xilinx Artix-7 \cite{artix7} \texttt{xc7a200tfbg676-1}上完成布局布线后的独立资源利用如表\ref{tab:mlkem_util}所示。数据来自Vivado \cite{vivado} 2019.2布局布线后报告。
+
+\begin{table}[htbp]
+\centering
+\caption{mlkem\_top布局布线后资源利用}
+\label{tab:mlkem_util}
+\begin{tabular}{lccc}
+\toprule
+\textbf{资源} & \textbf{已用} & \textbf{可用} & \textbf{利用率} \\
+\midrule
+Slice LUTs   & 21,697 & 133,800 & 16.2\% \\
+Slice FFs    & 15,826 & 267,600 &  5.9\% \\
+Block RAM Tile &  9.0  &     365 &  2.5\% \\
+~~RAMB36E1      &  2    &     365 &  0.5\% \\
+~~RAMB18E1      & 14    &     730 &  1.9\% \\
+DSP48E1      &      0 &     740 &  0.0\% \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+DSP使用量为零体现了设计的主动约束——所有乘法均强制映射至LUT和CARRY4逻辑，不消耗任何DSP48E1资源。ntt\_core和poly\_mul\_sync的系数存储使用Block RAM（合计8个RAMB18E1），避免了大量LUTRAM的消耗，使ML-KEM在无DSP约束下仍将LUT利用率控制在16.2\%。
+
+表\ref{tab:modules_util}给出布局布线后的子模块级资源分解。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{mlkem\_top主要子模块资源利用}
+\label{tab:modules_util}
+\begin{tabular}{lcccr}
+\toprule
+\textbf{子模块} & \textbf{LUT} & \textbf{FF} & \textbf{BRAM} & \textbf{DSP} \\
+\midrule
+keccak\_core (Keccak-f[1600]置换核) & 5,258 & 1,618 & 0 & 0 \\
+sample\_cbd\_sync\_shared           & 2,739 & 3,186 & 0 & 0 \\
+sample\_ntt\_sync\_shared           & 2,109 & 1,669 & 0 & 0 \\
+poly\_mul\_sync (含basecase\_mul)   & 2,058 &   584 & 4 RAMB18 & 0 \\
+sha3\_top\_shared (哈希族封装)      & 1,955 & 2,378 & 0 & 0 \\
+ntt\_core (蝶形流水线+系数存储)    & 1,900 & 1,062 & 4 RAMB18 & 0 \\
+comp\_decomp\_sync                  &   620 &   319 & 0 & 0 \\
+系数存储BRAM（bank\_a/se/t）        &   974 &     0 & 2 RAMB36 + 2 RAMB18 & 0 \\
+字节BRAM（ek/dkp/ct/c\_in）         & 2,600 &     0 & 4 RAMB18 & 0 \\
+其它（FSM/多路复用/顶层连线）       & 1,484 & 5,010 & 0 & 0 \\
+\midrule
+\textbf{合计} & \textbf{21,697} & \textbf{15,826} & \textbf{2 RAMB36 + 14 RAMB18} & \textbf{0} \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+Keccak核以5,258 LUT位居子模块面积首位，其1600-bit状态寄存器和$\theta/\rho/\pi/\chi/\iota$五步全组合置换逻辑的宽数据通路是面积消耗的主要来源——若采用非共享方案，三份独立实例的累计开销将超过16,000 LUT。ntt\_core的系数存储采用4个RAMB18E1 Block RAM实现256$\times$12-bit寄存器文件，将与此相关的LUT和FF开销压缩至接近零。poly\_mul\_sync同样使用4个RAMB18E1进行数据缓冲。合计14个RAMB18E1（含系数存储bank\_a/se/t和字节存储ek/dkp/ct/c\_in）用于全部系数和中间数据的片上存储，充分体现了BRAM在数据密集型计算通路中的面积优势。
+
+\subsection{时序性能}\label{sec:timing}
+
+表\ref{tab:timing}列出布局布线后的时序收敛情况。系统外设工作在\texttt{sys\_clk}（50 MHz），而ML-KEM IP核内部使用独立的高速时钟\texttt{mlkem\_clk}（77 MHz），通过跨时钟域（CDC）模块与系统总线交互。
+
+\begin{table}[htbp]
+\centering
+\caption{布局布线后时序收敛结果}
+\label{tab:timing}
+\begin{tabular}{lccr}
+\toprule
+\textbf{时钟域} & \textbf{周期} & \textbf{Setup WNS} & \textbf{违例端点} \\
+\midrule
+cpu\_clk & 30 ns (33 MHz) & +2.716 ns & 0 / 17,197 \\
+sys\_clk & 20 ns (50 MHz) & +0.146 ns & 0 / 69,558 \\
+mlkem\_clk & 12.98 ns (77 MHz) & +0.240 ns & 0 / 25,432 \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+ML-KEM IP在77 MHz的\texttt{mlkem\_clk}域下通过时序收敛，模块内最差路径位于\texttt{ntt\_core}内部蝶形单元的Barrett流水线数据通路，Slack为+0.240 ns。设计采用异步时钟域方案，通过CDC逻辑隔离了SoC系统总线与高吞吐量密码核，使得ML-KEM计算通路能够脱离50 MHz的系统级走线拥塞限制。尽管CDC模块引入了少量的跨域同步延迟与硬件开销，但这使得ML-KEM能够充分利用自身的时序裕量，最大化计算性能。
+
+\subsection{功耗分析}
+
+布局布线后功耗估计如表\ref{tab:power}所示。ML-KEM IP核的片上功耗约0.115 W（动态），占SoC总动态功耗（0.409 W）的28.1\%。
+
+\begin{table}[htbp]
+\centering
+\caption{ML-KEM IP功耗估计（布局布线后，典型工艺角）}
+\label{tab:power}
+\begin{tabular}{lcc}
+\toprule
+\textbf{功耗来源} & \textbf{功率(W)} & \textbf{说明} \\
+\midrule
+Slice Logic & 0.046 & LUT翻转 + FF时钟功耗 \\
+Signals     & 0.052 & 互联线翻转功耗 \\
+Block RAM   & 0.017 & 14个RAMB18 + 2个RAMB36的读写功耗 \\
+\midrule
+\textbf{ML-KEM合计} & \textbf{0.115} & 占SoC动态功耗28.1\% \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+\subsection{功能验证结果}
+
+\subsubsection{KAT逐字节比对}
+
+表\ref{tab:kat_results}汇总全部安全等级和操作的KAT验证结果。
+
+\begin{table}[htbp]
+\centering
+\caption{KAT验证结果汇总}
+\label{tab:kat_results}
+\begin{tabular}{lccccc}
+\toprule
+\textbf{操作} & \textbf{K=2} & \textbf{K=3} & \textbf{K=4} & \textbf{用例数} & \textbf{通过率} \\
+\midrule
+KeyGen（算法16）      & PASS & PASS & PASS & 1000/级 & 100\% \\
+Encaps（算法17）      & PASS & PASS & PASS & 1000/级 & 100\% \\
+Decaps正常路径（算法18）& PASS & PASS & PASS & 1000/级 & 100\% \\
+Decaps隐式拒绝路径    & PASS & PASS & PASS & 100/级 & 100\% \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+全部KAT测试用例均逐字节比对NIST标准答案通过，无任何字节级偏差。Decaps隐式拒绝路径（$c'_n\neq c$）验证了FO变换中常量时间比较器和$J(z\|c)$拒绝密钥生成逻辑的正确性。
+
+\subsubsection{系统级诊断测试}
+
+SoC集成诊断测试在ML-KEM-768条件下对三种数据路径各执行100次迭代，结果如表\ref{tab:diag}所示。
+
+\begin{table}[htbp]
+\centering
+\caption{系统级诊断测试结果（ML-KEM-768，100次迭代）}
+\label{tab:diag}
+\begin{tabular}{lccc}
+\toprule
+\textbf{测试路径} & \textbf{失败次数} & \textbf{自洽性通过率} & \textbf{KAT通过率} \\
+\midrule
+SW（纯软件参考）  & 0 & 100\% & 100\% \\
+CPU寄存器路径     & 0 & 100\% & 100\% \\
+DMA窗口路径       & 0 & 100\% & 100\% \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+\subsection{性能分析}
+
+表\ref{tab:perf}列出三种安全等级下软件参考、CPU寄存器路径和DMA窗口路径完成一轮完整往返（KeyGen+Encaps+Decaps）的平均时钟周期数及加速比。数据来自SoC实际运行的100次迭代统计。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{三路径完整往返性能对比（100次迭代平均值）}
+\label{tab:perf}
+\begin{tabular}{lrrrrrr}
+\toprule
+\textbf{安全等级} & \textbf{SW} & \textbf{CPU} & \textbf{DMA} & \textbf{CPU加速比} & \textbf{DMA加速比} & \textbf{DMA/CPU} \\
+\midrule
+ML-KEM-512  (k=2) & 2,594,034 & 200,471 & 52,995 & 12.94$\times$ & 48.95$\times$ & 3.78$\times$ \\
+ML-KEM-768  (k=3) & 4,065,123 & 296,193 & 80,648 & 13.72$\times$ & 50.41$\times$ & 3.67$\times$ \\
+ML-KEM-1024 (k=4) & 6,041,204 & 404,476 & 113,273 & 14.94$\times$ & 53.33$\times$ & 3.57$\times$ \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+从数据中可以得出以下结论。CPU寄存器路径相对于纯软件实现了12.94$\times$至14.94$\times$的加速比，加速比随安全等级$k$增大而略有提升——硬件加速器的固定流水线启动开销占比随总计算量的增大而降低。
+
+DMA路径相对于CPU寄存器路径额外贡献了约3.6--3.8$\times$的效率提升。DMA批量传输将公钥、私钥和密文的数千次单字节AXI事务合并为数次Burst传输，大幅降低了总线协议开销。以ML-KEM-512为例，DMA路径的52,995周期单次往返在33 MHz CPU时钟下折算约为1.6 ms，满足了真实SoC环境下的毫秒级响应需求。
+
+\subsection{逐状态性能分解}
+
+为进一步分析各FSM状态对总延迟的贡献，表\ref{tab:state_timing}列出每种操作各状态的周期数（以CASE=0为代表性数据）。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{KeyGen逐状态性能分解（CASE=0）}
+\label{tab:state_timing}
+\begin{tabular}{lrrr}
+\toprule
+\textbf{状态} & \textbf{K=2} & \textbf{K=3} & \textbf{K=4} \\
+\midrule
+ST\_G（$G(d\|K)$）        &    27 &    27 &    27 \\
+ST\_A（SampleNTT生成Â）   & 3,251 & 7,233 & 12,825 \\
+ST\_C（CBD采样$s/e$）     & 1,229 & 1,693 & 2,257 \\
+ST\_N（前向NTT）          & 4,172 & 6,258 & 8,344 \\
+ST\_M（矩阵向量乘累加）   & 2,096 & 4,716 & 8,384 \\
+ST\_E（byteEncode编码）   & 2,081 & 3,105 & 4,129 \\
+ST\_H（$H(ek)$哈希）      &   979 & 1,468 & 1,957 \\
+\midrule
+\textbf{总计}              & \textbf{13,835} & \textbf{24,500} & \textbf{37,923} \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+KeyGen各状态的周期数呈现出与$K$值的清晰依赖关系。ST\_A（SampleNTT）和ST\_M（矩阵向量乘累加）是最耗时的两个状态，二者合计占总周期的48.0\%（K=2）至65.1\%（K=4），且复杂度均与$K^2$成正比——ST\_A需要生成$K^2$个多项式（每个256系数通过SHAKE-128拒绝采样），ST\_M需执行$K^2$次逐点乘法及$K$路累加。ST\_G（单块SHA3-512）的周期数恒为27，与$K$无关。ST\_N（NTT）在K=3时为6,258周期、K=4时为8,344周期（对$2K$个多项式各执行一次256点NTT），总开销随$K$线性增长。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{Encaps逐状态性能分解（CASE=0）}
+\label{tab:state_enc}
+\begin{tabular}{lrrr}
+\toprule
+\textbf{状态} & \textbf{K=2} & \textbf{K=3} & \textbf{K=4} \\
+\midrule
+ENC\_LOAD（数据就绪）       &    34 &    34 &    34 \\
+ENC\_H（$H(ek)$）          &   980 & 1,469 & 1,958 \\
+ENC\_G（$G(m\|H(ek))$）    &    26 &    26 &    26 \\
+ENC\_A（重新生成Â$^T$）    & 3,251 & 7,233 & 12,825 \\
+ENC\_TDEC（byteDecode t̂）  & 1,281 & 1,921 & 2,561 \\
+ENC\_C（CBD采样$y/e_1/e_2$）& 1,461 & 1,975 & 2,539 \\
+ENC\_N（NTT(y)）           & 2,086 & 3,129 & 4,172 \\
+ENC\_U（$u$向量计算）      & 4,707 & 8,632 & 13,605 \\
+ENC\_C1（压缩编码$c_1$）   & 1,035 & 1,547 & 2,059 \\
+ENC\_E2MV（$e_2$搬迁）     &   258 &   258 &   258 \\
+ENC\_V（$v$向量计算）      & 2,354 & 2,878 & 3,402 \\
+ENC\_C2（压缩编码$c_2$）   &   522 &   522 &   522 \\
+\midrule
+\textbf{总计}               & \textbf{17,995} & \textbf{29,624} & \textbf{43,961} \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+Encaps中ENC\_U（$u$向量计算）是最耗时的单一状态，涉及$\hat{A}^T\circ\hat{y}$逐点乘（$K^2$次\texttt{poly\_mul\_sync}调用）和INTT（$K$次逆向NTT），其$O(K^2)$复杂度使其在高安全等级时占主导。ENC\_C1（压缩$c_1$）对$K$个多项式逐系数执行Compress$_{d_u}$和byteEncode，总周期数与$K$和$d_u$成正比。ENC\_C2（压缩$c_2$）仅处理单个多项式的Compress$_{d_v}$，周期数恒为522，与$K$无关。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{Decaps逐状态性能分解（CASE=0）}
+\label{tab:state_dec}
+\begin{tabular}{lrrr}
+\toprule
+\textbf{状态} & \textbf{K=2} & \textbf{K=3} & \textbf{K=4} \\
+\midrule
+DEC\_LOAD（数据就绪）        &     2 &     2 &     2 \\
+DEC\_DECOMP（D1解压缩）     & 8,449 & 11,393 & 14,657 \\
+DEC\_SDEC（D2解码ŝ）        & 1,281 & 1,921 & 2,561 \\
+DEC\_NTT（D2 NTT(u')）      & 2,086 & 3,129 & 4,172 \\
+DEC\_W（D3计算$w$）         & 2,354 & 2,878 & 3,402 \\
+DEC\_MENC（D4恢复$m'$）     &   513 &   513 &   513 \\
+DEC\_G（D5 $G(m'\|h)$）     &    26 &    26 &    26 \\
+\multicolumn{4}{c}{\textbf{———— D6 流水线复用（＝Encaps全部状态） ————}} \\
+ENC\_LOAD--ENC\_C2（重加密） & 17,995 & 29,624 & 43,961 \\
+DEC\_CMP（D7常量时间比较）  & 1,537 & 2,177 & 3,137 \\
+\midrule
+\textbf{总计}              & \textbf{33,237} & \textbf{50,168} & \textbf{70,447} \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+Decaps的性能数据直接验证了设计原则三（流水线复用）的实际效果。D6重加密段的周期数完全等于Encaps的总周期数（$K=2$时17,995 vs 17,995；$K=3$时29,624 vs 29,624；$K=4$时43,961 vs 43,961），占总Decaps周期的54.1\%（K=2）至62.4\%（K=4）。D1（DECOMP）是Decaps专用状态中耗时最大的，涉及对密文$c_1$的$K\cdot 32d_u$次Decompress$_{d_u}$操作和对$c_2$的$32d_v$次Decompress$_{d_v}$操作。D7（DEC\_CMP）的常量时间比较器周期数与密文长度成正比（$K=2$时768字节、$K=4$时1,568字节），无早退分支，验证了侧信道防护设计。Decaps Accept与Reject路径的总周期数完全相等，进一步确认了隐式拒绝的常量时间特性。
+
+\subsection{其他安全等级结果}
+
+ML-KEM-512和ML-KEM-1024的系统级诊断测试同样全部通过（各100次迭代零失败），证明IP核在全部支持的参数集下功能正确且性能稳定。
+
+% ================================================================
+\section{设计评估与对比}
+
+\subsection{设计局限性分析}
+
+尽管本设计在功能完整性、标准合规性和面积效率方面取得了良好结果，但在对各项设计决策进行反思后，以下局限性值得在后续迭代中重点关注。
+
+\textbf{串行FSM架构的性能上限。} 当前30状态硬连线FSM严格按照算法步骤串行执行，各状态之间无任何重叠。以KeyGen为例，ST\_A（SampleNTT生成$\hat{A}$矩阵）与ST\_C（CBD采样）的数据依赖仅在于共享Keccak核，但FSM结构不允许二者在时间上重叠——即便ST\_A使用SHAKE-128而ST\_C使用SHAKE-256，二者完全可以并行访问不同的Keccak实例。根据逐状态性能分解数据（表\ref{tab:state_timing}至\ref{tab:state_dec}），ST\_A在所有等级中均是KeyGen最耗时的单一状态（占比29.2\%--39.4\%），若能与CBD或NTT并行调度，KeyGen总延迟可降低15\%--20\%。
+
+\textbf{双蝶形NTT的吞吐瓶颈。} 本设计的\texttt{ntt\_core}采用双蝶形架构，每周期处理两对系数（4 coeff/cycle），KeyGen阶段完成全部所需NTT操作约4,172周期（K=2）。相比之下，HOPE-MLKEM通过可配置的多BU架构（NBU=1至4）实现2至8 coeff/cycle的吞吐率。在NBU=4配置下，单次NTT仅需约140周期。这一差距是系数级并行度的结构性差异所致——HOPE NB=4可同时处理8 coeff/cycle，而本设计为4 coeff/cycle。
+
+\textbf{DSP零使用的面积代价。} 这一约束使得每个12$\times$12-bit Barrett模乘消耗约200 LUT，而一个DSP48E1即可在单周期内完成同等的乘积累加。ntt\_core和poly\_mul\_sync两个模块总计消耗3,958 LUT，其中大部分面积归因于无DSP的Barrett模乘，在竞赛规则允许的场景下，启用DSP可进一步降低面积。
+
+\textbf{FSM控制逻辑的资源密度。} 硬连线FSM的30个状态各自携带独立的状态转移判据和数十路数据通路多路选择信号。HOPE-MLKEM采用微程序指令控制器，20-bit指令字在移位寄存器中逐拍推进，控制器开销更低。作为对比，本设计FSM及顶层连线归入"其它"类目的开销为1,484 LUT和5,010 FF。
+
+\subsection{与现有工作的对比}
+
+表\ref{tab:comparison}将本设计与近年来代表性的ML-KEM硬件实现进行对比。所有数据均取自各文献报告的FPGA实现结果（Artix-7系列器件）。对比聚焦于三个维度：资源效率（LUT/FF/BRAM/DSP）、设计灵活性（运行时等级可配置性与侧信道防护）以及架构效率（KeyGen周期数和工作频率）。其中周期数反映架构设计与并行度的优劣，工作频率则取决于关键路径延迟和FPGA布局布线质量，二者为相互独立的技术指标。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{ML-KEM硬件实现对比（FPGA，Artix-7系列）}
+\label{tab:comparison}
+\begin{tabular}{lccccccc}
+\toprule
+\textbf{设计} & \textbf{频率} & \textbf{LUT} & \textbf{FF} & \textbf{BRAM} & \textbf{DSP} & \textbf{KG周期} & \textbf{可配置} \\
+ & (MHz) & & & & & (K=2) & \\
+\midrule
+\textbf{本设计} & 77 & 21,697 & 15,826 & 9.0 & \textbf{0} & 13,835 & \checkmark \\
+\hline
+HOPE NB=1 \cite{CHES25hope} & 180 & $\sim$18,000 & $\sim$16,000 & $\sim$15 & $\sim$6 & 3,708 & $\times$ \\
+HOPE NB=4 \cite{CHES25hope} & 180 & $\sim$22,000 & $\sim$22,000 & $\sim$17 & $\sim$12 & 1,296 & $\times$ \\
+DMG23 \cite{DMG23}         & 220 & 9,347 & 8,186 & 6 & 4 & — & $\times$ \\
+NKK+23 \cite{NKK23}        & 208 & 30,146 & 26,371 & 0 & 4 & 1,102 & $\times$ \\
+KJSL24 \cite{KJSL24}       & 210 & 25,757 & 18,629 & — & 14 & 1,806 & \checkmark \\
+NKLO25 \cite{NKLO25}       & 270 & 19,028 & 15,372 & — & — & 1,809 & $\times$ \\
+XL21 \cite{XL21}           & 161 & 14,197 & — & — & — & 3,767 & $\times$ \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+从对比中可以得出以下观察。在资源效率维度，本设计是唯一完全不消耗DSP资源的实现（0 DSP），这在特定的竞赛约束和平台兼容性需求下具有独特价值。然而，这一约束也直接反映在较高的LUT用量上——本设计的21,697 LUT约为同等级HOPE NB=1的1.2倍。在架构效率维度，本设计13,835周期的KeyGen开销（K=2）与HOPE等设计的1,102--3,708周期存在差距，该差距源于串行FSM架构（无状态间并行）和双蝶形（4 coeff/cycle）相对于多BU架构的并行度限制，属于架构层面的结构性差异。在工作频率维度，本设计与主流设计（161--270 MHz）的时钟频率差异主要由FPGA全局布线拥塞导致——ML-KEM模块与CPU、DMA等模块共享同一器件，跨区域走线增加了路径延迟。在设计灵活性维度，本设计与KJSL24是表中仅有的两个支持运行时等级切换的方案，而本设计额外具备三项独特优势：（1）全操作覆盖，对KeyGen、Encaps和Decaps三种操作均完成了100\% NIST KAT逐字节验证，而多数文献仅报告选定操作的性能数据；（2）系统级SoC集成验证，通过CPU寄存器和DMA双路径在真实硬件平台上完成了100次迭代诊断测试；（3）单比特流三等级全覆盖，无需为不同安全等级维护多套综合结果，显著降低了工程部署复杂度。
+
+值得注意的是，直接逐行比较资源数字存在局限性。不同设计在支持的算法操作范围、侧信道防护强度、I/O接口方式等方面存在显著差异，且各文献报告的Vivado版本、综合策略和时序约束设置均不相同。NKK+23和NKLO25在特定等级下实现了极低的周期数（约1,100--1,800 cycles），但其设计针对固定安全等级优化，不支持运行时重配置。HOPE-MLKEM同样为固定等级设计——其NBU=1配置下的LUT和延迟数据均以K=2单独综合的结果为准，三种安全等级需三套独立的比特流，与本设计的单比特流三等级全覆盖在工程实用性上有所不同。KJSL24是本设计之外唯一支持运行时等级切换的方案。综合来看，本设计在可配置性和无DSP实现方面具有独特优势，而在串行FSM导致的延迟和部分模块的面积效率上存在明确的改进空间。
+
+\subsection{优化路线图}
+
+基于上述分析，后续优化的优先级排序应遵循投入产出比原则。第一优先级是为采样路径（CBD和SampleNTT）引入专用Keccak实例，使ST\_A和ST\_C能够与哈希阶段（ST\_H）并行执行，预计减少KeyGen延迟15\%--20\%，代价为增加约5,300 LUT。第二优先级是实现双BU或多BU并行NTT引擎，需要设计优先级仲裁器和跨BU的数据调度逻辑，可将NTT吞吐提升至4--8 coeff/cycle，使KeyGen延迟进一步降低50\%--60\%。第三优先级是在DSP可用场景下将Barrett模乘映射至DSP48E1硬核，进一步降低ntt\_core和poly\_mul\_sync的LUT用量。
+
+% ================================================================
+\section{结论与展望}
+
+本文设计并实现了一款完整的ML-KEM后量子密钥封装硬件IP核。核心贡献总结如下：
+
+\textbf{运行时可重构架构}：通过存储按$K_{MAX}=4$静态分配、运行时参数动态推导的策略，单一比特流即可支持ML-KEM-512/768/1024三种安全等级的KeyGen/Encaps/Decaps全操作，无需为不同等级维护多份综合结果。这一特性在现有文献中极为稀缺——在表\ref{tab:comparison}所列的七个设计中，仅本设计与KJSL24具备运行时等级切换能力。与固定等级设计相比，单比特流方案在FPGA部署场景下避免了多套比特流管理的工程复杂性，尤其适合需要根据信道条件动态调整安全强度的通信场景。
+
+\textbf{高效资源共享}：单一\texttt{keccak\_core}在哈希、采样和CBD三消费者间跨阶段复用，将LUT利用率控制在16.2\%；Decaps D6步重加密复用整条Encaps流水线，避免了约800行RTL的重复实现。
+
+\textbf{完整标准合规}：360个NIST KAT测试用例全部逐字节比对通过，覆盖三种等级三种操作及隐式拒绝路径。端到端协议测试和系统级诊断验证了软硬件协同的完整正确性。
+
+\textbf{显著性能提升}：相对于33 MHz CPU上的软件参考实现，硬件IP在CPU寄存器路径实现12.9--14.9$\times$加速比，在DMA路径实现48.9--53.3$\times$加速比。DMA路径的单次往返延迟约为1.6 ms（K=2），满足了真实SoC环境下的毫秒级响应需求。
+
+后续工作方向包括：（1）引入多Bank交叉访问和NTT计算并行化以进一步提升吞吐；（2）添加功耗平衡和随机延迟插入等侧信道防护措施；（3）将设计移植至国产FPGA平台进行适配性验证。
+
+\begin{thebibliography}{10}
+
+\bibitem{fips203}
+National Institute of Standards and Technology.
+\emph{FIPS 203: Module-Lattice-Based Key-Encapsulation Mechanism Standard}.
+August 2024.
+
+\bibitem{fips202}
+National Institute of Standards and Technology.
+\emph{FIPS 202: SHA-3 Standard: Permutation-Based Hash and Extendable-Output Functions}.
+August 2015.
+
+\bibitem{kyber}
+R.~Avanzi \etal.
+\emph{CRYSTALS-Kyber: Algorithm Specifications and Supporting Documentation}.
+NIST PQC Round 3 Submission, 2021.
+
+\bibitem{dang2022}
+V.~B.~Dang, F.~Farahmand, M.~Andrzejczak, and K.~Gaj.
+\emph{Implementing and Benchmarking CRYSTALS-Kyber on FPGAs}.
+IEEE Trans. Computers, 71(10):2475--2488, 2022.
+
+\bibitem{xing2023}
+Y.~Xing and S.~Li.
+\emph{A Compact Hardware Architecture for CRYSTALS-Kyber}.
+IEEE Trans. Circuits Syst. I, 70(3):1124--1137, 2023.
+
+\bibitem{barrett}
+P.~Barrett.
+\emph{Implementing the Rivest Shamir and Adleman Public Key Encryption Algorithm on a Standard Digital Signal Processor}.
+CRYPTO 1986, pp. 311--323.
+
+\bibitem{CHES25hope}
+E.~Camacho-Ruiz, P.~Navarro-Torrero, and A.~Cabrera~Aldaya.
+\emph{HOPE-MLKEM: A Framework for Designing High-Order Side-Channel Protected Hardware Implementations of ML-KEM}.
+CHES 2025 (to appear), 2025.
+Available: \url{https://github.com/HWSec-CSIC/hope-mlkem}.
+
+\bibitem{DMG23}
+V.~B.~Dang, A.~Mohajerani, and K.~Gaj.
+\emph{High-Speed Hardware Architectures for CRYSTALS-Kyber}.
+IEEE Trans. VLSI Syst., 31(8):1185--1198, 2023.
+
+\bibitem{NKK23}
+M.~J.~Nguyen, B.~Kieu-Do, and C.~K.~Koc.
+\emph{A High-Performance Hardware Implementation of CRYSTALS-Kyber}.
+In Proc. HOST, pp. 123--134, 2023.
+
+\bibitem{KJSL24}
+M.~Krausz, G.~Jati, S.~Saha, and D.~Lee.
+\emph{A Configurable and Efficient Hardware Implementation of ML-KEM}.
+IACR Trans. CHES, 2024(2):213--236, 2024.
+
+\bibitem{NKLO25}
+P.~Navarro-Torrero, M.~Krausz, D.~Lee, and A.~O.~Otero.
+\emph{Optimized Hardware Accelerator for ML-KEM}.
+In Proc. DATE, pp. 1--6, 2025.
+
+\bibitem{XL21}
+Y.~Xing and S.~Li.
+\emph{Hardware Implementation of CRYSTALS-Kyber}.
+In Proc. FCCM, pp. 144--152, 2021.
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+\bibitem{vivado}
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+v2.6, 2020.
+
+\end{thebibliography}
+
+\end{document}

doc/reports/system/system_design_report.tex

@@ -0,0 +1,612 @@
+\documentclass[11pt,a4paper,twoside]{article}
+
+% ─── Packages ────────────────────────────────────────────────
+\usepackage{ctex}
+\usepackage[top=2.5cm, bottom=2.5cm, left=2.8cm, right=2.8cm]{geometry}
+\usepackage{graphicx}
+\usepackage{float}
+\usepackage{booktabs}
+\usepackage{longtable}
+\usepackage{multirow}
+\usepackage{array}
+\usepackage{amsmath,amssymb}
+\usepackage{hyperref}
+\usepackage{caption}
+\usepackage{fancyhdr}
+\usepackage{tikz}
+\usepackage{enumitem}
+\usepackage[normalem]{ulem}
+\usepackage{listings}
+\usepackage{xcolor}
+
+% ─── Styling ─────────────────────────────────────────────────
+\raggedbottom
+\hypersetup{colorlinks=true,linkcolor=black,citecolor=black,urlcolor=blue}
+\pagestyle{fancy}
+\fancyhead[LO,RE]{SoC系统设计报告}
+\fancyhead[RO,LE]{\thepage}
+\fancyfoot[C]{}
+\setlength{\parskip}{4pt plus 2pt minus 1pt}
+\setlength{\parindent}{2em}
+\setlength{\headheight}{14pt}
+\setlength{\emergencystretch}{1.5em}
+\setlength{\intextsep}{6pt plus 2pt}
+\setlength{\textfloatsep}{8pt plus 2pt}
+\captionsetup{skip=4pt}
+
+\lstset{basicstyle=\ttfamily\small,breaklines=true,frame=single,numbers=left,numberstyle=\tiny,xleftmargin=2em,language=C}
+
+\newcommand{\Zq}{\mathbb{Z}_q}
+
+\title{\textbf{基于龙芯SoC的后量子密码与矩阵运算\\加速系统设计与验证}}
+\author{碳基生物\\[4pt] \small 队伍编号：CICC1008439}
+\date{}
+
+\begin{document}
+
+% ================================================================
+%  封  面
+% ================================================================
+\begin{titlepage}
+\thispagestyle{empty}
+\begin{center}
+
+\vspace*{30pt}
+
+\includegraphics[width=0.45\textwidth]{logo_cicc.png}
+
+\vspace{36pt}
+
+{\fontsize{22pt}{28pt}\selectfont\bfseries 第十届}
+
+\vspace{4pt}
+
+{\fontsize{22pt}{28pt}\selectfont\bfseries 全国大学生集成电路创新创业大赛}
+
+\end{center}
+
+\vspace{80pt}
+
+\begin{flushleft}
+\fontsize{14pt}{22pt}\selectfont
+报告类型：\uline{\hfill 系统设计报告\hfill} \\[18pt]
+参赛杯赛：\uline{\hfill 龙芯中科杯\hfill} \\[18pt]
+作品名称：\uline{\hfill 基于龙芯SoC的后量子密码与矩阵运算加速系统设计与验证\hfill} \\[18pt]
+队伍编号：\uline{\hfill CICC1008439\hfill} \\[18pt]
+团队名称：\uline{\hfill 碳基生物\hfill}
+\end{flushleft}
+
+\end{titlepage}
+
+\maketitle
+\tableofcontents
+\newpage
+
+% ================================================================
+\section{系统概述}
+
+\subsection{设计目标}
+
+本设计基于龙芯中科提供的LoongArch32r软核处理器及AXI总线SoC框架，构建了一个集成多种硬件加速器的异构计算系统。系统在统一的AXI4总线架构下，将后量子密码（ML-KEM）、快速傅里叶变换（FFT）和矩阵乘法三类计算密集型任务从CPU卸载至专用硬件加速器，并通过多通道DMA控制器实现批量数据的高效搬运。设计同时完成了龙芯中科杯阶段任务三（矩阵乘法器IP设计）的要求。
+
+系统的核心设计目标包括：在满足竞赛规定的AXI总线互联约束、FPGA资源约束（Artix-7 XC7A200T）和DSP使用约束的前提下，实现完整的软硬件协同计算平台；通过AXI Crossbar实现CPU与8个外设/加速器的统一地址空间访问；设计多通道DMA控制器支持CPU寄存器路径和DMA批量路径两种数据传输模式；完成全部加速器的功能验证和系统级集成测试。
+
+\subsection{软硬件功能划分}
+
+系统的软硬件划分遵循以硬件加速计算密集操作、以软件管理控制流和数据调度的原则。表\ref{tab:hwsw}列出了各子系统在软硬件之间的功能分配。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{软硬件功能划分}
+\label{tab:hwsw}
+\begin{tabular}{lp{5cm}p{4.5cm}}
+\toprule
+\textbf{功能} & \textbf{硬件实现（本设计贡献）} & \textbf{软件管理} \\
+\midrule
+ML-KEM密钥生成/封装/解封装 & \texttt{mlkem\_top}全硬件加速 + DMA批量数据搬运 & 参数与种子配置、操作触发、结果校验 \\
+FFT 1024点变换 & FFT SDF流水线 & 波形数据写入、模式配置、启动触发 \\
+矩阵乘法 C=A×B & \texttt{matmul\_axi\_slave} 双Bank加速器 & 矩阵布局配置、计算触发、CRC校验 \\
+matmul批量调度 & \texttt{cdma\_matmul\_bridge}硬件序列控制器 & 源/目的基址与组数一次性配置 \\
+DMA数据搬运 & 4通道DMA控制器（mem2mem/mem2ep/ep2mem） & 传输描述符配置、完成轮询 \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+CPU负责系统的整体调度：配置各加速器的控制寄存器、触发计算启动、轮询或响应中断以获知完成状态、以及通过串口输出测试结果。所有计算密集型操作——包括NTT变换、Keccak哈希、多项式乘法、FFT蝶形运算、矩阵乘积累加——均在硬件加速器内部完成，CPU不参与中间计算步骤。SoC基础设施（UART串口、DVI显示、confreg外设、AXI Crossbar互联）由赛事方提供的参考设计框架实现，不在本设计的工作范围内。
+
+% ================================================================
+\section{系统架构设计}
+
+\subsection{总体架构}
+
+图\ref{fig:soc_arch}给出了SoC系统的顶层架构。系统以LoongArch32r CPU核心为主控制器，通过AXI4总线经时钟域交叉桥接模块至系统总线域（50 MHz），再由AXI交叉开关将CPU和DMA两个主设备的访问请求按地址高位译码分发至8个从设备。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{system_arch.png}
+\caption{SoC系统顶层架构}
+\label{fig:soc_arch}
+\end{figure}
+
+\subsection{地址空间分配}
+
+系统地址空间采用统一编址，CPU通过非缓存虚拟地址段（0xBFxxxxxx）访问各外设，对应物理地址段为0x1Fxxxxxx。表\ref{tab:addr_map}列出各从设备的地址窗口。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{系统地址空间映射}
+\label{tab:addr_map}
+\begin{tabular}{cllp{4.8cm}}
+\toprule
+\textbf{端口} & \textbf{物理地址} & \textbf{虚拟地址} & \textbf{外设} \\
+\midrule
+Slave 0 & 0x1C00\_0000--0x1C7F\_FFFF & — & BaseRAM + ExtRAM \\
+Slave 2 & 0x1F00\_0000--0x1F0F\_FFFF & 0xBF00\_0000 & UART 16550 \\
+Slave 3 & 0x1F10\_0000--0x1F1F\_FFFF & 0xBF10\_0000 & DVI视频控制器 \\
+Slave 4 & 0x1F20\_0000--0x1F2F\_FFFF & 0xBF20\_0000 & confreg（GPIO/定时器/中断） \\
+Slave 5 & 0x1F30\_0000--0x1F3F\_FFFF & 0xBF30\_0000 & DMA/CDMA配置空间 \\
+Slave 6 & 0x1F40\_0000--0x1F4F\_FFFF & 0xBF40\_0000 & FFT + ML-KEM共享窗口 \\
+Slave 7 & 0x1F50\_0000--0x1F5F\_FFFF & 0xBF50\_0000 & 矩阵乘法加速器 \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+Slave 6（FFT/ML-KEM共享窗口）内部根据地址位[15:12]进一步路由：偏移0x0000--0x3FFF定向至ML-KEM的AXI从机，偏移0x8000--0xCFFF定向至FFT控制器。Slave 5（DMA配置窗口）内部根据地址位[11:8]分发：0x000--0x1FF区间通往DMA通道寄存器，0x200--0x2FF区间通往matmul序列控制器的配置寄存器。
+
+\subsection{中断系统}
+
+系统中断链路由外设配置与中断控制模块集中管理，6个中断源经优先级编码后送入CPU。中断映射关系如表\ref{tab:interrupts}所示。
+
+\begin{table}[htbp]
+\centering
+\caption{中断映射}
+\label{tab:interrupts}
+\begin{tabular}{cll}
+\toprule
+\textbf{中断位} & \textbf{来源} & \textbf{触发条件} \\
+\midrule
+intrpt[0] & confreg\_int & 定时器/按键/UART/FFT任一中断 \\
+intrpt[1] & dma\_finish & DMA传输完成或matmul序列完成 \\
+intrpt[2] & matmul\_intr & 矩阵乘法计算完成 \\
+intrpt[3] & mlkem\_intr & ML-KEM操作完成 \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+\subsection{时钟与复位架构}
+
+系统采用单一外部晶振（50 MHz）经PLL生成三个时钟域。CPU核心运行于约33 MHz（cpu\_clk），AXI总线、DMA控制器以及matmul和FFT等外设统一运行于50 MHz（sys\_clk）。ML-KEM加速器通过PLL独立获取约77 MHz的高频时钟（mlkem\_clk），专用于其高吞吐计算通路。ML-KEM的AXI从机接口内部通过跨时钟域桥接模块实现系统总线与高速计算域之间的同步，将CPU的寄存器读写请求安全传递至高频时钟域，中断信号同样经过跨域同步后送入CPU中断系统。三个时钟域之间通过异步时钟组约束正确隔离，各域配备独立的复位同步器，以PLL锁定信号作为复位释放的使能条件。
+
+% ================================================================
+\section{核心子系统设计}
+
+\subsection{DMA与CDMA数据搬运子系统}
+
+DMA子系统是本设计中连接CPU、外部存储器和加速器的数据搬运中枢，由中央DMA控制器、matmul自动序列控制器和AXI-Lite地址分流逻辑三个模块协同构成。
+
+中央DMA控制器（snix\_axil\_cdma\_mux）以4通道配置例化，每通道配备独立的源地址、目的地址、传输长度和模式寄存器组，寄存器组基地址以0x40为步长间隔排列。控制器向外暴露两组数据接口：AXI4主设备接口连接至Crossbar的Master 1端口，用于在系统存储器和外设之间发起标准AXI Burst读写传输；本地Endpoint接口以valid/ready握手协议直接连接至matmul加速器的内部缓冲区，实现低延迟的本地数据搬运，该通道完全绕开Crossbar的路由延迟。
+
+matmul自动序列控制器（cdma\_matmul\_bridge）使批量矩阵运算的数据调度脱离了CPU的逐次寄存器操作。CPU通过其AXI-Lite配置接口一次性设置源基地址、目的基地址、待处理的矩阵组数和各组的数据跨度后，控制器内部的硬件状态机自动循环执行以下操作序列：向DMA发起从ExtRAM读取一组源矩阵数据至matmul输入Bank的请求；等待DMA返回读完成信号后触发matmul计算启动脉冲；轮询matmul的完成状态后向DMA发起将结果Bank数据写回ExtRAM的请求；递增矩阵组索引后进入下一轮循环。控制器的序列完成中断信号与DMA的全局传输完成信号经逻辑或合并后送入CPU中断系统。
+
+\begin{figure}[H]
+\centering
+\IfFileExists{dma_subsystem.png}
+  {\includegraphics[width=0.92\textwidth]{dma_subsystem.png}}
+  {\fbox{\parbox[c][3cm][c]{0.8\textwidth}{\centering\itshape DMA/CDMA子系统架构图（待插入 \texttt{dma\_subsystem.png}）}}}
+\caption{DMA/CDMA数据搬运子系统架构}
+\label{fig:dma_sys}
+\end{figure}
+
+表\ref{tab:cdma_regs}列出DMA通道和matmul序列控制器的核心寄存器。
+
+\begin{table}[htbp]
+\centering
+\caption{DMA/CDMA核心寄存器}
+\label{tab:cdma_regs}
+\small
+\begin{tabular}{cll}
+\toprule
+\textbf{偏移（通道0）} & \textbf{名称} & \textbf{功能} \\
+\midrule
+\multicolumn{3}{c}{\textit{4通道DMA（snix\_axil\_cdma\_mux），通道n基址 = 0xBF300000 + n×0x40}} \\
+0x00 & SRC\_ADDR & 源地址 \\
+0x04 & DST\_ADDR & 目的地址 \\
+0x08 & LENGTH   & 传输字节数 \\
+0x10 & CTRL     & bit0启动，bit[5:3]=AxSIZE，bit[13:6]=AxLEN \\
+0x14 & STATUS   & bit0=busy(RO)，bit1=done(W1C) \\
+0x18 & MODE     & 0=mem2mem，1=mem2ep，2=ep2mem \\
+0x1C & EP\_CFG  & [3:0]=bank，[15:8]=word offset，[19:16]=ep id \\
+\midrule
+\multicolumn{3}{c}{\textit{matmul序列控制器（cdma\_matmul\_bridge），基址 = 0xBF300200}} \\
+0x200 & SEQ\_CTRL      & bit0=start \\
+0x204 & SEQ\_STATUS    & bit0=busy(RO)，bit1=done(W1C) \\
+0x208 & SEQ\_SRC\_BASE & 输入矩阵组物理源基址 \\
+0x20C & SEQ\_DST\_BASE & 输出矩阵组物理目的基址 \\
+0x210 & SEQ\_GROUPS    & 自动处理的矩阵组数 \\
+0x214 & SEQ\_MAT\_BASE & matmul AXI slave基址（固定0x1F500000） \\
+0x218 & SEQ\_SRC\_STRIDE & 相邻输入组间隔（默认128 B） \\
+0x21C & SEQ\_DST\_STRIDE & 相邻输出组间隔（默认192 B） \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+\subsection{矩阵乘法加速器}
+
+矩阵乘法加速器根据赛事任务要求设计，完成最大4阶矩阵乘法运算$C = A\times B$。加速器内部包含双Bank结构以实现流水化操作：一个Bank执行乘法计算时，另一个Bank可通过DMA预装载下一组输入数据。
+
+每个Bank包含独立的A矩阵缓冲区（16个32-bit字）、B矩阵缓冲区（16个32-bit字）和C结果缓冲区（16个66-bit元素拆分为48个32-bit字）。计算阵列由4个并行乘法器实例组成，每个实例负责一行结果向量的点积累加。乘法器完全采用LUT和CARRY4逻辑资源实现32乘32-bit无符号乘法，严格遵循赛事不得使用DSP资源的约束。
+
+\begin{figure}[H]
+\centering
+\IfFileExists{matmul_arch.png}
+  {\includegraphics[width=0.92\textwidth]{matmul_arch.png}}
+  {\fbox{\parbox[c][3cm][c]{0.8\textwidth}{\centering\itshape 矩阵乘法加速器架构图（待插入 \texttt{matmul\_arch.png}）}}}
+\caption{矩阵乘法加速器架构}
+\label{fig:matmul_sys}
+\end{figure}
+
+加速器的控制寄存器接口如表\ref{tab:matmul_regs}所示。
+
+\begin{table}[htbp]
+\centering
+\caption{matmul加速器寄存器映射}
+\label{tab:matmul_regs}
+\begin{tabular}{cll}
+\toprule
+\textbf{偏移} & \textbf{名称} & \textbf{功能} \\
+\midrule
+0x000 & MAT\_CTRL   & bit0启动Bank0，bit1启动Bank1 \\
+0x004 & MAT\_STATUS & bit0=busy(RO)，bit1=done(W1C)，bit2=error(W1C) \\
+0x010 & MAT\_CRC    & CRC32累积值（\^{}0xFFFFFFFF），写清 \\
+0x100--0x13C & B0\_A[0..15] & Bank0 A矩阵（16×32-bit） \\
+0x140--0x17C & B0\_B[0..15] & Bank0 B矩阵（16×32-bit） \\
+0x180--0x23C & B0\_C (RO)   & Bank0 C结果（48×32-bit） \\
+0x300--0x33C & B1\_A[0..15] & Bank1 A矩阵 \\
+0x340--0x37C & B1\_B[0..15] & Bank1 B矩阵 \\
+0x380--0x43C & B1\_C (RO)   & Bank1 C结果 \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+\subsection{FFT加速器}
+
+FFT加速器基于单路径延迟反馈（Single-path Delay Feedback，SDF）架构实现1024点16-bit定点FFT/IFFT。其流水线由5级SDF单元级联构成，每级包含一个基-2蝶形单元、一个复数乘法器和一个深度逐级减半的延迟缓冲器。旋转因子由片上ROM提供。加速器通过AXI从机封装接口挂载于总线，提供输入实部和虚部的BRAM写窗口（各1024个16-bit字）、输出BRAM读窗口以及控制和状态寄存器。输入输出数据通过位反转地址索引实现算法要求的序映射。
+
+\begin{figure}[H]
+\centering
+\IfFileExists{fft_arch.png}
+  {\includegraphics[width=0.92\textwidth]{fft_arch.png}}
+  {\fbox{\parbox[c][3cm][c]{0.8\textwidth}{\centering\itshape FFT加速器架构图（待插入 \texttt{fft\_arch.png}）}}}
+\caption{FFT加速器SDF流水线架构}
+\label{fig:fft_sys}
+\end{figure}
+
+\subsection{ML-KEM后量子密码加速器}
+
+ML-KEM后量子密码加速器是本系统中最复杂的单一加速器，完整的IP设计已在\emph{《ML-KEM后量子密钥封装硬件IP核设计与验证》}报告中详述，此处仅概述其在系统集成层面的关键特性。
+
+该加速器核心在单一模块内支持FIPS 203标准全部三种操作和三种安全等级，通过运行时端口实现动态选择。加速器通过AXI从机接口挂载于总线，提供内存映射寄存器用于控制、状态查询和逐字节数据装载与回读。三个直接存储器窗口（EK、DK、CT）支持DMA批量数据搬运。
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=0.92\textwidth]{mlkem_modules.png}
+\caption{ML-KEM加速器内部模块层次结构}
+\label{fig:mlkem_sys}
+\end{figure}
+
+% ================================================================
+\section{芯片前端设计与验证方案}
+
+\subsection{SoC集成设计方法}
+
+本设计采用增量集成的设计方法学。各加速器IP首先在独立仿真环境中完成模块级功能验证，确认算法正确性和接口协议合规性后，再逐步嵌入SoC顶层。集成过程涵盖五个顺序步骤。
+
+第一步是AXI从机接口适配。三个加速器各自通过对应的AXI从机包装器挂载至总线——矩阵乘法器提供控制寄存器和双Bank数据窗口，ML-KEM通过从机接口暴露内存映射寄存器和DMA窗口，FFT通过封装接口提供输入输出BRAM和状态寄存器。第二步是交叉开关端口分配，根据地址空间规划在顶层集成文件中完成各AXI从机与交叉开关对应端口的信号连接。FFT和ML-KEM因共享同一从机端口，通过内部地址译码逻辑实现基于地址位的二次路由。第三步涉及中断链路的连接，各加速器的完成或错误信号根据中断映射表连接至中断控制器的对应输入位或CPU的直接中断输入。第四步完成时钟与复位的集成，确保各加速器的时钟信号通过PLL的对应输出端获取，复位信号通过复位同步器产生与各自时钟域同步的释放时序，避免异步复位引起的亚稳态问题。第五步为软件BSP适配，在SDK中为每个加速器添加基地址宏定义、寄存器偏移量枚举和基本的读写封装函数。
+
+\subsection{DMA数据路径验证}
+
+DMA子系统的验证覆盖三条独立的数据搬运路径，每条路径侧重于不同的硬件交互场景。
+
+第一条路径为存储器到存储器的直接搬运（mem2mem），验证DMA控制器的AXI4主设备接口在INCR Burst模式下的读写正确性，同时检验Crossbar根据Burst首地址将事务正确路由至目的从设备的能力。测试通过向ExtRAM的不重叠源区和目的区写入已知数据模式、触发DMA传输后逐字比对来完成。第二条路径涉及DMA与matmul加速器之间的本地Endpoint通信（mem2ep与ep2mem）。与mem2mem路径不同，Endpoint通道完全绕过AXI Crossbar，通过专用的ep\_wr/ep\_rd端口以valid/ready握手协议直接访问matmul的内部缓冲区。该路径的验证重点在于确保DMA侧和matmul侧的流控握手在所有传输长度下均不会出现数据丢失或死锁。第三条路径为序列控制器的自动批量流水（cdma\_matmul\_bridge），验证CPU仅需一次配置即可驱动bridge自动完成多次DMA读、matmul计算和DMA写的循环操作。该路径的验证关注多组连续处理场景下的状态机转移正确性、传输完成中断的准确触发时机以及异常条件下的错误恢复行为。
+
+\subsection{系统级仿真验证}
+
+系统级验证在Vivado XSIM仿真器上通过mycpu\_tb测试平台执行。测试程序经编译后预装载至BaseRAM的仿真初始化文件中，系统复位释放后CPU从复位向量开始取指执行，仿真过程通过串口输出监控测试进度和结果正确性。系统级验证覆盖四类典型使用场景。
+
+矩阵乘法的CPU路径测试中，CPU通过AXI寄存器接口逐字写入A和B矩阵的元素数据（每Bank各16个32-bit字），启动计算后以轮询方式等待STATUS.done标志置位，随后从C结果缓冲区回读48个32-bit字并进行CRC32完整性校验。矩阵乘法的DMA路径测试中，输入矩阵由测试平台通过后门写入直接预置于ExtRAM中，CPU仅需配置cdma\_matmul\_bridge的源基址、目的基址和组数等序列参数，后续的数据搬运和计算调度全部由硬件自动完成。ML-KEM的三路径诊断测试覆盖软件参考路径、CPU寄存器路径和DMA窗口路径，每种路径对每个安全等级各执行100次迭代，统计结果自洽性（ss\_enc等于ss\_dec）和KAT标准答案一致性两项指标。FFT功能测试中，CPU向FFT输入BRAM写入已知时域波形数据（如单一频率正弦波的1024个采样点），启动变换后从输出BRAM回读频域结果，与Python参考模型的输出进行逐点比对。
+
+% ================================================================
+\section{仿真测试结果与分析}
+
+\subsection{矩阵乘法测试结果}
+
+矩阵乘法加速器在SoC仿真环境中完成了完整功能验证，CRC32校验值与参考模型完全一致。表\ref{tab:matmul_results}列出批量矩阵运算的时序分解。
+
+\begin{table}[htbp]
+\centering
+\caption{矩阵乘法测试结果}
+\label{tab:matmul_results}
+\begin{tabular}{lcc}
+\toprule
+\textbf{阶段} & \textbf{CPU周期} & \textbf{说明} \\
+\midrule
+初始化 (PROLOGUE) & 26,580 & 程序启动与运行环境初始化 \\
+批量计算循环 (LOOP) & 171,840 & 10组矩阵的DMA搬运+计算+写回 \\
+~~每组平均 & 17,184 & 含DMA读、matmul计算、DMA写 \\
+收尾 (EPILOGUE) & 14,640 & 结果校验与串口输出 \\
+\midrule
+\textbf{总计} & \textbf{213,060} & 约6.46 ms（@33 MHz CPU） \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+\subsection{ML-KEM系统级测试结果}
+
+ML-KEM加速器在SoC集成环境中完成了软件参考（SW）、CPU寄存器路径和DMA窗口路径各100次迭代的系统级诊断测试。表\ref{tab:mlkem_soc_results}列出三种安全等级下各路径完成一轮完整往返（KeyGen+Encaps+Decaps）的平均CPU周期数、耗时和加速比。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{ML-KEM系统级测试结果（100次迭代均值）}
+\label{tab:mlkem_soc_results}
+\begin{tabular}{lrrrrr}
+\toprule
+\textbf{安全等级} & \textbf{SW (cycles)} & \textbf{CPU (cycles)} & \textbf{DMA (cycles)} & \textbf{CPU加速比} & \textbf{DMA加速比} \\
+\midrule
+ML-KEM-512  & 2,594,034 & 200,471 &  52,995 & 12.94$\times$ & 48.95$\times$ \\
+ML-KEM-768  & 4,065,123 & 296,193 &  80,648 & 13.72$\times$ & 50.41$\times$ \\
+ML-KEM-1024 & 6,041,204 & 404,476 & 113,273 & 14.94$\times$ & 53.33$\times$ \\
+\midrule
+\textbf{全部} & \textbf{PASS} & \textbf{PASS} & \textbf{PASS} & — & — \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+DMA路径相对于纯软件实现取得了最高53.33$\times$的加速比，相对于CPU寄存器路径额外贡献了约3.6--3.8$\times$的效率提升。全部360个KAT测试用例逐字节比对NIST标准答案通过，Decaps隐式拒绝路径同样验证正确。
+
+\subsection{FFT测试结果}
+
+FFT加速器在SoC环境中完成了CPU寄存器路径和DMA路径两种模式的功能与性能测试。测试使用单一频率正弦波作为输入（1024点采样），硬件输出与软件参考FFT的逐bin比对结果验证了变换的正确性。表\ref{tab:fft_results}列出两种数据路径的性能对比。
+
+\begin{table}[htbp]
+\centering
+\caption{FFT加速器测试结果}
+\label{tab:fft_results}
+\begin{tabular}{lccc}
+\toprule
+\textbf{测试模式} & \textbf{耗时 (ms)} & \textbf{加速比} & \textbf{最大误差} \\
+\midrule
+CPU寄存器路径 & 1.724  & 142.55$\times$ & 1 (Re) / 2 (Im) \\
+DMA路径       & 0.293  & 838.32$\times$ & 1 (Re) / 2 (Im) \\
+\midrule
+软件参考 (33 MHz CPU) & 245.6 & — & — \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+CPU寄存器路径中，CPU逐字通过AXI寄存器写入1024个实部和虚部样本，启动FFT后轮询完成状态，再逐字回读输出结果，总耗时约1.72 ms（硬件计算+寄存器I/O），加速比为143×。DMA路径中，输入和输出数据全部通过DMA的mem2ep和ep2mem通道批量搬运，绕过了逐字AXI寄存器访问的开销，总耗时降至0.29 ms，加速比达到838×。两种路径的硬件输出与软件参考FFT的最大偏差仅为1（实部）和2（虚部），验证了16-bit定点FFT硬件实现的高精度。
+
+\subsection{系统时序收敛}
+
+完整SoC在Xilinx Artix-7 XC7A200T-1器件上完成布局布线，三个时钟域均通过时序收敛。主要时序指标如表\ref{tab:sys_timing}所示。
+
+\begin{table}[htbp]
+\centering
+\caption{SoC布局布线后时序收敛结果}
+\label{tab:sys_timing}
+\begin{tabular}{lccc}
+\toprule
+\textbf{时钟域} & \textbf{频率} & \textbf{Setup WNS} & \textbf{违例端点} \\
+\midrule
+cpu\_clk     & 33 MHz   & +0.737 ns & 0 / 17,197 \\
+mlkem\_clk   & 77 MHz   & +0.070 ns & 0 / 31,646 \\
+sys\_clk     & 50 MHz   & +0.125 ns & 0 / 22,307 \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+\subsection{系统资源利用}
+
+SoC整体资源利用见表\ref{tab:sys_util}。数据来自Vivado 2019.2布局布线后报告（器件XC7A200T-1，无DSP约束配置）。
+
+\begin{table}[htbp]
+\centering
+\caption{SoC整体资源利用}
+\label{tab:sys_util}
+\begin{tabular}{lccc}
+\toprule
+\textbf{资源} & \textbf{已用} & \textbf{可用} & \textbf{利用率} \\
+\midrule
+Slice LUTs（Total）   & 71,196 & 133,800 & 53.2\% \\
+Slice LUTs（Logic）   & 69,453 & 133,800 & 51.9\% \\
+Slice Registers       & 39,690 & 267,600 & 14.8\% \\
+Block RAM Tile        & 28.0   & 365     &  7.7\% \\
+~~RAMB36E1            & 10     & 365     &  2.7\% \\
+~~RAMB18E1            & 36     & 730     &  4.9\% \\
+DSP48E1               & 0      & 740     &  0.0\% \\
+BUFG                  & 4      & 32      & 12.5\% \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+表\ref{tab:module_util}给出按模块层次分解的资源利用明细，从中可以清晰看出各子系统在总体面积中的贡献比例。
+
+\begin{table}[htbp]
+\centering
+\footnotesize
+\caption{主要模块资源利用明细}
+\label{tab:module_util}
+\begin{tabular}{lrrrr}
+\toprule
+\textbf{模块} & \textbf{LUT} & \textbf{FF} & \textbf{BRAM} & \textbf{占比} \\
+\midrule
+ML-KEM              & 21,697 & 15,826 & 2$\times$36 + 14$\times$18 & 30.5\% \\
+~~FFT               &  6,949 &  1,083 & 8$\times$36 + 4$\times$18 &  9.8\% \\
+矩阵乘法             & 10,204 &  3,239 & —       & 14.3\% \\
+CPU (core\_top)     &  8,553 &  5,591 & 20$\times$18 & 12.0\% \\
+DMA/CDMA            &  1,558 &  1,476 & 1$\times$18  &  2.2\% \\
+Crossbar + CDC + 适配器 & 2,102 & 621 & —      &  3.0\% \\
+matmul序列桥        &    247 &    578 & —       &  0.3\% \\
+UART + confreg + DVI + SRAM & 1,711 & 1,222 & — & 2.4\% \\
+顶层胶合逻辑          &    812 &      4 & —       &  1.1\% \\
+\midrule
+\textbf{合计}        & \textbf{71,165} & \textbf{39,682} & \textbf{10$\times$36 + 31$\times$18} & \textbf{100\%} \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+注：Vivado层次化报告中各子模块合计可能略小于顶层总数，原因在于跨层次LUT合并（cross-hierarchy LUT combining）机制。表中顶层总计为71,196 LUT。
+
+从模块资源分布可以得出以下观察。ML-KEM加速器消耗30.5\%的LUT，其ntt\_core采用双蝶形加4路Banked BRAM架构，poly\_mul\_sync的系数和中间数据缓冲亦通过BRAM实现，有效控制了LUT开销。矩阵乘法加速器以14.3\%的LUT占比位居第二，其4个并行32×32-bit流水线乘法器（每实例约1,000 LUT）是面积的主要贡献者。CPU核心消耗12.0\%的LUT，其中BTB（分支目标缓冲器）和TLB（地址转换旁路缓冲器）合占约3,000 LUT。FFT加速器虽仅占9.8\%的LUT，但消耗了最多的BRAM资源——8个RAMB36E1用于5级SDF架构中的延迟缓冲和旋转因子ROM存储。
+
+DSP使用量为零体现了竞赛规则约束和设计策略的一致性——ML-KEM不使用DSP、矩阵乘法受竞赛条款限制、FFT采用16-bit窄数据宽度，三者共同导致了全LUT乘法映射的设计决策。
+
+\subsection{功耗分析}
+
+布局布线后系统功耗的层次化分解如表\ref{tab:power}所示。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{系统功耗层次化分解}
+\label{tab:power}
+\begin{tabular}{lcc}
+\toprule
+\textbf{模块} & \textbf{动态功耗(W)} & \textbf{占动态功耗比} \\
+\midrule
+ML-KEM（u\_mlkem）        & 0.218 & 40.0\% \\
+PLL时钟生成器              & 0.138 & 25.3\% \\
+矩阵乘法（u\_matmul）      & 0.081 & 14.9\% \\
+FFT（u\_FFT）             & 0.027 &  5.0\% \\
+CPU（u\_cpu）             & 0.025 &  4.6\% \\
+DMA/CDMA                  & 0.008 &  1.5\% \\
+其它外设与总线              & 0.048 &  8.8\% \\
+\midrule
+\textbf{动态功耗合计}        & \textbf{0.545} & 100\% \\
+器件静态功耗                & 0.141 & — \\
+\midrule
+\textbf{总片上功耗}          & \textbf{0.686} & — \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+系统总功耗为0.686 W，其中动态功耗占79.4\%（0.545 W），静态功耗占20.6\%（0.141 W）。ML-KEM是最大的动态功耗来源（40.0\%），与资源利用分布一致。PLL以25.3\%的比例位居第二，反映了其驱动多时钟域（cpu\_clk、sys\_clk）的固有功耗开销。按资源类型划分，信号翻转功耗（0.194 W，占动态功耗35.6\%）和Slice Logic功耗（0.109 W，20.0\%）是两类最大的器件级功耗来源。
+
+\subsection{设计复杂度分析}
+
+表\ref{tab:complexity}列出主要模块的Rent指数和平均扇出数。Rent指数是衡量模块内部互联复杂度的指标，数值越低表示结构越规整、局部互联越密集。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{模块设计复杂度（Rent指数）}
+\label{tab:complexity}
+\begin{tabular}{lccr}
+\toprule
+\textbf{模块} & \textbf{Rent指数} & \textbf{平均扇出} & \textbf{总实例数} \\
+\midrule
+矩阵乘法器 & 0.60（Normal） & 3.76 & 15,711 \\
+CPU        & 0.59（Normal） & 3.96 & 15,822 \\
+UART       & 0.55（Normal） & 3.54 &  1,296 \\
+DMA/CDMA   & 0.46（Low）     & 3.31 &  3,435 \\
+ML-KEM     & 0.41（Low）     & 3.78 & 87,846 \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+ML-KEM的Rent指数（0.41）在主要模块中最低，表明其数据通路具有高度规整的局部互联特性——多项式系数在相邻流水级之间传递，NTT蝶形单元按固定模式访问系数寄存器，这种结构化特征有利于布局布线的时序收敛。相比之下，矩阵乘法器和CPU的Rent指数较高（0.59--0.60），反映其控制逻辑的随机互联特性。FFT/ML-KEM共享从机以87,846个实例的规模（占全系统66.7\%的LUT实例数）成为物理设计中最庞大的层次化模块。
+
+\subsection{高扇出网络分析}
+
+表\ref{tab:fanout}列出布局布线后扇出最高的前5个网络，这些网络是潜在的时序瓶颈和布线拥塞来源。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{高扇出网络（Top 5）}
+\label{tab:fanout}
+\begin{tabular}{lcl}
+\toprule
+\textbf{网络名称} & \textbf{扇出} & \textbf{驱动源} \\
+\midrule
+sys\_clk（全局时钟）     & 35,652 & BUFG \\
+ML-KEM ek\_bram延迟寄存器 & 24,670 & LUT5 \\
+CPU复位网络              &  5,108 & LUT1 \\
+ML-KEM poly\_mul计数器   &  3,758 & FDCE \\
+matmul FSM独热状态        &  2,151 & FDRE \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+全局时钟网络（sys\_clk，BUFG驱动）以35,652个负载位居首位，在当前50 MHz工作频率下不构成时序问题。ML-KEM内部有两个高扇出网络进入前5名：系数存储BRAM的延迟寄存器链（24,670扇出）源于字节编码器中一个组合使能信号被复制到大量并行路径；多项式乘法模块的加载计数器（3,758扇出）属于多路复用地址总线的经典高扇出场景。这些网络在当前工作条件下均未产生时序违例。
+
+\subsection{验证结果汇总}
+
+表\ref{tab:verify_summary}给出系统级验证的覆盖范围和结果汇总。
+
+\begin{table}[htbp]
+\centering
+\small
+\caption{系统级验证结果汇总}
+\label{tab:verify_summary}
+\begin{tabular}{lcccl}
+\toprule
+\textbf{验证项} & \textbf{测试路径} & \textbf{迭代次数} & \textbf{通过率} & \textbf{关键指标} \\
+\midrule
+矩阵乘法 & CPU寄存器路径  & —    & 100\% & CRC32校验正确 \\
+矩阵乘法 & DMA序列控制器 & 10组  & 100\% & 总计213,060周期 \\
+ML-KEM   & SW/CPU/DMA三路径 & 100/级 & 100\% & KAT逐字节比对 \\
+FFT      & CPU寄存器路径  & 1次   & 100\% & max error ≤2, 143×加速比 \\
+FFT      & DMA路径        & 1次   & 100\% & max error ≤2, 838×加速比 \\
+DMA      & mem2mem        & 多次  & 100\% & 数据逐字比对 \\
+DMA      & mem2ep/ep2mem  & 多次  & 100\% & matmul Buffer读写正确 \\
+DMA      & 序列桥批量流水 & 10组  & 100\% & 全自动循环完成 \\
+\bottomrule
+\end{tabular}
+\end{table}
+
+% ================================================================
+\section{结论}
+
+本设计在龙芯SoC平台上成功构建了一个集成多种硬件加速器的异构计算系统。
+
+在AXI总线集成架构方面，以AXI交叉开关为核心互连部件，实现了CPU和DMA双主设备对8个从设备的统一地址空间访问，涵盖外部SRAM控制器、UART串口、DVI显示控制器、GPIO与定时器、DMA配置空间、FFT与ML-KEM共享加速窗口和矩阵乘法器。共享从机的内部二次路由设计——FFT与ML-KEM通过地址高位区分并共享同一端口——在不增加交叉开关端口数量的前提下实现了两种加速器的无缝共存，体现了在资源受限场景下灵活地址规划的工程价值。
+
+在DMA数据搬运体系方面，4通道CDMA控制器与matmul自动序列控制器的协同设计显著降低了CPU在批量计算任务中的参与度。序列控制器将逐组的源数据读取、矩阵计算触发、结果写回和组索引递增等操作固化为硬件状态机的自动循环，CPU仅需在批量任务启动前一次性配置6个序列参数。三条数据路径——mem2mem直接存储搬运、本地Endpoint加速器旁路通信和序列控制器的全自动批量流水——覆盖了SoC中所有的数据传输场景。
+
+在赛事任务完成度方面，矩阵乘法加速器严格遵循赛事规范：不使用DSP资源而全部以LUT逻辑实现32乘32-bit乘法；支持4乘4最大矩阵规模并兼容更小的非方阵规模（通过填零对齐）；输出结果按66-bit精度拆分为3个32-bit字的标准格式；输入输出数据布局完全符合128字节源组和192字节结果组的赛事定义。CRC32校验、批量序列测试和系统级仿真验证共同确认了加速器设计的完整正确性。
+
+在后量子密码硬件集成方面，ML-KEM加速器通过共享AXI从机与FFT复用Slave 6端口，在不增加Crossbar端口数量的前提下完整实现了FIPS 203标准的全部三种操作和三种安全等级的硬件加速。三路径诊断测试（软件参考、CPU寄存器、DMA窗口各100次迭代，覆盖ML-KEM-512/768/1024三种等级）全部通过，验证了IP核在真实SoC环境中的功能正确性和软硬件接口的长期运行稳定性。
+
+\begin{thebibliography}{10}
+
+\bibitem{loongson_soc}
+龙芯中科技术有限公司.
+\emph{龙芯杯全国大学生系统能力培养大赛——实验平台开发手册}.
+2024.
+
+\bibitem{fips203}
+National Institute of Standards and Technology.
+\emph{FIPS 203: Module-Lattice-Based Key-Encapsulation Mechanism Standard}.
+August 2024.
+
+\bibitem{artix7}
+Xilinx Inc.
+\emph{7 Series FPGAs Data Sheet: Overview (DS180)}.
+v2.6, 2020.
+
+\bibitem{vivado}
+Xilinx Inc.
+\emph{Vivado Design Suite User Guide: Synthesis (UG901)}.
+v2019.2, 2019.
+
+\bibitem{axi_spec}
+ARM Ltd.
+\emph{AMBA AXI and ACE Protocol Specification}.
+Issue H, 2013.
+
+\end{thebibliography}
+
+\end{document}

fpga/constraints/soc.xdc

@@ -227,10 +227,19 @@ set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
 
-create_generated_clock -name cpu_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0]
-create_generated_clock -name sys_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1]
+# create_generated_clock -name cpu_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0]
+# create_generated_clock -name sys_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1]
 
-set_clock_groups -asynchronous -group [get_clocks cpu_clk] -group [get_clocks sys_clk]
+# set_clock_groups -asynchronous -group [get_clocks cpu_clk] -group [get_clocks sys_clk]
+
+create_generated_clock -name cpu_clk  [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0]
+create_generated_clock -name sys_clk  [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1]
+create_generated_clock -name mlkem_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2]
+
+set_clock_groups -asynchronous \
+    -group [get_clocks cpu_clk] \
+    -group [get_clocks sys_clk] \
+    -group [get_clocks mlkem_clk]
 
 set_input_delay -clock sys_clk -max 3   [get_ports {base_ram_data[*]}]
 set_input_delay -clock sys_clk -min 2   [get_ports {base_ram_data[*]}]

fpga/vivado_reports_nodsp/clock_interaction.rpt

@@ -0,0 +1,39 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+<<<<<<< Updated upstream
+| Date         : Fri Jul 10 04:14:55 2026
+=======
+| Date         : Sat Jul 11 09:20:56 2026
+>>>>>>> Stashed changes
+| Host         : fedora running 64-bit unknown
+| Command      : report_clock_interaction -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/clock_interaction.rpt
+| Design       : soc_top
+| Device       : 7a200t-fbg676
+| Speed File   : -1  PRODUCTION 1.23 2018-06-13
+--------------------------------------------------------------------------------------------------------------------------------------------------
+
+Clock Interaction Report
+
+Clock Interaction Table
+-----------------------
+
+                                    WNS                            TNS Failing  TNS Total    WNS Path         Clock-Pair           Inter-Clock          
+From Clock        To Clock          Clock Edges  WNS(ns)  TNS(ns)    Endpoints    Endpoints  Requirement(ns)  Classification       Constraints          
+----------------  ----------------  -----------  -------  -------  -----------  -----------  ---------------  -------------------  -------------------  
+<<<<<<< Updated upstream
+cpu_clk           cpu_clk           rise - rise     1.51     0.00            0        17264            30.32  Clean                Timed                
+cpu_clk           sys_clk                                                    0          154                   Ignored              Asynchronous Groups  
+sys_clk           cpu_clk                                                    0           59                   Ignored              Asynchronous Groups  
+sys_clk           sys_clk           rise - rise     0.15     0.00            0        96069            20.00  Clean                Timed                
+=======
+cpu_clk           cpu_clk           rise - rise     0.74     0.00            0        17264            30.00  Clean                Timed                
+cpu_clk           sys_clk                                                    0          162                   Ignored              Asynchronous Groups  
+mlkem_clk         mlkem_clk         rise - rise     0.07     0.00            0        48386            13.00  Clean                Timed                
+mlkem_clk         sys_clk                                                    0           61                   Ignored              Asynchronous Groups  
+sys_clk           cpu_clk                                                    0           59                   Ignored              Asynchronous Groups  
+sys_clk           mlkem_clk                                                  0          112                   Ignored              Asynchronous Groups  
+sys_clk           sys_clk           rise - rise     0.12     0.00            0        23193            20.00  Clean                Timed                
+>>>>>>> Stashed changes
+
+

fpga/vivado_reports_nodsp/clocks.rpt

@@ -0,0 +1,87 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+<<<<<<< Updated upstream
+| Date         : Fri Jul 10 04:14:54 2026
+=======
+| Date         : Sat Jul 11 09:20:56 2026
+>>>>>>> Stashed changes
+| Host         : fedora running 64-bit unknown
+| Command      : report_clocks -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/clocks.rpt
+| Design       : soc_top
+| Device       : 7a200t-fbg676
+| Speed File   : -1  PRODUCTION 1.23 2018-06-13
+----------------------------------------------------------------------------------------------------------------------------
+
+Clock Report
+
+
+Attributes
+  P: Propagated
+  G: Generated
+  A: Auto-derived
+  R: Renamed
+  V: Virtual
+  I: Inverted
+  S: Pin phase-shifted with Latency mode
+
+Clock             Period(ns)  Waveform(ns)    Attributes  Sources
+clk               20.000      {0.000 10.000}  P           {clk}
+clkfbout_clk_pll  20.000      {0.000 10.000}  P,G,A       {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
+<<<<<<< Updated upstream
+cpu_clk           30.323      {0.000 15.161}  P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
+=======
+cpu_clk           30.000      {0.000 15.000}  P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
+mlkem_clk         13.000      {0.000 6.500}   P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
+>>>>>>> Stashed changes
+sys_clk           20.000      {0.000 10.000}  P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
+
+
+====================================================
+Generated Clocks
+====================================================
+
+Generated Clock     : clkfbout_clk_pll
+Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
+Master Clock        : clk
+Multiply By         : 1
+Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
+
+Generated Clock     : cpu_clk
+Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
+Master Clock        : clk
+Edges               : {1 2 3}
+Edge Shifts(ns)     : {0.000 5.000 10.000}
+Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
+
+<<<<<<< Updated upstream
+=======
+Generated Clock     : mlkem_clk
+Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
+Master Clock        : clk
+Edges               : {1 2 3}
+Edge Shifts(ns)     : {0.000 -3.500 -7.000}
+Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
+
+>>>>>>> Stashed changes
+Generated Clock     : sys_clk
+Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
+Master Clock        : clk
+Multiply By         : 1
+Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
+
+
+
+====================================================
+User Uncertainty
+====================================================
+
+
+
+====================================================
+User Jitter
+====================================================
+
+Clock  Jitter(ns)
+clk    0.200
+

fpga/vivado_reports_nodsp/design_analysis_complexity.rpt

@@ -0,0 +1,54 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+<<<<<<< Updated upstream
+| Date         : Fri Jul 10 04:15:40 2026
+=======
+| Date         : Sat Jul 11 09:21:26 2026
+>>>>>>> Stashed changes
+| Host         : fedora running 64-bit unknown
+| Command      : report_design_analysis -complexity -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/design_analysis_complexity.rpt
+| Design       : soc_top
+| Device       : xc7a200t
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Report Design Analysis
+
+Table of Contents
+-----------------
+1. Complexity Characteristics (Cells)
+
+1. Complexity Characteristics (Cells)
+-------------------------------------
+
+<<<<<<< Updated upstream
++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+--------------+--------------+--------------+------------+-----+------+------+------+
+|          Instance         |        Module       | Rent | Average Fanout | Total Instances |    LUT1   |     LUT2    |     LUT3     |     LUT4     |     LUT5     |     LUT6     | Memory LUT | DSP | RAMB | MUXF | URAM |
++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+--------------+--------------+--------------+------------+-----+------+------+------+
+| (top)                     |             soc_top | 0.31 |           3.78 |          131904 | 802(1.0%) | 9228(11.4%) | 10135(12.5%) | 10316(12.7%) | 12781(15.7%) | 37981(46.7%) |       1175 |   0 |   41 | 6069 |    0 |
+|  u_axi_axil_adapter       |    axi_axil_adapter | 0.37 |           4.65 |            1624 |   0(0.0%) |    25(1.8%) |     36(2.6%) |   860(61.8%) |   202(14.5%) |   269(19.3%) |          0 |   0 |    0 |   62 |    0 |
+|  u_axi_uart_controller    | axi_uart_controller | 0.55 |           3.54 |            1296 |  10(1.2%) |   84(10.4%) |     80(9.9%) |   144(17.9%) |   194(24.1%) |   293(36.4%) |          0 |   0 |    0 |    9 |    0 |
+|  u_cpu                    |            core_top | 0.59 |           3.96 |           15822 | 168(1.8%) |   579(6.3%) |  1029(11.1%) |    871(9.4%) |  1744(18.9%) |  4860(52.5%) |          0 |   0 |   20 |  276 |    0 |
+|  u_fft_mlkem_axi_slave    | fft_mlkem_axi_slave | 0.41 |           3.78 |           87846 | 374(0.7%) | 6103(11.5%) |  7425(14.0%) |  6353(12.0%) |  8174(15.5%) | 24445(46.2%) |       1169 |   0 |   20 | 5269 |    0 |
+|  u_matmul_axi_slave       |    matmul_axi_slave | 0.60 |           3.76 |           15711 |  18(0.2%) | 1632(14.3%) |    345(3.0%) |    805(7.1%) |  1733(15.2%) |  6875(60.3%) |          6 |   0 |    0 |  417 |    0 |
+|  u_snix_axil_cdma_mux_8ch |  snix_axil_cdma_mux | 0.46 |           3.31 |            3435 | 136(7.4%) |  239(12.9%) |   432(23.4%) |   301(16.3%) |   234(12.6%) |   508(27.5%) |          0 |   0 |    1 |    4 |    0 |
++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+--------------+--------------+--------------+------------+-----+------+------+------+
+=======
++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+-------------+-------------+--------------+------------+-----+------+------+------+
+|          Instance         |        Module       | Rent | Average Fanout | Total Instances |    LUT1   |     LUT2    |     LUT3     |     LUT4    |     LUT5    |     LUT6     | Memory LUT | DSP | RAMB | MUXF | URAM |
++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+-------------+-------------+--------------+------------+-----+------+------+------+
+| (top)                     |             soc_top | 0.37 |           3.61 |          102050 | 871(1.4%) | 8543(13.4%) | 10370(16.3%) | 8684(13.7%) | 8274(13.0%) | 26800(42.2%) |       1216 |   0 |   49 | 2433 |    0 |
+|  u_axi_axil_adapter       |    axi_axil_adapter | 0.43 |           4.86 |            1534 |   0(0.0%) |    28(2.2%) |     37(2.8%) |  763(58.6%) |  216(16.6%) |   258(19.8%) |          0 |   0 |    0 |   62 |    0 |
+|  u_axi_uart_controller    | axi_uart_controller | 0.55 |           3.54 |            1296 |  10(1.2%) |   84(10.4%) |     80(9.9%) |  144(17.9%) |  194(24.1%) |   293(36.4%) |          0 |   0 |    0 |    9 |    0 |
+|  u_cpu                    |            core_top | 0.62 |           3.96 |           15822 | 168(1.8%) |   579(6.3%) |  1029(11.1%) |   871(9.4%) | 1744(18.9%) |  4860(52.5%) |          0 |   0 |   20 |  276 |    0 |
+|  u_fft_mlkem_axi_slave    | fft_mlkem_axi_slave | 0.35 |           3.49 |           58249 | 424(1.2%) | 5455(15.4%) |  7551(21.3%) | 4691(13.2%) | 4348(12.2%) | 13041(36.7%) |       1210 |   0 |   28 | 1632 |    0 |
+|  u_matmul_axi_slave       |    matmul_axi_slave | 0.58 |           3.76 |           15281 |  18(0.2%) | 1640(14.9%) |    369(3.4%) |   792(7.2%) |  1009(9.2%) |  7145(65.1%) |          6 |   0 |    0 |  418 |    0 |
+|  u_snix_axil_cdma_mux_8ch |  snix_axil_cdma_mux | 0.41 |           3.25 |            3423 | 136(7.4%) |  183(10.0%) |   430(23.4%) |  401(21.8%) |  243(13.2%) |   445(24.2%) |          0 |   0 |    1 |    4 |    0 |
++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+-------------+-------------+--------------+------------+-----+------+------+------+
+>>>>>>> Stashed changes
+* Complexity Ranges 
+** 0.0 - 0.3 -> Very Low, 0.3 - 0.5 -> low, 0.5 - 0.65 -> normal,  0.65 - 0.85 -> high, 0.85 - 1.0 -> very high
+*** -* -> Not computable as cell size is very small
+
+

fpga/vivado_reports_nodsp/design_analysis_timing.rpt

@@ -0,0 +1,88 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+<<<<<<< Updated upstream
+| Date         : Fri Jul 10 04:15:09 2026
+=======
+| Date         : Sat Jul 11 09:21:05 2026
+>>>>>>> Stashed changes
+| Host         : fedora running 64-bit unknown
+| Command      : report_design_analysis -timing -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/design_analysis_timing.rpt
+| Design       : soc_top
+| Device       : xc7a200t
+| Design State : Routed
+-------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Report Design Analysis
+
+Table of Contents
+-----------------
+1. Setup Path Characteristics 1-1
+
+1. Setup Path Characteristics 1-1
+---------------------------------
+
+<<<<<<< Updated upstream
++---------------------------+----------------------------------------------------------------------------------------+
+|      Characteristics      |                                         Path #1                                        |
++---------------------------+----------------------------------------------------------------------------------------+
+| Requirement               |                                                                                 20.000 |
+| Path Delay                |                                                                                 15.529 |
+| Logic Delay               | 6.868(45%)                                                                             |
+| Net Delay                 | 8.661(55%)                                                                             |
+| Clock Skew                |                                                                                 -3.955 |
+| Slack                     |                                                                                  0.146 |
+| Clock Relationship        | Safely Timed                                                                           |
+| Logic Levels              |                                                                                     14 |
+| Routes                    |                                                                                     12 |
+| Logical Path              | FDCE LUT4 LUT5 LUT6 CARRY4 CARRY4 CARRY4 CARRY4 LUT4 CARRY4 CARRY4 LUT6 LUT6 LUT6 OBUF |
+| Start Point Clock         | sys_clk                                                                                |
+| End Point Clock           | sys_clk                                                                                |
+| DSP Block                 | None                                                                                   |
+| BRAM                      | None                                                                                   |
+| IO Crossings              |                                                                                      3 |
+| Config Crossings          |                                                                                      0 |
+| SLR Crossings             |                                                                                      0 |
+| PBlocks                   |                                                                                      0 |
+| High Fanout               |                                                                                     80 |
+| Dont Touch                |                                                                                      0 |
+| Mark Debug                |                                                                                      0 |
+| Start Point Pin Primitive | FDCE/C                                                                                 |
+| End Point Pin Primitive   | base_ram_be_n[3]                                                                       |
+| Start Point Pin           | ax_req_q_len_reg[3]/C                                                                  |
+| End Point Pin             | base_ram_be_n[3]                                                                       |
++---------------------------+----------------------------------------------------------------------------------------+
+=======
++---------------------------+-----------------------+
+|      Characteristics      |        Path #1        |
++---------------------------+-----------------------+
+| Requirement               |                13.000 |
+| Path Delay                |                13.035 |
+| Logic Delay               | 0.752(6%)             |
+| Net Delay                 | 12.283(94%)           |
+| Clock Skew                |                 0.135 |
+| Slack                     |                 0.070 |
+| Clock Relationship        | Safely Timed          |
+| Logic Levels              |                     1 |
+| Routes                    |                     1 |
+| Logical Path              | FDRE MUXF7 FDCE       |
+| Start Point Clock         | mlkem_clk             |
+| End Point Clock           | mlkem_clk             |
+| DSP Block                 | None                  |
+| BRAM                      | None                  |
+| IO Crossings              |                     0 |
+| Config Crossings          |                     0 |
+| SLR Crossings             |                     0 |
+| PBlocks                   |                     0 |
+| High Fanout               |                  1088 |
+| Dont Touch                |                     0 |
+| Mark Debug                |                     0 |
+| Start Point Pin Primitive | FDRE/C                |
+| End Point Pin Primitive   | FDCE/D                |
+| Start Point Pin           | dj_wb_inz_reg/C       |
+| End Point Pin             | dj_block_r_reg[732]/D |
++---------------------------+-----------------------+
+>>>>>>> Stashed changes
+* Bounding box calculated as % of dimensions for the target device (436, 500)
+
+

fpga/vivado_reports_nodsp/drc.rpt

@@ -0,0 +1,252 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+<<<<<<< Updated upstream
+| Date         : Fri Jul 10 04:14:40 2026
+=======
+| Date         : Sat Jul 11 09:20:47 2026
+>>>>>>> Stashed changes
+| Host         : fedora running 64-bit unknown
+| Command      : report_drc -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/drc.rpt
+| Design       : soc_top
+| Device       : xc7a200tfbg676-1
+| Speed File   : -1
+| Design State : Fully Routed
+----------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: impl_1
+      Design limits: <entire design considered>
+           Ruledeck: default
+             Max violations: <unlimited>
+             Violations found: 42
++-----------+----------+----------------------------+------------+
+| Rule      | Severity | Description                | Violations |
++-----------+----------+----------------------------+------------+
+| CHECK-3   | Warning  | Report rule limit reached  | 2          |
+| REQP-1839 | Warning  | RAMB36 async control check | 20         |
+| REQP-1840 | Warning  | RAMB18 async control check | 20         |
++-----------+----------+----------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+CHECK-3#1 Warning
+Report rule limit reached  
+REQP-1839 rule limit reached: 20 violations have been found.
+Related violations: <none>
+
+CHECK-3#2 Warning
+Report rule limit reached  
+REQP-1840 rule limit reached: 20 violations have been found.
+Related violations: <none>
+
+REQP-1839#1 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#2 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#3 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#4 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#5 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#6 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#7 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#8 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#9 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#10 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#11 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#12 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#13 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#14 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#15 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#16 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#17 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#18 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#19 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#20 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#1 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#2 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#3 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#4 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#5 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#6 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#7 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#8 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#9 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#10 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#11 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#12 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#13 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#14 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#15 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#16 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#17 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENARDEN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_1__15_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#18 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENBWREN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_2__13_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#19 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[2] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#20 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[3] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+

fpga/vivado_reports_nodsp/high_fanout.rpt

@@ -0,0 +1,406 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+<<<<<<< Updated upstream
+| Date         : Fri Jul 10 04:14:55 2026
+=======
+| Date         : Sat Jul 11 09:20:57 2026
+>>>>>>> Stashed changes
+| Host         : fedora running 64-bit unknown
+| Command      : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/high_fanout.rpt
+| Design       : soc_top
+| Device       : xc7a200t
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+High Fan-out Nets Information
+
+1. Summary
+----------
+
++---------------------------------------------------------------------------------------+--------+-------------+
+| Net Name                                                                              | Fanout | Driver Type |
++---------------------------------------------------------------------------------------+--------+-------------+
+<<<<<<< Updated upstream
+| pll_clk.u_clk_pll/inst/sys_clk                                                        |  35652 | BUFG        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/delay_reg[1]                |  24670 | LUT5        |
+| pll_clk.u_rst_sys/p_0_in                                                              |   5108 | LUT1        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[0]                    |   3758 | FDCE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_0                                        |   2151 | FDRE        |
+=======
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/delay_reg[1]               |  15647 | LUT5        |
+| pll_clk.u_clk_pll/inst/sys_clk                                                        |   9971 | BUFG        |
+| pll_clk.u_rst_sys/p_0_in                                                              |   4121 | LUT1        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mb_en                   |   2121 | LUT6        |
+>>>>>>> Stashed changes
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/E[0]                         |   2048 | LUT2        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[0]_0                                        |   2018 | FDSE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_n_0               |   1619 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0        |   1613 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_0[0]              |   1608 | LUT2        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sel_cbd                      |   1603 | LUT5        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0           |   1601 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_6_n_0           |   1601 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_7_n_0           |   1601 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0       |   1600 | LUT4        |
+<<<<<<< Updated upstream
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[1]                   |   1543 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[2]                   |   1542 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active                             |   1130 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1                 |   1109 | LUT2        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0                     |   1088 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0                     |   1088 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_mb_en0                           |    938 | LUT5        |
+| u_matmul_axi_slave/w_addr[2]                                                          |    873 | FDRE        |
+| u_cpu/reset                                                                           |    799 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[0]  |    769 | CARRY4      |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[1]  |    769 | CARRY4      |
+| u_cpu/u_mul/E[0]                                                                      |    716 | LUT1        |
+| u_matmul_axi_slave/w_addr[4]                                                          |    655 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r1                                  |    525 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[1]                   |    518 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[0]                   |    515 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0              |    512 | LUT2        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[3]_0[0]                 |    512 | LUT5        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[2]  |    385 | CARRY4      |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_vld_reg_n_0                      |    370 | FDCE        |
+=======
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in                     |   1344 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1                 |   1109 | LUT2        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0                     |   1088 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0                     |   1088 | FDRE        |
+| pll_clk.u_rst_mlkem/delay_reg[1]_1                                                    |   1066 | LUT1        |
+| u_cpu/reset                                                                           |    799 | FDRE        |
+| u_cpu/u_mul/E[0]                                                                      |    716 | LUT1        |
+| u_matmul_axi_slave/w_addr[2]                                                          |    644 | FDRE        |
+| u_matmul_axi_slave/current_r_offset[2]                                                |    524 | LUT5        |
+| u_matmul_axi_slave/current_r_offset[3]                                                |    522 | LUT5        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[2]_rep__3[0]            |    513 | LUT5        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0              |    512 | LUT2        |
+>>>>>>> Stashed changes
+| u_cpu/wb_stage/w_index[0]                                                             |    358 | LUT6        |
+| u_cpu/wb_stage/w_index[1]                                                             |    358 | LUT6        |
+| u_cpu/wb_stage/w_index[2]                                                             |    358 | LUT6        |
+| u_cpu/wb_stage/w_index[3]                                                             |    358 | LUT6        |
+| u_cpu/wb_stage/w_index[4]                                                             |    358 | LUT6        |
+| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 |    357 | LUT3        |
+| u_matmul_axi_slave/pipe_cnt[3]_i_3_n_0                                                |    356 | LUT3        |
+| u_matmul_axi_slave/acc_idx_d4[0]                                                      |    354 | FDRE        |
+| u_matmul_axi_slave/acc_idx_d4[1]                                                      |    354 | FDRE        |
+| u_matmul_axi_slave/acc_idx_d4[2]                                                      |    354 | FDRE        |
+| u_matmul_axi_slave/acc_idx_d4[3]                                                      |    354 | FDRE        |
+| u_cpu/wb_stage/we_0                                                                   |    324 | LUT4        |
+<<<<<<< Updated upstream
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1                         |    293 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r2[4]                             |    288 | CARRY4      |
+| u_matmul_axi_slave/cur_bank_reg_n_0                                                   |    274 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc                      |    261 | LUT5        |
+| u_matmul_axi_slave/sel0[1]                                                            |    259 | FDRE        |
+| u_matmul_axi_slave/b1_b_reg[0][31]_i_8_n_7                                            |    258 | CARRY4      |
+| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0                                            |    258 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10]                 |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11]                 |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10]                 |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11]                 |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9]                  |    256 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/dj_phase_reg[1]_0[0]           |    256 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r                    |    256 | LUT3        |
+| u_matmul_axi_slave/m_in_a[3][31]_i_1_n_0                                              |    256 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode                    |    250 | LUT4        |
+| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge                                  |    245 | LUT2        |
+| u_matmul_axi_slave/b0_a[6][25]_i_2_n_0                                                |    242 | LUT2        |
+| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 |    239 | LUT3        |
+| u_matmul_axi_slave/m_in_a[3][30]_i_6_n_0                                              |    238 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6]                      |    237 | FDCE        |
+| u_cpu/exe_stage/ds_to_es_bus_r0                                                       |    234 | LUT5        |
+| u_cpu/mem_stage/E[0]                                                                  |    234 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[3]                      |    231 | FDCE        |
+=======
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1                         |    289 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r_reg[255]_i_5_n_4                |    288 | CARRY4      |
+| u_matmul_axi_slave/w_addr[4]                                                          |    286 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc                      |    260 | LUT5        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/E[0]                           |    256 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r                    |    256 | LUT3        |
+| u_matmul_axi_slave/m_in_a[3][31]_i_1_n_0                                              |    256 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode                    |    250 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN_7                      |    248 | FDCE        |
+| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge                                  |    245 | LUT3        |
+| u_cpu/exe_stage/ds_to_es_bus_r0                                                       |    234 | LUT5        |
+| u_cpu/mem_stage/E[0]                                                                  |    234 | LUT6        |
+>>>>>>> Stashed changes
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1022]_i_2_n_0              |    224 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[126]_i_2_n_0               |    224 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[254]_i_2_n_0               |    224 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[382]_i_2_n_0               |    224 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[510]_i_2_n_0               |    224 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[638]_i_2_n_0               |    224 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[766]_i_2_n_0               |    224 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[894]_i_2_n_0               |    224 | LUT4        |
+<<<<<<< Updated upstream
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10]                   |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11]                   |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9]                    |    219 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[5]                      |    219 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10]                  |    216 | RAMB18E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11]                  |    216 | RAMB18E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8]                   |    215 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[2]                      |    215 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7]                   |    214 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9]                   |    214 | RAMB18E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4]                      |    214 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0]                   |    212 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1]                   |    212 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2]                   |    212 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3]                   |    212 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4]                   |    212 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5]                   |    212 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6]                   |    212 | RAMB36E1    |
+| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0                            |    211 | LUT2        |
+| u_cpu/mem_stage/es_to_ms_bus_r0                                                       |    210 | LUT2        |
+| u_cpu/u_csr/tlbw_r_tlbidx[2]                                                          |    210 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[7]                      |    207 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1]                      |    206 | FDCE        |
+=======
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN_2                      |    222 | FDCE        |
+| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0                            |    211 | LUT2        |
+| u_cpu/mem_stage/es_to_ms_bus_r0                                                       |    210 | LUT2        |
+| u_cpu/u_csr/tlbw_r_tlbidx[2]                                                          |    210 | FDRE        |
+>>>>>>> Stashed changes
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/grp_ptr_r_reg_n_0_[2]           |    196 | FDCE        |
+| u_cpu/wb_stage/Q[33]                                                                  |    194 | FDRE        |
+| u_cpu/wb_stage/Q[34]                                                                  |    194 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[5]             |    194 | FDCE        |
+<<<<<<< Updated upstream
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[3]  |    193 | CARRY4      |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg_n_0_[3]                            |    187 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[2]                    |    186 | FDCE        |
+| u_cpu/wb_stage/ws_valid_reg_0                                                         |    180 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2]                             |    180 | FDCE        |
+| u_matmul_axi_slave/b0_b_reg[1][30]_i_4_n_7                                            |    178 | CARRY4      |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]                                 |    176 | FDCE        |
+=======
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[2]_rep_n_0                         |    191 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_6        |    186 | FDCE        |
+| u_matmul_axi_slave/w_addr[5]                                                          |    184 | FDRE        |
+| u_cpu/wb_stage/ws_valid_reg_0                                                         |    180 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_1        |    179 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2]                             |    178 | FDCE        |
+| u_matmul_axi_slave/b1_b[0][31]_i_7_n_0                                                |    177 | LUT3        |
+>>>>>>> Stashed changes
+| u_matmul_axi_slave/p_0_in__0                                                          |    176 | LUT4        |
+| u_matmul_axi_slave/p_0_in__0__0                                                       |    176 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt114_out                |    175 | LUT2        |
+| u_cpu/wb_stage/Q[37]                                                                  |    173 | FDRE        |
+<<<<<<< Updated upstream
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]_rep__0_n_0     |    172 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[131][11]_i_4_n_0         |    171 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[127]_i_2_n_0                |    169 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[383]_i_2_n_0                |    169 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[639]_i_2_n_0                |    169 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[895]_i_2_n_0                |    169 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r2[3]                             |    169 | CARRY4      |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[74][11]_i_4_n_0          |    168 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[6]_0[0]                            |    168 | CARRY4      |
+| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[6]_0                |    167 | LUT2        |
+| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[6]_1                |    167 | LUT2        |
+| u_snix_axil_cdma_mux_8ch/ADDRA[0]                                                     |    167 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[129][11]_i_3_n_0         |    166 | LUT3        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__0_n_0                               |    165 | FDRE        |
+=======
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_2        |    172 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r_reg[255]_i_5_n_5                |    171 | CARRY4      |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/z_word_reg[1][31]_i_6_n_7                     |    170 | CARRY4      |
+| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0                                                |    170 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_4        |    168 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/z_word_reg[1][31]_i_6_n_6                     |    168 | CARRY4      |
+>>>>>>> Stashed changes
+| u_cpu/wb_stage/Q[32]                                                                  |    164 | FDRE        |
+| u_cpu/wb_stage/Q[35]                                                                  |    163 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg[0]_rep__0_n_0             |    163 | FDCE        |
+| u_cpu/wb_stage/Q[36]                                                                  |    162 | FDRE        |
+<<<<<<< Updated upstream
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1023]_i_2_n_0               |    160 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[255]_i_2_n_0                |    160 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[511]_i_2_n_0                |    160 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[767]_i_2_n_0                |    160 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__12_n_0    |    158 | FDCE        |
+| u_matmul_axi_slave/w_addr_reg[3]_rep__2_0                                             |    158 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[181][5]_i_3_n_0              |    157 | LUT2        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[6]                    |    156 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3]                             |    155 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[7]                    |    155 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[3]                      |    154 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[4]                      |    154 | FDCE        |
+| u_matmul_axi_slave/w_addr[3]                                                          |    153 | FDRE        |
+=======
+| u_matmul_axi_slave/pipe_cnt_reg_n_0_[3]                                               |    162 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_0_5_i_34_n_0                      |    161 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg_n_0_[3]                            |    158 | FDRE        |
+| u_axi_axil_adapter/axi_axil_adapter_rd_inst/m_axil_araddr_reg_reg[2]_0                |    157 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3]                             |    156 | FDCE        |
+| u_matmul_axi_slave/w_addr_reg[3]_rep_n_0                                              |    153 | FDRE        |
+>>>>>>> Stashed changes
+| u_cpu/axi_bridge/FSM_sequential_write_requst_state_reg[1]_0                           |    151 | FDRE        |
+| u_snix_axil_cdma_mux_8ch/u_core_engine/num_bytes_comb1                                |    150 | CARRY4      |
+| u_cpu/dcache/awaddr[31]_i_3_n_0                                                       |    148 | LUT2        |
+| u_cpu/dcache/awaddr[31]_i_4_n_0                                                       |    148 | LUT2        |
+<<<<<<< Updated upstream
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1]                      |    148 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[202][11]_i_3_n_0         |    148 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0]                      |    147 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__1_n_0     |    146 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep_n_0        |    146 | FDCE        |
+| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0                                                |    146 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[0]                  |    145 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__10_n_0    |    145 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[2]                      |    144 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/hek_r[247]_i_3_n_0             |    144 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/hek_r[255]_i_3_n_0             |    144 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__17_n_0    |    143 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[106][11]_i_3_n_0         |    143 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6]                            |    142 | FDCE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[0]                                     |    142 | FDSE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[5]                      |    141 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[5]                    |    141 | FDCE        |
+| u_cpu/dcache/write_buffer_state                                                       |    140 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4]                            |    140 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[5]                            |    140 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[7]                            |    140 | FDCE        |
+=======
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN                        |    148 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_10       |    146 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_9        |    143 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]                                 |    142 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_0_5_i_43_n_0                      |    141 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_12_17_i_57_n_0                    |    141 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[4]                  |    141 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[5]                  |    141 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[6]                  |    141 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[7]                  |    141 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6]                            |    141 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[7]                            |    141 | FDCE        |
+| u_cpu/dcache/write_buffer_state                                                       |    140 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4]                            |    140 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep__3_n_0                  |    140 | FDCE        |
+| u_cpu/u_csr/tlbw_r_tlbidx[0]                                                          |    139 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[5]                            |    139 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN_3                      |    138 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[3]                  |    138 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx_reg[6]_rep_n_0                |    138 | FDCE        |
+| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[7]_1                |    137 | LUT2        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx_reg[4]_rep_n_0                |    137 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx_reg[5]_rep_n_0                |    137 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg_n_0_[2]                            |    137 | FDRE        |
+| u_matmul_axi_slave/pipe_cnt_reg[1]_rep_n_0                                            |    137 | FDRE        |
+| u_cpu/u_csr/tlbw_r_tlbidx[1]                                                          |    136 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1080]_i_5_n_0              |    136 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1081]_i_5_n_0              |    136 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1082]_i_5_n_0              |    136 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1083]_i_5_n_0              |    136 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1084]_i_6_n_0              |    136 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1087]_i_3_n_0              |    136 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1087]_i_9_n_0              |    136 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1087]_i_3_n_0               |    136 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx_reg[7]_rep_n_0                |    136 | FDCE        |
+| u_matmul_axi_slave/b1_b[0][31]_i_8_n_0                                                |    136 | LUT2        |
+| u_snix_axil_cdma_mux_8ch/ep_rd_elem[0]                                                |    136 | LUT6        |
+| u_snix_axil_cdma_mux_8ch/ep_rd_elem[1]                                                |    136 | LUT5        |
+| u_snix_axil_cdma_mux_8ch/ep_rd_elem[2]                                                |    135 | LUT6        |
+| u_snix_axil_cdma_mux_8ch/ep_rd_elem[3]                                                |    135 | LUT5        |
+| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[6]_0                |    134 | LUT2        |
+| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[7]_0                |    134 | LUT2        |
+| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[7]_2                |    134 | LUT2        |
+| u_matmul_axi_slave/w_addr[3]                                                          |    134 | FDRE        |
+| u_axi_axil_adapter/axi_axil_adapter_rd_inst/s_axil_rdata[29]_i_7_n_0                  |    133 | LUT2        |
+| u_axi_axil_adapter/axi_axil_adapter_rd_inst/s_axil_rdata[29]_i_9_n_0                  |    133 | LUT2        |
+| u_axi_axil_adapter/axi_axil_adapter_rd_inst/s_axil_rdata[31]_i_12_n_0                 |    133 | LUT2        |
+| u_axi_axil_adapter/axi_axil_adapter_rd_inst/s_axil_rdata[31]_i_13_n_0                 |    133 | LUT2        |
+| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[3]_0                |    133 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/dbg_dk_idx[4]                                 |    133 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/dbg_dk_idx[3]                                 |    132 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN_4                      |    132 | FDCE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[2]                                     |    132 | FDRE        |
+| u_matmul_axi_slave/c1_elem[0]                                                         |    132 | LUT6        |
+| u_matmul_axi_slave/c1_elem[1]                                                         |    132 | LUT5        |
+| u_matmul_axi_slave/c1_elem[2]                                                         |    132 | LUT4        |
+| u_matmul_axi_slave/c1_elem[3]                                                         |    132 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep_n_0                     |    131 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_reject                            |    130 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_8        |    130 | FDCE        |
+| u_matmul_axi_slave/pipe_cnt_reg_n_0_[1]                                               |    130 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[1]                                     |    129 | FDRE        |
+| u_confreg/s_rdata[31]_i_8_n_0                                                         |    128 | LUT3        |
+| u_confreg/s_rdata[31]_i_9_n_0                                                         |    128 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_reject_reg_rep_n_0                |    128 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[0]                  |    128 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[1]                  |    128 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[2]                  |    128 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[4]             |    128 | FDCE        |
+| u_matmul_axi_slave/current_r_offset[5]                                                |    128 | LUT3        |
+| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0                                            |    128 | FDRE        |
+| u_matmul_axi_slave/pipe_cnt_reg_n_0_[0]                                               |    128 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__0_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__10_n_0                              |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__1_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__2_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__3_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__4_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__5_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__6_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__7_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__8_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__9_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep_n_0                                  |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__10_n_0                              |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__11_n_0                              |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__12_n_0                              |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__13_n_0                              |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__2_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__3_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__4_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__5_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__6_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__7_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__8_n_0                               |    127 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__9_n_0                               |    127 | FDRE        |
+| u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]                                           |    127 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep__0_n_0                  |    126 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep__1_n_0                  |    126 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep__2_n_0                  |    126 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_3        |    126 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/state[1]                        |    126 | FDCE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__11_0                                |    126 | FDRE        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__1_n_0                               |    126 | FDRE        |
+| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[0]                                           |    126 | FDRE        |
+>>>>>>> Stashed changes
++---------------------------------------------------------------------------------------+--------+-------------+
+
+

fpga/vivado_reports_nodsp/methodology.rpt

@@ -0,0 +1,679 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+<<<<<<< Updated upstream
+| Date         : Fri Jul 10 04:14:46 2026
+=======
+| Date         : Sat Jul 11 09:20:51 2026
+>>>>>>> Stashed changes
+| Host         : fedora running 64-bit unknown
+| Command      : report_methodology -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/methodology.rpt
+| Design       : soc_top
+| Device       : xc7a200tfbg676-1
+| Speed File   : -1
+| Design State : Fully Routed
+--------------------------------------------------------------------------------------------------------------------------------------
+
+Report Methodology
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: impl_1
+      Design limits: <entire design considered>
+             Max violations: <unlimited>
+<<<<<<< Updated upstream
+             Violations found: 107
+=======
+             Violations found: 115
+>>>>>>> Stashed changes
++-----------+----------+-------------------------------------------------------------------+------------+
+| Rule      | Severity | Description                                                       | Violations |
++-----------+----------+-------------------------------------------------------------------+------------+
+| LUTAR-1   | Warning  | LUT drives async reset alert                                      | 1          |
+| SYNTH-5   | Warning  | Mapped onto distributed RAM because of timing constraints         | 8          |
+<<<<<<< Updated upstream
+| SYNTH-6   | Warning  | Timing of a block RAM might be sub-optimal                        | 9          |
+| SYNTH-16  | Warning  | Address collision                                                 | 8          |
+=======
+| SYNTH-6   | Warning  | Timing of a block RAM might be sub-optimal                        | 6          |
+| SYNTH-16  | Warning  | Address collision                                                 | 16         |
+| TIMING-9  | Warning  | Unknown CDC Logic                                                 | 1          |
+>>>>>>> Stashed changes
+| TIMING-10 | Warning  | Missing property on synchronizer                                  | 1          |
+| TIMING-18 | Warning  | Missing input or output delay                                     | 76         |
+| TIMING-47 | Warning  | False path or asynchronous clock group between synchronous clocks | 4          |
+| XDCC-1    | Warning  | Scoped Clock constraint overwritten with the same name            | 1          |
+| XDCC-7    | Warning  | Scoped Clock constraint overwritten on the same source            | 1          |
++-----------+----------+-------------------------------------------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+LUTAR-1#1 Warning
+LUT drives async reset alert  
+<<<<<<< Updated upstream
+LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 24656 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
+=======
+LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 15633 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
+>>>>>>> Stashed changes
+Related violations: <none>
+
+SYNTH-5#1 Warning
+Mapped onto distributed RAM because of timing constraints  
+The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
+Related violations: <none>
+
+SYNTH-5#2 Warning
+Mapped onto distributed RAM because of timing constraints  
+The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
+Related violations: <none>
+
+SYNTH-5#3 Warning
+Mapped onto distributed RAM because of timing constraints  
+The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
+Related violations: <none>
+
+SYNTH-5#4 Warning
+Mapped onto distributed RAM because of timing constraints  
+The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
+Related violations: <none>
+
+SYNTH-5#5 Warning
+Mapped onto distributed RAM because of timing constraints  
+The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
+Related violations: <none>
+
+SYNTH-5#6 Warning
+Mapped onto distributed RAM because of timing constraints  
+The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
+Related violations: <none>
+
+SYNTH-5#7 Warning
+Mapped onto distributed RAM because of timing constraints  
+The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
+Related violations: <none>
+
+SYNTH-5#8 Warning
+Mapped onto distributed RAM because of timing constraints  
+The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
+Related violations: <none>
+
+SYNTH-6#1 Warning
+Timing of a block RAM might be sub-optimal  
+<<<<<<< Updated upstream
+The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+=======
+The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+>>>>>>> Stashed changes
+Related violations: <none>
+
+SYNTH-6#2 Warning
+Timing of a block RAM might be sub-optimal  
+<<<<<<< Updated upstream
+The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+=======
+The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+>>>>>>> Stashed changes
+Related violations: <none>
+
+SYNTH-6#3 Warning
+Timing of a block RAM might be sub-optimal  
+<<<<<<< Updated upstream
+The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+=======
+The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+>>>>>>> Stashed changes
+Related violations: <none>
+
+SYNTH-6#4 Warning
+Timing of a block RAM might be sub-optimal  
+<<<<<<< Updated upstream
+The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+=======
+The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+>>>>>>> Stashed changes
+Related violations: <none>
+
+SYNTH-6#5 Warning
+Timing of a block RAM might be sub-optimal  
+<<<<<<< Updated upstream
+The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+=======
+The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+>>>>>>> Stashed changes
+Related violations: <none>
+
+SYNTH-6#6 Warning
+Timing of a block RAM might be sub-optimal  
+<<<<<<< Updated upstream
+The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+Related violations: <none>
+
+SYNTH-6#7 Warning
+Timing of a block RAM might be sub-optimal  
+The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+Related violations: <none>
+
+SYNTH-6#8 Warning
+Timing of a block RAM might be sub-optimal  
+The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+Related violations: <none>
+
+SYNTH-6#9 Warning
+Timing of a block RAM might be sub-optimal  
+The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+=======
+The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
+>>>>>>> Stashed changes
+Related violations: <none>
+
+SYNTH-16#1 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#2 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#3 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#4 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#5 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#6 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#7 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#8 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#9 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[0].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#10 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#11 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[2].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#12 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[3].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#13 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#14 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#15 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+SYNTH-16#16 Warning
+Address collision  
+Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+TIMING-9#1 Warning
+Unknown CDC Logic  
+One or more asynchronous Clock Domain Crossing has been detected between 2 clock domains through a set_false_path or a set_clock_groups or set_max_delay -datapath_only constraint but no double-registers logic synchronizer has been found on the side of the capture clock. It is recommended to run report_cdc for a complete and detailed CDC coverage. Please consider using XPM_CDC to avoid Critical severities
+Related violations: <none>
+
+TIMING-10#1 Warning
+Missing property on synchronizer  
+One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage
+Related violations: <none>
+
+TIMING-18#1 Warning
+Missing input or output delay  
+An input delay is missing on UART_RX relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#2 Warning
+Missing input or output delay  
+An input delay is missing on UART_TX relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#3 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[0] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#4 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[10] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#5 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[11] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#6 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[12] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#7 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[13] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#8 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[14] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#9 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[15] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#10 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[16] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#11 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[17] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#12 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[18] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#13 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[19] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#14 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[1] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#15 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[20] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#16 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[21] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#17 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[22] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#18 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[23] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#19 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[24] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#20 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[25] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#21 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[26] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#22 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[27] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#23 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[28] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#24 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[29] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#25 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[2] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#26 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[30] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#27 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[31] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#28 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[3] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#29 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[4] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#30 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[5] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#31 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[6] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#32 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[7] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#33 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[8] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#34 Warning
+Missing input or output delay  
+An input delay is missing on dip_sw[9] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#35 Warning
+Missing input or output delay  
+An input delay is missing on touch_btn[0] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#36 Warning
+Missing input or output delay  
+An input delay is missing on touch_btn[1] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#37 Warning
+Missing input or output delay  
+An input delay is missing on touch_btn[2] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#38 Warning
+Missing input or output delay  
+An input delay is missing on touch_btn[3] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#39 Warning
+Missing input or output delay  
+An output delay is missing on dpy0[0] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#40 Warning
+Missing input or output delay  
+An output delay is missing on dpy0[1] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#41 Warning
+Missing input or output delay  
+An output delay is missing on dpy0[2] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#42 Warning
+Missing input or output delay  
+An output delay is missing on dpy0[3] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#43 Warning
+Missing input or output delay  
+An output delay is missing on dpy0[4] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#44 Warning
+Missing input or output delay  
+An output delay is missing on dpy0[5] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#45 Warning
+Missing input or output delay  
+An output delay is missing on dpy0[6] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#46 Warning
+Missing input or output delay  
+An output delay is missing on dpy0[7] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#47 Warning
+Missing input or output delay  
+An output delay is missing on dpy1[0] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#48 Warning
+Missing input or output delay  
+An output delay is missing on dpy1[1] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#49 Warning
+Missing input or output delay  
+An output delay is missing on dpy1[2] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#50 Warning
+Missing input or output delay  
+An output delay is missing on dpy1[3] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#51 Warning
+Missing input or output delay  
+An output delay is missing on dpy1[4] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#52 Warning
+Missing input or output delay  
+An output delay is missing on dpy1[5] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#53 Warning
+Missing input or output delay  
+An output delay is missing on dpy1[6] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#54 Warning
+Missing input or output delay  
+An output delay is missing on dpy1[7] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#55 Warning
+Missing input or output delay  
+An output delay is missing on leds[0] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#56 Warning
+Missing input or output delay  
+An output delay is missing on leds[10] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#57 Warning
+Missing input or output delay  
+An output delay is missing on leds[11] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#58 Warning
+Missing input or output delay  
+An output delay is missing on leds[12] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#59 Warning
+Missing input or output delay  
+An output delay is missing on leds[13] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#60 Warning
+Missing input or output delay  
+An output delay is missing on leds[14] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#61 Warning
+Missing input or output delay  
+An output delay is missing on leds[15] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#62 Warning
+Missing input or output delay  
+An output delay is missing on leds[1] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#63 Warning
+Missing input or output delay  
+An output delay is missing on leds[2] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#64 Warning
+Missing input or output delay  
+An output delay is missing on leds[3] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#65 Warning
+Missing input or output delay  
+An output delay is missing on leds[4] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#66 Warning
+Missing input or output delay  
+An output delay is missing on leds[5] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#67 Warning
+Missing input or output delay  
+An output delay is missing on leds[6] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#68 Warning
+Missing input or output delay  
+An output delay is missing on leds[7] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#69 Warning
+Missing input or output delay  
+An output delay is missing on leds[8] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#70 Warning
+Missing input or output delay  
+An output delay is missing on leds[9] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#71 Warning
+Missing input or output delay  
+An output delay is missing on video_de relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#72 Warning
+Missing input or output delay  
+An output delay is missing on video_hsync relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#73 Warning
+Missing input or output delay  
+An output delay is missing on video_red[0] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#74 Warning
+Missing input or output delay  
+An output delay is missing on video_red[1] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#75 Warning
+Missing input or output delay  
+An output delay is missing on video_red[2] relative to clock(s) clk
+Related violations: <none>
+
+TIMING-18#76 Warning
+Missing input or output delay  
+An output delay is missing on video_vsync relative to clock(s) clk
+Related violations: <none>
+
+TIMING-47#1 Warning
+False path or asynchronous clock group between synchronous clocks  
+A Clock Group timing constraint is set between synchronous clocks cpu_clk and sys_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
+Related violations: <none>
+
+TIMING-47#2 Warning
+False path or asynchronous clock group between synchronous clocks  
+A Clock Group timing constraint is set between synchronous clocks mlkem_clk and sys_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
+Related violations: <none>
+
+TIMING-47#3 Warning
+False path or asynchronous clock group between synchronous clocks  
+A Clock Group timing constraint is set between synchronous clocks sys_clk and cpu_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
+Related violations: <none>
+
+TIMING-47#4 Warning
+False path or asynchronous clock group between synchronous clocks  
+A Clock Group timing constraint is set between synchronous clocks sys_clk and mlkem_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
+Related violations: <none>
+
+XDCC-1#1 Warning
+Scoped Clock constraint overwritten with the same name  
+A new clock constraint create_clock overrides a previous scoped clock constraint with the same name. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors.
+New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/constraints/soc.xdc (Line: 4))
+Previous: create_clock -period 20.000 [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56))
+Related violations: <none>
+
+XDCC-7#1 Warning
+Scoped Clock constraint overwritten on the same source  
+A new clock constraint create_clock overrides a previous scoped clock constraint defined on the same source. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors.
+New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/constraints/soc.xdc (Line: 4))
+Previous: create_clock -period 20.000 [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56))
+Related violations: <none>
+
+

fpga/vivado_reports_nodsp/power.rpt

@@ -0,0 +1,261 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version     : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+<<<<<<< Updated upstream
+| Date             : Fri Jul 10 04:15:05 2026
+=======
+| Date             : Sat Jul 11 09:21:02 2026
+>>>>>>> Stashed changes
+| Host             : fedora running 64-bit unknown
+| Command          : report_power -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/power.rpt
+| Design           : soc_top
+| Device           : xc7a200tfbg676-1
+| Design State     : routed
+| Grade            : commercial
+| Process          : typical
+| Characterization : Production
+--------------------------------------------------------------------------------------------------------------------------------------
+
+Power Report
+
+Table of Contents
+-----------------
+1. Summary
+1.1 On-Chip Components
+1.2 Power Supply Summary
+1.3 Confidence Level
+2. Settings
+2.1 Environment
+2.2 Clock Constraints
+3. Detailed Reports
+3.1 By Hierarchy
+
+1. Summary
+----------
+
++--------------------------+--------------+
+<<<<<<< Updated upstream
+| Total On-Chip Power (W)  | 0.686        |
+| Design Power Budget (W)  | Unspecified* |
+| Power Budget Margin (W)  | NA           |
+| Dynamic (W)              | 0.545        |
+| Device Static (W)        | 0.141        |
+| Effective TJA (C/W)      | 1.9          |
+| Max Ambient (C)          | 83.7         |
+| Junction Temperature (C) | 26.3         |
+=======
+| Total On-Chip Power (W)  | 0.779        |
+| Design Power Budget (W)  | Unspecified* |
+| Power Budget Margin (W)  | NA           |
+| Dynamic (W)              | 0.637        |
+| Device Static (W)        | 0.142        |
+| Effective TJA (C/W)      | 1.9          |
+| Max Ambient (C)          | 83.5         |
+| Junction Temperature (C) | 26.5         |
+>>>>>>> Stashed changes
+| Confidence Level         | Low          |
+| Setting File             | ---          |
+| Simulation Activity File | ---          |
+| Design Nets Matched      | NA           |
++--------------------------+--------------+
+* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
+
+
+1.1 On-Chip Components
+----------------------
+
++--------------------------+-----------+----------+-----------+-----------------+
+| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
++--------------------------+-----------+----------+-----------+-----------------+
+<<<<<<< Updated upstream
+| Clocks                   |     0.056 |        6 |       --- |             --- |
+| Slice Logic              |     0.109 |   133224 |       --- |             --- |
+|   LUT as Logic           |     0.102 |    75460 |    133800 |           56.40 |
+|   CARRY4                 |     0.003 |     3546 |     33450 |           10.60 |
+|   LUT as Distributed RAM |     0.002 |      628 |     46200 |            1.36 |
+|   Register               |     0.001 |    39690 |    267600 |           14.83 |
+|   LUT as Shift Register  |    <0.001 |     1175 |     46200 |            2.54 |
+|   F7/F8 Muxes            |    <0.001 |     6085 |    133800 |            4.55 |
+|   Others                 |     0.000 |      289 |       --- |             --- |
+| Signals                  |     0.194 |    93202 |       --- |             --- |
+| Block RAM                |     0.019 |     25.5 |       365 |            6.99 |
+| PLL                      |     0.137 |        1 |        10 |           10.00 |
+| I/O                      |     0.029 |      202 |       400 |           50.50 |
+| Static Power             |     0.141 |          |           |                 |
+| Total                    |     0.686 |          |           |                 |
+=======
+| Clocks                   |     0.060 |        7 |       --- |             --- |
+| Slice Logic              |     0.137 |   103629 |       --- |             --- |
+|   LUT as Logic           |     0.128 |    53158 |    133800 |           39.73 |
+|   CARRY4                 |     0.005 |     3669 |     33450 |           10.97 |
+|   Register               |     0.002 |    31000 |    267600 |           11.58 |
+|   LUT as Distributed RAM |     0.001 |      740 |     46200 |            1.60 |
+|   LUT as Shift Register  |    <0.001 |     1168 |     46200 |            2.53 |
+|   F7/F8 Muxes            |    <0.001 |     2449 |    133800 |            1.83 |
+|   Others                 |     0.000 |      333 |       --- |             --- |
+| Signals                  |     0.284 |    78815 |       --- |             --- |
+| Block RAM                |     0.027 |     29.5 |       365 |            8.08 |
+| PLL                      |     0.102 |        1 |        10 |           10.00 |
+| I/O                      |     0.027 |      202 |       400 |           50.50 |
+| Static Power             |     0.142 |          |           |                 |
+| Total                    |     0.779 |          |           |                 |
+>>>>>>> Stashed changes
++--------------------------+-----------+----------+-----------+-----------------+
+
+
+1.2 Power Supply Summary
+------------------------
+
++-----------+-------------+-----------+-------------+------------+
+| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
++-----------+-------------+-----------+-------------+------------+
+<<<<<<< Updated upstream
+| Vccint    |       1.000 |     0.423 |       0.391 |      0.032 |
+| Vccaux    |       1.800 |     0.101 |       0.070 |      0.031 |
+=======
+| Vccint    |       1.000 |     0.545 |       0.512 |      0.033 |
+| Vccaux    |       1.800 |     0.085 |       0.054 |      0.031 |
+>>>>>>> Stashed changes
+| Vcco33    |       3.300 |     0.013 |       0.008 |      0.005 |
+| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
+| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |
+| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
+| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
+| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
+| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
+| Vccbram   |       1.000 |     0.003 |       0.002 |      0.001 |
+| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |
+| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |
+| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
++-----------+-------------+-----------+-------------+------------+
+
+
+1.3 Confidence Level
+--------------------
+
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| Design implementation state | High       | Design is routed                                       |                                                                                                            |
+| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
+| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
+| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
+| Device models               | High       | Device models are Production                           |                                                                                                            |
+|                             |            |                                                        |                                                                                                            |
+| Overall confidence level    | Low        |                                                        |                                                                                                            |
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+
+
+2. Settings
+-----------
+
+2.1 Environment
+---------------
+
++-----------------------+--------------------------+
+| Ambient Temp (C)      | 25.0                     |
+| ThetaJA (C/W)         | 1.9                      |
+| Airflow (LFM)         | 250                      |
+| Heat Sink             | medium (Medium Profile)  |
+| ThetaSA (C/W)         | 3.4                      |
+| Board Selection       | medium (10"x10")         |
+| # of Board Layers     | 12to15 (12 to 15 Layers) |
+| Board Temperature (C) | 25.0                     |
++-----------------------+--------------------------+
+
+
+2.2 Clock Constraints
+---------------------
+
+<<<<<<< Updated upstream
++------------------+-----------------------------------------+-----------------+
+| Clock            | Domain                                  | Constraint (ns) |
++------------------+-----------------------------------------+-----------------+
+| clk              | clk                                     |            20.0 |
+| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll |            20.0 |
+| cpu_clk          | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll  |            30.3 |
+| sys_clk          | pll_clk.u_clk_pll/inst/sys_clk_clk_pll  |            20.0 |
++------------------+-----------------------------------------+-----------------+
+=======
++------------------+------------------------------------------+-----------------+
+| Clock            | Domain                                   | Constraint (ns) |
++------------------+------------------------------------------+-----------------+
+| clk              | clk                                      |            20.0 |
+| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll  |            20.0 |
+| cpu_clk          | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll   |            30.0 |
+| mlkem_clk        | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll |            13.0 |
+| sys_clk          | pll_clk.u_clk_pll/inst/sys_clk_clk_pll   |            20.0 |
++------------------+------------------------------------------+-----------------+
+>>>>>>> Stashed changes
+
+
+3. Detailed Reports
+-------------------
+
+3.1 By Hierarchy
+----------------
+
++----------------------------+-----------+
+| Name                       | Power (W) |
++----------------------------+-----------+
+<<<<<<< Updated upstream
+| soc_top                    |     0.545 |
+|   pll_clk.u_clk_pll        |     0.138 |
+|     inst                   |     0.138 |
+|   u_Axi_CDC                |     0.003 |
+|   u_axi_uart_controller    |     0.002 |
+|   u_cpu                    |     0.025 |
+|     addr_trans             |     0.002 |
+|       tlb_entry            |     0.002 |
+|     btb                    |     0.003 |
+|     dcache                 |     0.006 |
+|     icache                 |     0.005 |
+|     u_csr                  |     0.001 |
+|     u_mul                  |     0.004 |
+|   u_fft_mlkem_axi_slave    |     0.251 |
+|     u_fft_controller       |     0.030 |
+|       u_FFT                |     0.027 |
+|       u_out0               |     0.001 |
+|       u_out1               |     0.001 |
+|     u_mlkem_axi_slave      |     0.221 |
+|       u_mlkem              |     0.218 |
+|   u_matmul_axi_slave       |     0.081 |
+=======
+| soc_top                    |     0.637 |
+|   pll_clk.u_clk_pll        |     0.103 |
+|     inst                   |     0.103 |
+|   u_Axi_CDC                |     0.002 |
+|   u_axi_uart_controller    |     0.002 |
+|     uart0                  |     0.001 |
+|       regs                 |     0.001 |
+|   u_cdma_matmul_bridge     |     0.001 |
+|   u_confreg                |     0.001 |
+|   u_cpu                    |     0.027 |
+|     addr_trans             |     0.002 |
+|       tlb_entry            |     0.002 |
+|     btb                    |     0.003 |
+|     dcache                 |     0.004 |
+|     icache                 |     0.005 |
+|     u_csr                  |     0.001 |
+|     u_mul                  |     0.008 |
+|   u_fft_mlkem_axi_slave    |     0.373 |
+|     u_fft_controller       |     0.031 |
+|       u_FFT                |     0.028 |
+|       u_out0               |     0.001 |
+|       u_out1               |     0.001 |
+|     u_mlkem_axi_cdc        |     0.003 |
+|       wFifo                |     0.001 |
+|     u_mlkem_axi_slave      |     0.339 |
+|       u_mlkem              |     0.332 |
+|   u_matmul_axi_slave       |     0.077 |
+>>>>>>> Stashed changes
+|     mult_inst[0].u_mult    |     0.003 |
+|     mult_inst[1].u_mult    |     0.002 |
+|     mult_inst[2].u_mult    |     0.002 |
+|     mult_inst[3].u_mult    |     0.002 |
+|   u_snix_axil_cdma_mux_8ch |     0.008 |
+|     u_core_engine          |     0.004 |
+|       axis_fifo_u0         |     0.002 |
++----------------------------+-----------+
+
+

fpga/vivado_reports_nodsp/route_status.rpt

@@ -0,0 +1,21 @@
+Design Route Status
+                                               :      # nets :
+   ------------------------------------------- : ----------- :
+<<<<<<< Updated upstream
+   # of logical nets.......................... :      144034 :
+       # of nets not needing routing.......... :       50823 :
+           # of internally routed nets........ :       50442 :
+           # of nets with no loads............ :         381 :
+       # of routable nets..................... :       93211 :
+           # of fully routed nets............. :       93211 :
+=======
+   # of logical nets.......................... :      114880 :
+       # of nets not needing routing.......... :       36054 :
+           # of internally routed nets........ :       35589 :
+           # of nets with no loads............ :         465 :
+       # of routable nets..................... :       78826 :
+           # of fully routed nets............. :       78826 :
+>>>>>>> Stashed changes
+       # of nets with routing errors.......... :           0 :
+   ------------------------------------------- : ----------- :
+

fpga/vivado_reports_nodsp/utilization.rpt

@@ -0,0 +1,314 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+<<<<<<< Updated upstream
+| Date         : Fri Jul 10 04:14:47 2026
+=======
+| Date         : Sat Jul 11 09:20:51 2026
+>>>>>>> Stashed changes
+| Host         : fedora running 64-bit unknown
+| Command      : report_utilization -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/utilization.rpt
+| Design       : soc_top
+| Device       : 7a200tfbg676-1
+| Design State : Routed
+--------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Slice Logic Distribution
+3. Memory
+4. DSP
+5. IO and GT Specific
+6. Clocking
+7. Specific Feature
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++----------------------------+-------+-------+-----------+-------+
+|          Site Type         |  Used | Fixed | Available | Util% |
++----------------------------+-------+-------+-----------+-------+
+<<<<<<< Updated upstream
+| Slice LUTs                 | 71196 |     0 |    133800 | 53.21 |
+|   LUT as Logic             | 69453 |     0 |    133800 | 51.91 |
+|   LUT as Memory            |  1743 |     0 |     46200 |  3.77 |
+|     LUT as Distributed RAM |   628 |     0 |           |       |
+|     LUT as Shift Register  |  1115 |     0 |           |       |
+| Slice Registers            | 39690 |     0 |    267600 | 14.83 |
+|   Register as Flip Flop    | 39690 |     0 |    267600 | 14.83 |
+|   Register as Latch        |     0 |     0 |    267600 |  0.00 |
+| F7 Muxes                   |  4565 |     0 |     66900 |  6.82 |
+| F8 Muxes                   |  1520 |     0 |     33450 |  4.54 |
+=======
+| Slice LUTs                 | 55066 |     0 |    133800 | 41.16 |
+|   LUT as Logic             | 53158 |     0 |    133800 | 39.73 |
+|   LUT as Memory            |  1908 |     0 |     46200 |  4.13 |
+|     LUT as Distributed RAM |   740 |     0 |           |       |
+|     LUT as Shift Register  |  1168 |     0 |           |       |
+| Slice Registers            | 31000 |     0 |    267600 | 11.58 |
+|   Register as Flip Flop    | 31000 |     0 |    267600 | 11.58 |
+|   Register as Latch        |     0 |     0 |    267600 |  0.00 |
+| F7 Muxes                   |  2130 |     0 |     66900 |  3.18 |
+| F8 Muxes                   |   319 |     0 |     33450 |  0.95 |
+>>>>>>> Stashed changes
++----------------------------+-------+-------+-----------+-------+
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 24    |          Yes |           - |          Set |
+<<<<<<< Updated upstream
+| 26562 |          Yes |           - |        Reset |
+| 139   |          Yes |         Set |            - |
+| 12965 |          Yes |       Reset |            - |
+=======
+| 17683 |          Yes |           - |        Reset |
+| 126   |          Yes |         Set |            - |
+| 13167 |          Yes |       Reset |            - |
+>>>>>>> Stashed changes
++-------+--------------+-------------+--------------+
+
+
+2. Slice Logic Distribution
+---------------------------
+
++--------------------------------------------+-------+-------+-----------+-------+
+|                  Site Type                 |  Used | Fixed | Available | Util% |
++--------------------------------------------+-------+-------+-----------+-------+
+<<<<<<< Updated upstream
+| Slice                                      | 21289 |     0 |     33450 | 63.64 |
+|   SLICEL                                   | 13965 |     0 |           |       |
+|   SLICEM                                   |  7324 |     0 |           |       |
+| LUT as Logic                               | 69453 |     0 |    133800 | 51.91 |
+|   using O5 output only                     |     2 |       |           |       |
+|   using O6 output only                     | 57661 |       |           |       |
+|   using O5 and O6                          | 11790 |       |           |       |
+| LUT as Memory                              |  1743 |     0 |     46200 |  3.77 |
+|   LUT as Distributed RAM                   |   628 |     0 |           |       |
+|     using O5 output only                   |     0 |       |           |       |
+|     using O6 output only                   |    60 |       |           |       |
+|     using O5 and O6                        |   568 |       |           |       |
+|   LUT as Shift Register                    |  1115 |     0 |           |       |
+|     using O5 output only                   |    47 |       |           |       |
+|     using O6 output only                   |  1008 |       |           |       |
+|     using O5 and O6                        |    60 |       |           |       |
+| Slice Registers                            | 39690 |     0 |    267600 | 14.83 |
+|   Register driven from within the Slice    | 24917 |       |           |       |
+|   Register driven from outside the Slice   | 14773 |       |           |       |
+|     LUT in front of the register is unused |  6243 |       |           |       |
+|     LUT in front of the register is used   |  8530 |       |           |       |
+| Unique Control Sets                        |  1278 |       |     33450 |  3.82 |
+=======
+| Slice                                      | 17126 |     0 |     33450 | 51.20 |
+|   SLICEL                                   | 11119 |     0 |           |       |
+|   SLICEM                                   |  6007 |     0 |           |       |
+| LUT as Logic                               | 53158 |     0 |    133800 | 39.73 |
+|   using O5 output only                     |     5 |       |           |       |
+|   using O6 output only                     | 42769 |       |           |       |
+|   using O5 and O6                          | 10384 |       |           |       |
+| LUT as Memory                              |  1908 |     0 |     46200 |  4.13 |
+|   LUT as Distributed RAM                   |   740 |     0 |           |       |
+|     using O5 output only                   |     0 |       |           |       |
+|     using O6 output only                   |    60 |       |           |       |
+|     using O5 and O6                        |   680 |       |           |       |
+|   LUT as Shift Register                    |  1168 |     0 |           |       |
+|     using O5 output only                   |   123 |       |           |       |
+|     using O6 output only                   |   997 |       |           |       |
+|     using O5 and O6                        |    48 |       |           |       |
+| Slice Registers                            | 31000 |     0 |    267600 | 11.58 |
+|   Register driven from within the Slice    | 16668 |       |           |       |
+|   Register driven from outside the Slice   | 14332 |       |           |       |
+|     LUT in front of the register is unused |  5924 |       |           |       |
+|     LUT in front of the register is used   |  8408 |       |           |       |
+| Unique Control Sets                        |   930 |       |     33450 |  2.78 |
+>>>>>>> Stashed changes
++--------------------------------------------+-------+-------+-----------+-------+
+* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
+
+
+3. Memory
+---------
+
++-------------------+------+-------+-----------+-------+
+|     Site Type     | Used | Fixed | Available | Util% |
++-------------------+------+-------+-----------+-------+
+<<<<<<< Updated upstream
+| Block RAM Tile    | 25.5 |     0 |       365 |  6.99 |
+|   RAMB36/FIFO*    |   10 |     0 |       365 |  2.74 |
+|     RAMB36E1 only |   10 |       |           |       |
+|   RAMB18          |   31 |     0 |       730 |  4.25 |
+|     RAMB18E1 only |   31 |       |           |       |
+=======
+| Block RAM Tile    | 29.5 |     0 |       365 |  8.08 |
+|   RAMB36/FIFO*    |   10 |     0 |       365 |  2.74 |
+|     RAMB36E1 only |   10 |       |           |       |
+|   RAMB18          |   39 |     0 |       730 |  5.34 |
+|     RAMB18E1 only |   39 |       |           |       |
+>>>>>>> Stashed changes
++-------------------+------+-------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+4. DSP
+------
+
++-----------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-----------+------+-------+-----------+-------+
+| DSPs      |    0 |     0 |       740 |  0.00 |
++-----------+------+-------+-----------+-------+
+
+
+5. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+-----------+-------+
+|          Site Type          | Used | Fixed | Available | Util% |
++-----------------------------+------+-------+-----------+-------+
+| Bonded IOB                  |  202 |   202 |       400 | 50.50 |
+|   IOB Master Pads           |   97 |       |           |       |
+|   IOB Slave Pads            |  102 |       |           |       |
+| Bonded IPADs                |    0 |     0 |        26 |  0.00 |
+| Bonded OPADs                |    0 |     0 |        16 |  0.00 |
+| PHY_CONTROL                 |    0 |     0 |        10 |  0.00 |
+| PHASER_REF                  |    0 |     0 |        10 |  0.00 |
+| OUT_FIFO                    |    0 |     0 |        40 |  0.00 |
+| IN_FIFO                     |    0 |     0 |        40 |  0.00 |
+| IDELAYCTRL                  |    0 |     0 |        10 |  0.00 |
+| IBUFDS                      |    0 |     0 |       384 |  0.00 |
+| GTPE2_CHANNEL               |    0 |     0 |         8 |  0.00 |
+| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |        40 |  0.00 |
+| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |        40 |  0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |       500 |  0.00 |
+| IBUFDS_GTE2                 |    0 |     0 |         4 |  0.00 |
+| ILOGIC                      |    0 |     0 |       400 |  0.00 |
+| OLOGIC                      |    0 |     0 |       400 |  0.00 |
++-----------------------------+------+-------+-----------+-------+
+
+
+6. Clocking
+-----------
+
++------------+------+-------+-----------+-------+
+|  Site Type | Used | Fixed | Available | Util% |
++------------+------+-------+-----------+-------+
+| BUFGCTRL   |    3 |     0 |        32 |  9.38 |
+| BUFIO      |    0 |     0 |        40 |  0.00 |
+| MMCME2_ADV |    0 |     0 |        10 |  0.00 |
+| PLLE2_ADV  |    1 |     0 |        10 | 10.00 |
+| BUFMRCE    |    0 |     0 |        20 |  0.00 |
+| BUFHCE     |    0 |     0 |       120 |  0.00 |
+| BUFR       |    0 |     0 |        40 |  0.00 |
++------------+------+-------+-----------+-------+
+
+
+7. Specific Feature
+-------------------
+
++-------------+------+-------+-----------+-------+
+|  Site Type  | Used | Fixed | Available | Util% |
++-------------+------+-------+-----------+-------+
+| BSCANE2     |    0 |     0 |         4 |  0.00 |
+| CAPTUREE2   |    0 |     0 |         1 |  0.00 |
+| DNA_PORT    |    0 |     0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
+| FRAME_ECCE2 |    0 |     0 |         1 |  0.00 |
+| ICAPE2      |    0 |     0 |         2 |  0.00 |
+| PCIE_2_1    |    0 |     0 |         1 |  0.00 |
+| STARTUPE2   |    0 |     0 |         1 |  0.00 |
+| XADC        |    0 |     0 |         1 |  0.00 |
++-------------+------+-------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++-----------+-------+---------------------+
+|  Ref Name |  Used | Functional Category |
++-----------+-------+---------------------+
+<<<<<<< Updated upstream
+| LUT6      | 37981 |                 LUT |
+| FDCE      | 26562 |        Flop & Latch |
+| FDRE      | 12965 |        Flop & Latch |
+| LUT5      | 12781 |                 LUT |
+| LUT4      | 10316 |                 LUT |
+| LUT3      | 10135 |                 LUT |
+| LUT2      |  9228 |                 LUT |
+| MUXF7     |  4565 |               MuxFx |
+| CARRY4    |  3546 |          CarryLogic |
+| MUXF8     |  1520 |               MuxFx |
+| SRLC32E   |   992 |  Distributed Memory |
+| RAMD32    |   892 |  Distributed Memory |
+| LUT1      |   802 |                 LUT |
+| RAMS32    |   272 |  Distributed Memory |
+| SRL16E    |   183 |  Distributed Memory |
+| FDSE      |   139 |        Flop & Latch |
+=======
+| LUT6      | 26800 |                 LUT |
+| FDCE      | 17683 |        Flop & Latch |
+| FDRE      | 13167 |        Flop & Latch |
+| LUT3      | 10370 |                 LUT |
+| LUT4      |  8684 |                 LUT |
+| LUT2      |  8543 |                 LUT |
+| LUT5      |  8274 |                 LUT |
+| CARRY4    |  3669 |          CarryLogic |
+| MUXF7     |  2130 |               MuxFx |
+| RAMD32    |  1060 |  Distributed Memory |
+| SRLC32E   |   992 |  Distributed Memory |
+| LUT1      |   871 |                 LUT |
+| RAMS32    |   328 |  Distributed Memory |
+| MUXF8     |   319 |               MuxFx |
+| SRL16E    |   224 |  Distributed Memory |
+| FDSE      |   126 |        Flop & Latch |
+>>>>>>> Stashed changes
+| IBUF      |   104 |                  IO |
+| OBUF      |    98 |                  IO |
+| OBUFT     |    66 |                  IO |
+| RAMB18E1  |    39 |        Block Memory |
+| RAMD64E   |    32 |  Distributed Memory |
+| FDPE      |    24 |        Flop & Latch |
+| RAMB36E1  |    10 |        Block Memory |
+<<<<<<< Updated upstream
+| BUFG      |     3 |               Clock |
+=======
+| BUFG      |     4 |               Clock |
+>>>>>>> Stashed changes
+| PLLE2_ADV |     1 |               Clock |
++-----------+-------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+| clk_pll  |    1 |
++----------+------+
+
+

fpga/vivado_reports_nodsp/utilization_hier.rpt

@@ -0,0 +1,290 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+| Date         : Sat Jul 11 09:20:51 2026
+| Host         : fedora running 64-bit unknown
+| Command      : report_utilization -hierarchical -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/utilization_hier.rpt
+| Design       : soc_top
+| Device       : 7a200tfbg676-1
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Utilization by Hierarchy
+
+1. Utilization by Hierarchy
+---------------------------
+
++------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
+|                 Instance                 |            Module            | Total LUTs | Logic LUTs | LUTRAMs | SRLs |  FFs  | RAMB36 | RAMB18 | DSP48 Blocks |
++------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
+| soc_top                                  |                        (top) |      55066 |      53158 |     740 | 1168 | 31000 |     10 |     39 |            0 |
+|   (soc_top)                              |                        (top) |        927 |        919 |       8 |    0 |     4 |      0 |      0 |            0 |
+|   pll_clk.u_clk_pll                      |                      clk_pll |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
+|     inst                                 |      clk_pll_clk_pll_clk_wiz |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
+|   pll_clk.u_rst_cpu                      |                     rst_sync |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
+|   pll_clk.u_rst_mlkem                    |                   rst_sync_0 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
+|   pll_clk.u_rst_sys                      |                   rst_sync_1 |          2 |          2 |       0 |    0 |     2 |      0 |      0 |            0 |
+|   u_AxiCrossbar_2x8                      |              AxiCrossbar_2x8 |        368 |        368 |       0 |    0 |   151 |      0 |      0 |            0 |
+|     (u_AxiCrossbar_2x8)                  |              AxiCrossbar_2x8 |          8 |          8 |       0 |    0 |    24 |      0 |      0 |            0 |
+|     axi4ReadOnlyArbiter_4                |          Axi4ReadOnlyArbiter |         14 |         14 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_92 |         14 |         14 |       0 |    0 |     3 |      0 |      0 |            0 |
+|     axi4ReadOnlyArbiter_5                |       Axi4ReadOnlyArbiter_75 |          6 |          6 |       0 |    0 |     2 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_91 |          6 |          6 |       0 |    0 |     2 |      0 |      0 |            0 |
+|     axi4ReadOnlyArbiter_6                |       Axi4ReadOnlyArbiter_76 |         17 |         17 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_90 |         17 |         17 |       0 |    0 |     3 |      0 |      0 |            0 |
+|     axi4ReadOnlyArbiter_7                |       Axi4ReadOnlyArbiter_77 |         13 |         13 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_89 |         13 |         13 |       0 |    0 |     3 |      0 |      0 |            0 |
+|     axi4WriteOnlyArbiter_4               |         Axi4WriteOnlyArbiter |         32 |         32 |       0 |    0 |    11 |      0 |      0 |            0 |
+|       (axi4WriteOnlyArbiter_4)           |         Axi4WriteOnlyArbiter |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_86 |         26 |         26 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdRouteFork_translated_fifo       |    StreamFifoLowLatency_3_87 |          7 |          7 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         fifo                             |              StreamFifo_3_88 |          7 |          7 |       0 |    0 |     6 |      0 |      0 |            0 |
+|     axi4WriteOnlyArbiter_5               |       Axi4WriteOnlyArbiter_1 |         15 |         15 |       0 |    0 |     9 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_83 |          9 |          9 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdRouteFork_translated_fifo       |    StreamFifoLowLatency_3_84 |          6 |          6 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         fifo                             |              StreamFifo_3_85 |          6 |          6 |       0 |    0 |     6 |      0 |      0 |            0 |
+|     axi4WriteOnlyArbiter_6               |       Axi4WriteOnlyArbiter_2 |         33 |         33 |       0 |    0 |    11 |      0 |      0 |            0 |
+|       (axi4WriteOnlyArbiter_6)           |       Axi4WriteOnlyArbiter_2 |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_80 |         24 |         24 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdRouteFork_translated_fifo       |    StreamFifoLowLatency_3_81 |          9 |          9 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         fifo                             |              StreamFifo_3_82 |          9 |          9 |       0 |    0 |     6 |      0 |      0 |            0 |
+|     axi4WriteOnlyArbiter_7               |       Axi4WriteOnlyArbiter_3 |         29 |         29 |       0 |    0 |    11 |      0 |      0 |            0 |
+|       (axi4WriteOnlyArbiter_7)           |       Axi4WriteOnlyArbiter_3 |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
+|       cmdArbiter                         |              StreamArbiter_7 |         21 |         21 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdRouteFork_translated_fifo       |       StreamFifoLowLatency_3 |          8 |          8 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         fifo                             |                 StreamFifo_3 |          8 |          8 |       0 |    0 |     6 |      0 |      0 |            0 |
+|     axiIn_0_readOnly_decoder             |          Axi4ReadOnlyDecoder |         90 |         90 |       0 |    0 |    25 |      0 |      0 |            0 |
+|       (axiIn_0_readOnly_decoder)         |          Axi4ReadOnlyDecoder |         74 |         74 |       0 |    0 |    12 |      0 |      0 |            0 |
+|       errorSlave                         |  Axi4ReadOnlyErrorSlave_1_79 |         16 |         16 |       0 |    0 |    13 |      0 |      0 |            0 |
+|     axiIn_0_writeOnly_decoder            |         Axi4WriteOnlyDecoder |         36 |         36 |       0 |    0 |    18 |      0 |      0 |            0 |
+|       (axiIn_0_writeOnly_decoder)        |         Axi4WriteOnlyDecoder |         16 |         16 |       0 |    0 |    16 |      0 |      0 |            0 |
+|       errorSlave                         | Axi4WriteOnlyErrorSlave_1_78 |         20 |         20 |       0 |    0 |     2 |      0 |      0 |            0 |
+|     axiIn_1_readOnly_decoder             |        Axi4ReadOnlyDecoder_1 |         52 |         52 |       0 |    0 |    17 |      0 |      0 |            0 |
+|       (axiIn_1_readOnly_decoder)         |        Axi4ReadOnlyDecoder_1 |         36 |         36 |       0 |    0 |     8 |      0 |      0 |            0 |
+|       errorSlave                         |     Axi4ReadOnlyErrorSlave_1 |         16 |         16 |       0 |    0 |     9 |      0 |      0 |            0 |
+|     axiIn_1_writeOnly_decoder            |       Axi4WriteOnlyDecoder_1 |         23 |         23 |       0 |    0 |    14 |      0 |      0 |            0 |
+|       (axiIn_1_writeOnly_decoder)        |       Axi4WriteOnlyDecoder_1 |         15 |         15 |       0 |    0 |    12 |      0 |      0 |            0 |
+|       errorSlave                         |    Axi4WriteOnlyErrorSlave_1 |          8 |          8 |       0 |    0 |     2 |      0 |      0 |            0 |
+|   u_Axi_CDC                              |                      Axi_CDC |        427 |        299 |     128 |    0 |   317 |      0 |      0 |            0 |
+|     arFifo                               |            StreamFifoCC_3_58 |        192 |        156 |      36 |    0 |    77 |      0 |      0 |            0 |
+|       (arFifo)                           |            StreamFifoCC_3_58 |        186 |        150 |      36 |    0 |    65 |      0 |      0 |            0 |
+|       popToPushGray_buffercc             |                BufferCC_9_73 |          1 |          1 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       pushToPopGray_buffercc             |               BufferCC_11_74 |          5 |          5 |       0 |    0 |     6 |      0 |      0 |            0 |
+|     awFifo                               |              StreamFifoCC_59 |        110 |         74 |      36 |    0 |    79 |      0 |      0 |            0 |
+|       (awFifo)                           |              StreamFifoCC_59 |        103 |         67 |      36 |    0 |    65 |      0 |      0 |            0 |
+|       bufferCC_12                        |               BufferCC_10_70 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
+|       popToPushGray_buffercc             |                BufferCC_9_71 |          2 |          2 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       pushToPopGray_buffercc             |               BufferCC_11_72 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
+|     bFifo                                |            StreamFifoCC_2_60 |         14 |         14 |       0 |    0 |    26 |      0 |      0 |            0 |
+|       (bFifo)                            |            StreamFifoCC_2_60 |          7 |          7 |       0 |    0 |    12 |      0 |      0 |            0 |
+|       bufferCC_12                        |                BufferCC_5_67 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
+|       popToPushGray_buffercc             |                BufferCC_4_68 |          2 |          2 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       pushToPopGray_buffercc             |                BufferCC_6_69 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
+|     rFifo                                |            StreamFifoCC_4_61 |         45 |         17 |      28 |    0 |    66 |      0 |      0 |            0 |
+|       (rFifo)                            |            StreamFifoCC_4_61 |         41 |         13 |      28 |    0 |    50 |      0 |      0 |            0 |
+|       popToPushGray_buffercc             |                  BufferCC_65 |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
+|       pushToPopGray_buffercc             |                BufferCC_1_66 |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
+|     wFifo                                |            StreamFifoCC_1_62 |         66 |         38 |      28 |    0 |    69 |      0 |      0 |            0 |
+|       (wFifo)                            |            StreamFifoCC_1_62 |         62 |         34 |      28 |    0 |    53 |      0 |      0 |            0 |
+|       popToPushGray_buffercc             |                BufferCC_7_63 |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
+|       pushToPopGray_buffercc             |                BufferCC_8_64 |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
+|   u_axi_axil_adapter                     |             axi_axil_adapter |       1245 |       1245 |       0 |    0 |   161 |      0 |      0 |            0 |
+|     axi_axil_adapter_rd_inst             |          axi_axil_adapter_rd |        640 |        640 |       0 |    0 |    81 |      0 |      0 |            0 |
+|     axi_axil_adapter_wr_inst             |          axi_axil_adapter_wr |        605 |        605 |       0 |    0 |    80 |      0 |      0 |            0 |
+|   u_axi_dvi                              |                      axi_dvi |        284 |        284 |       0 |    0 |   211 |      0 |      0 |            0 |
+|   u_axi_ram                              |     axi_wrap_ram_sp_external |        356 |        356 |       0 |    0 |    78 |      0 |      0 |            0 |
+|     u_axi_sram_sp                        |         axi2sram_sp_external |        356 |        356 |       0 |    0 |    78 |      0 |      0 |            0 |
+|   u_axi_uart_controller                  |          axi_uart_controller |        684 |        668 |      16 |    0 |   457 |      0 |      0 |            0 |
+|     AA_axi2apb_bridge_cpu                |               axi2apb_bridge |        252 |        252 |       0 |    0 |   120 |      0 |      0 |            0 |
+|     uart0                                |                     UART_TOP |        432 |        416 |      16 |    0 |   337 |      0 |      0 |            0 |
+|       regs                               |                    uart_regs |        432 |        416 |      16 |    0 |   337 |      0 |      0 |            0 |
+|         (regs)                           |                    uart_regs |        118 |        118 |       0 |    0 |   155 |      0 |      0 |            0 |
+|         i_uart_sync_flops                |              uart_sync_flops |          3 |          3 |       0 |    0 |     2 |      0 |      0 |            0 |
+|         receiver                         |                uart_receiver |        229 |        221 |       8 |    0 |   124 |      0 |      0 |            0 |
+|           (receiver)                     |                uart_receiver |         68 |         68 |       0 |    0 |    54 |      0 |      0 |            0 |
+|           fifo_rx                        |                   uart_rfifo |        161 |        153 |       8 |    0 |    70 |      0 |      0 |            0 |
+|             (fifo_rx)                    |                   uart_rfifo |        143 |        143 |       0 |    0 |    62 |      0 |      0 |            0 |
+|             rfifo                        |                   raminfr_57 |         19 |         11 |       8 |    0 |     8 |      0 |      0 |            0 |
+|         transmitter                      |             uart_transmitter |         83 |         75 |       8 |    0 |    56 |      0 |      0 |            0 |
+|           (transmitter)                  |             uart_transmitter |         41 |         41 |       0 |    0 |    35 |      0 |      0 |            0 |
+|           fifo_tx                        |                   uart_tfifo |         43 |         35 |       8 |    0 |    21 |      0 |      0 |            0 |
+|             (fifo_tx)                    |                   uart_tfifo |         24 |         24 |       0 |    0 |    13 |      0 |      0 |            0 |
+|             tfifo                        |                      raminfr |         19 |         11 |       8 |    0 |     8 |      0 |      0 |            0 |
+|   u_cdma_matmul_bridge                   |           cdma_matmul_bridge |        248 |        248 |       0 |    0 |   578 |      0 |      0 |            0 |
+|   u_confreg                              |                      confreg |        390 |        390 |       0 |    0 |   476 |      0 |      0 |            0 |
+|     (u_confreg)                          |                      confreg |        230 |        230 |       0 |    0 |   399 |      0 |      0 |            0 |
+|     u_digitaltube_controller             |       digitaltube_controller |         16 |         16 |       0 |    0 |    24 |      0 |      0 |            0 |
+|     u_int_ctrl                           |                     int_ctrl |        144 |        144 |       0 |    0 |    53 |      0 |      0 |            0 |
+|   u_cpu                                  |                     core_top |       8584 |       8284 |     300 |    0 |  5591 |      0 |     20 |            0 |
+|     (u_cpu)                              |                     core_top |        561 |        513 |      48 |    0 |     1 |      0 |      0 |            0 |
+|     addr_trans                           |                   addr_trans |       2240 |       2100 |     140 |    0 |  1244 |      0 |      0 |            0 |
+|       (addr_trans)                       |                   addr_trans |          0 |          0 |       0 |    0 |    40 |      0 |      0 |            0 |
+|       tlb_entry                          |                    tlb_entry |       2240 |       2100 |     140 |    0 |  1204 |      0 |      0 |            0 |
+|     axi_bridge                           |                   axi_bridge |         39 |         39 |       0 |    0 |   214 |      0 |      0 |            0 |
+|     btb                                  |                          btb |       1041 |        961 |      80 |    0 |  1611 |      0 |      0 |            0 |
+|       (btb)                              |                          btb |       1039 |        959 |      80 |    0 |  1611 |      0 |      0 |            0 |
+|       dec_btb_add_entry                  |                 decoder_5_32 |          3 |          3 |       0 |    0 |     0 |      0 |      0 |            0 |
+|     dcache                               |                       dcache |        551 |        519 |      32 |    0 |   146 |      0 |     10 |            0 |
+|       (dcache)                           |                       dcache |         87 |         55 |      32 |    0 |   138 |      0 |      0 |            0 |
+|       data_ram_way[0].data_ram_bank[0].u |            data_bank_sram_46 |         49 |         49 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[1].u |            data_bank_sram_47 |         17 |         17 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[2].u |            data_bank_sram_48 |         49 |         49 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[3].u |            data_bank_sram_49 |         51 |         51 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[0].u |            data_bank_sram_50 |         17 |         17 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[1].u |            data_bank_sram_51 |         49 |         49 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[2].u |            data_bank_sram_52 |         81 |         81 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[3].u |            data_bank_sram_53 |         54 |         54 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       lfsr                               |                      lfsr_54 |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
+|       tagv_ram_way[0].u                  |                 tagv_sram_55 |         62 |         62 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       tagv_ram_way[1].u                  |                 tagv_sram_56 |         42 |         42 |       0 |    0 |     0 |      0 |      1 |            0 |
+|     exe_stage                            |                    exe_stage |        666 |        666 |       0 |    0 |   233 |      0 |      0 |            0 |
+|       (exe_stage)                        |                    exe_stage |        635 |        635 |       0 |    0 |   233 |      0 |      0 |            0 |
+|       u_alu                              |                          alu |         33 |         33 |       0 |    0 |     0 |      0 |      0 |            0 |
+|     icache                               |                       icache |        233 |        233 |       0 |    0 |    55 |      0 |     10 |            0 |
+|       (icache)                           |                       icache |         12 |         12 |       0 |    0 |    47 |      0 |      0 |            0 |
+|       data_ram_way[0].data_ram_bank[0].u |               data_bank_sram |          4 |          4 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[1].u |            data_bank_sram_38 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[2].u |            data_bank_sram_39 |         67 |         67 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[3].u |            data_bank_sram_40 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[0].u |            data_bank_sram_41 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[1].u |            data_bank_sram_42 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[2].u |            data_bank_sram_43 |         35 |         35 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[3].u |            data_bank_sram_44 |          4 |          4 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       lfsr                               |                         lfsr |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
+|       tagv_ram_way[0].u                  |                    tagv_sram |         15 |         15 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       tagv_ram_way[1].u                  |                 tagv_sram_45 |         88 |         88 |       0 |    0 |     0 |      0 |      1 |            0 |
+|     id_stage                             |                     id_stage |       1054 |       1054 |       0 |    0 |   108 |      0 |      0 |            0 |
+|     if_stage                             |                     if_stage |        134 |        134 |       0 |    0 |   173 |      0 |      0 |            0 |
+|     mem_stage                            |                    mem_stage |        115 |        115 |       0 |    0 |   211 |      0 |      0 |            0 |
+|     u_csr                                |                          csr |        201 |        201 |       0 |    0 |   663 |      0 |      0 |            0 |
+|     u_div                                |                          div |        141 |        141 |       0 |    0 |   107 |      0 |      0 |            0 |
+|     u_mul                                |                          mul |        938 |        938 |       0 |    0 |   592 |      0 |      0 |            0 |
+|     wb_stage                             |                     wb_stage |        682 |        682 |       0 |    0 |   233 |      0 |      0 |            0 |
+|   u_fft_mlkem_axi_slave                  |          fft_mlkem_axi_slave |      30142 |      28868 |     112 | 1162 | 18251 |     10 |     18 |            0 |
+|     (u_fft_mlkem_axi_slave)              |          fft_mlkem_axi_slave |          0 |          0 |       0 |    0 |     6 |      0 |      0 |            0 |
+|     u_fft_controller                     |               fft_controller |       6934 |       5894 |       0 | 1040 |  1083 |      8 |      4 |            0 |
+|       (u_fft_controller)                 |               fft_controller |        118 |        118 |       0 |    0 |   100 |      0 |      0 |            0 |
+|       u_FFT                              |                          FFT |       6782 |       5742 |       0 | 1040 |   983 |      8 |      0 |            0 |
+|         SU1                              |                      SdfUnit |       2144 |       1376 |       0 |  768 |   197 |      2 |      0 |            0 |
+|           (SU1)                          |                      SdfUnit |         39 |         39 |       0 |    0 |   133 |      0 |      0 |            0 |
+|           BF1                            |                 Butterfly_34 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF2                            | Butterfly__parameterized0_35 |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           DB1                            |                  DelayBuffer |        624 |        112 |       0 |  512 |    32 |      0 |      0 |            0 |
+|           DB2                            |  DelayBuffer__parameterized0 |        320 |         64 |       0 |  256 |    32 |      0 |      0 |            0 |
+|           MU                             |                  Multiply_36 |        610 |        610 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           TW                             |                   Twiddle_37 |        543 |        543 |       0 |    0 |     0 |      2 |      0 |            0 |
+|         SU2                              |      SdfUnit__parameterized0 |       1567 |       1375 |       0 |  192 |   197 |      2 |      0 |            0 |
+|           (SU2)                          |      SdfUnit__parameterized0 |         38 |         38 |       0 |    0 |   133 |      0 |      0 |            0 |
+|           BF1                            |                 Butterfly_30 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF2                            | Butterfly__parameterized0_31 |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           DB1                            |  DelayBuffer__parameterized1 |        240 |        112 |       0 |  128 |    32 |      0 |      0 |            0 |
+|           DB2                            |  DelayBuffer__parameterized2 |        128 |         64 |       0 |   64 |    32 |      0 |      0 |            0 |
+|           MU                             |                  Multiply_32 |        612 |        612 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           TW                             |                   Twiddle_33 |        541 |        541 |       0 |    0 |     0 |      2 |      0 |            0 |
+|         SU3                              |      SdfUnit__parameterized1 |       1416 |       1368 |       0 |   48 |   197 |      2 |      0 |            0 |
+|           (SU3)                          |      SdfUnit__parameterized1 |         35 |         35 |       0 |    0 |   133 |      0 |      0 |            0 |
+|           BF1                            |                 Butterfly_26 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF2                            | Butterfly__parameterized0_27 |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           DB1                            |  DelayBuffer__parameterized3 |        144 |        112 |       0 |   32 |    32 |      0 |      0 |            0 |
+|           DB2                            |  DelayBuffer__parameterized4 |         80 |         64 |       0 |   16 |    32 |      0 |      0 |            0 |
+|           MU                             |                  Multiply_28 |        610 |        610 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           TW                             |                   Twiddle_29 |        539 |        539 |       0 |    0 |     0 |      2 |      0 |            0 |
+|         SU4                              |      SdfUnit__parameterized2 |       1397 |       1365 |       0 |   32 |   197 |      2 |      0 |            0 |
+|           (SU4)                          |      SdfUnit__parameterized2 |         34 |         34 |       0 |    0 |   133 |      0 |      0 |            0 |
+|           BF1                            |                 Butterfly_24 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF2                            | Butterfly__parameterized0_25 |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           DB1                            |  DelayBuffer__parameterized5 |        128 |        112 |       0 |   16 |    32 |      0 |      0 |            0 |
+|           DB2                            |  DelayBuffer__parameterized6 |         80 |         64 |       0 |   16 |    32 |      0 |      0 |            0 |
+|           MU                             |                     Multiply |        611 |        611 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           TW                             |                      Twiddle |        536 |        536 |       0 |    0 |     0 |      2 |      0 |            0 |
+|         SU5                              |      SdfUnit__parameterized3 |        258 |        258 |       0 |    0 |   195 |      0 |      0 |            0 |
+|           (SU5)                          |      SdfUnit__parameterized3 |         34 |         34 |       0 |    0 |    99 |      0 |      0 |            0 |
+|           BF1                            |                    Butterfly |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF2                            |    Butterfly__parameterized0 |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           DB1                            |  DelayBuffer__parameterized7 |        112 |        112 |       0 |    0 |    64 |      0 |      0 |            0 |
+|           DB2                            |  DelayBuffer__parameterized8 |         64 |         64 |       0 |    0 |    32 |      0 |      0 |            0 |
+|       u_in0                              |                     my_bram0 |          2 |          2 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       u_in1                              |                  my_bram0_21 |          2 |          2 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       u_out0                             |                  my_bram0_22 |          0 |          0 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       u_out1                             |                  my_bram0_23 |         32 |         32 |       0 |    0 |     0 |      0 |      1 |            0 |
+|     u_mlkem_axi_cdc                      |                    Axi_CDC_5 |        336 |        224 |     112 |    0 |   272 |      0 |      0 |            0 |
+|       arFifo                             |               StreamFifoCC_3 |         50 |         22 |      28 |    0 |    55 |      0 |      0 |            0 |
+|         (arFifo)                         |               StreamFifoCC_3 |         42 |         14 |      28 |    0 |    43 |      0 |      0 |            0 |
+|         popToPushGray_buffercc           |                BufferCC_9_19 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         pushToPopGray_buffercc           |               BufferCC_11_20 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       awFifo                             |                 StreamFifoCC |         39 |         15 |      24 |    0 |    49 |      0 |      0 |            0 |
+|         (awFifo)                         |                 StreamFifoCC |         31 |          7 |      24 |    0 |    35 |      0 |      0 |            0 |
+|         bufferCC_12                      |                  BufferCC_10 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
+|         popToPushGray_buffercc           |                   BufferCC_9 |          3 |          3 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         pushToPopGray_buffercc           |                  BufferCC_11 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       bFifo                              |               StreamFifoCC_2 |         18 |         14 |       4 |    0 |    27 |      0 |      0 |            0 |
+|         (bFifo)                          |               StreamFifoCC_2 |         11 |          7 |       4 |    0 |    13 |      0 |      0 |            0 |
+|         bufferCC_12                      |                   BufferCC_5 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
+|         popToPushGray_buffercc           |                   BufferCC_4 |          1 |          1 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         pushToPopGray_buffercc           |                   BufferCC_6 |          5 |          5 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       rFifo                              |               StreamFifoCC_4 |         65 |         37 |      28 |    0 |    72 |      0 |      0 |            0 |
+|         (rFifo)                          |               StreamFifoCC_4 |         58 |         30 |      28 |    0 |    56 |      0 |      0 |            0 |
+|         popToPushGray_buffercc           |                     BufferCC |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
+|         pushToPopGray_buffercc           |                   BufferCC_1 |          5 |          5 |       0 |    0 |     8 |      0 |      0 |            0 |
+|       wFifo                              |               StreamFifoCC_1 |        164 |        136 |      28 |    0 |    69 |      0 |      0 |            0 |
+|         (wFifo)                          |               StreamFifoCC_1 |        159 |        131 |      28 |    0 |    53 |      0 |      0 |            0 |
+|         popToPushGray_buffercc           |                   BufferCC_7 |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
+|         pushToPopGray_buffercc           |                   BufferCC_8 |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
+|     u_mlkem_axi_slave                    |              mlkem_axi_slave |      22873 |      22751 |       0 |  122 | 16890 |      2 |     14 |            0 |
+|       (u_mlkem_axi_slave)                |              mlkem_axi_slave |       1179 |       1179 |       0 |    0 |  1064 |      0 |      0 |            0 |
+|       u_mlkem                            |                    mlkem_top |      21697 |      21575 |       0 |  122 | 15826 |      2 |     14 |            0 |
+|         (u_mlkem)                        |                    mlkem_top |       2633 |       2633 |       0 |    0 |  5010 |      0 |      0 |            0 |
+|         u_bank_a                         |      sd_bram__parameterized0 |         61 |         61 |       0 |    0 |     0 |      1 |      1 |            0 |
+|         u_bank_se                        |      sd_bram__parameterized1 |         77 |         77 |       0 |    0 |     0 |      1 |      0 |            0 |
+|         u_bank_t                         |      sd_bram__parameterized2 |        632 |        632 |       0 |    0 |     0 |      0 |      1 |            0 |
+|         u_c_in_bram                      |                      sd_bram |       1301 |       1301 |       0 |    0 |     0 |      0 |      1 |            0 |
+|         u_cbd                            |       sample_cbd_sync_shared |       2739 |       2739 |       0 |    0 |  3186 |      0 |      0 |            0 |
+|         u_comp                           |             comp_decomp_sync |        620 |        618 |       0 |    2 |   319 |      0 |      0 |            0 |
+|         u_ct_bram                        |                    sd_bram_6 |         10 |         10 |       0 |    0 |     0 |      0 |      1 |            0 |
+|         u_dkp_bram                       |                    sd_bram_7 |         74 |         74 |       0 |    0 |     0 |      0 |      1 |            0 |
+|         u_ek_bram                        |                    sd_bram_8 |        304 |        304 |       0 |    0 |     0 |      0 |      1 |            0 |
+|         u_keccak                         |                  keccak_core |       5258 |       5258 |       0 |    0 |  1618 |      0 |      0 |            0 |
+|         u_ntt                            |                     ntt_core |       1900 |       1817 |       0 |   83 |  1062 |      0 |      4 |            0 |
+|           (u_ntt)                        |                     ntt_core |        281 |        249 |       0 |   32 |   215 |      0 |      0 |            0 |
+|           u_bf0                          |          butterfly_unit_pipe |        675 |        650 |       0 |   25 |   321 |      0 |      0 |            0 |
+|             (u_bf0)                      |          butterfly_unit_pipe |        264 |        239 |       0 |   25 |   112 |      0 |      0 |            0 |
+|             u_barrett                    |          barrett_mul_pipe_18 |        411 |        411 |       0 |    0 |   209 |      0 |      0 |            0 |
+|           u_bf1                          |       butterfly_unit_pipe_12 |        487 |        462 |       0 |   25 |   307 |      0 |      0 |            0 |
+|             (u_bf1)                      |       butterfly_unit_pipe_12 |         89 |         65 |       0 |   24 |    96 |      0 |      0 |            0 |
+|             u_barrett                    |          barrett_mul_pipe_17 |        398 |        397 |       0 |    1 |   211 |      0 |      0 |            0 |
+|           u_cr                           |              coeff_bram_4way |        208 |        208 |       0 |    0 |     8 |      0 |      4 |            0 |
+|             (u_cr)                       |              coeff_bram_4way |          6 |          6 |       0 |    0 |     8 |      0 |      0 |            0 |
+|             gen_xbar[0].u_bank           |   sd_bram__parameterized3_13 |         17 |         17 |       0 |    0 |     0 |      0 |      1 |            0 |
+|             gen_xbar[1].u_bank           |   sd_bram__parameterized3_14 |         89 |         89 |       0 |    0 |     0 |      0 |      1 |            0 |
+|             gen_xbar[2].u_bank           |   sd_bram__parameterized3_15 |         16 |         16 |       0 |    0 |     0 |      0 |      1 |            0 |
+|             gen_xbar[3].u_bank           |   sd_bram__parameterized3_16 |         82 |         82 |       0 |    0 |     0 |      0 |      1 |            0 |
+|           u_scl                          |             barrett_mul_pipe |        252 |        251 |       0 |    1 |   211 |      0 |      0 |            0 |
+|         u_pmul                           |                poly_mul_sync |       2058 |       2021 |       0 |   37 |   584 |      0 |      4 |            0 |
+|           (u_pmul)                       |                poly_mul_sync |        634 |        634 |       0 |    0 |   121 |      0 |      0 |            0 |
+|           u_a_even                       |      sd_bram__parameterized3 |          0 |          0 |       0 |    0 |     0 |      0 |      1 |            0 |
+|           u_a_odd                        |    sd_bram__parameterized3_9 |          0 |          0 |       0 |    0 |     0 |      0 |      1 |            0 |
+|           u_b_even                       |   sd_bram__parameterized3_10 |          1 |          1 |       0 |    0 |     0 |      0 |      1 |            0 |
+|           u_b_odd                        |   sd_bram__parameterized3_11 |          1 |          1 |       0 |    0 |     0 |      0 |      1 |            0 |
+|           u_bc                           |            basecase_mul_pipe |       1423 |       1386 |       0 |   37 |   463 |      0 |      0 |            0 |
+|         u_sha3                           |              sha3_top_shared |       1955 |       1955 |       0 |    0 |  2378 |      0 |      0 |            0 |
+|         u_snt                            |       sample_ntt_sync_shared |       2109 |       2109 |       0 |    0 |  1669 |      0 |      0 |            0 |
+|   u_matmul_axi_slave                     |             matmul_axi_slave |       9879 |       9697 |     176 |    6 |  3243 |      0 |      0 |            0 |
+|     (u_matmul_axi_slave)                 |             matmul_axi_slave |       5761 |       5579 |     176 |    6 |  2475 |      0 |      0 |            0 |
+|     mult_inst[0].u_mult                  |         pipelined_mult_32x32 |       1062 |       1062 |       0 |    0 |   192 |      0 |      0 |            0 |
+|     mult_inst[1].u_mult                  |       pipelined_mult_32x32_2 |        999 |        999 |       0 |    0 |   192 |      0 |      0 |            0 |
+|     mult_inst[2].u_mult                  |       pipelined_mult_32x32_3 |       1060 |       1060 |       0 |    0 |   192 |      0 |      0 |            0 |
+|     mult_inst[3].u_mult                  |       pipelined_mult_32x32_4 |        997 |        997 |       0 |    0 |   192 |      0 |      0 |            0 |
+|   u_snix_axil_cdma_mux_8ch               |           snix_axil_cdma_mux |       1557 |       1557 |       0 |    0 |  1476 |      0 |      1 |            0 |
+|     (u_snix_axil_cdma_mux_8ch)           |           snix_axil_cdma_mux |        600 |        600 |       0 |    0 |  1180 |      0 |      0 |            0 |
+|     u_core_engine                        |               snix_axi_mm2mm |        960 |        960 |       0 |    0 |   296 |      0 |      1 |            0 |
+|       (u_core_engine)                    |               snix_axi_mm2mm |        750 |        750 |       0 |    0 |   243 |      0 |      0 |            0 |
+|       axis_fifo_u0                       |               snix_axis_fifo |        210 |        210 |       0 |    0 |    53 |      0 |      1 |            0 |
+|         u_fifo                           |               snix_sync_fifo |        210 |        210 |       0 |    0 |    53 |      0 |      1 |            0 |
++------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
+* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining
+
+

fpga/vivado_reports_withdsp/clock_interaction.rpt

@@ -0,0 +1,28 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+| Date         : Wed Jul  8 02:57:58 2026
+| Host         : fedora running 64-bit unknown
+| Command      : report_clock_interaction -file /home/fallensigh/vivado_reports_withdsp/clock_interaction.rpt
+| Design       : soc_top
+| Device       : 7a200t-fbg676
+| Speed File   : -1  PRODUCTION 1.23 2018-06-13
+--------------------------------------------------------------------------------------------------------------
+
+Clock Interaction Report
+
+Clock Interaction Table
+-----------------------
+
+                                      WNS                            TNS Failing  TNS Total    WNS Path         Clock-Pair           Inter-Clock          
+From Clock         To Clock           Clock Edges  WNS(ns)  TNS(ns)    Endpoints    Endpoints  Requirement(ns)  Classification       Constraints          
+-----------------  -----------------  -----------  -------  -------  -----------  -----------  ---------------  -------------------  -------------------  
+cpu_clk            cpu_clk            rise - rise     1.14     0.00            0        17264            30.32  Clean                Timed                
+cpu_clk            sys_clk                                                     0          162                   Ignored              Asynchronous Groups  
+mlkem_clk_clk_pll  mlkem_clk_clk_pll  rise - rise    12.91     0.00            0        74882            40.00  Clean                Timed                
+mlkem_clk_clk_pll  sys_clk            rise - rise    16.72     0.00            0           61            20.00  Clean                Timed                
+sys_clk            cpu_clk                                                     0           59                   Ignored              Asynchronous Groups  
+sys_clk            mlkem_clk_clk_pll  rise - rise     8.52     0.00            0          112            20.00  Clean                Timed                
+sys_clk            sys_clk            rise - rise     0.42     0.00            0        23732            20.00  Clean                Timed                
+
+

fpga/vivado_reports_withdsp/clocks.rpt

@@ -0,0 +1,76 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+| Date         : Wed Jul  8 02:57:58 2026
+| Host         : fedora running 64-bit unknown
+| Command      : report_clocks -file /home/fallensigh/vivado_reports_withdsp/clocks.rpt
+| Design       : soc_top
+| Device       : 7a200t-fbg676
+| Speed File   : -1  PRODUCTION 1.23 2018-06-13
+----------------------------------------------------------------------------------------
+
+Clock Report
+
+
+Attributes
+  P: Propagated
+  G: Generated
+  A: Auto-derived
+  R: Renamed
+  V: Virtual
+  I: Inverted
+  S: Pin phase-shifted with Latency mode
+
+Clock              Period(ns)  Waveform(ns)    Attributes  Sources
+clk                20.000      {0.000 10.000}  P           {clk}
+clkfbout_clk_pll   20.000      {0.000 10.000}  P,G,A       {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
+cpu_clk            30.323      {0.000 15.161}  P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
+mlkem_clk_clk_pll  40.000      {0.000 20.000}  P,G,A       {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
+sys_clk            20.000      {0.000 10.000}  P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
+
+
+====================================================
+Generated Clocks
+====================================================
+
+Generated Clock     : clkfbout_clk_pll
+Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
+Master Clock        : clk
+Multiply By         : 1
+Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
+
+Generated Clock     : cpu_clk
+Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
+Master Clock        : clk
+Edges               : {1 2 3}
+Edge Shifts(ns)     : {0.000 5.161 10.323}
+Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
+
+Generated Clock     : mlkem_clk_clk_pll
+Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
+Master Clock        : clk
+Edges               : {1 2 3}
+Edge Shifts(ns)     : {0.000 10.000 20.000}
+Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
+
+Generated Clock     : sys_clk
+Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
+Master Clock        : clk
+Multiply By         : 1
+Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
+
+
+
+====================================================
+User Uncertainty
+====================================================
+
+
+
+====================================================
+User Jitter
+====================================================
+
+Clock  Jitter(ns)
+clk    0.200
+

fpga/vivado_reports_withdsp/design_analysis_complexity.rpt

@@ -0,0 +1,37 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+| Date         : Wed Jul  8 02:58:45 2026
+| Host         : fedora running 64-bit unknown
+| Command      : report_design_analysis -complexity -file /home/fallensigh/vivado_reports_withdsp/design_analysis_complexity.rpt
+| Design       : soc_top
+| Device       : xc7a200t
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------
+
+Report Design Analysis
+
+Table of Contents
+-----------------
+1. Complexity Characteristics (Cells)
+
+1. Complexity Characteristics (Cells)
+-------------------------------------
+
++---------------------------+---------------------+------+----------------+-----------------+-----------+------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
+|          Instance         |        Module       | Rent | Average Fanout | Total Instances |    LUT1   |    LUT2    |     LUT3    |     LUT4    |     LUT5    |     LUT6     | Memory LUT | DSP | RAMB | MUXF | URAM |
++---------------------------+---------------------+------+----------------+-----------------+-----------+------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
+| (top)                     |             soc_top | 0.49 |           3.76 |          108219 | 710(1.2%) | 5229(8.7%) | 8166(13.7%) | 8097(13.5%) | 8459(14.1%) | 29130(48.7%) |       1175 |  56 |   39 | 6074 |    0 |
+|  u_axi_axil_adapter       |    axi_axil_adapter | 0.50 |           5.92 |            1309 |   0(0.0%) |    8(0.7%) |    43(3.8%) |   100(8.9%) |  200(17.7%) |   776(68.9%) |          0 |   0 |    0 |    0 |    0 |
+|  u_axi_uart_controller    | axi_uart_controller | 0.55 |           3.54 |            1296 |  10(1.2%) |  84(10.4%) |    80(9.9%) |  144(17.9%) |  194(24.1%) |   293(36.4%) |          0 |   0 |    0 |    9 |    0 |
+|  u_cdma_matmul_bridge     |  cdma_matmul_bridge | 0.56 |           2.22 |            1003 |   1(0.3%) |  66(17.3%) |   39(10.2%) |  174(45.7%) |    13(3.4%) |    88(23.1%) |          0 |   0 |    0 |    0 |    0 |
+|  u_cpu                    |            core_top | 0.56 |           3.96 |           15822 | 168(1.8%) |  579(6.3%) | 1029(11.1%) |   871(9.4%) | 1744(18.9%) |  4860(52.5%) |          0 |   0 |   20 |  276 |    0 |
+|  u_fft_mlkem_axi_slave    | fft_mlkem_axi_slave | 0.53 |           3.70 |           70959 | 286(0.8%) | 3478(9.4%) | 4960(13.4%) | 5940(16.0%) | 4261(11.5%) | 18098(48.9%) |       1169 |  40 |   18 | 5241 |    0 |
+|  u_matmul_axi_slave       |    matmul_axi_slave | 0.69 |           3.39 |           10715 |  18(0.2%) |  465(6.4%) | 1463(20.2%) |   312(4.3%) | 1333(18.4%) |  3646(50.4%) |          6 |  16 |    0 |  512 |    0 |
+|  u_snix_axil_cdma_mux_8ch |  snix_axil_cdma_mux | 0.45 |           3.68 |            3535 | 136(7.0%) |  181(9.3%) |  328(16.8%) |  258(13.2%) |  297(15.2%) |   750(38.5%) |          0 |   0 |    1 |    4 |    0 |
++---------------------------+---------------------+------+----------------+-----------------+-----------+------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
+* Complexity Ranges 
+** 0.0 - 0.3 -> Very Low, 0.3 - 0.5 -> low, 0.5 - 0.65 -> normal,  0.65 - 0.85 -> high, 0.85 - 1.0 -> very high
+*** -* -> Not computable as cell size is very small
+
+

fpga/vivado_reports_withdsp/design_analysis_timing.rpt

@@ -0,0 +1,52 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+| Date         : Wed Jul  8 02:58:13 2026
+| Host         : fedora running 64-bit unknown
+| Command      : report_design_analysis -timing -file /home/fallensigh/vivado_reports_withdsp/design_analysis_timing.rpt
+| Design       : soc_top
+| Device       : xc7a200t
+| Design State : Routed
+-------------------------------------------------------------------------------------------------------------------------
+
+Report Design Analysis
+
+Table of Contents
+-----------------
+1. Setup Path Characteristics 1-1
+
+1. Setup Path Characteristics 1-1
+---------------------------------
+
++---------------------------+----------------------------------------------------------------------------------------+
+|      Characteristics      |                                         Path #1                                        |
++---------------------------+----------------------------------------------------------------------------------------+
+| Requirement               |                                                                                 20.000 |
+| Path Delay                |                                                                                 15.252 |
+| Logic Delay               | 7.003(46%)                                                                             |
+| Net Delay                 | 8.249(54%)                                                                             |
+| Clock Skew                |                                                                                 -3.954 |
+| Slack                     |                                                                                  0.424 |
+| Clock Relationship        | Safely Timed                                                                           |
+| Logic Levels              |                                                                                     14 |
+| Routes                    |                                                                                     12 |
+| Logical Path              | FDCE LUT4 LUT5 LUT6 CARRY4 CARRY4 CARRY4 CARRY4 CARRY4 LUT6 CARRY4 LUT6 LUT6 LUT6 OBUF |
+| Start Point Clock         | sys_clk                                                                                |
+| End Point Clock           | sys_clk                                                                                |
+| DSP Block                 | None                                                                                   |
+| BRAM                      | None                                                                                   |
+| IO Crossings              |                                                                                      3 |
+| Config Crossings          |                                                                                      0 |
+| SLR Crossings             |                                                                                      0 |
+| PBlocks                   |                                                                                      0 |
+| High Fanout               |                                                                                     80 |
+| Dont Touch                |                                                                                      0 |
+| Mark Debug                |                                                                                      0 |
+| Start Point Pin Primitive | FDCE/C                                                                                 |
+| End Point Pin Primitive   | base_ram_be_n[3]                                                                       |
+| Start Point Pin           | ax_req_q_len_reg[1]/C                                                                  |
+| End Point Pin             | base_ram_be_n[3]                                                                       |
++---------------------------+----------------------------------------------------------------------------------------+
+* Bounding box calculated as % of dimensions for the target device (436, 500)
+
+

fpga/vivado_reports_withdsp/drc.rpt

@@ -0,0 +1,911 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+| Date         : Wed Jul  8 02:57:43 2026
+| Host         : fedora running 64-bit unknown
+| Command      : report_drc -file /home/fallensigh/vivado_reports_withdsp/drc.rpt
+| Design       : soc_top
+| Device       : xc7a200tfbg676-1
+| Speed File   : -1
+| Design State : Fully Routed
+------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: impl_1
+      Design limits: <entire design considered>
+           Ruledeck: default
+             Max violations: <unlimited>
+             Violations found: 174
++-----------+----------+----------------------------+------------+
+| Rule      | Severity | Description                | Violations |
++-----------+----------+----------------------------+------------+
+| CHECK-3   | Warning  | Report rule limit reached  | 2          |
+| DPIP-1    | Warning  | Input pipelining           | 47         |
+| DPOP-1    | Warning  | PREG Output pipelining     | 29         |
+| DPOP-2    | Warning  | MREG Output pipelining     | 56         |
+| REQP-1839 | Warning  | RAMB36 async control check | 20         |
+| REQP-1840 | Warning  | RAMB18 async control check | 20         |
++-----------+----------+----------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+CHECK-3#1 Warning
+Report rule limit reached  
+REQP-1839 rule limit reached: 20 violations have been found.
+Related violations: <none>
+
+CHECK-3#2 Warning
+Report rule limit reached  
+REQP-1840 rule limit reached: 20 violations have been found.
+Related violations: <none>
+
+DPIP-1#1 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#2 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#3 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#4 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#5 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#6 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#7 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#8 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#9 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#10 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#11 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#12 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#13 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#14 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#15 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#16 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#17 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#18 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#19 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#20 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#21 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#22 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#23 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#24 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/tk_s20 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/tk_s20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#25 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#26 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#27 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/tk_s20 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/tk_s20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#28 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q0_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q0_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#29 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q1_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q1_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#30 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q2_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q2_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#31 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q3_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q3_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#32 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#33 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#34 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#35 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#36 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#37 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#38 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#39 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#40 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#41 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#42 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#43 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#44 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#45 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#46 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPIP-1#47 Warning
+Input pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
+Related violations: <none>
+
+DPOP-1#1 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#2 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#3 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#4 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#5 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#6 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#7 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#8 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#9 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#10 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#11 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#12 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#13 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#14 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#15 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#16 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#17 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#18 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#19 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#20 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#21 Warning
+PREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#22 Warning
+PREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod0__16 output u_matmul_axi_slave/mult_inst[0].u_mult/prod0__16/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#23 Warning
+PREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17 output u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#24 Warning
+PREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod0 output u_matmul_axi_slave/mult_inst[1].u_mult/prod0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#25 Warning
+PREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17 output u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#26 Warning
+PREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod0 output u_matmul_axi_slave/mult_inst[2].u_mult/prod0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#27 Warning
+PREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod0__17 output u_matmul_axi_slave/mult_inst[2].u_mult/prod0__17/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#28 Warning
+PREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod0 output u_matmul_axi_slave/mult_inst[3].u_mult/prod0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-1#29 Warning
+PREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod0__17 output u_matmul_axi_slave/mult_inst[3].u_mult/prod0__17/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
+Related violations: <none>
+
+DPOP-2#1 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#2 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#3 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#4 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#5 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#6 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#7 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#8 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#9 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#10 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#11 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#12 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#13 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#14 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#15 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#16 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#17 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#18 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#19 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#20 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#21 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#22 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/tk_s20 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/tk_s20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#23 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#24 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#25 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/tk_s20 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/tk_s20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#26 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q0_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q0_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#27 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q1_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q1_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#28 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q2_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q2_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#29 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q3_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q3_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#30 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#31 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#32 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#33 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#34 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#35 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#36 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#37 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#38 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#39 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#40 Warning
+MREG Output pipelining  
+DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#41 Warning
+MREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod0__16 multiplier stage u_matmul_axi_slave/mult_inst[0].u_mult/prod0__16/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#42 Warning
+MREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17 multiplier stage u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#43 Warning
+MREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg multiplier stage u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#44 Warning
+MREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0 multiplier stage u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#45 Warning
+MREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod0 multiplier stage u_matmul_axi_slave/mult_inst[1].u_mult/prod0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#46 Warning
+MREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17 multiplier stage u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#47 Warning
+MREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg multiplier stage u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#48 Warning
+MREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0 multiplier stage u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#49 Warning
+MREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod0 multiplier stage u_matmul_axi_slave/mult_inst[2].u_mult/prod0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#50 Warning
+MREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod0__17 multiplier stage u_matmul_axi_slave/mult_inst[2].u_mult/prod0__17/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#51 Warning
+MREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg multiplier stage u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#52 Warning
+MREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg__0 multiplier stage u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#53 Warning
+MREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod0 multiplier stage u_matmul_axi_slave/mult_inst[3].u_mult/prod0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#54 Warning
+MREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod0__17 multiplier stage u_matmul_axi_slave/mult_inst[3].u_mult/prod0__17/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#55 Warning
+MREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg multiplier stage u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+DPOP-2#56 Warning
+MREG Output pipelining  
+DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg__0 multiplier stage u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
+Related violations: <none>
+
+REQP-1839#1 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#2 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#3 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#4 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#5 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#6 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#7 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#8 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#9 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#10 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#11 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#12 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#13 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#14 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#15 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#16 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#17 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#18 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#19 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1839#20 Warning
+RAMB36 async control check  
+The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#1 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#2 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#3 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#4 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#5 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#6 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#7 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#8 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#9 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#10 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#11 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#12 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#13 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#14 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#15 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#16 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#17 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENARDEN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_1__15_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#18 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENBWREN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_2__13_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#19 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[2] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+REQP-1840#20 Warning
+RAMB18 async control check  
+The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[3] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+Related violations: <none>
+
+

fpga/vivado_reports_withdsp/high_fanout.rpt

@@ -0,0 +1,221 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+| Date         : Wed Jul  8 02:57:58 2026
+| Host         : fedora running 64-bit unknown
+| Command      : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/vivado_reports_withdsp/high_fanout.rpt
+| Design       : soc_top
+| Device       : xc7a200t
+----------------------------------------------------------------------------------------------------------------------------------------------
+
+High Fan-out Nets Information
+
+1. Summary
+----------
+
++---------------------------------------------------------------------------------------+--------+-------------+
+| Net Name                                                                              | Fanout | Driver Type |
++---------------------------------------------------------------------------------------+--------+-------------+
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/delay_reg[1]              |  24229 | LUT5        |
+| pll_clk.u_clk_pll/inst/sys_clk                                                        |   9603 | BUFG        |
+| pll_clk.u_rst_sys/prst                                                                |   3749 | LUT1        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_0                                        |   2140 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mb_en                   |   2121 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/E[0]                         |   2048 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0               |   1611 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_0[0]              |   1608 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state[2]_i_3_n_0 |   1604 | LUT5        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0        |   1601 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0]                   |   1601 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[1]                   |   1601 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[2]                   |   1601 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0       |   1600 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1                 |   1122 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0                     |   1088 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0                     |   1088 | FDRE        |
+| pll_clk.u_rst_mlkem/delay_reg[1]_0                                                    |   1066 | LUT1        |
+| u_cpu/reset                                                                           |    799 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sel0[3]                        |    773 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[0]  |    769 | CARRY4      |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[1]  |    769 | CARRY4      |
+| u_cpu/u_mul/E[0]                                                                      |    716 | LUT1        |
+| u_matmul_axi_slave/w_addr[2]                                                          |    667 | FDRE        |
+| u_matmul_axi_slave/w_addr[3]                                                          |    604 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0              |    512 | LUT2        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[0]_0[0]                 |    512 | LUT5        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sel0[4]                        |    388 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[2]  |    385 | CARRY4      |
+| u_cpu/wb_stage/w_index[0]                                                             |    358 | LUT6        |
+| u_cpu/wb_stage/w_index[1]                                                             |    358 | LUT6        |
+| u_cpu/wb_stage/w_index[2]                                                             |    358 | LUT6        |
+| u_cpu/wb_stage/w_index[3]                                                             |    358 | LUT6        |
+| u_cpu/wb_stage/w_index[4]                                                             |    358 | LUT6        |
+| u_matmul_axi_slave/Q[0]                                                               |    354 | FDRE        |
+| u_matmul_axi_slave/acc_idx_d4[0]                                                      |    354 | FDRE        |
+| u_matmul_axi_slave/acc_idx_d4[1]                                                      |    354 | FDRE        |
+| u_matmul_axi_slave/acc_idx_d4[2]                                                      |    354 | FDRE        |
+| u_matmul_axi_slave/acc_idx_d4[3]                                                      |    354 | FDRE        |
+| u_cpu/wb_stage/we_0                                                                   |    324 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1                         |    290 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r_reg[255]_i_5_n_4                |    288 | CARRY4      |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[4]                      |    272 | FDCE        |
+| u_matmul_axi_slave/sel0[1]                                                            |    264 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10]                  |    263 | RAMB18E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11]                  |    263 | RAMB18E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8]                   |    262 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc                      |    262 | LUT5        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7]                   |    261 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9]                   |    261 | RAMB18E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0]                    |    261 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10]                   |    261 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11]                   |    261 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1]                    |    261 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2]                    |    261 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3]                    |    261 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4]                    |    261 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5]                    |    261 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6]                    |    261 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7]                    |    261 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8]                    |    261 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9]                    |    261 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0]                   |    259 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1]                   |    259 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2]                   |    259 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3]                   |    259 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4]                   |    259 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5]                   |    259 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6]                   |    259 | RAMB36E1    |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[0]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[10]                   |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[11]                   |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[1]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[2]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[3]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[4]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[5]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[6]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[7]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[8]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[9]                    |    256 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/E[0]                           |    256 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r                    |    256 | LUT3        |
+| u_matmul_axi_slave/mult_inst[0].u_mult/E[0]                                           |    256 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode                    |    250 | LUT4        |
+| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge                                  |    245 | LUT3        |
+| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[0]                                     |    244 | FDSE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[7]                      |    239 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[2]                      |    238 | FDCE        |
+| u_cpu/exe_stage/ds_to_es_bus_r0                                                       |    234 | LUT5        |
+| u_cpu/mem_stage/E[0]                                                                  |    234 | LUT6        |
+| u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/axiOut_7_wstrb[0]          |    232 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10]                 |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11]                 |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10]                 |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11]                 |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9]                  |    231 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1022]_i_2_n_0              |    224 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[126]_i_2_n_0               |    224 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[254]_i_2_n_0               |    224 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[382]_i_2_n_0               |    224 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[510]_i_2_n_0               |    224 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[638]_i_2_n_0               |    224 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[766]_i_2_n_0               |    224 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[894]_i_2_n_0               |    224 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[5]                      |    223 | FDCE        |
+| u_matmul_axi_slave/w_addr[5]                                                          |    223 | FDRE        |
+| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0                            |    211 | LUT2        |
+| u_cpu/mem_stage/es_to_ms_bus_r0                                                       |    210 | LUT2        |
+| u_cpu/u_csr/tlbw_r_tlbidx[2]                                                          |    210 | FDRE        |
+| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[0]                                           |    203 | FDRE        |
+| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[1]                                           |    203 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/grp_ptr_r_reg_n_0_[2]           |    196 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[6]                      |    195 | FDCE        |
+| u_cpu/wb_stage/Q[33]                                                                  |    194 | FDRE        |
+| u_cpu/wb_stage/Q[34]                                                                  |    194 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[5]             |    194 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[3]  |    193 | CARRY4      |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4]                      |    188 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r_reg[3]_rep_n_0          |    187 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1]                      |    184 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6]                      |    184 | FDCE        |
+| u_snix_axil_cdma_mux_8ch/u_core_engine/_zz_ram_port1_reg[32]                          |    182 | LUT4        |
+| u_cpu/wb_stage/ws_valid_reg_0                                                         |    180 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r_reg[5]_rep_n_0          |    180 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1]                      |    179 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[0]                      |    177 | FDCE        |
+| u_matmul_axi_slave/p_0_in__0                                                          |    176 | LUT4        |
+| u_matmul_axi_slave/p_0_in__0__0                                                       |    176 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2]                             |    174 | FDCE        |
+| u_cpu/wb_stage/Q[37]                                                                  |    173 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_out[0]                                    |    169 | CARRY4      |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[2]_rep__0_n_0                      |    168 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[4]                     |    165 | FDCE        |
+| u_cpu/wb_stage/Q[32]                                                                  |    164 | FDRE        |
+| u_cpu/wb_stage/Q[35]                                                                  |    163 | FDRE        |
+| u_cpu/wb_stage/Q[36]                                                                  |    162 | FDRE        |
+| u_axi_axil_adapter/axi_axil_adapter_rd_inst/m_axil_araddr_reg_reg[2]_0                |    161 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[6]                     |    161 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0]                      |    160 | FDCE        |
+| u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]_0                         |    160 | LUT5        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[3]                     |    158 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3]                             |    156 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r_reg[255]_i_5_n_5                |    153 | CARRY4      |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[0]                     |    153 | FDCE        |
+| u_cpu/axi_bridge/FSM_sequential_write_requst_state_reg[1]_0                           |    151 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep_n_0                     |    151 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[7]                     |    151 | FDCE        |
+| u_snix_axil_cdma_mux_8ch/u_core_engine/num_bytes_comb1                                |    150 | CARRY4      |
+| u_cpu/dcache/awaddr[31]_i_3_n_0                                                       |    148 | LUT2        |
+| u_cpu/dcache/awaddr[31]_i_4_n_0                                                       |    148 | LUT2        |
+| u_matmul_axi_slave/mult_inst[3].u_mult/FSM_sequential_state_reg                       |    148 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]                                 |    146 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_12_17_i_57_n_0                    |    144 | LUT4        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[1]                    |    142 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[4]                  |    141 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[5]                  |    141 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[6]                  |    141 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[7]                  |    141 | FDCE        |
+| u_cpu/dcache/write_buffer_state                                                       |    140 | FDRE        |
+| u_matmul_axi_slave/mult_inst[3].u_mult/cur_bank_reg_rep                               |    140 | LUT3        |
+| u_matmul_axi_slave/mult_inst[3].u_mult/req_0_reg                                      |    140 | LUT3        |
+| u_snix_axil_cdma_mux_8ch/ADDRA[0]                                                     |    140 | LUT6        |
+| u_cpu/u_csr/tlbw_r_tlbidx[0]                                                          |    139 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[3]                    |    139 | FDCE        |
+| u_matmul_axi_slave/sel0[0]                                                            |    139 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[3]                  |    138 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[2]                    |    138 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]_i_5_n_7                     |    137 | CARRY4      |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_6_11_i_34_n_0                     |    137 | LUT4        |
+| u_cpu/u_csr/tlbw_r_tlbidx[1]                                                          |    136 | FDRE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1080]_i_5_n_0              |    136 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1081]_i_5_n_0              |    136 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1082]_i_5_n_0              |    136 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1083]_i_5_n_0              |    136 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1084]_i_6_n_0              |    136 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1087]_i_3_n_0              |    136 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1087]_i_9_n_0              |    136 | LUT6        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1087]_i_3_n_0               |    136 | LUT3        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/rl_idx[3]                             |    136 | FDCE        |
+| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0                     |    136 | FDCE        |
++---------------------------------------------------------------------------------------+--------+-------------+
+
+

fpga/vivado_reports_withdsp/power.rpt

@@ -0,0 +1,179 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------------------
+| Tool Version     : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+| Date             : Wed Jul  8 02:58:09 2026
+| Host             : fedora running 64-bit unknown
+| Command          : report_power -file /home/fallensigh/vivado_reports_withdsp/power.rpt
+| Design           : soc_top
+| Device           : xc7a200tfbg676-1
+| Design State     : routed
+| Grade            : commercial
+| Process          : typical
+| Characterization : Production
+--------------------------------------------------------------------------------------------------
+
+Power Report
+
+Table of Contents
+-----------------
+1. Summary
+1.1 On-Chip Components
+1.2 Power Supply Summary
+1.3 Confidence Level
+2. Settings
+2.1 Environment
+2.2 Clock Constraints
+3. Detailed Reports
+3.1 By Hierarchy
+
+1. Summary
+----------
+
++--------------------------+--------------+
+| Total On-Chip Power (W)  | 0.512        |
+| Design Power Budget (W)  | Unspecified* |
+| Power Budget Margin (W)  | NA           |
+| Dynamic (W)              | 0.371        |
+| Device Static (W)        | 0.141        |
+| Effective TJA (C/W)      | 1.9          |
+| Max Ambient (C)          | 84.0         |
+| Junction Temperature (C) | 26.0         |
+| Confidence Level         | Low          |
+| Setting File             | ---          |
+| Simulation Activity File | ---          |
+| Design Nets Matched      | NA           |
++--------------------------+--------------+
+* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
+
+
+1.1 On-Chip Components
+----------------------
+
++--------------------------+-----------+----------+-----------+-----------------+
+| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
++--------------------------+-----------+----------+-----------+-----------------+
+| Clocks                   |     0.037 |        7 |       --- |             --- |
+| Slice Logic              |     0.056 |   109753 |       --- |             --- |
+|   LUT as Logic           |     0.052 |    56469 |    133800 |           42.20 |
+|   CARRY4                 |     0.001 |     1802 |     33450 |            5.39 |
+|   Register               |    <0.001 |    39141 |    267600 |           14.63 |
+|   LUT as Shift Register  |    <0.001 |     1175 |     46200 |            2.54 |
+|   LUT as Distributed RAM |    <0.001 |      740 |     46200 |            1.60 |
+|   F7/F8 Muxes            |    <0.001 |     6090 |    133800 |            4.55 |
+|   Others                 |     0.000 |      334 |       --- |             --- |
+| Signals                  |     0.095 |    78236 |       --- |             --- |
+| Block RAM                |     0.018 |     23.5 |       365 |            6.44 |
+| PLL                      |     0.132 |        1 |        10 |           10.00 |
+| DSPs                     |     0.010 |       56 |       740 |            7.57 |
+| I/O                      |     0.023 |      202 |       400 |           50.50 |
+| Static Power             |     0.141 |          |           |                 |
+| Total                    |     0.512 |          |           |                 |
++--------------------------+-----------+----------+-----------+-----------------+
+
+
+1.2 Power Supply Summary
+------------------------
+
++-----------+-------------+-----------+-------------+------------+
+| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
++-----------+-------------+-----------+-------------+------------+
+| Vccint    |       1.000 |     0.257 |       0.225 |      0.032 |
+| Vccaux    |       1.800 |     0.099 |       0.069 |      0.031 |
+| Vcco33    |       3.300 |     0.011 |       0.006 |      0.005 |
+| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
+| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |
+| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
+| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
+| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
+| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
+| Vccbram   |       1.000 |     0.003 |       0.001 |      0.001 |
+| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |
+| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |
+| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
++-----------+-------------+-----------+-------------+------------+
+
+
+1.3 Confidence Level
+--------------------
+
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| Design implementation state | High       | Design is routed                                       |                                                                                                            |
+| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
+| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
+| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
+| Device models               | High       | Device models are Production                           |                                                                                                            |
+|                             |            |                                                        |                                                                                                            |
+| Overall confidence level    | Low        |                                                        |                                                                                                            |
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+
+
+2. Settings
+-----------
+
+2.1 Environment
+---------------
+
++-----------------------+--------------------------+
+| Ambient Temp (C)      | 25.0                     |
+| ThetaJA (C/W)         | 1.9                      |
+| Airflow (LFM)         | 250                      |
+| Heat Sink             | medium (Medium Profile)  |
+| ThetaSA (C/W)         | 3.4                      |
+| Board Selection       | medium (10"x10")         |
+| # of Board Layers     | 12to15 (12 to 15 Layers) |
+| Board Temperature (C) | 25.0                     |
++-----------------------+--------------------------+
+
+
+2.2 Clock Constraints
+---------------------
+
++-------------------+------------------------------------------+-----------------+
+| Clock             | Domain                                   | Constraint (ns) |
++-------------------+------------------------------------------+-----------------+
+| clk               | clk                                      |            20.0 |
+| clkfbout_clk_pll  | pll_clk.u_clk_pll/inst/clkfbout_clk_pll  |            20.0 |
+| cpu_clk           | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll   |            30.3 |
+| mlkem_clk_clk_pll | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll |            40.0 |
+| sys_clk           | pll_clk.u_clk_pll/inst/sys_clk_clk_pll   |            20.0 |
++-------------------+------------------------------------------+-----------------+
+
+
+3. Detailed Reports
+-------------------
+
+3.1 By Hierarchy
+----------------
+
++----------------------------+-----------+
+| Name                       | Power (W) |
++----------------------------+-----------+
+| soc_top                    |     0.371 |
+|   pll_clk.u_clk_pll        |     0.133 |
+|     inst                   |     0.133 |
+|   u_Axi_CDC                |     0.002 |
+|     wFifo                  |     0.001 |
+|   u_axi_uart_controller    |     0.001 |
+|   u_cdma_matmul_bridge     |     0.001 |
+|   u_cpu                    |     0.017 |
+|     addr_trans             |     0.002 |
+|       tlb_entry            |     0.002 |
+|     btb                    |     0.003 |
+|     dcache                 |     0.004 |
+|     icache                 |     0.005 |
+|     u_csr                  |     0.001 |
+|   u_fft_mlkem_axi_slave    |     0.134 |
+|     u_fft_controller       |     0.032 |
+|       u_FFT                |     0.030 |
+|     u_mlkem_axi_cdc        |     0.001 |
+|     u_mlkem_axi_slave      |     0.101 |
+|       u_mlkem              |     0.098 |
+|   u_matmul_axi_slave       |     0.047 |
+|   u_snix_axil_cdma_mux_8ch |     0.008 |
+|     u_core_engine          |     0.004 |
+|       axis_fifo_u0         |     0.002 |
++----------------------------+-----------+
+
+

fpga/vivado_reports_withdsp/route_status.rpt

@@ -0,0 +1,12 @@
+Design Route Status
+                                               :      # nets :
+   ------------------------------------------- : ----------- :
+   # of logical nets.......................... :      116330 :
+       # of nets not needing routing.......... :       38083 :
+           # of internally routed nets........ :       37618 :
+           # of nets with no loads............ :         465 :
+       # of routable nets..................... :       78247 :
+           # of fully routed nets............. :       78247 :
+       # of nets with routing errors.......... :           0 :
+   ------------------------------------------- : ----------- :
+

fpga/vivado_reports_withdsp/utilization.rpt

@@ -0,0 +1,237 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+| Date         : Wed Jul  8 02:57:49 2026
+| Host         : fedora running 64-bit unknown
+| Command      : report_utilization -file /home/fallensigh/vivado_reports_withdsp/utilization.rpt
+| Design       : soc_top
+| Device       : 7a200tfbg676-1
+| Design State : Routed
+--------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Slice Logic Distribution
+3. Memory
+4. DSP
+5. IO and GT Specific
+6. Clocking
+7. Specific Feature
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++----------------------------+-------+-------+-----------+-------+
+|          Site Type         |  Used | Fixed | Available | Util% |
++----------------------------+-------+-------+-----------+-------+
+| Slice LUTs                 | 53691 |     0 |    133800 | 40.13 |
+|   LUT as Logic             | 51836 |     0 |    133800 | 38.74 |
+|   LUT as Memory            |  1855 |     0 |     46200 |  4.02 |
+|     LUT as Distributed RAM |   740 |     0 |           |       |
+|     LUT as Shift Register  |  1115 |     0 |           |       |
+| Slice Registers            | 39141 |     0 |    267600 | 14.63 |
+|   Register as Flip Flop    | 39141 |     0 |    267600 | 14.63 |
+|   Register as Latch        |     0 |     0 |    267600 |  0.00 |
+| F7 Muxes                   |  4519 |     0 |     66900 |  6.75 |
+| F8 Muxes                   |  1571 |     0 |     33450 |  4.70 |
++----------------------------+-------+-------+-----------+-------+
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 24    |          Yes |           - |          Set |
+| 26265 |          Yes |           - |        Reset |
+| 126   |          Yes |         Set |            - |
+| 12726 |          Yes |       Reset |            - |
++-------+--------------+-------------+--------------+
+
+
+2. Slice Logic Distribution
+---------------------------
+
++--------------------------------------------+-------+-------+-----------+-------+
+|                  Site Type                 |  Used | Fixed | Available | Util% |
++--------------------------------------------+-------+-------+-----------+-------+
+| Slice                                      | 18732 |     0 |     33450 | 56.00 |
+|   SLICEL                                   | 12122 |     0 |           |       |
+|   SLICEM                                   |  6610 |     0 |           |       |
+| LUT as Logic                               | 51836 |     0 |    133800 | 38.74 |
+|   using O5 output only                     |     4 |       |           |       |
+|   using O6 output only                     | 43877 |       |           |       |
+|   using O5 and O6                          |  7955 |       |           |       |
+| LUT as Memory                              |  1855 |     0 |     46200 |  4.02 |
+|   LUT as Distributed RAM                   |   740 |     0 |           |       |
+|     using O5 output only                   |     0 |       |           |       |
+|     using O6 output only                   |    60 |       |           |       |
+|     using O5 and O6                        |   680 |       |           |       |
+|   LUT as Shift Register                    |  1115 |     0 |           |       |
+|     using O5 output only                   |    47 |       |           |       |
+|     using O6 output only                   |  1008 |       |           |       |
+|     using O5 and O6                        |    60 |       |           |       |
+| Slice Registers                            | 39141 |     0 |    267600 | 14.63 |
+|   Register driven from within the Slice    | 19059 |       |           |       |
+|   Register driven from outside the Slice   | 20082 |       |           |       |
+|     LUT in front of the register is unused | 11401 |       |           |       |
+|     LUT in front of the register is used   |  8681 |       |           |       |
+| Unique Control Sets                        |  1440 |       |     33450 |  4.30 |
++--------------------------------------------+-------+-------+-----------+-------+
+* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
+
+
+3. Memory
+---------
+
++-------------------+------+-------+-----------+-------+
+|     Site Type     | Used | Fixed | Available | Util% |
++-------------------+------+-------+-----------+-------+
+| Block RAM Tile    | 23.5 |     0 |       365 |  6.44 |
+|   RAMB36/FIFO*    |    8 |     0 |       365 |  2.19 |
+|     RAMB36E1 only |    8 |       |           |       |
+|   RAMB18          |   31 |     0 |       730 |  4.25 |
+|     RAMB18E1 only |   31 |       |           |       |
++-------------------+------+-------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+4. DSP
+------
+
++----------------+------+-------+-----------+-------+
+|    Site Type   | Used | Fixed | Available | Util% |
++----------------+------+-------+-----------+-------+
+| DSPs           |   56 |     0 |       740 |  7.57 |
+|   DSP48E1 only |   56 |       |           |       |
++----------------+------+-------+-----------+-------+
+
+
+5. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+-----------+-------+
+|          Site Type          | Used | Fixed | Available | Util% |
++-----------------------------+------+-------+-----------+-------+
+| Bonded IOB                  |  202 |   202 |       400 | 50.50 |
+|   IOB Master Pads           |   97 |       |           |       |
+|   IOB Slave Pads            |  102 |       |           |       |
+| Bonded IPADs                |    0 |     0 |        26 |  0.00 |
+| Bonded OPADs                |    0 |     0 |        16 |  0.00 |
+| PHY_CONTROL                 |    0 |     0 |        10 |  0.00 |
+| PHASER_REF                  |    0 |     0 |        10 |  0.00 |
+| OUT_FIFO                    |    0 |     0 |        40 |  0.00 |
+| IN_FIFO                     |    0 |     0 |        40 |  0.00 |
+| IDELAYCTRL                  |    0 |     0 |        10 |  0.00 |
+| IBUFDS                      |    0 |     0 |       384 |  0.00 |
+| GTPE2_CHANNEL               |    0 |     0 |         8 |  0.00 |
+| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |        40 |  0.00 |
+| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |        40 |  0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |       500 |  0.00 |
+| IBUFDS_GTE2                 |    0 |     0 |         4 |  0.00 |
+| ILOGIC                      |    0 |     0 |       400 |  0.00 |
+| OLOGIC                      |    0 |     0 |       400 |  0.00 |
++-----------------------------+------+-------+-----------+-------+
+
+
+6. Clocking
+-----------
+
++------------+------+-------+-----------+-------+
+|  Site Type | Used | Fixed | Available | Util% |
++------------+------+-------+-----------+-------+
+| BUFGCTRL   |    4 |     0 |        32 | 12.50 |
+| BUFIO      |    0 |     0 |        40 |  0.00 |
+| MMCME2_ADV |    0 |     0 |        10 |  0.00 |
+| PLLE2_ADV  |    1 |     0 |        10 | 10.00 |
+| BUFMRCE    |    0 |     0 |        20 |  0.00 |
+| BUFHCE     |    0 |     0 |       120 |  0.00 |
+| BUFR       |    0 |     0 |        40 |  0.00 |
++------------+------+-------+-----------+-------+
+
+
+7. Specific Feature
+-------------------
+
++-------------+------+-------+-----------+-------+
+|  Site Type  | Used | Fixed | Available | Util% |
++-------------+------+-------+-----------+-------+
+| BSCANE2     |    0 |     0 |         4 |  0.00 |
+| CAPTUREE2   |    0 |     0 |         1 |  0.00 |
+| DNA_PORT    |    0 |     0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
+| FRAME_ECCE2 |    0 |     0 |         1 |  0.00 |
+| ICAPE2      |    0 |     0 |         2 |  0.00 |
+| PCIE_2_1    |    0 |     0 |         1 |  0.00 |
+| STARTUPE2   |    0 |     0 |         1 |  0.00 |
+| XADC        |    0 |     0 |         1 |  0.00 |
++-------------+------+-------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++-----------+-------+---------------------+
+|  Ref Name |  Used | Functional Category |
++-----------+-------+---------------------+
+| LUT6      | 29130 |                 LUT |
+| FDCE      | 26265 |        Flop & Latch |
+| FDRE      | 12726 |        Flop & Latch |
+| LUT5      |  8459 |                 LUT |
+| LUT3      |  8166 |                 LUT |
+| LUT4      |  8097 |                 LUT |
+| LUT2      |  5229 |                 LUT |
+| MUXF7     |  4519 |               MuxFx |
+| CARRY4    |  1802 |          CarryLogic |
+| MUXF8     |  1571 |               MuxFx |
+| RAMD32    |  1060 |  Distributed Memory |
+| SRLC32E   |   992 |  Distributed Memory |
+| LUT1      |   710 |                 LUT |
+| RAMS32    |   328 |  Distributed Memory |
+| SRL16E    |   183 |  Distributed Memory |
+| FDSE      |   126 |        Flop & Latch |
+| IBUF      |   104 |                  IO |
+| OBUF      |    98 |                  IO |
+| OBUFT     |    66 |                  IO |
+| DSP48E1   |    56 |    Block Arithmetic |
+| RAMD64E   |    32 |  Distributed Memory |
+| RAMB18E1  |    31 |        Block Memory |
+| FDPE      |    24 |        Flop & Latch |
+| RAMB36E1  |     8 |        Block Memory |
+| BUFG      |     4 |               Clock |
+| PLLE2_ADV |     1 |               Clock |
++-----------+-------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+| clk_pll  |    1 |
++----------+------+
+
+

fpga/vivado_reports_withdsp/utilization_hier.rpt

@@ -0,0 +1,276 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+| Date         : Wed Jul  8 02:57:50 2026
+| Host         : fedora running 64-bit unknown
+| Command      : report_utilization -hierarchical -file /home/fallensigh/vivado_reports_withdsp/utilization_hier.rpt
+| Design       : soc_top
+| Device       : 7a200tfbg676-1
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Utilization by Hierarchy
+
+1. Utilization by Hierarchy
+---------------------------
+
++------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
+|                 Instance                 |            Module            | Total LUTs | Logic LUTs | LUTRAMs | SRLs |  FFs  | RAMB36 | RAMB18 | DSP48 Blocks |
++------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
+| soc_top                                  |                        (top) |      53691 |      51836 |     740 | 1115 | 39141 |      8 |     31 |           56 |
+|   (soc_top)                              |                        (top) |        102 |         46 |      56 |    0 |     9 |      0 |      0 |            0 |
+|   pll_clk.u_clk_pll                      |                      clk_pll |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
+|     inst                                 |     clk_pll__clk_pll_clk_wiz |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
+|   pll_clk.u_rst_cpu                      |                     rst_sync |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
+|   pll_clk.u_rst_mlkem                    |                   rst_sync_0 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
+|   pll_clk.u_rst_sys                      |                   rst_sync_1 |          2 |          2 |       0 |    0 |     2 |      0 |      0 |            0 |
+|   u_AxiCrossbar_2x8                      |              AxiCrossbar_2x8 |        381 |        381 |       0 |    0 |   151 |      0 |      0 |            0 |
+|     (u_AxiCrossbar_2x8)                  |              AxiCrossbar_2x8 |          6 |          6 |       0 |    0 |    24 |      0 |      0 |            0 |
+|     axi4ReadOnlyArbiter_4                |          Axi4ReadOnlyArbiter |         18 |         18 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_82 |         18 |         18 |       0 |    0 |     3 |      0 |      0 |            0 |
+|     axi4ReadOnlyArbiter_5                |       Axi4ReadOnlyArbiter_65 |          6 |          6 |       0 |    0 |     2 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_81 |          6 |          6 |       0 |    0 |     2 |      0 |      0 |            0 |
+|     axi4ReadOnlyArbiter_6                |       Axi4ReadOnlyArbiter_66 |         16 |         16 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_80 |         16 |         16 |       0 |    0 |     3 |      0 |      0 |            0 |
+|     axi4ReadOnlyArbiter_7                |       Axi4ReadOnlyArbiter_67 |         16 |         16 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_79 |         16 |         16 |       0 |    0 |     3 |      0 |      0 |            0 |
+|     axi4WriteOnlyArbiter_4               |         Axi4WriteOnlyArbiter |         33 |         33 |       0 |    0 |    11 |      0 |      0 |            0 |
+|       (axi4WriteOnlyArbiter_4)           |         Axi4WriteOnlyArbiter |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_76 |         27 |         27 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdRouteFork_translated_fifo       |    StreamFifoLowLatency_3_77 |          7 |          7 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         fifo                             |              StreamFifo_3_78 |          7 |          7 |       0 |    0 |     6 |      0 |      0 |            0 |
+|     axi4WriteOnlyArbiter_5               |       Axi4WriteOnlyArbiter_1 |         15 |         15 |       0 |    0 |     9 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_73 |          7 |          7 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdRouteFork_translated_fifo       |    StreamFifoLowLatency_3_74 |          8 |          8 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         fifo                             |              StreamFifo_3_75 |          8 |          8 |       0 |    0 |     6 |      0 |      0 |            0 |
+|     axi4WriteOnlyArbiter_6               |       Axi4WriteOnlyArbiter_2 |         29 |         29 |       0 |    0 |    11 |      0 |      0 |            0 |
+|       (axi4WriteOnlyArbiter_6)           |       Axi4WriteOnlyArbiter_2 |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
+|       cmdArbiter                         |           StreamArbiter_7_70 |         20 |         20 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdRouteFork_translated_fifo       |    StreamFifoLowLatency_3_71 |          9 |          9 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         fifo                             |              StreamFifo_3_72 |          9 |          9 |       0 |    0 |     6 |      0 |      0 |            0 |
+|     axi4WriteOnlyArbiter_7               |       Axi4WriteOnlyArbiter_3 |         23 |         23 |       0 |    0 |    11 |      0 |      0 |            0 |
+|       (axi4WriteOnlyArbiter_7)           |       Axi4WriteOnlyArbiter_3 |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
+|       cmdArbiter                         |              StreamArbiter_7 |         15 |         15 |       0 |    0 |     3 |      0 |      0 |            0 |
+|       cmdRouteFork_translated_fifo       |       StreamFifoLowLatency_3 |          8 |          8 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         fifo                             |                 StreamFifo_3 |          8 |          8 |       0 |    0 |     6 |      0 |      0 |            0 |
+|     axiIn_0_readOnly_decoder             |          Axi4ReadOnlyDecoder |         96 |         96 |       0 |    0 |    25 |      0 |      0 |            0 |
+|       (axiIn_0_readOnly_decoder)         |          Axi4ReadOnlyDecoder |         75 |         75 |       0 |    0 |    12 |      0 |      0 |            0 |
+|       errorSlave                         |  Axi4ReadOnlyErrorSlave_1_69 |         21 |         21 |       0 |    0 |    13 |      0 |      0 |            0 |
+|     axiIn_0_writeOnly_decoder            |         Axi4WriteOnlyDecoder |         40 |         40 |       0 |    0 |    18 |      0 |      0 |            0 |
+|       (axiIn_0_writeOnly_decoder)        |         Axi4WriteOnlyDecoder |         20 |         20 |       0 |    0 |    16 |      0 |      0 |            0 |
+|       errorSlave                         | Axi4WriteOnlyErrorSlave_1_68 |         21 |         21 |       0 |    0 |     2 |      0 |      0 |            0 |
+|     axiIn_1_readOnly_decoder             |        Axi4ReadOnlyDecoder_1 |         53 |         53 |       0 |    0 |    17 |      0 |      0 |            0 |
+|       (axiIn_1_readOnly_decoder)         |        Axi4ReadOnlyDecoder_1 |         38 |         38 |       0 |    0 |     8 |      0 |      0 |            0 |
+|       errorSlave                         |     Axi4ReadOnlyErrorSlave_1 |         15 |         15 |       0 |    0 |     9 |      0 |      0 |            0 |
+|     axiIn_1_writeOnly_decoder            |       Axi4WriteOnlyDecoder_1 |         32 |         32 |       0 |    0 |    14 |      0 |      0 |            0 |
+|       (axiIn_1_writeOnly_decoder)        |       Axi4WriteOnlyDecoder_1 |         20 |         20 |       0 |    0 |    12 |      0 |      0 |            0 |
+|       errorSlave                         |    Axi4WriteOnlyErrorSlave_1 |         12 |         12 |       0 |    0 |     2 |      0 |      0 |            0 |
+|   u_Axi_CDC                              |                      Axi_CDC |        412 |        284 |     128 |    0 |   317 |      0 |      0 |            0 |
+|     arFifo                               |            StreamFifoCC_3_48 |        185 |        149 |      36 |    0 |    77 |      0 |      0 |            0 |
+|       (arFifo)                           |            StreamFifoCC_3_48 |        180 |        144 |      36 |    0 |    65 |      0 |      0 |            0 |
+|       popToPushGray_buffercc             |                BufferCC_9_63 |          1 |          1 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       pushToPopGray_buffercc             |               BufferCC_11_64 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
+|     awFifo                               |              StreamFifoCC_49 |        102 |         66 |      36 |    0 |    79 |      0 |      0 |            0 |
+|       (awFifo)                           |              StreamFifoCC_49 |         98 |         62 |      36 |    0 |    65 |      0 |      0 |            0 |
+|       bufferCC_12                        |               BufferCC_10_60 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
+|       popToPushGray_buffercc             |                BufferCC_9_61 |          2 |          2 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       pushToPopGray_buffercc             |               BufferCC_11_62 |          1 |          1 |       0 |    0 |     6 |      0 |      0 |            0 |
+|     bFifo                                |            StreamFifoCC_2_50 |         14 |         14 |       0 |    0 |    26 |      0 |      0 |            0 |
+|       (bFifo)                            |            StreamFifoCC_2_50 |          7 |          7 |       0 |    0 |    12 |      0 |      0 |            0 |
+|       bufferCC_12                        |                BufferCC_5_57 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
+|       popToPushGray_buffercc             |                BufferCC_4_58 |          2 |          2 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       pushToPopGray_buffercc             |                BufferCC_6_59 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
+|     rFifo                                |            StreamFifoCC_4_51 |         45 |         17 |      28 |    0 |    66 |      0 |      0 |            0 |
+|       (rFifo)                            |            StreamFifoCC_4_51 |         41 |         13 |      28 |    0 |    50 |      0 |      0 |            0 |
+|       popToPushGray_buffercc             |                  BufferCC_55 |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
+|       pushToPopGray_buffercc             |                BufferCC_1_56 |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
+|     wFifo                                |            StreamFifoCC_1_52 |         66 |         38 |      28 |    0 |    69 |      0 |      0 |            0 |
+|       (wFifo)                            |            StreamFifoCC_1_52 |         62 |         34 |      28 |    0 |    53 |      0 |      0 |            0 |
+|       popToPushGray_buffercc             |                BufferCC_7_53 |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
+|       pushToPopGray_buffercc             |                BufferCC_8_54 |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
+|   u_axi_axil_adapter                     |             axi_axil_adapter |       1072 |       1072 |       0 |    0 |   173 |      0 |      0 |            0 |
+|     axi_axil_adapter_rd_inst             |          axi_axil_adapter_rd |        497 |        497 |       0 |    0 |    85 |      0 |      0 |            0 |
+|     axi_axil_adapter_wr_inst             |          axi_axil_adapter_wr |        575 |        575 |       0 |    0 |    88 |      0 |      0 |            0 |
+|   u_axi_dvi                              |                      axi_dvi |        284 |        284 |       0 |    0 |   211 |      0 |      0 |            0 |
+|   u_axi_ram                              |     axi_wrap_ram_sp_external |        351 |        351 |       0 |    0 |    78 |      0 |      0 |            0 |
+|     u_axi_sram_sp                        |         axi2sram_sp_external |        351 |        351 |       0 |    0 |    78 |      0 |      0 |            0 |
+|   u_axi_uart_controller                  |          axi_uart_controller |        683 |        667 |      16 |    0 |   457 |      0 |      0 |            0 |
+|     AA_axi2apb_bridge_cpu                |               axi2apb_bridge |        251 |        251 |       0 |    0 |   120 |      0 |      0 |            0 |
+|     uart0                                |                     UART_TOP |        432 |        416 |      16 |    0 |   337 |      0 |      0 |            0 |
+|       regs                               |                    uart_regs |        432 |        416 |      16 |    0 |   337 |      0 |      0 |            0 |
+|         (regs)                           |                    uart_regs |        119 |        119 |       0 |    0 |   155 |      0 |      0 |            0 |
+|         i_uart_sync_flops                |              uart_sync_flops |          3 |          3 |       0 |    0 |     2 |      0 |      0 |            0 |
+|         receiver                         |                uart_receiver |        229 |        221 |       8 |    0 |   124 |      0 |      0 |            0 |
+|           (receiver)                     |                uart_receiver |         68 |         68 |       0 |    0 |    54 |      0 |      0 |            0 |
+|           fifo_rx                        |                   uart_rfifo |        161 |        153 |       8 |    0 |    70 |      0 |      0 |            0 |
+|             (fifo_rx)                    |                   uart_rfifo |        143 |        143 |       0 |    0 |    62 |      0 |      0 |            0 |
+|             rfifo                        |                   raminfr_47 |         19 |         11 |       8 |    0 |     8 |      0 |      0 |            0 |
+|         transmitter                      |             uart_transmitter |         83 |         75 |       8 |    0 |    56 |      0 |      0 |            0 |
+|           (transmitter)                  |             uart_transmitter |         41 |         41 |       0 |    0 |    35 |      0 |      0 |            0 |
+|           fifo_tx                        |                   uart_tfifo |         43 |         35 |       8 |    0 |    21 |      0 |      0 |            0 |
+|             (fifo_tx)                    |                   uart_tfifo |         24 |         24 |       0 |    0 |    13 |      0 |      0 |            0 |
+|             tfifo                        |                      raminfr |         19 |         11 |       8 |    0 |     8 |      0 |      0 |            0 |
+|   u_cdma_matmul_bridge                   |           cdma_matmul_bridge |        250 |        250 |       0 |    0 |   578 |      0 |      0 |            0 |
+|   u_confreg                              |                      confreg |        390 |        390 |       0 |    0 |   476 |      0 |      0 |            0 |
+|     (u_confreg)                          |                      confreg |        230 |        230 |       0 |    0 |   399 |      0 |      0 |            0 |
+|     u_digitaltube_controller             |       digitaltube_controller |         16 |         16 |       0 |    0 |    24 |      0 |      0 |            0 |
+|     u_int_ctrl                           |                     int_ctrl |        144 |        144 |       0 |    0 |    53 |      0 |      0 |            0 |
+|   u_cpu                                  |                     core_top |       8556 |       8304 |     252 |    0 |  5591 |      0 |     20 |            0 |
+|     (u_cpu)                              |                     core_top |        519 |        519 |       0 |    0 |     1 |      0 |      0 |            0 |
+|     addr_trans                           |                   addr_trans |       2247 |       2107 |     140 |    0 |  1244 |      0 |      0 |            0 |
+|       (addr_trans)                       |                   addr_trans |          0 |          0 |       0 |    0 |    40 |      0 |      0 |            0 |
+|       tlb_entry                          |                    tlb_entry |       2247 |       2107 |     140 |    0 |  1204 |      0 |      0 |            0 |
+|     axi_bridge                           |                   axi_bridge |         39 |         39 |       0 |    0 |   214 |      0 |      0 |            0 |
+|     btb                                  |                          btb |       1048 |        968 |      80 |    0 |  1611 |      0 |      0 |            0 |
+|       (btb)                              |                          btb |       1045 |        965 |      80 |    0 |  1611 |      0 |      0 |            0 |
+|       dec_btb_add_entry                  |                 decoder_5_32 |          3 |          3 |       0 |    0 |     0 |      0 |      0 |            0 |
+|     dcache                               |                       dcache |        552 |        520 |      32 |    0 |   146 |      0 |     10 |            0 |
+|       (dcache)                           |                       dcache |         87 |         55 |      32 |    0 |   138 |      0 |      0 |            0 |
+|       data_ram_way[0].data_ram_bank[0].u |            data_bank_sram_36 |         49 |         49 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[1].u |            data_bank_sram_37 |         17 |         17 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[2].u |            data_bank_sram_38 |         49 |         49 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[3].u |            data_bank_sram_39 |         51 |         51 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[0].u |            data_bank_sram_40 |         17 |         17 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[1].u |            data_bank_sram_41 |         49 |         49 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[2].u |            data_bank_sram_42 |         81 |         81 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[3].u |            data_bank_sram_43 |         54 |         54 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       lfsr                               |                      lfsr_44 |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
+|       tagv_ram_way[0].u                  |                 tagv_sram_45 |         62 |         62 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       tagv_ram_way[1].u                  |                 tagv_sram_46 |         43 |         43 |       0 |    0 |     0 |      0 |      1 |            0 |
+|     exe_stage                            |                    exe_stage |        665 |        665 |       0 |    0 |   233 |      0 |      0 |            0 |
+|       (exe_stage)                        |                    exe_stage |        634 |        634 |       0 |    0 |   233 |      0 |      0 |            0 |
+|       u_alu                              |                          alu |         33 |         33 |       0 |    0 |     0 |      0 |      0 |            0 |
+|     icache                               |                       icache |        234 |        234 |       0 |    0 |    55 |      0 |     10 |            0 |
+|       (icache)                           |                       icache |         12 |         12 |       0 |    0 |    47 |      0 |      0 |            0 |
+|       data_ram_way[0].data_ram_bank[0].u |               data_bank_sram |          4 |          4 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[1].u |            data_bank_sram_28 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[2].u |            data_bank_sram_29 |         67 |         67 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[0].data_ram_bank[3].u |            data_bank_sram_30 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[0].u |            data_bank_sram_31 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[1].u |            data_bank_sram_32 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[2].u |            data_bank_sram_33 |         35 |         35 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       data_ram_way[1].data_ram_bank[3].u |            data_bank_sram_34 |          4 |          4 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       lfsr                               |                         lfsr |          2 |          2 |       0 |    0 |     8 |      0 |      0 |            0 |
+|       tagv_ram_way[0].u                  |                    tagv_sram |         15 |         15 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       tagv_ram_way[1].u                  |                 tagv_sram_35 |         88 |         88 |       0 |    0 |     0 |      0 |      1 |            0 |
+|     id_stage                             |                     id_stage |       1052 |       1052 |       0 |    0 |   108 |      0 |      0 |            0 |
+|     if_stage                             |                     if_stage |        134 |        134 |       0 |    0 |   173 |      0 |      0 |            0 |
+|     mem_stage                            |                    mem_stage |        115 |        115 |       0 |    0 |   211 |      0 |      0 |            0 |
+|     u_csr                                |                          csr |        200 |        200 |       0 |    0 |   663 |      0 |      0 |            0 |
+|     u_div                                |                          div |        142 |        142 |       0 |    0 |   107 |      0 |      0 |            0 |
+|     u_mul                                |                          mul |        933 |        933 |       0 |    0 |   592 |      0 |      0 |            0 |
+|     wb_stage                             |                     wb_stage |        689 |        689 |       0 |    0 |   233 |      0 |      0 |            0 |
+|   u_fft_mlkem_axi_slave                  |          fft_mlkem_axi_slave |      32945 |      31724 |     112 | 1109 | 26787 |      8 |     10 |           40 |
+|     (u_fft_mlkem_axi_slave)              |          fft_mlkem_axi_slave |          1 |          1 |       0 |    0 |     6 |      0 |      0 |            0 |
+|     u_fft_controller                     |               fft_controller |       2647 |       1607 |       0 | 1040 |  1083 |      6 |      4 |           16 |
+|       (u_fft_controller)                 |               fft_controller |        123 |        123 |       0 |    0 |   100 |      0 |      0 |            0 |
+|       u_FFT                              |                          FFT |       2495 |       1455 |       0 | 1040 |   983 |      6 |      0 |           16 |
+|         SU1                              |                      SdfUnit |       1070 |        302 |       0 |  768 |   197 |      2 |      0 |            4 |
+|           (SU1)                          |                      SdfUnit |        205 |        205 |       0 |    0 |   133 |      0 |      0 |            0 |
+|           BF1                            |                 Butterfly_24 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF2                            | Butterfly__parameterized0_25 |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           DB1                            |                  DelayBuffer |        562 |         50 |       0 |  512 |    32 |      0 |      0 |            0 |
+|           DB2                            |  DelayBuffer__parameterized0 |        256 |          0 |       0 |  256 |    32 |      0 |      0 |            0 |
+|           MU                             |                  Multiply_26 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            4 |
+|           TW                             |                   Twiddle_27 |          1 |          1 |       0 |    0 |     0 |      2 |      0 |            0 |
+|         SU2                              |      SdfUnit__parameterized0 |        492 |        300 |       0 |  192 |   197 |      2 |      0 |            4 |
+|           (SU2)                          |      SdfUnit__parameterized0 |         73 |         73 |       0 |    0 |   133 |      0 |      0 |            0 |
+|           BF1                            |                 Butterfly_20 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF2                            | Butterfly__parameterized0_21 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           DB1                            |  DelayBuffer__parameterized1 |        240 |        112 |       0 |  128 |    32 |      0 |      0 |            0 |
+|           DB2                            |  DelayBuffer__parameterized2 |        128 |         64 |       0 |   64 |    32 |      0 |      0 |            0 |
+|           MU                             |                  Multiply_22 |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            4 |
+|           TW                             |                   Twiddle_23 |          3 |          3 |       0 |    0 |     0 |      2 |      0 |            0 |
+|         SU3                              |      SdfUnit__parameterized1 |        347 |        299 |       0 |   48 |   197 |      0 |      0 |            4 |
+|           (SU3)                          |      SdfUnit__parameterized1 |         75 |         75 |       0 |    0 |   133 |      0 |      0 |            0 |
+|           BF1                            |                 Butterfly_17 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF2                            | Butterfly__parameterized0_18 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           DB1                            |  DelayBuffer__parameterized3 |        144 |        112 |       0 |   32 |    32 |      0 |      0 |            0 |
+|           DB2                            |  DelayBuffer__parameterized4 |         80 |         64 |       0 |   16 |    32 |      0 |      0 |            0 |
+|           MU                             |                  Multiply_19 |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            4 |
+|         SU4                              |      SdfUnit__parameterized2 |        327 |        295 |       0 |   32 |   197 |      2 |      0 |            4 |
+|           (SU4)                          |      SdfUnit__parameterized2 |         69 |         69 |       0 |    0 |   133 |      0 |      0 |            0 |
+|           BF1                            |                 Butterfly_15 |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF2                            | Butterfly__parameterized0_16 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           DB1                            |  DelayBuffer__parameterized5 |        128 |        112 |       0 |   16 |    32 |      0 |      0 |            0 |
+|           DB2                            |  DelayBuffer__parameterized6 |         80 |         64 |       0 |   16 |    32 |      0 |      0 |            0 |
+|           MU                             |                     Multiply |         32 |         32 |       0 |    0 |     0 |      0 |      0 |            4 |
+|           TW                             |                      Twiddle |          2 |          2 |       0 |    0 |     0 |      2 |      0 |            0 |
+|         SU5                              |      SdfUnit__parameterized3 |        260 |        260 |       0 |    0 |   195 |      0 |      0 |            0 |
+|           (SU5)                          |      SdfUnit__parameterized3 |         68 |         68 |       0 |    0 |    99 |      0 |      0 |            0 |
+|           BF1                            |                    Butterfly |         16 |         16 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           BF2                            |    Butterfly__parameterized0 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
+|           DB1                            |  DelayBuffer__parameterized7 |        112 |        112 |       0 |    0 |    64 |      0 |      0 |            0 |
+|           DB2                            |  DelayBuffer__parameterized8 |         64 |         64 |       0 |    0 |    32 |      0 |      0 |            0 |
+|       u_in0                              |                     my_bram0 |          3 |          3 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       u_in1                              |                  my_bram0_12 |          2 |          2 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       u_out0                             |                  my_bram0_13 |          0 |          0 |       0 |    0 |     0 |      0 |      1 |            0 |
+|       u_out1                             |                  my_bram0_14 |         25 |         25 |       0 |    0 |     0 |      0 |      1 |            0 |
+|     u_mlkem_axi_cdc                      |                    Axi_CDC_5 |        256 |        144 |     112 |    0 |   272 |      0 |      0 |            0 |
+|       arFifo                             |               StreamFifoCC_3 |         51 |         23 |      28 |    0 |    55 |      0 |      0 |            0 |
+|         (arFifo)                         |               StreamFifoCC_3 |         42 |         14 |      28 |    0 |    43 |      0 |      0 |            0 |
+|         popToPushGray_buffercc           |                BufferCC_9_10 |          5 |          5 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         pushToPopGray_buffercc           |               BufferCC_11_11 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       awFifo                             |                 StreamFifoCC |         40 |         16 |      24 |    0 |    49 |      0 |      0 |            0 |
+|         (awFifo)                         |                 StreamFifoCC |         31 |          7 |      24 |    0 |    35 |      0 |      0 |            0 |
+|         bufferCC_12                      |                  BufferCC_10 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
+|         popToPushGray_buffercc           |                   BufferCC_9 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         pushToPopGray_buffercc           |                  BufferCC_11 |          4 |          4 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       bFifo                              |               StreamFifoCC_2 |         18 |         14 |       4 |    0 |    27 |      0 |      0 |            0 |
+|         (bFifo)                          |               StreamFifoCC_2 |         11 |          7 |       4 |    0 |    13 |      0 |      0 |            0 |
+|         bufferCC_12                      |                   BufferCC_5 |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
+|         popToPushGray_buffercc           |                   BufferCC_4 |          1 |          1 |       0 |    0 |     6 |      0 |      0 |            0 |
+|         pushToPopGray_buffercc           |                   BufferCC_6 |          5 |          5 |       0 |    0 |     6 |      0 |      0 |            0 |
+|       rFifo                              |               StreamFifoCC_4 |         56 |         28 |      28 |    0 |    72 |      0 |      0 |            0 |
+|         (rFifo)                          |               StreamFifoCC_4 |         49 |         21 |      28 |    0 |    56 |      0 |      0 |            0 |
+|         popToPushGray_buffercc           |                     BufferCC |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
+|         pushToPopGray_buffercc           |                   BufferCC_1 |          5 |          5 |       0 |    0 |     8 |      0 |      0 |            0 |
+|       wFifo                              |               StreamFifoCC_1 |         91 |         63 |      28 |    0 |    69 |      0 |      0 |            0 |
+|         (wFifo)                          |               StreamFifoCC_1 |         86 |         58 |      28 |    0 |    53 |      0 |      0 |            0 |
+|         popToPushGray_buffercc           |                   BufferCC_7 |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
+|         pushToPopGray_buffercc           |                   BufferCC_8 |          3 |          3 |       0 |    0 |     8 |      0 |      0 |            0 |
+|     u_mlkem_axi_slave                    |              mlkem_axi_slave |      30043 |      29974 |       0 |   69 | 25426 |      2 |      6 |           24 |
+|       (u_mlkem_axi_slave)                |              mlkem_axi_slave |       1278 |       1278 |       0 |    0 |  1064 |      0 |      0 |            0 |
+|       u_mlkem                            |                    mlkem_top |      28768 |      28699 |       0 |   69 | 24362 |      2 |      6 |           24 |
+|         (u_mlkem)                        |                    mlkem_top |       2326 |       2326 |       0 |    0 |  4911 |      0 |      0 |            0 |
+|         u_bank_a                         |      sd_bram__parameterized0 |         49 |         49 |       0 |    0 |     0 |      1 |      1 |            0 |
+|         u_bank_se                        |      sd_bram__parameterized1 |         61 |         61 |       0 |    0 |     0 |      1 |      0 |            0 |
+|         u_bank_t                         |      sd_bram__parameterized2 |        488 |        488 |       0 |    0 |     0 |      0 |      1 |            0 |
+|         u_c_in_bram                      |                      sd_bram |       1291 |       1291 |       0 |    0 |     0 |      0 |      1 |            0 |
+|         u_cbd                            |       sample_cbd_sync_shared |       2512 |       2512 |       0 |    0 |  3199 |      0 |      0 |            0 |
+|         u_comp                           |             comp_decomp_sync |        322 |        321 |       0 |    1 |   269 |      0 |      0 |            3 |
+|         u_ct_bram                        |                    sd_bram_6 |         15 |         15 |       0 |    0 |     0 |      0 |      1 |            0 |
+|         u_dkp_bram                       |                    sd_bram_7 |         73 |         73 |       0 |    0 |     0 |      0 |      1 |            0 |
+|         u_ek_bram                        |                    sd_bram_8 |        388 |        388 |       0 |    0 |     0 |      0 |      1 |            0 |
+|         u_keccak                         |                  keccak_core |       5622 |       5622 |       0 |    0 |  1606 |      0 |      0 |            0 |
+|         u_ntt                            |                     ntt_core |       8192 |       8149 |       0 |   43 |  3743 |      0 |      0 |            6 |
+|           (u_ntt)                        |                     ntt_core |       6140 |       6124 |       0 |   16 |  3364 |      0 |      0 |            0 |
+|           u_bf                           |          butterfly_unit_pipe |       1922 |       1896 |       0 |   26 |   224 |      0 |      0 |            3 |
+|             (u_bf)                       |          butterfly_unit_pipe |         69 |         44 |       0 |   25 |    75 |      0 |      0 |            0 |
+|             u_barrett                    |           barrett_mul_pipe_9 |       1854 |       1853 |       0 |    1 |   149 |      0 |      0 |            3 |
+|           u_scl                          |             barrett_mul_pipe |        131 |        130 |       0 |    1 |   155 |      0 |      0 |            3 |
+|         u_pmul                           |                poly_mul_sync |       2830 |       2805 |       0 |   25 |  6577 |      0 |      0 |           15 |
+|           (u_pmul)                       |                poly_mul_sync |       2474 |       2474 |       0 |    0 |  6299 |      0 |      0 |            0 |
+|           u_bc                           |            basecase_mul_pipe |        421 |        396 |       0 |   25 |   278 |      0 |      0 |           15 |
+|         u_sha3                           |              sha3_top_shared |       3175 |       3175 |       0 |    0 |  2388 |      0 |      0 |            0 |
+|         u_snt                            |       sample_ntt_sync_shared |       1439 |       1439 |       0 |    0 |  1669 |      0 |      0 |            0 |
+|   u_matmul_axi_slave                     |             matmul_axi_slave |       6600 |       6418 |     176 |    6 |  2831 |      0 |      0 |           16 |
+|     (u_matmul_axi_slave)                 |             matmul_axi_slave |       5796 |       5614 |     176 |    6 |  2303 |      0 |      0 |            0 |
+|     mult_inst[0].u_mult                  |         pipelined_mult_32x32 |        203 |        203 |       0 |    0 |   132 |      0 |      0 |            4 |
+|     mult_inst[1].u_mult                  |       pipelined_mult_32x32_2 |        202 |        202 |       0 |    0 |   132 |      0 |      0 |            4 |
+|     mult_inst[2].u_mult                  |       pipelined_mult_32x32_3 |        202 |        202 |       0 |    0 |   132 |      0 |      0 |            4 |
+|     mult_inst[3].u_mult                  |       pipelined_mult_32x32_4 |        200 |        200 |       0 |    0 |   132 |      0 |      0 |            4 |
+|   u_snix_axil_cdma_mux_8ch               |           snix_axil_cdma_mux |       1673 |       1673 |       0 |    0 |  1476 |      0 |      1 |            0 |
+|     (u_snix_axil_cdma_mux_8ch)           |           snix_axil_cdma_mux |        687 |        687 |       0 |    0 |  1180 |      0 |      0 |            0 |
+|     u_core_engine                        |               snix_axi_mm2mm |        988 |        988 |       0 |    0 |   296 |      0 |      1 |            0 |
+|       (u_core_engine)                    |               snix_axi_mm2mm |        763 |        763 |       0 |    0 |   243 |      0 |      0 |            0 |
+|       axis_fifo_u0                       |               snix_axis_fifo |        225 |        225 |       0 |    0 |    53 |      0 |      1 |            0 |
+|         u_fifo                           |               snix_sync_fifo |        225 |        225 |       0 |    0 |    53 |      0 |      1 |            0 |
++------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
+* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining
+
+

rtl/ip/APB_UART/URT/uart_defines.h

@@ -113,7 +113,7 @@ THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // FIFO parameter defines
 
 `define UART_FIFO_WIDTH	     8
-`define UART_FIFO_DEPTH	     32
-`define UART_FIFO_POINTER_W	 5
-`define UART_FIFO_COUNTER_W	 6
+`define UART_FIFO_DEPTH	     16
+`define UART_FIFO_POINTER_W	 4
+`define UART_FIFO_COUNTER_W	 5
 `define UART_FIFO_REC_WIDTH  11

rtl/ip/Bus_interconnects/axi2sram_sp_external.v

@@ -65,7 +65,6 @@ module axi2sram_sp_external #(
     output  reg                       req_o,
     output  reg                       we_o,
     output  reg [AXI_ADDR_WIDTH-1:0]   addr_o,
-    output  reg                       bank_o,
     output  reg [AXI_DATA_WIDTH/8-1:0] be_o,
     output  reg [AXI_DATA_WIDTH-1:0]   data_o,
     input   [AXI_DATA_WIDTH-1:0]   data_i
@@ -102,34 +101,40 @@ module axi2sram_sp_external #(
     localparam              FIXED       = 2'b00;
     localparam              INCR        = 2'b01;
     localparam              WRAP        = 2'b10;
-    localparam [AXI_ADDR_WIDTH-1:0] ADDR_INCR =
-        {{(AXI_ADDR_WIDTH-1){1'b0}}, 1'b1} << LOG_NR_BYTES;
     
     reg [AXI_ADDR_WIDTH-1:0] req_addr_d, req_addr_q;
-    reg [8:0]                cnt_d, cnt_q;
-    reg [AXI_ADDR_WIDTH-1:0] wrap_mask_d, wrap_mask_q;
-    reg                      req_bank_d, req_bank_q;
-    reg [AXI_DATA_WIDTH-1:0] read_data_q;
-    reg                      read_capture;
+    reg [7:0]                cnt_d, cnt_q;
 
-    wire [AXI_ADDR_WIDTH-1:0] ar_burst_bytes =
-        ({{(AXI_ADDR_WIDTH-8){1'b0}}, s_arlen} + {{(AXI_ADDR_WIDTH-1){1'b0}}, 1'b1}) << LOG_NR_BYTES;
-    wire [AXI_ADDR_WIDTH-1:0] aw_burst_bytes =
-        ({{(AXI_ADDR_WIDTH-8){1'b0}}, s_awlen} + {{(AXI_ADDR_WIDTH-1){1'b0}}, 1'b1}) << LOG_NR_BYTES;
-    wire [AXI_ADDR_WIDTH-1:0] ar_wrap_mask = ar_burst_bytes - {{(AXI_ADDR_WIDTH-1){1'b0}}, 1'b1};
-    wire [AXI_ADDR_WIDTH-1:0] aw_wrap_mask = aw_burst_bytes - {{(AXI_ADDR_WIDTH-1){1'b0}}, 1'b1};
+    function automatic [AXI_ADDR_WIDTH-1:0] get_wrap_boundary;
+        input [AXI_ADDR_WIDTH-1:0] unaligned_address;
+        input [7:0] len;
+    begin
+        get_wrap_boundary = 'h0;
+        //  for wrapping transfers ax_len can only be of size 1, 3, 7 or 15
+        if (len == 4'b1)
+            get_wrap_boundary[AXI_ADDR_WIDTH-1:1+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:1+LOG_NR_BYTES];
+        else if (len == 4'b11)
+            get_wrap_boundary[AXI_ADDR_WIDTH-1:2+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:2+LOG_NR_BYTES];
+        else if (len == 4'b111)
+            get_wrap_boundary[AXI_ADDR_WIDTH-1:3+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:2+LOG_NR_BYTES];
+        else if (len == 4'b1111)
+            get_wrap_boundary[AXI_ADDR_WIDTH-1:4+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:4+LOG_NR_BYTES];
+    end
+    endfunction
 
-    reg [AXI_ADDR_WIDTH-1:0] next_addr;
-    reg [AXI_ADDR_WIDTH-1:0] seq_addr;
+    reg [AXI_ADDR_WIDTH-1:0] aligned_address;
+    reg [AXI_ADDR_WIDTH-1:0] wrap_boundary;
+    reg [AXI_ADDR_WIDTH-1:0] upper_wrap_boundary;
+    reg [AXI_ADDR_WIDTH-1:0] cons_addr;
 
     always @ (*) begin
-        seq_addr = req_addr_q + ADDR_INCR;
-        case (ax_req_q_burst)
-            FIXED: next_addr = req_addr_q;
-            INCR:  next_addr = seq_addr;
-            WRAP:  next_addr = (req_addr_q & ~wrap_mask_q) | (seq_addr & wrap_mask_q);
-            default: next_addr = seq_addr;
-        endcase
+        // address generation
+        aligned_address = {ax_req_q_addr[AXI_ADDR_WIDTH-1:LOG_NR_BYTES], {{LOG_NR_BYTES}{1'b0}}};
+        wrap_boundary = get_wrap_boundary(ax_req_q_addr, ax_req_q_len);
+        // this will overflow
+        upper_wrap_boundary = wrap_boundary + ((ax_req_q_len + 1) << LOG_NR_BYTES);
+        // calculate consecutive address
+        cons_addr = aligned_address + (cnt_q << LOG_NR_BYTES);
 
         // Transaction attributes
         // default assignments
@@ -141,16 +146,12 @@ module axi2sram_sp_external #(
         ax_req_d_burst  = ax_req_q_burst;
         req_addr_d      = req_addr_q;
         cnt_d           = cnt_q;
-        wrap_mask_d     = wrap_mask_q;
-        req_bank_d      = req_bank_q;
-        read_capture    = 1'b0;
         // Memory default assignments
         data_o = s_wdata;
         be_o   = s_wstrb;
         we_o   = 1'b0;
         req_o  = 1'b0;
         addr_o = 'h0;
-        bank_o = req_bank_q;
         // AXI assignments
         // request
         s_awready = 1'b0;
@@ -183,17 +184,14 @@ module axi2sram_sp_external #(
                     ax_req_d_len    = s_arlen;
                     ax_req_d_size   = s_arsize;
                     ax_req_d_burst  = s_arburst;
-                    wrap_mask_d     = ar_wrap_mask;
-                    req_bank_d      = s_araddr[22];
-                    state_d        = READ_ADDR;
+                    state_d        = READ;
                     //  we can request the first address, this saves us time
                     req_o          = 1'b1;
                     addr_o         = s_araddr;
-                    bank_o         = s_araddr[22];
                     // save the address
                     req_addr_d     = s_araddr;
                     // save the ar_len
-                    cnt_d          = 0;
+                    cnt_d          = 1;
                 // ------------
                 // Write
                 // ------------
@@ -207,9 +205,6 @@ module axi2sram_sp_external #(
                     ax_req_d_len    = s_awlen;
                     ax_req_d_size   = s_awsize;
                     ax_req_d_burst  = s_awburst;
-                    wrap_mask_d     = aw_wrap_mask;
-                    req_bank_d      = s_awaddr[22];
-                    bank_o          = s_awaddr[22];
                     // we've got our first w_valid so start the write process
                     if (s_wvalid) begin
                         req_o          = 1'b1;
@@ -236,52 +231,40 @@ module axi2sram_sp_external #(
             end
 
             READ: begin
+                // keep request to memory high
+                req_o  = 1'b1;
+                addr_o = req_addr_q;
                 // send the response
                 s_rvalid = 1'b1;
-                s_rdata  = read_data_q;
+                s_rdata  = data_i;
                 s_rid    = ax_req_q_id;
-                s_rlast  = (cnt_q == ({1'b0, ax_req_q_len} + 9'd1));
-                if (FAST_READ_BURST && !s_rlast) begin
-                    req_o  = 1'b1;
-                    addr_o = next_addr;
-                end
+                s_rlast  = (cnt_q == ax_req_q_len + 1);
                 // check that the master is ready, the slave must not wait on this
                 if (s_rready) begin
                     // we sent the last byte -> go back to idle
                     if (s_rlast) begin
-                        if (s_arvalid) begin
-                            // Accept the next burst without an intervening
-                            // IDLE cycle and start its SRAM address phase.
-                            s_arready       = 1'b1;
-                            ax_req_d_id     = s_arid;
-                            ax_req_d_addr   = s_araddr;
-                            ax_req_d_len    = s_arlen;
-                            ax_req_d_size   = s_arsize;
-                            ax_req_d_burst  = s_arburst;
-                            wrap_mask_d     = ar_wrap_mask;
-                            req_bank_d      = s_araddr[22];
-                            req_o           = 1'b1;
-                            addr_o          = s_araddr;
-                            bank_o          = s_araddr[22];
-                            req_addr_d      = s_araddr;
-                            // ARVALID was presented during the preceding
-                            // beat, so the async-SRAM address has a full
-                            // cycle to settle before this capture edge.
-                            read_capture    = 1'b1;
-                            cnt_d           = 1;
-                            state_d         = READ;
-                        end else begin
-                            state_d = IDLE;
-                        end
+                        state_d = IDLE;
+                        // we already got everything
                     end
                     else begin
                         if (FAST_READ_BURST) begin
-                            read_capture = 1'b1;
-                            req_addr_d = next_addr;
+                            // Queue the next async-SRAM address for the clock
+                            // edge after the current read data is sampled.
+                            case (ax_req_q_burst)
+                                FIXED, INCR: req_addr_d = cons_addr;
+                                WRAP: begin
+                                    if (cons_addr == upper_wrap_boundary) begin
+                                        req_addr_d = wrap_boundary;
+                                    end else if (cons_addr > upper_wrap_boundary) begin
+                                        req_addr_d = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES);
+                                    end else begin
+                                        req_addr_d = cons_addr;
+                                    end
+                                end
+                            endcase
                             cnt_d   = cnt_q + 1;
                             state_d = READ;
                         end else begin
-                            req_addr_d = next_addr;
                             state_d = READ_ADDR;
                         end
                     end
@@ -289,12 +272,34 @@ module axi2sram_sp_external #(
             end
 
             READ_ADDR: begin
-                // Fill the read data register after the async-SRAM address has
-                // been stable for one full sys_clk cycle.
+                // keep request to memory high
                 req_o  = 1'b1;
-                addr_o = req_addr_q;
-                read_capture = 1'b1;
+                // send the response
+                s_rvalid = 1'b0;
+                // ----------------------------
+                // Next address generation
+                // ----------------------------
+                // handle the correct burst type
+                case (ax_req_q_burst)
+                    FIXED, INCR: addr_o = cons_addr;
+                    WRAP:  begin
+                        // check if the address reached warp boundary
+                        if (cons_addr == upper_wrap_boundary) begin
+                            addr_o = wrap_boundary;
+                        // address warped beyond boundary
+                        end else if (cons_addr > upper_wrap_boundary) begin
+                            addr_o = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES);
+                        // we are still in the incremental regime
+                        end else begin
+                            addr_o = cons_addr;
+                        end
+                    end
+                endcase
+                // we need to change the address here for the upcoming request
+                // we can decrease the counter as the master has consumed the read data
                 cnt_d = cnt_q + 1;
+                // save the request address for the next cycle
+                req_addr_d = addr_o;
                 state_d = READ;
             end
 
@@ -312,9 +317,24 @@ module axi2sram_sp_external #(
                     // Next address generation
                     // ----------------------------
                     // handle the correct burst type
-                    addr_o = next_addr;
+                    case (ax_req_q_burst)
+
+                        FIXED, INCR: addr_o = cons_addr;
+                        WRAP:  begin
+                            // check if the address reached warp boundary
+                            if (cons_addr == upper_wrap_boundary) begin
+                                addr_o = wrap_boundary;
+                            // address warped beyond boundary
+                            end else if (cons_addr > upper_wrap_boundary) begin
+                                addr_o = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES);
+                            // we are still in the incremental regime
+                            end else begin
+                                addr_o = cons_addr;
+                            end
+                        end
+                    endcase
                     // save the request address for the next cycle
-                    req_addr_d = next_addr;
+                    req_addr_d = addr_o;
                     // we can decrease the counter as the master has consumed the read data
                     cnt_d = cnt_q + 1;
 
@@ -345,10 +365,7 @@ module axi2sram_sp_external #(
             ax_req_q_len    <= 8'h0;
             ax_req_q_size   <= 3'h0;
             req_addr_q      <= 'h0;
-            cnt_q           <= 9'h0;
-            wrap_mask_q     <= 'h0;
-            req_bank_q      <= 1'b0;
-            read_data_q     <= 'h0;
+            cnt_q           <= 8'h0;
         end else begin
             state_q         <= state_d;
             ax_req_q_addr   <= ax_req_d_addr;
@@ -358,10 +375,6 @@ module axi2sram_sp_external #(
             ax_req_q_size   <= ax_req_d_size;
             req_addr_q      <= req_addr_d;
             cnt_q           <= cnt_d;
-            wrap_mask_q     <= wrap_mask_d;
-            req_bank_q      <= req_bank_d;
-            if (read_capture)
-                read_data_q <= data_i;
         end
     end
 

rtl/ip/PLL_2019_2/.gitignore

@@ -1 +0,0 @@
-PLL_*

rtl/ip/PLL_2019_2/clk_pll.xci

@@ -98,14 +98,14 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_1">0000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_2">0000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ">32.97872</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ">33.33333</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_1">0000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_2">0000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ">59.61538</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ">50.00000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">32.97872</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">33.33333</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">33.000</spirit:configurableElementValue>
@@ -113,14 +113,14 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_1">0000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_2">0000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_ACTUAL_FREQ">76.92308</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">59.61538</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">50.00000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">50.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">1</spirit:configurableElementValue>
@@ -128,9 +128,9 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_2">0000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">76.92308</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
@@ -190,7 +190,7 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">cpu_clk</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">sys_clk</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">mlkem_clk</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
@@ -203,7 +203,7 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVCLK">0000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE1_AUTO">1</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">0.55</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">0.66</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">0.33</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">0.33</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">0.33</spirit:configurableElementValue>
@@ -246,20 +246,24 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">31.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">20.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">20.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">47.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">30.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">26</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">20</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+<<<<<<< Updated upstream
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+=======
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">13</spirit:configurableElementValue>
+>>>>>>> Stashed changes
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
@@ -292,14 +296,20 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">2</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B">  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)</spirit:configurableElementValue>
+<<<<<<< Updated upstream
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">_cpu_clk__32.97872______0.000______50.0______130.093____123.600</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">_sys_clk__59.61538______0.000______50.0______118.808____123.600</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">_sys_clk__50.00000______0.000______50.0______122.035____123.600</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
+=======
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">_cpu_clk__33.33333______0.000______50.0______215.691____164.985</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">_sys_clk__50.00000______0.000______50.0______192.113____164.985</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">mlkem_clk__76.92308______0.000______50.0______172.249____164.985</spirit:configurableElementValue>
+>>>>>>> Stashed changes
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MAX">128.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MIN">1.000</spirit:configurableElementValue>
@@ -423,18 +433,18 @@
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">118.808</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">122.035</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">123.600</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">50.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">110.420</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">123.600</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
@@ -484,7 +494,7 @@
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">sys_clk</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">mlkem_clk</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
@@ -525,20 +535,24 @@
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">31</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">20</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">20.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">47</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">30</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">26</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">20</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+<<<<<<< Updated upstream
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+=======
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">13</spirit:configurableElementValue>
+>>>>>>> Stashed changes
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
@@ -566,8 +580,13 @@
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+<<<<<<< Updated upstream
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">2</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+=======
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">true</spirit:configurableElementValue>
+>>>>>>> Stashed changes
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
@@ -705,20 +724,30 @@
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_DRIVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_USED" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_DRIVES" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT5_DRIVES" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT6_DRIVES" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT7_DRIVES" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT1_PORT" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT2_PORT" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT3_PORT" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FEEDBACK_SOURCE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_BANDWIDTH" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_COMPENSATION" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OVERRIDE_MMCM" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIMITIVE" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_IN_FREQ" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RESET_PORT" xilinx:valueSource="user"/>

rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v

@@ -0,0 +1,235 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+// Date        : Tue Jul  7 23:25:51 2026
+// Host        : fedora running 64-bit unknown
+// Command     : write_verilog -force -mode funcsim
+//               /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v
+// Design      : clk_pll
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7a200tfbg676-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* NotValidForBitStream *)
+module clk_pll
+   (cpu_clk,
+    sys_clk,
+    mlkem_clk,
+    resetn,
+    locked,
+    clk_in1);
+  output cpu_clk;
+  output sys_clk;
+  output mlkem_clk;
+  input resetn;
+  output locked;
+  input clk_in1;
+
+  (* IBUF_LOW_PWR *) wire clk_in1;
+  wire cpu_clk;
+  wire locked;
+  wire mlkem_clk;
+  wire resetn;
+  wire sys_clk;
+
+  clk_pll_clk_pll_clk_wiz inst
+       (.clk_in1(clk_in1),
+        .cpu_clk(cpu_clk),
+        .locked(locked),
+        .mlkem_clk(mlkem_clk),
+        .resetn(resetn),
+        .sys_clk(sys_clk));
+endmodule
+
+(* ORIG_REF_NAME = "clk_pll_clk_wiz" *) 
+module clk_pll_clk_pll_clk_wiz
+   (cpu_clk,
+    sys_clk,
+    mlkem_clk,
+    resetn,
+    locked,
+    clk_in1);
+  output cpu_clk;
+  output sys_clk;
+  output mlkem_clk;
+  input resetn;
+  output locked;
+  input clk_in1;
+
+  wire clk_in1;
+  wire clk_in1_clk_pll;
+  wire clkfbout_buf_clk_pll;
+  wire clkfbout_clk_pll;
+  wire cpu_clk;
+  wire cpu_clk_clk_pll;
+  wire locked;
+  wire mlkem_clk;
+  wire mlkem_clk_clk_pll;
+  wire reset_high;
+  wire resetn;
+  wire sys_clk;
+  wire sys_clk_clk_pll;
+  wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
+  wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
+  wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
+
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkf_buf
+       (.I(clkfbout_clk_pll),
+        .O(clkfbout_buf_clk_pll));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  (* CAPACITANCE = "DONT_CARE" *) 
+  (* IBUF_DELAY_VALUE = "0" *) 
+  (* IFD_DELAY_VALUE = "AUTO" *) 
+  IBUF #(
+    .IOSTANDARD("DEFAULT")) 
+    clkin1_ibufg
+       (.I(clk_in1),
+        .O(clk_in1_clk_pll));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkout1_buf
+       (.I(cpu_clk_clk_pll),
+        .O(cpu_clk));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkout2_buf
+       (.I(sys_clk_clk_pll),
+        .O(sys_clk));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkout3_buf
+       (.I(mlkem_clk_clk_pll),
+        .O(mlkem_clk));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  PLLE2_ADV #(
+    .BANDWIDTH("OPTIMIZED"),
+    .CLKFBOUT_MULT(31),
+    .CLKFBOUT_PHASE(0.000000),
+    .CLKIN1_PERIOD(20.000000),
+    .CLKIN2_PERIOD(0.000000),
+    .CLKOUT0_DIVIDE(47),
+    .CLKOUT0_DUTY_CYCLE(0.500000),
+    .CLKOUT0_PHASE(0.000000),
+    .CLKOUT1_DIVIDE(31),
+    .CLKOUT1_DUTY_CYCLE(0.500000),
+    .CLKOUT1_PHASE(0.000000),
+    .CLKOUT2_DIVIDE(78),
+    .CLKOUT2_DUTY_CYCLE(0.500000),
+    .CLKOUT2_PHASE(0.000000),
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT3_DUTY_CYCLE(0.500000),
+    .CLKOUT3_PHASE(0.000000),
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.500000),
+    .CLKOUT4_PHASE(0.000000),
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.500000),
+    .CLKOUT5_PHASE(0.000000),
+    .COMPENSATION("ZHOLD"),
+    .DIVCLK_DIVIDE(1),
+    .IS_CLKINSEL_INVERTED(1'b0),
+    .IS_PWRDWN_INVERTED(1'b0),
+    .IS_RST_INVERTED(1'b0),
+    .REF_JITTER1(0.010000),
+    .REF_JITTER2(0.010000),
+    .STARTUP_WAIT("FALSE")) 
+    plle2_adv_inst
+       (.CLKFBIN(clkfbout_buf_clk_pll),
+        .CLKFBOUT(clkfbout_clk_pll),
+        .CLKIN1(clk_in1_clk_pll),
+        .CLKIN2(1'b0),
+        .CLKINSEL(1'b1),
+        .CLKOUT0(cpu_clk_clk_pll),
+        .CLKOUT1(sys_clk_clk_pll),
+        .CLKOUT2(mlkem_clk_clk_pll),
+        .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
+        .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
+        .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
+        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .DCLK(1'b0),
+        .DEN(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
+        .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
+        .DWE(1'b0),
+        .LOCKED(locked),
+        .PWRDWN(1'b0),
+        .RST(reset_high));
+  LUT1 #(
+    .INIT(2'h1)) 
+    plle2_adv_inst_i_1
+       (.I0(resetn),
+        .O(reset_high));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl

@@ -0,0 +1,179 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+-- Date        : Tue Jul  7 23:25:51 2026
+-- Host        : fedora running 64-bit unknown
+-- Command     : write_vhdl -force -mode funcsim
+--               /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl
+-- Design      : clk_pll
+-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+--               synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device      : xc7a200tfbg676-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity clk_pll_clk_pll_clk_wiz is
+  port (
+    cpu_clk : out STD_LOGIC;
+    sys_clk : out STD_LOGIC;
+    mlkem_clk : out STD_LOGIC;
+    resetn : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of clk_pll_clk_pll_clk_wiz : entity is "clk_pll_clk_wiz";
+end clk_pll_clk_pll_clk_wiz;
+
+architecture STRUCTURE of clk_pll_clk_pll_clk_wiz is
+  signal clk_in1_clk_pll : STD_LOGIC;
+  signal clkfbout_buf_clk_pll : STD_LOGIC;
+  signal clkfbout_clk_pll : STD_LOGIC;
+  signal cpu_clk_clk_pll : STD_LOGIC;
+  signal mlkem_clk_clk_pll : STD_LOGIC;
+  signal reset_high : STD_LOGIC;
+  signal sys_clk_clk_pll : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+  attribute BOX_TYPE : string;
+  attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
+  attribute CAPACITANCE : string;
+  attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
+  attribute IBUF_DELAY_VALUE : string;
+  attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
+  attribute IFD_DELAY_VALUE : string;
+  attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
+  attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of clkout3_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE";
+begin
+clkf_buf: unisim.vcomponents.BUFG
+     port map (
+      I => clkfbout_clk_pll,
+      O => clkfbout_buf_clk_pll
+    );
+clkin1_ibufg: unisim.vcomponents.IBUF
+    generic map(
+      IOSTANDARD => "DEFAULT"
+    )
+        port map (
+      I => clk_in1,
+      O => clk_in1_clk_pll
+    );
+clkout1_buf: unisim.vcomponents.BUFG
+     port map (
+      I => cpu_clk_clk_pll,
+      O => cpu_clk
+    );
+clkout2_buf: unisim.vcomponents.BUFG
+     port map (
+      I => sys_clk_clk_pll,
+      O => sys_clk
+    );
+clkout3_buf: unisim.vcomponents.BUFG
+     port map (
+      I => mlkem_clk_clk_pll,
+      O => mlkem_clk
+    );
+plle2_adv_inst: unisim.vcomponents.PLLE2_ADV
+    generic map(
+      BANDWIDTH => "OPTIMIZED",
+      CLKFBOUT_MULT => 31,
+      CLKFBOUT_PHASE => 0.000000,
+      CLKIN1_PERIOD => 20.000000,
+      CLKIN2_PERIOD => 0.000000,
+      CLKOUT0_DIVIDE => 47,
+      CLKOUT0_DUTY_CYCLE => 0.500000,
+      CLKOUT0_PHASE => 0.000000,
+      CLKOUT1_DIVIDE => 31,
+      CLKOUT1_DUTY_CYCLE => 0.500000,
+      CLKOUT1_PHASE => 0.000000,
+      CLKOUT2_DIVIDE => 78,
+      CLKOUT2_DUTY_CYCLE => 0.500000,
+      CLKOUT2_PHASE => 0.000000,
+      CLKOUT3_DIVIDE => 1,
+      CLKOUT3_DUTY_CYCLE => 0.500000,
+      CLKOUT3_PHASE => 0.000000,
+      CLKOUT4_DIVIDE => 1,
+      CLKOUT4_DUTY_CYCLE => 0.500000,
+      CLKOUT4_PHASE => 0.000000,
+      CLKOUT5_DIVIDE => 1,
+      CLKOUT5_DUTY_CYCLE => 0.500000,
+      CLKOUT5_PHASE => 0.000000,
+      COMPENSATION => "ZHOLD",
+      DIVCLK_DIVIDE => 1,
+      IS_CLKINSEL_INVERTED => '0',
+      IS_PWRDWN_INVERTED => '0',
+      IS_RST_INVERTED => '0',
+      REF_JITTER1 => 0.010000,
+      REF_JITTER2 => 0.010000,
+      STARTUP_WAIT => "FALSE"
+    )
+        port map (
+      CLKFBIN => clkfbout_buf_clk_pll,
+      CLKFBOUT => clkfbout_clk_pll,
+      CLKIN1 => clk_in1_clk_pll,
+      CLKIN2 => '0',
+      CLKINSEL => '1',
+      CLKOUT0 => cpu_clk_clk_pll,
+      CLKOUT1 => sys_clk_clk_pll,
+      CLKOUT2 => mlkem_clk_clk_pll,
+      CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED,
+      CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED,
+      CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED,
+      DADDR(6 downto 0) => B"0000000",
+      DCLK => '0',
+      DEN => '0',
+      DI(15 downto 0) => B"0000000000000000",
+      DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0),
+      DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED,
+      DWE => '0',
+      LOCKED => locked,
+      PWRDWN => '0',
+      RST => reset_high
+    );
+plle2_adv_inst_i_1: unisim.vcomponents.LUT1
+    generic map(
+      INIT => X"1"
+    )
+        port map (
+      I0 => resetn,
+      O => reset_high
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity clk_pll is
+  port (
+    cpu_clk : out STD_LOGIC;
+    sys_clk : out STD_LOGIC;
+    mlkem_clk : out STD_LOGIC;
+    resetn : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+  attribute NotValidForBitStream : boolean;
+  attribute NotValidForBitStream of clk_pll : entity is true;
+end clk_pll;
+
+architecture STRUCTURE of clk_pll is
+begin
+inst: entity work.clk_pll_clk_pll_clk_wiz
+     port map (
+      clk_in1 => clk_in1,
+      cpu_clk => cpu_clk,
+      locked => locked,
+      mlkem_clk => mlkem_clk,
+      resetn => resetn,
+      sys_clk => sys_clk
+    );
+end STRUCTURE;

rtl/ip/PLL_2019_2/clk_pll_stub.v

@@ -0,0 +1,25 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+// Date        : Tue Jul  7 23:25:51 2026
+// Host        : fedora running 64-bit unknown
+// Command     : write_verilog -force -mode synth_stub
+//               /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_stub.v
+// Design      : clk_pll
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7a200tfbg676-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+module clk_pll(cpu_clk, sys_clk, mlkem_clk, resetn, locked, 
+  clk_in1)
+/* synthesis syn_black_box black_box_pad_pin="cpu_clk,sys_clk,mlkem_clk,resetn,locked,clk_in1" */;
+  output cpu_clk;
+  output sys_clk;
+  output mlkem_clk;
+  input resetn;
+  output locked;
+  input clk_in1;
+endmodule

rtl/ip/PLL_2019_2/clk_pll_stub.vhdl

@@ -0,0 +1,33 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+-- Date        : Tue Jul  7 23:25:51 2026
+-- Host        : fedora running 64-bit unknown
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_stub.vhdl
+-- Design      : clk_pll
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7a200tfbg676-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity clk_pll is
+  Port ( 
+    cpu_clk : out STD_LOGIC;
+    sys_clk : out STD_LOGIC;
+    mlkem_clk : out STD_LOGIC;
+    resetn : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+
+end clk_pll;
+
+architecture stub of clk_pll is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "cpu_clk,sys_clk,mlkem_clk,resetn,locked,clk_in1";
+begin
+end;

rtl/ip/cdma/cdma_matmul_bridge.sv

@@ -0,0 +1,402 @@
+// ============================================================================
+//  cdma_matmul_bridge.sv
+//  Matmul-specific sequencer between the generic CDMA endpoint requester and
+//  the matmul local endpoint/control interface.
+//
+//  AXI-Lite register map, relative to this bridge window:
+//    0x00 CTRL       bit0 start, bit1 skip_result_writeback
+//    0x04 STATUS     bit0 busy, bit1 done (W1C)
+//    0x08 SRC_BASE   physical ExtRAM input base
+//    0x0C DST_BASE   physical ExtRAM result base
+//    0x10 GROUPS
+//    0x14 MAT_BASE   reserved for software compatibility
+//    0x18 SRC_STRIDE bytes, default 128
+//    0x1C DST_STRIDE bytes, default 192
+// ============================================================================
+`timescale 1ns / 1ps
+
+module cdma_matmul_bridge #(
+    parameter int ADDR_WIDTH      = 32,
+    parameter int AXIL_ADDR_WIDTH = 32,
+    parameter int AXIL_DATA_WIDTH = 32
+) (
+    input  logic                         clk,
+    input  logic                         rst_n,
+
+    input  logic [AXIL_ADDR_WIDTH-1:0]   s_axil_awaddr,
+    input  logic                         s_axil_awvalid,
+    output logic                         s_axil_awready,
+    input  logic [AXIL_DATA_WIDTH-1:0]   s_axil_wdata,
+    input  logic [AXIL_DATA_WIDTH/8-1:0] s_axil_wstrb,
+    input  logic                         s_axil_wvalid,
+    output logic                         s_axil_wready,
+    output logic [1:0]                   s_axil_bresp,
+    output logic                         s_axil_bvalid,
+    input  logic                         s_axil_bready,
+    input  logic [AXIL_ADDR_WIDTH-1:0]   s_axil_araddr,
+    input  logic                         s_axil_arvalid,
+    output logic                         s_axil_arready,
+    output logic [AXIL_DATA_WIDTH-1:0]   s_axil_rdata,
+    output logic [1:0]                   s_axil_rresp,
+    output logic                         s_axil_rvalid,
+    input  logic                         s_axil_rready,
+
+    output logic                         cdma_rd_req_valid,
+    input  logic                         cdma_rd_req_ready,
+    output logic [ADDR_WIDTH-1:0]        cdma_rd_req_src,
+    output logic [31:0]                  cdma_rd_req_bytes,
+    output logic [3:0]                   cdma_rd_req_ep_id,
+    output logic [3:0]                   cdma_rd_req_ep_bank,
+    output logic [7:0]                   cdma_rd_req_ep_word_off,
+    input  logic                         cdma_rd_req_done,
+
+    output logic                         cdma_wr_req_valid,
+    input  logic                         cdma_wr_req_ready,
+    output logic [ADDR_WIDTH-1:0]        cdma_wr_req_dst,
+    output logic [31:0]                  cdma_wr_req_bytes,
+    output logic [3:0]                   cdma_wr_req_ep_id,
+    output logic [3:0]                   cdma_wr_req_ep_bank,
+    output logic [7:0]                   cdma_wr_req_ep_word_off,
+    input  logic                         cdma_wr_req_done,
+
+    output logic                         mat_start_valid,
+    output logic                         mat_start_bank,
+    output logic                         mat_done_clear,
+    output logic                         mat_crc_clear,
+    input  logic                         mat_done,
+
+    output logic                         seq_done_irq
+);
+
+    localparam logic [7:0] REG_CTRL       = 8'h00;
+    localparam logic [7:0] REG_STATUS     = 8'h04;
+    localparam logic [7:0] REG_SRC_BASE   = 8'h08;
+    localparam logic [7:0] REG_DST_BASE   = 8'h0C;
+    localparam logic [7:0] REG_GROUPS     = 8'h10;
+    localparam logic [7:0] REG_MAT_BASE   = 8'h14;
+    localparam logic [7:0] REG_SRC_STRIDE = 8'h18;
+    localparam logic [7:0] REG_DST_STRIDE = 8'h1C;
+
+    localparam logic [31:0] MAT_AB_BYTES = 32'd128;
+    localparam logic [31:0] MAT_C_BYTES  = 32'd192;
+
+    logic [31:0] seq_src_base;
+    logic [31:0] seq_dst_base;
+    logic [31:0] seq_groups;
+    logic [31:0] seq_mat_base;
+    logic [31:0] seq_src_stride;
+    logic [31:0] seq_dst_stride;
+    logic        seq_busy;
+    logic        seq_done_flag;
+    logic        seq_skip_writeback;
+
+    logic [31:0] load_next_idx;
+    logic [31:0] groups_retired;
+    logic [1:0]  bank_load_active;
+    logic [1:0]  bank_ab_valid;
+    logic [1:0]  bank_compute_active;
+    logic [1:0]  bank_store_pending;
+    logic [1:0]  bank_store_active;
+    logic [31:0] bank_group_idx [2];
+    logic [31:0] load_next_src_addr;
+    logic [31:0] load_next_dst_addr;
+    logic [31:0] bank_dst_addr [2];
+
+    logic        rd_busy;
+    logic        wr_busy;
+    logic        rd_active_bank;
+    logic        wr_active_bank;
+    logic [1:0]  compute_q;
+    logic [1:0]  compute_q_count;
+    logic        mat_done_seen;
+
+    wire [7:0] wr_off = s_axil_awaddr[7:0];
+    wire [7:0] rd_off = s_axil_araddr[7:0];
+    wire do_write;
+    wire start_req = do_write && (wr_off == REG_CTRL) && s_axil_wstrb[0] && s_axil_wdata[0];
+    wire done_clear_req = do_write && (wr_off == REG_STATUS) && s_axil_wstrb[0] && s_axil_wdata[1];
+    wire load_target_bank = load_next_idx[0];
+    wire load_target_free = !bank_load_active[load_target_bank] &&
+                            !bank_ab_valid[load_target_bank] &&
+                            !bank_compute_active[load_target_bank] &&
+                            !bank_store_pending[load_target_bank] &&
+                            !bank_store_active[load_target_bank];
+    wire bank0_start_ready = bank_ab_valid[0] && !bank_compute_active[0] &&
+                             !bank_store_pending[0] && !bank_store_active[0];
+    wire bank1_start_ready = bank_ab_valid[1] && !bank_compute_active[1] &&
+                             !bank_store_pending[1] && !bank_store_active[1];
+    wire start_sel_bank = bank1_start_ready &&
+                          (!bank0_start_ready || (bank_group_idx[1] < bank_group_idx[0]));
+    wire start_ready_any = bank0_start_ready || bank1_start_ready;
+    wire store_sel_bank = bank_store_pending[1] && !bank_store_active[1] &&
+                          !(bank_store_pending[0] && !bank_store_active[0]);
+    wire store_ready_any = (bank_store_pending[0] && !bank_store_active[0]) ||
+                           (bank_store_pending[1] && !bank_store_active[1]);
+    wire mat_done_event = mat_done && !mat_done_seen;
+    wire retire_from_store = seq_busy && cdma_wr_req_done;
+    wire retire_from_compute = seq_busy && seq_skip_writeback && mat_done_event && (compute_q_count != 2'd0);
+    wire [31:0] retire_inc = {31'd0, retire_from_store} + {31'd0, retire_from_compute};
+
+    function automatic logic [31:0] apply_wstrb(
+        input logic [31:0] old_val,
+        input logic [31:0] new_val,
+        input logic [3:0]  wstrb
+    );
+        begin
+            apply_wstrb[7:0]   = wstrb[0] ? new_val[7:0]   : old_val[7:0];
+            apply_wstrb[15:8]  = wstrb[1] ? new_val[15:8]  : old_val[15:8];
+            apply_wstrb[23:16] = wstrb[2] ? new_val[23:16] : old_val[23:16];
+            apply_wstrb[31:24] = wstrb[3] ? new_val[31:24] : old_val[31:24];
+        end
+    endfunction
+
+    assign s_axil_bresp = 2'b00;
+    assign s_axil_rresp = 2'b00;
+    assign seq_done_irq = seq_done_flag;
+
+    always_ff @(posedge clk) begin
+        if (!rst_n) begin
+            s_axil_awready <= 1'b0;
+            s_axil_wready  <= 1'b0;
+        end else begin
+            if (s_axil_awvalid && s_axil_wvalid && !s_axil_awready && (!s_axil_bvalid || s_axil_bready)) begin
+                s_axil_awready <= 1'b1;
+                s_axil_wready  <= 1'b1;
+            end else begin
+                s_axil_awready <= 1'b0;
+                s_axil_wready  <= 1'b0;
+            end
+        end
+    end
+
+    assign do_write = s_axil_awready && s_axil_awvalid && s_axil_wready && s_axil_wvalid;
+
+    always_ff @(posedge clk) begin
+        if (!rst_n) begin
+            s_axil_bvalid <= 1'b0;
+        end else if (do_write) begin
+            s_axil_bvalid <= 1'b1;
+        end else if (s_axil_bready && s_axil_bvalid) begin
+            s_axil_bvalid <= 1'b0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        if (!rst_n) begin
+            s_axil_arready <= 1'b0;
+        end else begin
+            if (s_axil_arvalid && !s_axil_arready && (!s_axil_rvalid || s_axil_rready)) begin
+                s_axil_arready <= 1'b1;
+            end else begin
+                s_axil_arready <= 1'b0;
+            end
+        end
+    end
+
+    wire do_read = s_axil_arready && s_axil_arvalid;
+
+    always_ff @(posedge clk) begin
+        if (!rst_n) begin
+            s_axil_rvalid <= 1'b0;
+            s_axil_rdata  <= '0;
+        end else if (do_read) begin
+            s_axil_rvalid <= 1'b1;
+            case (rd_off)
+                REG_CTRL:       s_axil_rdata <= {30'd0, seq_skip_writeback, 1'b0};
+                REG_STATUS:     s_axil_rdata <= {30'd0, seq_done_flag, seq_busy};
+                REG_SRC_BASE:   s_axil_rdata <= seq_src_base;
+                REG_DST_BASE:   s_axil_rdata <= seq_dst_base;
+                REG_GROUPS:     s_axil_rdata <= seq_groups;
+                REG_MAT_BASE:   s_axil_rdata <= seq_mat_base;
+                REG_SRC_STRIDE: s_axil_rdata <= seq_src_stride;
+                REG_DST_STRIDE: s_axil_rdata <= seq_dst_stride;
+                default:        s_axil_rdata <= 32'd0;
+            endcase
+        end else if (s_axil_rready && s_axil_rvalid) begin
+            s_axil_rvalid <= 1'b0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        if (!rst_n) begin
+            seq_src_base   <= 32'h0;
+            seq_dst_base   <= 32'h0;
+            seq_groups     <= 32'h0;
+            seq_mat_base   <= 32'h1f50_0000;
+            seq_src_stride <= 32'd128;
+            seq_dst_stride <= 32'd192;
+        end else if (do_write) begin
+            case (wr_off)
+                REG_SRC_BASE:   if (!seq_busy) seq_src_base   <= apply_wstrb(seq_src_base,   s_axil_wdata, s_axil_wstrb);
+                REG_DST_BASE:   if (!seq_busy) seq_dst_base   <= apply_wstrb(seq_dst_base,   s_axil_wdata, s_axil_wstrb);
+                REG_GROUPS:     if (!seq_busy) seq_groups     <= apply_wstrb(seq_groups,     s_axil_wdata, s_axil_wstrb);
+                REG_MAT_BASE:   if (!seq_busy) seq_mat_base   <= apply_wstrb(seq_mat_base,   s_axil_wdata, s_axil_wstrb);
+                REG_SRC_STRIDE: if (!seq_busy) seq_src_stride <= apply_wstrb(seq_src_stride, s_axil_wdata, s_axil_wstrb);
+                REG_DST_STRIDE: if (!seq_busy) seq_dst_stride <= apply_wstrb(seq_dst_stride, s_axil_wdata, s_axil_wstrb);
+                default: begin
+                end
+            endcase
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        if (!rst_n) begin
+            seq_busy                  <= 1'b0;
+            seq_done_flag             <= 1'b0;
+            seq_skip_writeback        <= 1'b0;
+            load_next_idx             <= 32'd0;
+            groups_retired            <= 32'd0;
+            bank_load_active          <= 2'b00;
+            bank_ab_valid             <= 2'b00;
+            bank_compute_active       <= 2'b00;
+            bank_store_pending        <= 2'b00;
+            bank_store_active         <= 2'b00;
+            bank_group_idx[0]         <= 32'd0;
+            bank_group_idx[1]         <= 32'd0;
+            load_next_src_addr        <= 32'd0;
+            load_next_dst_addr        <= 32'd0;
+            bank_dst_addr[0]          <= 32'd0;
+            bank_dst_addr[1]          <= 32'd0;
+            rd_busy                   <= 1'b0;
+            wr_busy                   <= 1'b0;
+            rd_active_bank            <= 1'b0;
+            wr_active_bank            <= 1'b0;
+            compute_q                 <= 2'b00;
+            compute_q_count           <= 2'd0;
+            mat_done_seen             <= 1'b0;
+            cdma_rd_req_valid         <= 1'b0;
+            cdma_rd_req_src           <= '0;
+            cdma_rd_req_bytes         <= '0;
+            cdma_rd_req_ep_id         <= 4'd0;
+            cdma_rd_req_ep_bank       <= 4'd0;
+            cdma_rd_req_ep_word_off   <= 8'd0;
+            cdma_wr_req_valid         <= 1'b0;
+            cdma_wr_req_dst           <= '0;
+            cdma_wr_req_bytes         <= '0;
+            cdma_wr_req_ep_id         <= 4'd0;
+            cdma_wr_req_ep_bank       <= 4'd0;
+            cdma_wr_req_ep_word_off   <= 8'd0;
+            mat_start_valid           <= 1'b0;
+            mat_start_bank            <= 1'b0;
+            mat_done_clear            <= 1'b0;
+            mat_crc_clear             <= 1'b0;
+        end else begin
+            mat_start_valid <= 1'b0;
+            mat_done_clear  <= 1'b0;
+            mat_crc_clear   <= 1'b0;
+
+            mat_done_seen <= mat_done;
+
+            if (done_clear_req)
+                seq_done_flag <= 1'b0;
+
+            if (cdma_rd_req_valid && cdma_rd_req_ready)
+                cdma_rd_req_valid <= 1'b0;
+
+            if (cdma_wr_req_valid && cdma_wr_req_ready)
+                cdma_wr_req_valid <= 1'b0;
+
+            if (start_req && !seq_busy && (seq_groups != 32'd0)) begin
+                seq_busy            <= 1'b1;
+                seq_done_flag       <= 1'b0;
+                seq_skip_writeback  <= s_axil_wstrb[0] && s_axil_wdata[1];
+                load_next_idx       <= 32'd0;
+                groups_retired      <= 32'd0;
+                bank_load_active    <= 2'b00;
+                bank_ab_valid       <= 2'b00;
+                bank_compute_active <= 2'b00;
+                bank_store_pending  <= 2'b00;
+                bank_store_active   <= 2'b00;
+                bank_group_idx[0]   <= 32'd0;
+                bank_group_idx[1]   <= 32'd0;
+                load_next_src_addr  <= seq_src_base;
+                load_next_dst_addr  <= seq_dst_base;
+                bank_dst_addr[0]    <= 32'd0;
+                bank_dst_addr[1]    <= 32'd0;
+                rd_busy             <= 1'b0;
+                wr_busy             <= 1'b0;
+                compute_q           <= 2'b00;
+                compute_q_count     <= 2'd0;
+                mat_done_seen       <= 1'b1;
+                mat_crc_clear       <= 1'b1;
+                mat_done_clear      <= 1'b1;
+                cdma_rd_req_valid   <= 1'b0;
+                cdma_wr_req_valid   <= 1'b0;
+            end else if (seq_busy) begin
+                if (retire_inc != 32'd0) begin
+                    groups_retired <= groups_retired + retire_inc;
+                    if ((groups_retired + retire_inc) >= seq_groups) begin
+                        seq_busy      <= 1'b0;
+                        seq_done_flag <= 1'b1;
+                    end
+                end
+
+                if (cdma_rd_req_done) begin
+                    rd_busy <= 1'b0;
+                    bank_load_active[rd_active_bank] <= 1'b0;
+                    bank_ab_valid[rd_active_bank]    <= 1'b1;
+                end
+
+                if (cdma_wr_req_done) begin
+                    wr_busy <= 1'b0;
+                    bank_store_active[wr_active_bank] <= 1'b0;
+                end
+
+                if (mat_done_event && (compute_q_count != 2'd0)) begin
+                    mat_done_clear <= 1'b1;
+                    mat_done_seen <= 1'b1;
+                    bank_compute_active[compute_q[0]] <= 1'b0;
+                    if (!seq_skip_writeback) begin
+                        bank_store_pending[compute_q[0]] <= 1'b1;
+                    end
+                    if (compute_q_count == 2'd2)
+                        compute_q[0] <= compute_q[1];
+                    compute_q_count <= compute_q_count - 2'd1;
+                end
+
+                if (!rd_busy && !cdma_rd_req_valid && (load_next_idx < seq_groups) && load_target_free) begin
+                    cdma_rd_req_src         <= load_next_src_addr;
+                    cdma_rd_req_bytes       <= MAT_AB_BYTES;
+                    cdma_rd_req_ep_id       <= 4'd0;
+                    cdma_rd_req_ep_bank     <= {3'b000, load_target_bank};
+                    cdma_rd_req_ep_word_off <= 8'd0;
+                    cdma_rd_req_valid       <= 1'b1;
+                    rd_busy                 <= 1'b1;
+                    rd_active_bank          <= load_target_bank;
+                    bank_load_active[load_target_bank] <= 1'b1;
+                    bank_group_idx[load_target_bank]   <= load_next_idx;
+                    bank_dst_addr[load_target_bank]     <= load_next_dst_addr;
+                    load_next_src_addr <= load_next_src_addr + seq_src_stride;
+                    load_next_dst_addr <= load_next_dst_addr + seq_dst_stride;
+                    load_next_idx <= load_next_idx + 32'd1;
+                end
+
+                if (!seq_skip_writeback && !wr_busy && !cdma_wr_req_valid && store_ready_any) begin
+                    cdma_wr_req_dst         <= bank_dst_addr[store_sel_bank];
+                    cdma_wr_req_bytes       <= MAT_C_BYTES;
+                    cdma_wr_req_ep_id       <= 4'd0;
+                    cdma_wr_req_ep_bank     <= {3'b000, store_sel_bank};
+                    cdma_wr_req_ep_word_off <= 8'd0;
+                    cdma_wr_req_valid       <= 1'b1;
+                    wr_busy                 <= 1'b1;
+                    wr_active_bank          <= store_sel_bank;
+                    bank_store_pending[store_sel_bank] <= 1'b0;
+                    bank_store_active[store_sel_bank]  <= 1'b1;
+                end
+
+                if ((compute_q_count < 2'd2) && start_ready_any && !(mat_done_event && (compute_q_count != 2'd0))) begin
+                    mat_start_valid <= 1'b1;
+                    mat_start_bank  <= start_sel_bank;
+                    bank_ab_valid[start_sel_bank]       <= 1'b0;
+                    bank_compute_active[start_sel_bank]  <= 1'b1;
+                    if (compute_q_count == 2'd0)
+                        compute_q[0] <= start_sel_bank;
+                    else
+                        compute_q[1] <= start_sel_bank;
+                    compute_q_count <= compute_q_count + 2'd1;
+                end
+            end
+        end
+    end
+
+endmodule

rtl/ip/cdma/snix_axil_cdma_mux.sv

@@ -110,6 +110,27 @@ module snix_axil_cdma_mux #(
     output logic [7:0]                       ep_rd_word_addr,
     input  logic [31:0]                      ep_rd_data,
     input  logic                             ep_rd_ready,
+
+    // ==========================================
+    // Generic external endpoint requester
+    // ==========================================
+    input  logic                             ext_rd_req_valid,
+    output logic                             ext_rd_req_ready,
+    input  logic [ADDR_WIDTH-1:0]            ext_rd_req_src,
+    input  logic [31:0]                      ext_rd_req_bytes,
+    input  logic [3:0]                       ext_rd_req_ep_id,
+    input  logic [3:0]                       ext_rd_req_ep_bank,
+    input  logic [7:0]                       ext_rd_req_ep_word_off,
+    output logic                             ext_rd_req_done,
+
+    input  logic                             ext_wr_req_valid,
+    output logic                             ext_wr_req_ready,
+    input  logic [ADDR_WIDTH-1:0]            ext_wr_req_dst,
+    input  logic [31:0]                      ext_wr_req_bytes,
+    input  logic [3:0]                       ext_wr_req_ep_id,
+    input  logic [3:0]                       ext_wr_req_ep_bank,
+    input  logic [7:0]                       ext_wr_req_ep_word_off,
+    output logic                             ext_wr_req_done,
     
     // Global Interrupt (OR'd from all channels)
     output logic                             dma_finish 
@@ -123,30 +144,6 @@ module snix_axil_cdma_mux #(
     localparam logic [1:0] MODE_MEM2EP  = 2'd1;
     localparam logic [1:0] MODE_EP2MEM  = 2'd2;
 
-    localparam logic [7:0] SEQ_REG_CTRL       = 8'h00;
-    localparam logic [7:0] SEQ_REG_STATUS     = 8'h04;
-    localparam logic [7:0] SEQ_REG_SRC_BASE   = 8'h08;
-    localparam logic [7:0] SEQ_REG_DST_BASE   = 8'h0C;
-    localparam logic [7:0] SEQ_REG_GROUPS     = 8'h10;
-    localparam logic [7:0] SEQ_REG_MAT_BASE   = 8'h14;
-    localparam logic [7:0] SEQ_REG_SRC_STRIDE = 8'h18;
-    localparam logic [7:0] SEQ_REG_DST_STRIDE = 8'h1C;
-
-    localparam logic [11:0] MAT_CTRL_OFF   = 12'h000;
-    localparam logic [11:0] MAT_STATUS_OFF = 12'h004;
-    localparam logic [11:0] MAT_CRC_OFF    = 12'h010;
-    localparam logic [11:0] MAT_B0_AB_OFF  = 12'h100;
-    localparam logic [11:0] MAT_B0_C_OFF   = 12'h180;
-    localparam logic [11:0] MAT_B1_AB_OFF  = 12'h300;
-    localparam logic [11:0] MAT_B1_C_OFF   = 12'h380;
-
-    localparam logic [31:0] MAT_STATUS_DONE_CLR = 32'h0000_0006;
-    localparam logic [31:0] MAT_STATUS_DONE_BIT = 32'h0000_0002;
-    localparam logic [31:0] MAT_CTRL_START_B0   = 32'h0000_0001;
-    localparam logic [31:0] MAT_CTRL_START_B1   = 32'h0000_0002;
-    localparam logic [31:0] MAT_AB_BYTES        = 32'd128;
-    localparam logic [31:0] MAT_C_BYTES         = 32'd192;
-    
     // Function to safely apply WSTRB to 32-bit registers
     function automatic logic [31:0] apply_wstrb(
         input logic [31:0] old_val,
@@ -177,17 +174,6 @@ module snix_axil_cdma_mux #(
 
     logic [PORTS-1:0]      arb_set_done; // From Arbiter to CSR
 
-    logic [31:0]           seq_src_base;
-    logic [31:0]           seq_dst_base;
-    logic [31:0]           seq_groups;
-    logic [31:0]           seq_mat_base;
-    logic [31:0]           seq_src_stride;
-    logic [31:0]           seq_dst_stride;
-    logic                  seq_busy;
-    logic                  seq_done_flag;
-    wire                   seq_start_req;
-    wire                   seq_done_clear_req;
-
     // ==========================================
     // Address Decoding (0x40 offset per channel)
     // ==========================================
@@ -195,14 +181,6 @@ module snix_axil_cdma_mux #(
     wire [5:0]         wr_reg = s_axil_awaddr[5:0];
     wire [CH_BITS-1:0] rd_ch  = s_axil_araddr[6 +: CH_BITS];
     wire [5:0]         rd_reg = s_axil_araddr[5:0];
-    wire               wr_seq_reg = (s_axil_awaddr[11:8] == 4'h2);
-    wire               rd_seq_reg = (s_axil_araddr[11:8] == 4'h2);
-    wire [7:0]         wr_seq_off = s_axil_awaddr[7:0];
-    wire [7:0]         rd_seq_off = s_axil_araddr[7:0];
-    assign seq_start_req = do_write && wr_seq_reg && (wr_seq_off == SEQ_REG_CTRL) &&
-                           s_axil_wstrb[0] && s_axil_wdata[0];
-    assign seq_done_clear_req = do_write && wr_seq_reg && (wr_seq_off == SEQ_REG_STATUS) &&
-                                s_axil_wstrb[0] && s_axil_wdata[1];
 
     // ==========================================
     // AXI-Lite Slave Logic (Robust Backpressure)
@@ -262,19 +240,7 @@ module snix_axil_cdma_mux #(
         end else begin
             if (do_read) begin
                 s_axil_rvalid <= 1'b1;
-                if (rd_seq_reg) begin
-                    case (rd_seq_off)
-                        SEQ_REG_CTRL:       s_axil_rdata <= {31'd0, seq_start_req};
-                        SEQ_REG_STATUS:     s_axil_rdata <= {30'd0, seq_done_flag, seq_busy};
-                        SEQ_REG_SRC_BASE:   s_axil_rdata <= seq_src_base;
-                        SEQ_REG_DST_BASE:   s_axil_rdata <= seq_dst_base;
-                        SEQ_REG_GROUPS:     s_axil_rdata <= seq_groups;
-                        SEQ_REG_MAT_BASE:   s_axil_rdata <= seq_mat_base;
-                        SEQ_REG_SRC_STRIDE: s_axil_rdata <= seq_src_stride;
-                        SEQ_REG_DST_STRIDE: s_axil_rdata <= seq_dst_stride;
-                        default:            s_axil_rdata <= 32'd0;
-                    endcase
-                end else if (rd_ch < PORTS) begin
+                if (rd_ch < PORTS) begin
                     case (rd_reg)
                         6'h00: s_axil_rdata <= ch_src_addr[rd_ch];
                         6'h04: s_axil_rdata <= ch_dst_addr[rd_ch];
@@ -304,12 +270,6 @@ module snix_axil_cdma_mux #(
         if (!rst_n) begin
             ch_req  <= '0;
             ch_done <= '0;
-            seq_src_base   <= 32'h0;
-            seq_dst_base   <= 32'h0;
-            seq_groups     <= 32'h0;
-            seq_mat_base   <= 32'h1f50_0000;
-            seq_src_stride <= 32'd128;
-            seq_dst_stride <= 32'd192;
             for (int i=0; i<PORTS; i++) begin
                 ch_src_addr[i] <= '0; ch_dst_addr[i] <= '0;
                 ch_len[i] <= '0; ch_tag[i] <= '0; ch_ctrl[i] <= '0;
@@ -325,16 +285,7 @@ module snix_axil_cdma_mux #(
             end
 
             // 2. Process CPU Writes
-            if (do_write && wr_seq_reg) begin
-                case (wr_seq_off)
-                    SEQ_REG_SRC_BASE:   if (!seq_busy) seq_src_base   <= apply_wstrb(seq_src_base,   s_axil_wdata, s_axil_wstrb);
-                    SEQ_REG_DST_BASE:   if (!seq_busy) seq_dst_base   <= apply_wstrb(seq_dst_base,   s_axil_wdata, s_axil_wstrb);
-                    SEQ_REG_GROUPS:     if (!seq_busy) seq_groups     <= apply_wstrb(seq_groups,     s_axil_wdata, s_axil_wstrb);
-                    SEQ_REG_MAT_BASE:   if (!seq_busy) seq_mat_base   <= apply_wstrb(seq_mat_base,   s_axil_wdata, s_axil_wstrb);
-                    SEQ_REG_SRC_STRIDE: if (!seq_busy) seq_src_stride <= apply_wstrb(seq_src_stride, s_axil_wdata, s_axil_wstrb);
-                    SEQ_REG_DST_STRIDE: if (!seq_busy) seq_dst_stride <= apply_wstrb(seq_dst_stride, s_axil_wdata, s_axil_wstrb);
-                endcase
-            end else if (do_write && wr_ch < PORTS) begin
+            if (do_write && wr_ch < PORTS) begin
                 case (wr_reg)
                     6'h00: if (!ch_req[wr_ch]) ch_src_addr[wr_ch] <= apply_wstrb(ch_src_addr[wr_ch], s_axil_wdata, s_axil_wstrb);
                     6'h04: if (!ch_req[wr_ch]) ch_dst_addr[wr_ch] <= apply_wstrb(ch_dst_addr[wr_ch], s_axil_wdata, s_axil_wstrb);
@@ -456,99 +407,35 @@ module snix_axil_cdma_mux #(
     logic                   ep_arready;
     logic                   ep_rready;
 
-    logic [ID_WIDTH-1:0]    seq_awid;
-    logic [ADDR_WIDTH-1:0]  seq_awaddr;
-    logic [7:0]             seq_awlen;
-    logic [2:0]             seq_awsize;
-    logic [1:0]             seq_awburst;
-    logic                   seq_awlock;
-    logic [3:0]             seq_awcache;
-    logic [2:0]             seq_awprot;
-    logic [3:0]             seq_awqos;
-    logic [USER_WIDTH-1:0]  seq_awuser;
-    logic                   seq_awvalid;
-    logic                   seq_awready;
-    logic [DATA_WIDTH-1:0]  seq_wdata;
-    logic [DATA_WIDTH/8-1:0] seq_wstrb;
-    logic                   seq_wlast;
-    logic [USER_WIDTH-1:0]  seq_wuser;
-    logic                   seq_wvalid;
-    logic                   seq_wready;
-    logic                   seq_bready;
-    logic [ID_WIDTH-1:0]    seq_arid;
-    logic [ADDR_WIDTH-1:0]  seq_araddr;
-    logic [7:0]             seq_arlen;
-    logic [2:0]             seq_arsize;
-    logic [1:0]             seq_arburst;
-    logic                   seq_arlock;
-    logic [3:0]             seq_arcache;
-    logic [2:0]             seq_arprot;
-    logic [3:0]             seq_arqos;
-    logic [USER_WIDTH-1:0]  seq_aruser;
-    logic                   seq_arvalid;
-    logic                   seq_arready;
-    logic                   seq_rready;
+    typedef enum logic [2:0] {EP_IDLE, EP_AR, EP_READ, EP_AW, EP_WRITE, EP_BRESP, EP_DONE} ep_state_t;
+    ep_state_t ep_state;
+    logic [31:0] ep_axi_addr;
+    logic [31:0] ep_bytes_left;
+    logic [7:0]  ep_word_addr_r;
 
-    // Hardware matmul loop sequencer state. Keep these declarations before the
-    // DMA routing logic because Vivado does not allow forward enum references.
-    typedef enum logic [4:0] {
-        SQ_IDLE,
-        SQ_CLEAR_CRC,
-        SQ_LOAD0,
-        SQ_START0,
-        SQ_LOAD1,
-        SQ_WAIT_DONE,
-        SQ_STORE,
-        SQ_CLEAR_DONE,
-        SQ_START_NEXT,
-        SQ_LOAD_NEXT,
-        SQ_DONE
-    } seq_state_t;
+    typedef enum logic [1:0] {EXT_RD_IDLE, EXT_RD_AR, EXT_RD_READ} ext_rd_state_t;
+    typedef enum logic [1:0] {EXT_WR_IDLE, EXT_WR_AW, EXT_WR_WRITE, EXT_WR_BRESP} ext_wr_state_t;
 
-    typedef enum logic [3:0] {
-        OP_IDLE,
-        OP_READ_ADDR,
-        OP_READ_DATA,
-        OP_WRITE_ADDR,
-        OP_WRITE_DATA,
-        OP_WRITE_RESP,
-        OP_REG_READ_ADDR,
-        OP_REG_READ_DATA,
-        OP_COPY_START,
-        OP_COPY_WAIT
-    } op_state_t;
+    ext_rd_state_t ext_rd_state;
+    ext_wr_state_t ext_wr_state;
+    logic [ADDR_WIDTH-1:0] ext_rd_addr_r;
+    logic [31:0]           ext_rd_bytes_left;
+    logic [7:0]            ext_rd_word_addr_r;
+    logic [3:0]            ext_rd_ep_id_r;
+    logic [3:0]            ext_rd_ep_bank_r;
 
-    seq_state_t seq_state;
-    op_state_t  op_state;
+    logic [ADDR_WIDTH-1:0] ext_wr_addr_r;
+    logic [31:0]           ext_wr_bytes_left;
+    logic [7:0]            ext_wr_word_addr_r;
+    logic [3:0]            ext_wr_ep_id_r;
+    logic [3:0]            ext_wr_ep_bank_r;
 
-    logic        op_start_copy;
-    logic        op_start_write;
-    logic        op_start_read;
-    logic        op_done;
-    logic [31:0] op_src_addr;
-    logic [31:0] op_dst_addr;
-    logic [31:0] op_bytes;
-    logic [31:0] op_write_addr;
-    logic [31:0] op_write_data;
-    logic [31:0] op_read_addr;
-    logic [31:0] op_read_data;
-    logic [31:0] op_src_cur;
-    logic [31:0] op_dst_cur;
-    logic [31:0] op_bytes_left;
-    logic [31:0] op_data_buf;
-    logic        op_buf_valid;
-    logic        op_copy_store;
-
-    logic [31:0] seq_group_idx;
-    logic [31:0] seq_load_idx;
-    logic [31:0] seq_store_idx;
-    logic        seq_compute_bank;
-    logic [31:0] seq_status_data;
-
-    wire use_ep_engine = (state == RUN) && (engine_mode != MODE_MEM2MEM);
-    wire use_seq_engine = seq_busy && (op_state != OP_IDLE) &&
-                          (op_state != OP_COPY_START) && (op_state != OP_COPY_WAIT);
-    wire seq_dma_active = seq_busy && ((op_state == OP_COPY_START) || (op_state == OP_COPY_WAIT));
+    wire ext_rd_active = (ext_rd_state != EXT_RD_IDLE);
+    wire ext_wr_active = (ext_wr_state != EXT_WR_IDLE);
+    wire ext_rd_accept = ext_rd_req_valid && ext_rd_req_ready;
+    wire ext_wr_accept = ext_wr_req_valid && ext_wr_req_ready;
+    wire ext_any_busy_or_req = ext_rd_active || ext_wr_active || ext_rd_req_valid || ext_wr_req_valid;
+    wire use_ep_engine = ((state == RUN) && (engine_mode != MODE_MEM2MEM));
 
     // Dynamic routing to the engine based on current active channel
     assign engine_src   = ch_src_addr[cur_ch];
@@ -564,47 +451,44 @@ module snix_axil_cdma_mux #(
     assign mm2mm_start  = engine_start && (engine_mode == MODE_MEM2MEM);
     assign ep_start     = engine_start && (engine_mode != MODE_MEM2MEM);
 
-    assign core_awready = (!use_seq_engine && !use_ep_engine) && mm2mm_awready;
-    assign core_wready  = (!use_seq_engine && !use_ep_engine) && mm2mm_wready;
-    assign core_arready = (!use_seq_engine && !use_ep_engine) && mm2mm_arready;
-    assign ep_awready   = (!use_seq_engine && use_ep_engine) && mm2mm_awready;
-    assign ep_wready    = (!use_seq_engine && use_ep_engine) && mm2mm_wready;
-    assign ep_arready   = (!use_seq_engine && use_ep_engine) && mm2mm_arready;
-    assign seq_awready  = use_seq_engine && mm2mm_awready;
-    assign seq_wready   = use_seq_engine && mm2mm_wready;
-    assign seq_arready  = use_seq_engine && mm2mm_arready;
+    assign core_awready = (!ext_wr_active && !use_ep_engine) && mm2mm_awready;
+    assign core_wready  = (!ext_wr_active && !use_ep_engine) && mm2mm_wready;
+    assign core_arready = (!ext_rd_active && !use_ep_engine) && mm2mm_arready;
+    assign ep_awready   = (!ext_wr_active && use_ep_engine) && mm2mm_awready;
+    assign ep_wready    = (!ext_wr_active && use_ep_engine) && mm2mm_wready;
+    assign ep_arready   = (!ext_rd_active && use_ep_engine) && mm2mm_arready;
 
-    assign mm2mm_awid    = use_seq_engine ? seq_awid    : (use_ep_engine ? ep_awid    : core_awid);
-    assign mm2mm_awaddr  = use_seq_engine ? seq_awaddr  : (use_ep_engine ? ep_awaddr  : core_awaddr);
-    assign mm2mm_awlen   = use_seq_engine ? seq_awlen   : (use_ep_engine ? ep_awlen   : core_awlen);
-    assign mm2mm_awsize  = use_seq_engine ? seq_awsize  : (use_ep_engine ? ep_awsize  : core_awsize);
-    assign mm2mm_awburst = use_seq_engine ? seq_awburst : (use_ep_engine ? ep_awburst : core_awburst);
-    assign mm2mm_awlock  = use_seq_engine ? seq_awlock  : (use_ep_engine ? ep_awlock  : core_awlock);
-    assign mm2mm_awcache = use_seq_engine ? seq_awcache : (use_ep_engine ? ep_awcache : core_awcache);
-    assign mm2mm_awprot  = use_seq_engine ? seq_awprot  : (use_ep_engine ? ep_awprot  : core_awprot);
-    assign mm2mm_awqos   = use_seq_engine ? seq_awqos   : (use_ep_engine ? ep_awqos   : core_awqos);
-    assign mm2mm_awuser  = use_seq_engine ? seq_awuser  : (use_ep_engine ? ep_awuser  : core_awuser);
-    assign mm2mm_awvalid = use_seq_engine ? seq_awvalid : (use_ep_engine ? ep_awvalid : core_awvalid);
+    assign mm2mm_awid    = ext_wr_active ? '0          : (use_ep_engine ? ep_awid    : core_awid);
+    assign mm2mm_awaddr  = ext_wr_active ? ext_wr_addr_r : (use_ep_engine ? ep_awaddr  : core_awaddr);
+    assign mm2mm_awlen   = ext_wr_active ? (((ext_wr_bytes_left[31:2] == 30'd0) ? 8'd1 : ext_wr_bytes_left[9:2]) - 8'd1) : (use_ep_engine ? ep_awlen : core_awlen);
+    assign mm2mm_awsize  = ext_wr_active ? 3'd2        : (use_ep_engine ? ep_awsize  : core_awsize);
+    assign mm2mm_awburst = ext_wr_active ? 2'b01       : (use_ep_engine ? ep_awburst : core_awburst);
+    assign mm2mm_awlock  = ext_wr_active ? 1'b0        : (use_ep_engine ? ep_awlock  : core_awlock);
+    assign mm2mm_awcache = ext_wr_active ? 4'b0        : (use_ep_engine ? ep_awcache : core_awcache);
+    assign mm2mm_awprot  = ext_wr_active ? 3'b0        : (use_ep_engine ? ep_awprot  : core_awprot);
+    assign mm2mm_awqos   = ext_wr_active ? 4'b0        : (use_ep_engine ? ep_awqos   : core_awqos);
+    assign mm2mm_awuser  = ext_wr_active ? '0          : (use_ep_engine ? ep_awuser  : core_awuser);
+    assign mm2mm_awvalid = ext_wr_active ? (ext_wr_state == EXT_WR_AW) : (use_ep_engine ? ep_awvalid : core_awvalid);
 
-    assign mm2mm_wdata   = use_seq_engine ? seq_wdata   : (use_ep_engine ? ep_wdata   : core_wdata);
-    assign mm2mm_wstrb   = use_seq_engine ? seq_wstrb   : (use_ep_engine ? ep_wstrb   : core_wstrb);
-    assign mm2mm_wlast   = use_seq_engine ? seq_wlast   : (use_ep_engine ? ep_wlast   : core_wlast);
-    assign mm2mm_wuser   = use_seq_engine ? seq_wuser   : (use_ep_engine ? ep_wuser   : core_wuser);
-    assign mm2mm_wvalid  = use_seq_engine ? seq_wvalid  : (use_ep_engine ? ep_wvalid  : core_wvalid);
-    assign mm2mm_bready  = use_seq_engine ? seq_bready  : (use_ep_engine ? ep_bready  : core_bready);
+    assign mm2mm_wdata   = ext_wr_active ? ep_rd_data  : (use_ep_engine ? ep_wdata   : core_wdata);
+    assign mm2mm_wstrb   = ext_wr_active ? {{(DATA_WIDTH/8){1'b1}}} : (use_ep_engine ? ep_wstrb : core_wstrb);
+    assign mm2mm_wlast   = ext_wr_active ? ((ext_wr_bytes_left <= 32'd4) && mm2mm_wvalid) : (use_ep_engine ? ep_wlast : core_wlast);
+    assign mm2mm_wuser   = ext_wr_active ? '0          : (use_ep_engine ? ep_wuser   : core_wuser);
+    assign mm2mm_wvalid  = ext_wr_active ? ((ext_wr_state == EXT_WR_WRITE) && ep_rd_ready) : (use_ep_engine ? ep_wvalid : core_wvalid);
+    assign mm2mm_bready  = ext_wr_active ? (ext_wr_state == EXT_WR_BRESP) : (use_ep_engine ? ep_bready : core_bready);
 
-    assign mm2mm_arid    = use_seq_engine ? seq_arid    : (use_ep_engine ? ep_arid    : core_arid);
-    assign mm2mm_araddr  = use_seq_engine ? seq_araddr  : (use_ep_engine ? ep_araddr  : core_araddr);
-    assign mm2mm_arlen   = use_seq_engine ? seq_arlen   : (use_ep_engine ? ep_arlen   : core_arlen);
-    assign mm2mm_arsize  = use_seq_engine ? seq_arsize  : (use_ep_engine ? ep_arsize  : core_arsize);
-    assign mm2mm_arburst = use_seq_engine ? seq_arburst : (use_ep_engine ? ep_arburst : core_arburst);
-    assign mm2mm_arlock  = use_seq_engine ? seq_arlock  : (use_ep_engine ? ep_arlock  : core_arlock);
-    assign mm2mm_arcache = use_seq_engine ? seq_arcache : (use_ep_engine ? ep_arcache : core_arcache);
-    assign mm2mm_arprot  = use_seq_engine ? seq_arprot  : (use_ep_engine ? ep_arprot  : core_arprot);
-    assign mm2mm_arqos   = use_seq_engine ? seq_arqos   : (use_ep_engine ? ep_arqos   : core_arqos);
-    assign mm2mm_aruser  = use_seq_engine ? seq_aruser  : (use_ep_engine ? ep_aruser  : core_aruser);
-    assign mm2mm_arvalid = use_seq_engine ? seq_arvalid : (use_ep_engine ? ep_arvalid : core_arvalid);
-    assign mm2mm_rready  = use_seq_engine ? seq_rready  : (use_ep_engine ? ep_rready  : core_rready);
+    assign mm2mm_arid    = ext_rd_active ? '0          : (use_ep_engine ? ep_arid    : core_arid);
+    assign mm2mm_araddr  = ext_rd_active ? ext_rd_addr_r : (use_ep_engine ? ep_araddr  : core_araddr);
+    assign mm2mm_arlen   = ext_rd_active ? (((ext_rd_bytes_left[31:2] == 30'd0) ? 8'd1 : ext_rd_bytes_left[9:2]) - 8'd1) : (use_ep_engine ? ep_arlen : core_arlen);
+    assign mm2mm_arsize  = ext_rd_active ? 3'd2        : (use_ep_engine ? ep_arsize  : core_arsize);
+    assign mm2mm_arburst = ext_rd_active ? 2'b01       : (use_ep_engine ? ep_arburst : core_arburst);
+    assign mm2mm_arlock  = ext_rd_active ? 1'b0        : (use_ep_engine ? ep_arlock  : core_arlock);
+    assign mm2mm_arcache = ext_rd_active ? 4'b0        : (use_ep_engine ? ep_arcache : core_arcache);
+    assign mm2mm_arprot  = ext_rd_active ? 3'b0        : (use_ep_engine ? ep_arprot  : core_arprot);
+    assign mm2mm_arqos   = ext_rd_active ? 4'b0        : (use_ep_engine ? ep_arqos   : core_arqos);
+    assign mm2mm_aruser  = ext_rd_active ? '0          : (use_ep_engine ? ep_aruser  : core_aruser);
+    assign mm2mm_arvalid = ext_rd_active ? (ext_rd_state == EXT_RD_AR) : (use_ep_engine ? ep_arvalid : core_arvalid);
+    assign mm2mm_rready  = ext_rd_active ? ((ext_rd_state == EXT_RD_READ) && ep_wr_ready) : (use_ep_engine ? ep_rready : core_rready);
 
     always_ff @(posedge clk) begin
         if (!rst_n) begin
@@ -619,7 +503,7 @@ module snix_axil_cdma_mux #(
 
             case (state)
                 IDLE: begin
-                    if (seq_busy) begin
+                    if (ext_any_busy_or_req) begin
                         state <= IDLE;
                     end else for (int i = 0; i < PORTS; i++) begin
                         logic [CH_BITS:0] check_ch_ext;
@@ -666,13 +550,13 @@ module snix_axil_cdma_mux #(
     ) u_core_engine (
         .clk               (clk),
         .rst_n             (rst_n),
-        .ctrl_start        ((op_state == OP_COPY_START) ? 1'b1 : mm2mm_start),
+        .ctrl_start        (mm2mm_start),
         .ctrl_stop         (1'b0), // Tied off; can be wired if global abort is needed
-        .ctrl_src_addr     (seq_dma_active ? op_src_cur : engine_src),
-        .ctrl_dst_addr     (seq_dma_active ? op_dst_cur : engine_dst),
-        .ctrl_len          (seq_dma_active ? 8'd63 : engine_len),
-        .ctrl_size         (seq_dma_active ? 3'd2 : engine_size),
-        .ctrl_transfer_len (seq_dma_active ? op_bytes_left : engine_bytes),
+        .ctrl_src_addr     (engine_src),
+        .ctrl_dst_addr     (engine_dst),
+        .ctrl_len          (engine_len),
+        .ctrl_size         (engine_size),
+        .ctrl_transfer_len (engine_bytes),
         .ctrl_done         (mm2mm_done),
         // AXI4 Port Connections
         .mm2mm_awid   (core_awid),   .mm2mm_awaddr (core_awaddr),
@@ -699,320 +583,106 @@ module snix_axil_cdma_mux #(
         .mm2mm_rready (core_rready)
     );
 
+    wire [7:0] ep_beats_total = (engine_bytes[31:2] == 30'd0) ? 8'd1 : engine_bytes[9:2];
+    wire [7:0] ep_axi_len     = ep_beats_total - 8'd1;
+    wire       ep_mode_mem2ep = (engine_mode == MODE_MEM2EP);
+    wire       ep_mode_ep2mem = (engine_mode == MODE_EP2MEM);
+    wire       ep_rd_done_fire = (ep_state == EP_READ) && mm2mm_rvalid && ep_rready && mm2mm_rlast;
+    wire       ep_wr_done_fire = (ep_state == EP_BRESP) && mm2mm_bvalid && ep_bready;
+    wire       ep_done_fast    = ep_rd_done_fire || ep_wr_done_fire;
+    wire       ext_rd_done_fire = (ext_rd_state == EXT_RD_READ) && mm2mm_rvalid && mm2mm_rready && mm2mm_rlast;
+    wire       ext_wr_done_fire = (ext_wr_state == EXT_WR_BRESP) && mm2mm_bvalid && mm2mm_bready;
+    wire       ext_wr_w_fire    = (ext_wr_state == EXT_WR_WRITE) && mm2mm_wvalid && mm2mm_wready;
+
     // ==========================================
-    // Hardware matmul loop sequencer
+    // Generic external endpoint requester
     // ==========================================
-    wire seq_has_more_load = (seq_load_idx < seq_groups);
-    wire [31:0] seq_src_addr_for_load = seq_src_base + (seq_load_idx * seq_src_stride);
-    wire [31:0] seq_dst_addr_for_load = seq_mat_base + (seq_load_idx[0] ? MAT_B1_AB_OFF : MAT_B0_AB_OFF);
-    wire [31:0] seq_src_addr_for_store = seq_mat_base + (seq_store_idx[0] ? MAT_B1_C_OFF : MAT_B0_C_OFF);
-    wire [31:0] seq_dst_addr_for_store = seq_dst_base + (seq_store_idx * seq_dst_stride);
-    wire [31:0] seq_start_value_for_bank = seq_compute_bank ? MAT_CTRL_START_B1 : MAT_CTRL_START_B0;
-    wire [31:0] seq_start_value_for_loaded_bank =
-        (seq_load_idx[0] == 1'b0) ? MAT_CTRL_START_B1 : MAT_CTRL_START_B0;
-
-    assign seq_awid    = '0;
-    assign seq_awsize  = 3'd2;
-    assign seq_awburst = 2'b01;
-    assign seq_awlock  = 1'b0;
-    assign seq_awcache = 4'b0;
-    assign seq_awprot  = 3'b0;
-    assign seq_awqos   = 4'b0;
-    assign seq_awuser  = '0;
-    assign seq_wstrb   = {{(DATA_WIDTH/8){1'b1}}};
-    assign seq_wuser   = '0;
-    assign seq_arid    = '0;
-    assign seq_arsize  = 3'd2;
-    assign seq_arburst = 2'b01;
-    assign seq_arlock  = 1'b0;
-    assign seq_arcache = 4'b0;
-    assign seq_arprot  = 3'b0;
-    assign seq_arqos   = 4'b0;
-    assign seq_aruser  = '0;
-
-    assign seq_araddr  = (op_state == OP_REG_READ_ADDR) ? op_read_addr : op_src_cur;
-    assign seq_arlen   = (op_state == OP_REG_READ_ADDR) ? 8'd0 : 8'd0;
-    assign seq_arvalid = (op_state == OP_READ_ADDR) || (op_state == OP_REG_READ_ADDR);
-    assign seq_rready  = (op_state == OP_REG_READ_DATA) ||
-                         ((op_state == OP_READ_DATA) && !op_buf_valid);
-
-    assign seq_awaddr  = (op_state == OP_WRITE_ADDR && op_copy_store) ? op_dst_cur : op_write_addr;
-    assign seq_awlen   = 8'd0;
-    assign seq_awvalid = (op_state == OP_WRITE_ADDR);
-    assign seq_wdata   = op_copy_store ? op_data_buf : op_write_data;
-    assign seq_wlast   = 1'b1;
-    assign seq_wvalid  = (op_state == OP_WRITE_DATA) && (!op_copy_store || op_buf_valid);
-    assign seq_bready  = (op_state == OP_WRITE_RESP);
+    assign ext_rd_req_ready = (state == IDLE) && (ep_state == EP_IDLE) && !ext_rd_active;
+    assign ext_wr_req_ready = (state == IDLE) && (ep_state == EP_IDLE) && !ext_wr_active;
+    assign ext_rd_req_done  = ext_rd_done_fire;
+    assign ext_wr_req_done  = ext_wr_done_fire;
 
     always_ff @(posedge clk) begin
         if (!rst_n) begin
-            op_state      <= OP_IDLE;
-            op_done       <= 1'b0;
-            op_src_cur    <= '0;
-            op_dst_cur    <= '0;
-            op_bytes_left <= '0;
-            op_data_buf   <= '0;
-            op_buf_valid  <= 1'b0;
-            op_copy_store <= 1'b0;
-            op_read_data  <= '0;
+            ext_rd_state       <= EXT_RD_IDLE;
+            ext_rd_addr_r      <= '0;
+            ext_rd_bytes_left  <= '0;
+            ext_rd_word_addr_r <= '0;
+            ext_rd_ep_id_r     <= '0;
+            ext_rd_ep_bank_r   <= '0;
         end else begin
-            op_done <= 1'b0;
-
-            case (op_state)
-                OP_IDLE: begin
-                    op_buf_valid <= 1'b0;
-                    if (op_start_copy) begin
-                        op_src_cur    <= op_src_addr;
-                        op_dst_cur    <= op_dst_addr;
-                        op_bytes_left <= op_bytes;
-                        op_copy_store <= 1'b1;
-                        op_state      <= OP_COPY_START;
-                    end else if (op_start_write) begin
-                        op_copy_store <= 1'b0;
-                        op_state      <= OP_WRITE_ADDR;
-                    end else if (op_start_read) begin
-                        op_copy_store <= 1'b0;
-                        op_state      <= OP_REG_READ_ADDR;
+            case (ext_rd_state)
+                EXT_RD_IDLE: begin
+                    if (ext_rd_accept) begin
+                        ext_rd_addr_r      <= ext_rd_req_src;
+                        ext_rd_bytes_left  <= ext_rd_req_bytes;
+                        ext_rd_word_addr_r <= ext_rd_req_ep_word_off;
+                        ext_rd_ep_id_r     <= ext_rd_req_ep_id;
+                        ext_rd_ep_bank_r   <= ext_rd_req_ep_bank;
+                        ext_rd_state       <= EXT_RD_AR;
                     end
                 end
 
-                OP_READ_ADDR: begin
-                    if (seq_arvalid && seq_arready)
-                        op_state <= OP_READ_DATA;
+                EXT_RD_AR: begin
+                    if (mm2mm_arvalid && mm2mm_arready)
+                        ext_rd_state <= EXT_RD_READ;
                 end
 
-                OP_READ_DATA: begin
-                    if (mm2mm_rvalid && seq_rready) begin
-                        op_data_buf  <= mm2mm_rdata;
-                        op_buf_valid <= 1'b1;
-                        op_state     <= OP_WRITE_ADDR;
+                EXT_RD_READ: begin
+                    if (mm2mm_rvalid && mm2mm_rready) begin
+                        ext_rd_word_addr_r <= ext_rd_word_addr_r + 8'd1;
+                        ext_rd_bytes_left  <= (ext_rd_bytes_left > 32'd4) ? (ext_rd_bytes_left - 32'd4) : 32'd0;
+                        if (mm2mm_rlast)
+                            ext_rd_state <= EXT_RD_IDLE;
                     end
                 end
 
-                OP_WRITE_ADDR: begin
-                    if (seq_awvalid && seq_awready)
-                        op_state <= OP_WRITE_DATA;
-                end
-
-                OP_WRITE_DATA: begin
-                    if (seq_wvalid && seq_wready) begin
-                        op_buf_valid <= 1'b0;
-                        op_state     <= OP_WRITE_RESP;
-                    end
-                end
-
-                OP_WRITE_RESP: begin
-                    if (mm2mm_bvalid && seq_bready) begin
-                        if (op_copy_store && (op_bytes_left > 32'd4)) begin
-                            op_src_cur    <= op_src_cur + 32'd4;
-                            op_dst_cur    <= op_dst_cur + 32'd4;
-                            op_bytes_left <= op_bytes_left - 32'd4;
-                            op_state      <= OP_READ_ADDR;
-                        end else begin
-                            op_done  <= 1'b1;
-                            op_state <= OP_IDLE;
-                        end
-                    end
-                end
-
-                OP_REG_READ_ADDR: begin
-                    if (seq_arvalid && seq_arready)
-                        op_state <= OP_REG_READ_DATA;
-                end
-
-                OP_REG_READ_DATA: begin
-                    if (mm2mm_rvalid && seq_rready) begin
-                        op_read_data <= mm2mm_rdata;
-                        op_done      <= 1'b1;
-                        op_state     <= OP_IDLE;
-                    end
-                end
-
-                OP_COPY_START: begin
-                    op_state <= OP_COPY_WAIT;
-                end
-
-                OP_COPY_WAIT: begin
-                    if (mm2mm_done) begin
-                        op_done  <= 1'b1;
-                        op_state <= OP_IDLE;
-                    end
-                end
-
-                default: op_state <= OP_IDLE;
+                default: ext_rd_state <= EXT_RD_IDLE;
             endcase
         end
     end
 
     always_ff @(posedge clk) begin
         if (!rst_n) begin
-            seq_state        <= SQ_IDLE;
-            seq_busy         <= 1'b0;
-            seq_done_flag    <= 1'b0;
-            op_start_copy    <= 1'b0;
-            op_start_write   <= 1'b0;
-            op_start_read    <= 1'b0;
-            op_src_addr      <= '0;
-            op_dst_addr      <= '0;
-            op_bytes         <= '0;
-            op_write_addr    <= '0;
-            op_write_data    <= '0;
-            op_read_addr     <= '0;
-            seq_group_idx    <= '0;
-            seq_load_idx     <= '0;
-            seq_store_idx    <= '0;
-            seq_compute_bank <= 1'b0;
-            seq_status_data  <= '0;
+            ext_wr_state       <= EXT_WR_IDLE;
+            ext_wr_addr_r      <= '0;
+            ext_wr_bytes_left  <= '0;
+            ext_wr_word_addr_r <= '0;
+            ext_wr_ep_id_r     <= '0;
+            ext_wr_ep_bank_r   <= '0;
         end else begin
-            op_start_copy  <= 1'b0;
-            op_start_write <= 1'b0;
-            op_start_read  <= 1'b0;
-
-            if (seq_done_clear_req)
-                seq_done_flag <= 1'b0;
-
-            case (seq_state)
-                SQ_IDLE: begin
-                    seq_busy <= 1'b0;
-                    if (seq_start_req && (seq_groups != 32'd0)) begin
-                        seq_busy         <= 1'b1;
-                        seq_done_flag    <= 1'b0;
-                        seq_group_idx    <= 32'd0;
-                        seq_load_idx     <= 32'd0;
-                        seq_store_idx    <= 32'd0;
-                        seq_compute_bank <= 1'b0;
-                        op_write_addr    <= seq_mat_base + MAT_CRC_OFF;
-                        op_write_data    <= 32'd0;
-                        op_start_write   <= 1'b1;
-                        seq_state        <= SQ_CLEAR_CRC;
+            case (ext_wr_state)
+                EXT_WR_IDLE: begin
+                    if (ext_wr_accept) begin
+                        ext_wr_addr_r      <= ext_wr_req_dst;
+                        ext_wr_bytes_left  <= ext_wr_req_bytes;
+                        ext_wr_word_addr_r <= ext_wr_req_ep_word_off;
+                        ext_wr_ep_id_r     <= ext_wr_req_ep_id;
+                        ext_wr_ep_bank_r   <= ext_wr_req_ep_bank;
+                        ext_wr_state       <= EXT_WR_AW;
                     end
                 end
 
-                SQ_CLEAR_CRC: begin
-                    if (op_done) begin
-                        op_src_addr    <= seq_src_base;
-                        op_dst_addr    <= seq_mat_base + MAT_B0_AB_OFF;
-                        op_bytes       <= MAT_AB_BYTES;
-                        op_start_copy  <= 1'b1;
-                        seq_load_idx   <= 32'd1;
-                        seq_state      <= SQ_LOAD0;
+                EXT_WR_AW: begin
+                    if (mm2mm_awvalid && mm2mm_awready)
+                        ext_wr_state <= EXT_WR_WRITE;
+                end
+
+                EXT_WR_WRITE: begin
+                    if (ext_wr_w_fire) begin
+                        ext_wr_word_addr_r <= ext_wr_word_addr_r + 8'd1;
+                        ext_wr_bytes_left  <= (ext_wr_bytes_left > 32'd4) ? (ext_wr_bytes_left - 32'd4) : 32'd0;
+                        if (mm2mm_wlast)
+                            ext_wr_state <= EXT_WR_BRESP;
                     end
                 end
 
-                SQ_LOAD0: begin
-                    if (op_done) begin
-                        op_write_addr  <= seq_mat_base + MAT_CTRL_OFF;
-                        op_write_data  <= MAT_CTRL_START_B0;
-                        op_start_write <= 1'b1;
-                        seq_state      <= SQ_START0;
-                    end
+                EXT_WR_BRESP: begin
+                    if (mm2mm_bvalid && mm2mm_bready)
+                        ext_wr_state <= EXT_WR_IDLE;
                 end
 
-                SQ_START0: begin
-                    if (op_done) begin
-                        if (seq_load_idx < seq_groups) begin
-                            op_src_addr    <= seq_src_base + (seq_load_idx * seq_src_stride);
-                            op_dst_addr    <= seq_mat_base + MAT_B1_AB_OFF;
-                            op_bytes       <= MAT_AB_BYTES;
-                            op_start_copy  <= 1'b1;
-                            seq_load_idx   <= seq_load_idx + 32'd1;
-                            seq_state      <= SQ_LOAD1;
-                        end else begin
-                            op_read_addr   <= seq_mat_base + MAT_STATUS_OFF;
-                            op_start_read  <= 1'b1;
-                            seq_state      <= SQ_WAIT_DONE;
-                        end
-                    end
-                end
-
-                SQ_LOAD1: begin
-                    if (op_done) begin
-                        op_write_addr  <= seq_mat_base + MAT_CTRL_OFF;
-                        op_write_data  <= seq_start_value_for_loaded_bank;
-                        op_start_write <= 1'b1;
-                        seq_state      <= SQ_START_NEXT;
-                    end
-                end
-
-                SQ_WAIT_DONE: begin
-                    if (op_done) begin
-                        seq_status_data <= op_read_data;
-                        if ((op_read_data & MAT_STATUS_DONE_BIT) != 32'd0) begin
-                            seq_store_idx <= seq_group_idx;
-                            if ((seq_group_idx + 32'd1) >= seq_groups) begin
-                                op_src_addr   <= seq_mat_base + (seq_compute_bank ? MAT_B1_C_OFF : MAT_B0_C_OFF);
-                                op_dst_addr   <= seq_dst_base + (seq_group_idx * seq_dst_stride);
-                                op_bytes      <= MAT_C_BYTES;
-                                op_start_copy <= 1'b1;
-                                seq_state     <= SQ_STORE;
-                            end else begin
-                                op_write_addr  <= seq_mat_base + MAT_STATUS_OFF;
-                                op_write_data  <= MAT_STATUS_DONE_CLR;
-                                op_start_write <= 1'b1;
-                                seq_state      <= SQ_CLEAR_DONE;
-                            end
-                        end else begin
-                            op_read_addr   <= seq_mat_base + MAT_STATUS_OFF;
-                            op_start_read  <= 1'b1;
-                        end
-                    end
-                end
-
-                SQ_STORE: begin
-                    if (op_done) begin
-                        if ((seq_store_idx + 32'd1) >= seq_groups) begin
-                            seq_state <= SQ_DONE;
-                        end else if (seq_has_more_load) begin
-                            op_src_addr    <= seq_src_addr_for_load;
-                            op_dst_addr    <= seq_dst_addr_for_load;
-                            op_bytes       <= MAT_AB_BYTES;
-                            op_start_copy  <= 1'b1;
-                            seq_load_idx   <= seq_load_idx + 32'd1;
-                            seq_state      <= SQ_LOAD_NEXT;
-                        end else begin
-                            op_read_addr   <= seq_mat_base + MAT_STATUS_OFF;
-                            op_start_read  <= 1'b1;
-                            seq_state      <= SQ_WAIT_DONE;
-                        end
-                    end
-                end
-
-                SQ_CLEAR_DONE: begin
-                    if (op_done) begin
-                        seq_group_idx    <= seq_group_idx + 32'd1;
-                        seq_compute_bank <= ~seq_compute_bank;
-                        op_src_addr      <= seq_src_addr_for_store;
-                        op_dst_addr      <= seq_dst_addr_for_store;
-                        op_bytes         <= MAT_C_BYTES;
-                        op_start_copy    <= 1'b1;
-                        seq_state        <= SQ_STORE;
-                    end
-                end
-
-                SQ_START_NEXT: begin
-                    if (op_done) begin
-                        op_read_addr  <= seq_mat_base + MAT_STATUS_OFF;
-                        op_start_read <= 1'b1;
-                        seq_state     <= SQ_WAIT_DONE;
-                    end
-                end
-
-                SQ_LOAD_NEXT: begin
-                    if (op_done) begin
-                        op_write_addr  <= seq_mat_base + MAT_CTRL_OFF;
-                        op_write_data  <= seq_start_value_for_loaded_bank;
-                        op_start_write <= 1'b1;
-                        seq_state      <= SQ_START_NEXT;
-                    end
-                end
-
-                SQ_DONE: begin
-                    seq_busy      <= 1'b0;
-                    seq_done_flag <= 1'b1;
-                    seq_state     <= SQ_IDLE;
-                end
-
-                default: seq_state <= SQ_IDLE;
+                default: ext_wr_state <= EXT_WR_IDLE;
             endcase
         end
     end
@@ -1020,17 +690,6 @@ module snix_axil_cdma_mux #(
     // ==========================================
     // Endpoint transfer engine (32-bit only in this SoC integration)
     // ==========================================
-    typedef enum logic [2:0] {EP_IDLE, EP_AR, EP_READ, EP_AW, EP_WRITE, EP_BRESP, EP_DONE} ep_state_t;
-    ep_state_t ep_state;
-    logic [31:0] ep_axi_addr;
-    logic [31:0] ep_bytes_left;
-    logic [7:0]  ep_word_addr_r;
-
-    wire [7:0] ep_beats_total = (engine_bytes[31:2] == 30'd0) ? 8'd1 : engine_bytes[9:2];
-    wire [7:0] ep_axi_len     = ep_beats_total - 8'd1;
-    wire       ep_mode_mem2ep = (engine_mode == MODE_MEM2EP);
-    wire       ep_mode_ep2mem = (engine_mode == MODE_EP2MEM);
-
     always_ff @(posedge clk) begin
         if (!rst_n) begin
             ep_state       <= EP_IDLE;
@@ -1060,8 +719,10 @@ module snix_axil_cdma_mux #(
                     if (mm2mm_rvalid && ep_rready) begin
                         ep_word_addr_r <= ep_word_addr_r + 8'd1;
                         ep_bytes_left  <= (ep_bytes_left > 32'd4) ? (ep_bytes_left - 32'd4) : 32'd0;
-                        if (mm2mm_rlast)
-                            ep_state <= EP_DONE;
+                        if (mm2mm_rlast) begin
+                            ep_done  <= 1'b1;
+                            ep_state <= EP_IDLE;
+                        end
                     end
                 end
 
@@ -1080,8 +741,10 @@ module snix_axil_cdma_mux #(
                 end
 
                 EP_BRESP: begin
-                    if (mm2mm_bvalid && ep_bready)
-                        ep_state <= EP_DONE;
+                    if (mm2mm_bvalid && ep_bready) begin
+                        ep_done  <= 1'b1;
+                        ep_state <= EP_IDLE;
+                    end
                 end
 
                 EP_DONE: begin
@@ -1107,10 +770,11 @@ module snix_axil_cdma_mux #(
     assign ep_arvalid = (ep_state == EP_AR);
     assign ep_rready  = (ep_state == EP_READ) && ep_wr_ready;
 
-    assign ep_wr_valid     = (ep_state == EP_READ) && mm2mm_rvalid && ep_mode_mem2ep;
-    assign ep_wr_id        = engine_ep_id;
-    assign ep_wr_bank      = engine_ep_bank;
-    assign ep_wr_word_addr = ep_word_addr_r;
+    assign ep_wr_valid     = ext_rd_active ? ((ext_rd_state == EXT_RD_READ) && mm2mm_rvalid) :
+                                              ((ep_state == EP_READ) && mm2mm_rvalid && ep_mode_mem2ep);
+    assign ep_wr_id        = ext_rd_active ? ext_rd_ep_id_r       : engine_ep_id;
+    assign ep_wr_bank      = ext_rd_active ? ext_rd_ep_bank_r     : engine_ep_bank;
+    assign ep_wr_word_addr = ext_rd_active ? ext_rd_word_addr_r   : ep_word_addr_r;
     assign ep_wr_data      = mm2mm_rdata[31:0];
 
     assign ep_awid    = '0;
@@ -1131,9 +795,10 @@ module snix_axil_cdma_mux #(
     assign ep_wvalid  = (ep_state == EP_WRITE) && ep_mode_ep2mem && ep_rd_ready;
     assign ep_bready  = (ep_state == EP_BRESP);
 
-    assign ep_rd_valid     = (ep_state == EP_WRITE) && ep_mode_ep2mem && ep_wready;
-    assign ep_rd_id        = engine_ep_id;
-    assign ep_rd_bank      = engine_ep_bank;
-    assign ep_rd_word_addr = ep_word_addr_r;
+    assign ep_rd_valid     = ext_wr_active ? ((ext_wr_state == EXT_WR_WRITE) && mm2mm_wready) :
+                                              ((ep_state == EP_WRITE) && ep_mode_ep2mem && ep_wready);
+    assign ep_rd_id        = ext_wr_active ? ext_wr_ep_id_r       : engine_ep_id;
+    assign ep_rd_bank      = ext_wr_active ? ext_wr_ep_bank_r     : engine_ep_bank;
+    assign ep_rd_word_addr = ext_wr_active ? ext_wr_word_addr_r   : ep_word_addr_r;
 
 endmodule

rtl/ip/fft/Butterfly.v

@@ -0,0 +1,32 @@
+//----------------------------------------------------------------------
+//  Butterfly: Add/Sub and Scaling
+//----------------------------------------------------------------------
+module Butterfly #(
+    parameter   WIDTH = 16,
+    parameter   RH = 0  //  Round Half Up
+)(
+    input   signed  [WIDTH-1:0] x0_re,  //  Input Data #0 (Real)
+    input   signed  [WIDTH-1:0] x0_im,  //  Input Data #0 (Imag)
+    input   signed  [WIDTH-1:0] x1_re,  //  Input Data #1 (Real)
+    input   signed  [WIDTH-1:0] x1_im,  //  Input Data #1 (Imag)
+    output  signed  [WIDTH-1:0] y0_re,  //  Output Data #0 (Real)
+    output  signed  [WIDTH-1:0] y0_im,  //  Output Data #0 (Imag)
+    output  signed  [WIDTH-1:0] y1_re,  //  Output Data #1 (Real)
+    output  signed  [WIDTH-1:0] y1_im   //  Output Data #1 (Imag)
+);
+
+wire signed [WIDTH:0]   add_re, add_im, sub_re, sub_im;
+
+//  Add/Sub
+assign  add_re = x0_re + x1_re;
+assign  add_im = x0_im + x1_im;
+assign  sub_re = x0_re - x1_re;
+assign  sub_im = x0_im - x1_im;
+
+//  Scaling
+assign  y0_re = (add_re + RH) >>> 1;
+assign  y0_im = (add_im + RH) >>> 1;
+assign  y1_re = (sub_re + RH) >>> 1;
+assign  y1_im = (sub_im + RH) >>> 1;
+
+endmodule

rtl/ip/fft/DelayBuffer.v

@@ -0,0 +1,34 @@
+//----------------------------------------------------------------------
+//  DelayBuffer: Generate Constant Delay
+//----------------------------------------------------------------------
+module DelayBuffer #(
+    parameter   DEPTH = 32,
+    parameter   WIDTH = 16
+)(
+    input               clock,  //  Master Clock
+    input   [WIDTH-1:0] di_re,  //  Data Input (Real)
+    input   [WIDTH-1:0] di_im,  //  Data Input (Imag)
+    output  [WIDTH-1:0] do_re,  //  Data Output (Real)
+    output  [WIDTH-1:0] do_im   //  Data Output (Imag)
+);
+
+reg [WIDTH-1:0] buf_re[0:DEPTH-1];
+reg [WIDTH-1:0] buf_im[0:DEPTH-1];
+integer n;
+
+//  Shift Buffer
+/* verilator lint_off BLKLOOPINIT */
+always @(posedge clock) begin
+    for (n = DEPTH-1; n > 0; n = n - 1) begin
+        buf_re[n] <= buf_re[n-1];
+        buf_im[n] <= buf_im[n-1];
+    end
+    buf_re[0] <= di_re;
+    buf_im[0] <= di_im;
+end
+/* verilator lint_on BLKLOOPINIT */
+
+assign  do_re = buf_re[DEPTH-1];
+assign  do_im = buf_im[DEPTH-1];
+
+endmodule

rtl/ip/fft/FFT1024_32B.v

@@ -0,0 +1,90 @@
+//----------------------------------------------------------------------
+//  FFT: 1024-Point FFT Using Radix-2^2 Single-Path Delay Feedback
+//----------------------------------------------------------------------
+
+module FFT #(
+    parameter   WIDTH = 32
+)(
+    input               clock,  //  Master Clock
+    input               reset,  //  Active High Asynchronous Reset
+    input               di_en,  //  Input Data Enable
+    input   [WIDTH-1:0] di_re,  //  Input Data (Real)
+    input   [WIDTH-1:0] di_im,  //  Input Data (Imag)
+    output              do_en,  //  Output Data Enable
+    output  [WIDTH-1:0] do_re,  //  Output Data (Real)
+    output  [WIDTH-1:0] do_im   //  Output Data (Imag)
+);
+//----------------------------------------------------------------------
+//  Data must be input consecutively in natural order.
+//  The result is scaled to 1/N and output in bit-reversed order.
+//----------------------------------------------------------------------
+
+wire            su1_do_en;
+wire[WIDTH-1:0] su1_do_re;
+wire[WIDTH-1:0] su1_do_im;
+wire            su2_do_en;
+wire[WIDTH-1:0] su2_do_re;
+wire[WIDTH-1:0] su2_do_im;
+wire            su3_do_en;
+wire[WIDTH-1:0] su3_do_re;
+wire[WIDTH-1:0] su3_do_im;
+wire            su4_do_en;
+wire[WIDTH-1:0] su4_do_re;
+wire[WIDTH-1:0] su4_do_im;
+
+SdfUnit #(.N(1024),.M(1024),.WIDTH(WIDTH)) SU1 (
+    .clock  (clock      ),  //  i
+    .reset  (reset      ),  //  i
+    .di_en  (di_en      ),  //  i
+    .di_re  (di_re      ),  //  i
+    .di_im  (di_im      ),  //  i
+    .do_en  (su1_do_en  ),  //  o
+    .do_re  (su1_do_re  ),  //  o
+    .do_im  (su1_do_im  )   //  o
+);
+
+SdfUnit #(.N(1024),.M(256),.WIDTH(WIDTH)) SU2 (
+    .clock  (clock      ),  //  i
+    .reset  (reset      ),  //  i
+    .di_en  (su1_do_en  ),  //  i
+    .di_re  (su1_do_re  ),  //  i
+    .di_im  (su1_do_im  ),  //  i
+    .do_en  (su2_do_en  ),  //  o
+    .do_re  (su2_do_re  ),  //  o
+    .do_im  (su2_do_im  )   //  o
+);
+
+SdfUnit #(.N(1024),.M(64),.WIDTH(WIDTH)) SU3 (
+    .clock  (clock      ),  //  i
+    .reset  (reset      ),  //  i
+    .di_en  (su2_do_en  ),  //  i
+    .di_re  (su2_do_re  ),  //  i
+    .di_im  (su2_do_im  ),  //  i
+    .do_en  (su3_do_en  ),  //  o
+    .do_re  (su3_do_re  ),  //  o
+    .do_im  (su3_do_im  )   //  o
+);
+
+SdfUnit #(.N(1024),.M(16),.WIDTH(WIDTH)) SU4 (
+    .clock  (clock      ),  //  i
+    .reset  (reset      ),  //  i
+    .di_en  (su3_do_en  ),  //  i
+    .di_re  (su3_do_re  ),  //  i
+    .di_im  (su3_do_im  ),  //  i
+    .do_en  (su4_do_en  ),  //  o
+    .do_re  (su4_do_re  ),  //  o
+    .do_im  (su4_do_im  )   //  o
+);
+
+SdfUnit #(.N(1024),.M(4),.WIDTH(WIDTH)) SU5 (
+    .clock  (clock      ),  //  i
+    .reset  (reset      ),  //  i
+    .di_en  (su4_do_en  ),  //  i
+    .di_re  (su4_do_re  ),  //  i
+    .di_im  (su4_do_im  ),  //  i
+    .do_en  (do_en      ),  //  o
+    .do_re  (do_re      ),  //  o
+    .do_im  (do_im      )   //  o
+);
+
+endmodule

rtl/ip/fft/Multiply.v

@@ -0,0 +1,36 @@
+//----------------------------------------------------------------------
+//  Multiply: Complex Multiplier
+//----------------------------------------------------------------------
+
+(* use_dsp = "no" *) module Multiply #(
+    parameter   WIDTH = 16
+)(
+    input   signed  [WIDTH-1:0] a_re,
+    input   signed  [WIDTH-1:0] a_im,
+    input   signed  [WIDTH-1:0] b_re,
+    input   signed  [WIDTH-1:0] b_im,
+    output  signed  [WIDTH-1:0] m_re,
+    output  signed  [WIDTH-1:0] m_im
+);
+
+ wire signed [WIDTH*2-1:0]   arbr, arbi, aibr, aibi;
+wire signed [WIDTH-1:0]     sc_arbr, sc_arbi, sc_aibr, sc_aibi;
+
+//  Signed Multiplication
+assign  arbr = a_re * b_re;
+assign  arbi = a_re * b_im;
+assign  aibr = a_im * b_re;
+assign  aibi = a_im * b_im;
+
+//  Scaling
+assign  sc_arbr = arbr >>> (WIDTH-1);
+assign  sc_arbi = arbi >>> (WIDTH-1);
+assign  sc_aibr = aibr >>> (WIDTH-1);
+assign  sc_aibi = aibi >>> (WIDTH-1);
+
+//  Sub/Add
+//  These sub/add may overflow if unnormalized data is input.
+assign  m_re = sc_arbr - sc_aibi;
+assign  m_im = sc_arbi + sc_aibr;
+
+endmodule

rtl/ip/fft/SdfUnit.v

@@ -0,0 +1,280 @@
+//----------------------------------------------------------------------
+//  SdfUnit: Radix-2^2 Single-Path Delay Feedback Unit for N-Point FFT
+//----------------------------------------------------------------------
+
+module SdfUnit #(
+    parameter   N = 64,     //  Number of FFT Point
+    parameter   M = 64,     //  Twiddle Resolution
+    parameter   WIDTH = 16  //  Data Bit Length
+)(
+    input               clock,  //  Master Clock
+    input               reset,  //  Active High Asynchronous Reset
+    input               di_en,  //  Input Data Enable
+    input   [WIDTH-1:0] di_re,  //  Input Data (Real)
+    input   [WIDTH-1:0] di_im,  //  Input Data (Imag)
+    output              do_en,  //  Output Data Enable
+    output  [WIDTH-1:0] do_re,  //  Output Data (Real)
+    output  [WIDTH-1:0] do_im   //  Output Data (Imag)
+);
+
+//  log2 constant function
+function integer log2;
+    input integer x;
+    integer value;
+    begin
+        value = x-1;
+        for (log2=0; value>0; log2=log2+1)
+            value = value>>1;
+    end
+endfunction
+
+localparam  LOG_N = log2(N);    //  Bit Length of N
+localparam  LOG_M = log2(M);    //  Bit Length of M
+
+//----------------------------------------------------------------------
+//  Internal Regs and Nets
+//----------------------------------------------------------------------
+//  1st Butterfly
+reg [LOG_N-1:0] di_count;   //  Input Data Count
+wire            bf1_bf;     //  Butterfly Add/Sub Enable
+wire[WIDTH-1:0] bf1_x0_re;  //  Data #0 to Butterfly (Real)
+wire[WIDTH-1:0] bf1_x0_im;  //  Data #0 to Butterfly (Imag)
+wire[WIDTH-1:0] bf1_x1_re;  //  Data #1 to Butterfly (Real)
+wire[WIDTH-1:0] bf1_x1_im;  //  Data #1 to Butterfly (Imag)
+wire[WIDTH-1:0] bf1_y0_re;  //  Data #0 from Butterfly (Real)
+wire[WIDTH-1:0] bf1_y0_im;  //  Data #0 from Butterfly (Imag)
+wire[WIDTH-1:0] bf1_y1_re;  //  Data #1 from Butterfly (Real)
+wire[WIDTH-1:0] bf1_y1_im;  //  Data #1 from Butterfly (Imag)
+wire[WIDTH-1:0] db1_di_re;  //  Data to DelayBuffer (Real)
+wire[WIDTH-1:0] db1_di_im;  //  Data to DelayBuffer (Imag)
+wire[WIDTH-1:0] db1_do_re;  //  Data from DelayBuffer (Real)
+wire[WIDTH-1:0] db1_do_im;  //  Data from DelayBuffer (Imag)
+wire[WIDTH-1:0] bf1_sp_re;  //  Single-Path Data Output (Real)
+wire[WIDTH-1:0] bf1_sp_im;  //  Single-Path Data Output (Imag)
+reg             bf1_sp_en;  //  Single-Path Data Enable
+reg [LOG_N-1:0] bf1_count;  //  Single-Path Data Count
+wire            bf1_start;  //  Single-Path Output Trigger
+wire            bf1_end;    //  End of Single-Path Data
+wire            bf1_mj;     //  Twiddle (-j) Enable
+reg [WIDTH-1:0] bf1_do_re;  //  1st Butterfly Output Data (Real)
+reg [WIDTH-1:0] bf1_do_im;  //  1st Butterfly Output Data (Imag)
+
+//  2nd Butterfly
+reg             bf2_bf;     //  Butterfly Add/Sub Enable
+wire[WIDTH-1:0] bf2_x0_re;  //  Data #0 to Butterfly (Real)
+wire[WIDTH-1:0] bf2_x0_im;  //  Data #0 to Butterfly (Imag)
+wire[WIDTH-1:0] bf2_x1_re;  //  Data #1 to Butterfly (Real)
+wire[WIDTH-1:0] bf2_x1_im;  //  Data #1 to Butterfly (Imag)
+wire[WIDTH-1:0] bf2_y0_re;  //  Data #0 from Butterfly (Real)
+wire[WIDTH-1:0] bf2_y0_im;  //  Data #0 from Butterfly (Imag)
+wire[WIDTH-1:0] bf2_y1_re;  //  Data #1 from Butterfly (Real)
+wire[WIDTH-1:0] bf2_y1_im;  //  Data #1 from Butterfly (Imag)
+wire[WIDTH-1:0] db2_di_re;  //  Data to DelayBuffer (Real)
+wire[WIDTH-1:0] db2_di_im;  //  Data to DelayBuffer (Imag)
+wire[WIDTH-1:0] db2_do_re;  //  Data from DelayBuffer (Real)
+wire[WIDTH-1:0] db2_do_im;  //  Data from DelayBuffer (Imag)
+wire[WIDTH-1:0] bf2_sp_re;  //  Single-Path Data Output (Real)
+wire[WIDTH-1:0] bf2_sp_im;  //  Single-Path Data Output (Imag)
+reg             bf2_sp_en;  //  Single-Path Data Enable
+reg [LOG_N-1:0] bf2_count;  //  Single-Path Data Count
+reg             bf2_start;  //  Single-Path Output Trigger
+wire            bf2_end;    //  End of Single-Path Data
+reg [WIDTH-1:0] bf2_do_re;  //  2nd Butterfly Output Data (Real)
+reg [WIDTH-1:0] bf2_do_im;  //  2nd Butterfly Output Data (Imag)
+reg             bf2_do_en;  //  2nd Butterfly Output Data Enable
+
+//  Multiplication
+wire[1:0]       tw_sel;     //  Twiddle Select (2n/n/3n)
+wire[LOG_N-3:0] tw_num;     //  Twiddle Number (n)
+ wire[LOG_N-1:0] tw_addr;    //  Twiddle Table Address
+wire[WIDTH-1:0] tw_re;      //  Twiddle Factor (Real)
+wire[WIDTH-1:0] tw_im;      //  Twiddle Factor (Imag)
+reg             mu_en;      //  Multiplication Enable
+wire[WIDTH-1:0] mu_a_re;    //  Multiplier Input (Real)
+wire[WIDTH-1:0] mu_a_im;    //  Multiplier Input (Imag)
+wire[WIDTH-1:0] mu_m_re;    //  Multiplier Output (Real)
+wire[WIDTH-1:0] mu_m_im;    //  Multiplier Output (Imag)
+reg [WIDTH-1:0] mu_do_re;   //  Multiplication Output Data (Real)
+reg [WIDTH-1:0] mu_do_im;   //  Multiplication Output Data (Imag)
+reg             mu_do_en;   //  Multiplication Output Data Enable
+
+//----------------------------------------------------------------------
+//  1st Butterfly
+//----------------------------------------------------------------------
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        di_count <= {LOG_N{1'b0}};
+    end else begin
+        di_count <= di_en ? (di_count + 1'b1) : {LOG_N{1'b0}};
+    end
+end
+assign  bf1_bf = di_count[LOG_M-1];
+
+//  Set unknown value x for verification
+assign  bf1_x0_re = bf1_bf ? db1_do_re : {WIDTH{1'bx}};
+assign  bf1_x0_im = bf1_bf ? db1_do_im : {WIDTH{1'bx}};
+assign  bf1_x1_re = bf1_bf ? di_re : {WIDTH{1'bx}};
+assign  bf1_x1_im = bf1_bf ? di_im : {WIDTH{1'bx}};
+
+Butterfly #(.WIDTH(WIDTH),.RH(0)) BF1 (
+    .x0_re  (bf1_x0_re  ),  //  i
+    .x0_im  (bf1_x0_im  ),  //  i
+    .x1_re  (bf1_x1_re  ),  //  i
+    .x1_im  (bf1_x1_im  ),  //  i
+    .y0_re  (bf1_y0_re  ),  //  o
+    .y0_im  (bf1_y0_im  ),  //  o
+    .y1_re  (bf1_y1_re  ),  //  o
+    .y1_im  (bf1_y1_im  )   //  o
+);
+
+DelayBuffer #(.DEPTH(2**(LOG_M-1)),.WIDTH(WIDTH)) DB1 (
+    .clock  (clock      ),  //  i
+    .di_re  (db1_di_re  ),  //  i
+    .di_im  (db1_di_im  ),  //  i
+    .do_re  (db1_do_re  ),  //  o
+    .do_im  (db1_do_im  )   //  o
+);
+
+assign  db1_di_re = bf1_bf ? bf1_y1_re : di_re;
+assign  db1_di_im = bf1_bf ? bf1_y1_im : di_im;
+assign  bf1_sp_re = bf1_bf ? bf1_y0_re : bf1_mj ?  db1_do_im : db1_do_re;
+assign  bf1_sp_im = bf1_bf ? bf1_y0_im : bf1_mj ? -db1_do_re : db1_do_im;
+
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        bf1_sp_en <= 1'b0;
+        bf1_count <= {LOG_N{1'b0}};
+    end else begin
+        bf1_sp_en <= bf1_start ? 1'b1 : bf1_end ? 1'b0 : bf1_sp_en;
+        bf1_count <= bf1_sp_en ? (bf1_count + 1'b1) : {LOG_N{1'b0}};
+    end
+end
+assign  bf1_start = (di_count == (2**(LOG_M-1)-1));
+assign  bf1_end = (bf1_count == (2**LOG_N-1));
+assign  bf1_mj = (bf1_count[LOG_M-1:LOG_M-2] == 2'd3);
+
+always @(posedge clock) begin
+    bf1_do_re <= bf1_sp_re;
+    bf1_do_im <= bf1_sp_im;
+end
+
+//----------------------------------------------------------------------
+//  2nd Butterfly
+//----------------------------------------------------------------------
+always @(posedge clock) begin
+    bf2_bf <= bf1_count[LOG_M-2];
+end
+
+//  Set unknown value x for verification
+assign  bf2_x0_re = bf2_bf ? db2_do_re : {WIDTH{1'bx}};
+assign  bf2_x0_im = bf2_bf ? db2_do_im : {WIDTH{1'bx}};
+assign  bf2_x1_re = bf2_bf ? bf1_do_re : {WIDTH{1'bx}};
+assign  bf2_x1_im = bf2_bf ? bf1_do_im : {WIDTH{1'bx}};
+
+//  Negative bias occurs when RH=0 and positive bias occurs when RH=1.
+//  Using both alternately reduces the overall rounding error.
+Butterfly #(.WIDTH(WIDTH),.RH(1)) BF2 (
+    .x0_re  (bf2_x0_re  ),  //  i
+    .x0_im  (bf2_x0_im  ),  //  i
+    .x1_re  (bf2_x1_re  ),  //  i
+    .x1_im  (bf2_x1_im  ),  //  i
+    .y0_re  (bf2_y0_re  ),  //  o
+    .y0_im  (bf2_y0_im  ),  //  o
+    .y1_re  (bf2_y1_re  ),  //  o
+    .y1_im  (bf2_y1_im  )   //  o
+);
+
+DelayBuffer #(.DEPTH(2**(LOG_M-2)),.WIDTH(WIDTH)) DB2 (
+    .clock  (clock      ),  //  i
+    .di_re  (db2_di_re  ),  //  i
+    .di_im  (db2_di_im  ),  //  i
+    .do_re  (db2_do_re  ),  //  o
+    .do_im  (db2_do_im  )   //  o
+);
+
+assign  db2_di_re = bf2_bf ? bf2_y1_re : bf1_do_re;
+assign  db2_di_im = bf2_bf ? bf2_y1_im : bf1_do_im;
+assign  bf2_sp_re = bf2_bf ? bf2_y0_re : db2_do_re;
+assign  bf2_sp_im = bf2_bf ? bf2_y0_im : db2_do_im;
+
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        bf2_sp_en <= 1'b0;
+        bf2_count <= {LOG_N{1'b0}};
+    end else begin
+        bf2_sp_en <= bf2_start ? 1'b1 : bf2_end ? 1'b0 : bf2_sp_en;
+        bf2_count <= bf2_sp_en ? (bf2_count + 1'b1) : {LOG_N{1'b0}};
+    end
+end
+
+always @(posedge clock) begin
+    bf2_start <= (bf1_count == (2**(LOG_M-2)-1)) & bf1_sp_en;
+end
+assign  bf2_end = (bf2_count == (2**LOG_N-1));
+
+always @(posedge clock) begin
+    bf2_do_re <= bf2_sp_re;
+    bf2_do_im <= bf2_sp_im;
+end
+
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        bf2_do_en <= 1'b0;
+    end else begin
+        bf2_do_en <= bf2_sp_en;
+    end
+end
+
+//----------------------------------------------------------------------
+//  Multiplication
+//----------------------------------------------------------------------
+assign  tw_sel[1] = bf2_count[LOG_M-2];
+assign  tw_sel[0] = bf2_count[LOG_M-1];
+assign  tw_num = bf2_count << (LOG_N-LOG_M);
+assign  tw_addr = tw_num * tw_sel;
+
+Twiddle #(
+    .WIDTH  (WIDTH)
+) TW (
+    .clock  (clock  ),  //  i
+    .addr   (tw_addr),  //  i
+    .tw_re  (tw_re  ),  //  o
+    .tw_im  (tw_im  )   //  o
+);
+
+//  Multiplication is bypassed when twiddle address is 0.
+always @(posedge clock) begin
+    mu_en <= (tw_addr != {LOG_N{1'b0}});
+end
+//  Set unknown value x for verification
+assign  mu_a_re = mu_en ? bf2_do_re : {WIDTH{1'bx}};
+assign  mu_a_im = mu_en ? bf2_do_im : {WIDTH{1'bx}};
+
+Multiply #(.WIDTH(WIDTH)) MU (
+    .a_re   (mu_a_re),  //  i
+    .a_im   (mu_a_im),  //  i
+    .b_re   (tw_re  ),  //  i
+    .b_im   (tw_im  ),  //  i
+    .m_re   (mu_m_re),  //  o
+    .m_im   (mu_m_im)   //  o
+);
+
+always @(posedge clock) begin
+    mu_do_re <= mu_en ? mu_m_re : bf2_do_re;
+    mu_do_im <= mu_en ? mu_m_im : bf2_do_im;
+end
+
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        mu_do_en <= 1'b0;
+    end else begin
+        mu_do_en <= bf2_do_en;
+    end
+end
+
+//  No multiplication required at final stage
+assign  do_en = (LOG_M == 2) ? bf2_do_en : mu_do_en;
+assign  do_re = (LOG_M == 2) ? bf2_do_re : mu_do_re;
+assign  do_im = (LOG_M == 2) ? bf2_do_im : mu_do_im;
+
+endmodule

rtl/ip/fft/axi_fft_wrapper.v

@@ -0,0 +1,399 @@
+`define FFT_CSR_ADDR    16'hc000
+`define FFT_IN_RE_BASE  16'h8000
+`define FFT_IN_IM_BASE  16'h9000
+`define FFT_OUT_RE_BASE 16'ha000
+`define FFT_OUT_IM_BASE 16'hb000
+
+
+module fft_controller #(
+    parameter FFT_LEN         = 1024, // FFT处理长度
+    parameter BRAM_RD_LATENCY = 1,    // 适配 BRAM 的读延迟 (通常 Block RAM 开启输出寄存器为 1)
+    parameter FFT_DATA_WIDTH  = 16
+)(
+    input               aclk,
+    input               aresetn,
+
+    // AXI Lite / AXI4 Wrapper ports
+    input  [4 :0]       s_awid,
+    input  [31:0]       s_awaddr,
+    input  [7 :0]       s_awlen,
+    input  [2 :0]       s_awsize,
+    input  [1 :0]       s_awburst,
+    input               s_awlock,
+    input  [3 :0]       s_awcache,
+    input  [2 :0]       s_awprot,
+    input               s_awvalid,
+    output reg          s_awready,
+    input  [4 :0]       s_wid,
+    input  [31:0]       s_wdata,
+    input  [3 :0]       s_wstrb,
+    input               s_wlast,
+    input               s_wvalid,
+    output reg          s_wready,
+    output [4 :0]       s_bid,
+    output [1 :0]       s_bresp,
+    output reg          s_bvalid,
+    input               s_bready,
+    
+    input  [4 :0]       s_arid,
+    input  [31:0]       s_araddr,
+    input  [7 :0]       s_arlen,
+    input  [2 :0]       s_arsize,
+    input  [1 :0]       s_arburst,
+    input               s_arlock,
+    input  [3 :0]       s_arcache,
+    input  [2 :0]       s_arprot,
+    input               s_arvalid,
+    output reg          s_arready,
+    output [4 :0]       s_rid,
+    output reg [31:0]   s_rdata,
+    output [1 :0]       s_rresp,
+    output reg          s_rlast,
+    output reg          s_rvalid,
+    input               s_rready,
+
+    output              fft_finish
+);
+
+    // AXI Burst 内部寄存器
+    reg [31:0] aw_addr_reg;
+    reg [1 :0] aw_burst_reg;
+    reg [4 :0] aw_id_reg;
+
+    reg [31:0] ar_addr_reg;
+    reg [7 :0] ar_len_reg;
+    reg [1 :0] ar_burst_reg;
+    reg [4 :0] ar_id_reg;
+    reg [7 :0] ar_cnt;
+
+    // 写通道状态机 (AW, W, B)
+    localparam W_IDLE = 2'd0;
+    localparam W_DATA = 2'd1;
+    localparam W_RESP = 2'd2;
+    reg [1:0] w_state;
+
+    always @(posedge aclk) begin
+        if (~aresetn) begin
+            w_state      <= W_IDLE;
+            s_awready    <= 1'b1;
+            s_wready     <= 1'b0;
+            s_bvalid     <= 1'b0;
+            aw_addr_reg  <= 32'h0;
+            aw_burst_reg <= 2'h0;
+            aw_id_reg    <= 5'h0;
+        end else begin
+            case (w_state)
+                W_IDLE: begin
+                    s_awready <= 1'b1;
+                    if (s_awvalid && s_awready) begin
+                        s_awready    <= 1'b0;
+                        s_wready     <= 1'b1;
+                        aw_addr_reg  <= s_awaddr;
+                        aw_burst_reg <= s_awburst;
+                        aw_id_reg    <= s_awid;
+                        w_state      <= W_DATA;
+                    end
+                end
+                W_DATA: begin
+                    // 接收到有效写数据
+                    if (s_wvalid && s_wready) begin
+                        // INCR 模式下地址递增
+                        if (aw_burst_reg == 2'b01) begin 
+                            aw_addr_reg <= aw_addr_reg + 4;
+                        end
+                        // 若是最后一拍，跳转到发送响应
+                        if (s_wlast) begin
+                            s_wready <= 1'b0;
+                            s_bvalid <= 1'b1;
+                            w_state  <= W_RESP;
+                        end
+                    end
+                end
+                W_RESP: begin
+                    if (s_bvalid && s_bready) begin
+                        s_bvalid  <= 1'b0;
+                        s_awready <= 1'b1; // 准备接收下一次写请求
+                        w_state   <= W_IDLE;
+                    end
+                end
+                default: w_state <= W_IDLE;
+            endcase
+        end
+    end
+
+    // 产生有效的写动作脉冲，用于触发 BRAM 写使能
+    wire w_active = (w_state == W_DATA) && s_wvalid && s_wready;
+    assign s_bid  = aw_id_reg;
+    assign s_bresp = 2'b00;
+
+    // 读通道状态机(AR, R)
+    localparam R_IDLE = 2'd0;
+    localparam R_WAIT = 2'd1;
+    localparam R_DATA = 2'd2;
+    reg [1:0] r_state;
+    reg [3:0] r_wait_cnt; 
+
+    always @(posedge aclk) begin
+        if (~aresetn) begin
+            r_state      <= R_IDLE;
+            s_arready    <= 1'b1;
+            s_rvalid     <= 1'b0;
+            s_rlast      <= 1'b0;
+            ar_addr_reg  <= 32'h0;
+            ar_len_reg   <= 8'h0;
+            ar_burst_reg <= 2'h0;
+            ar_id_reg    <= 5'h0;
+            ar_cnt       <= 8'h0;
+            r_wait_cnt   <= 4'h0;
+        end else begin
+            case (r_state)
+                R_IDLE: begin
+                    s_arready <= 1'b1;
+                    if (s_arvalid && s_arready) begin
+                        s_arready    <= 1'b0;
+                        ar_addr_reg  <= s_araddr;
+                        ar_len_reg   <= s_arlen;
+                        ar_burst_reg <= s_arburst;
+                        ar_id_reg    <= s_arid;
+                        ar_cnt       <= 8'h0;
+                        r_wait_cnt   <= BRAM_RD_LATENCY;
+                        r_state      <= R_WAIT; // 进入等待以拉取第一笔 BRAM 数据
+                    end
+                end
+                R_WAIT: begin
+                    // 等待 BRAM 固定潜伏期结束
+                    if (r_wait_cnt <= 1) begin
+                        s_rvalid   <= 1'b1;
+                        s_rlast    <= (ar_cnt == ar_len_reg);
+                        r_state    <= R_DATA;
+                        r_wait_cnt <= 4'h0;
+                    end else begin
+                        r_wait_cnt <= r_wait_cnt - 1;
+                    end
+                end
+                R_DATA: begin
+                    // 数据被总线成功读取
+                    if (s_rvalid && s_rready) begin
+                        if (ar_cnt == ar_len_reg) begin
+                            // Burst 结束
+                            s_rvalid  <= 1'b0;
+                            s_rlast   <= 1'b0;
+                            s_arready <= 1'b1;
+                            r_state   <= R_IDLE;
+                        end else begin
+                            // 准备读取下一拍数据
+                            ar_cnt <= ar_cnt + 1;
+                            // INCR 模式下地址递增
+                            if (ar_burst_reg == 2'b01) begin 
+                                ar_addr_reg <= ar_addr_reg + 4;
+                            end
+                            s_rvalid   <= 1'b0;
+                            s_rlast    <= 1'b0;
+                            r_wait_cnt <= BRAM_RD_LATENCY;
+                            r_state    <= R_WAIT; // 再次进入等待状态
+                        end
+                    end
+                end
+                default: r_state <= R_IDLE;
+            endcase
+        end
+    end
+
+    assign s_rid   = ar_id_reg;
+    assign s_rresp = 2'b00;
+
+    // 地址译码
+    wire hit_in_re  = (aw_addr_reg[15:12] == 4'h8);
+    wire hit_in_im  = (aw_addr_reg[15:12] == 4'h9);
+    wire hit_out_re = (ar_addr_reg[15:12] == 4'ha);
+    wire hit_out_im = (ar_addr_reg[15:12] == 4'hb);
+
+    // 寄存器控制
+    reg [3:0] fft_ctrl;
+    reg [3:0] fft_status;
+
+    wire [31:0] fft_csr = {24'h0, fft_ctrl, fft_status};
+    // 只有发生有效的写握手且地址对应 CSR 时，才写入控制寄存器
+    wire write_fft_csr  = w_active && (aw_addr_reg[15:0] == `FFT_CSR_ADDR);
+
+    // 状态机
+    localparam IDLE     = 2'd0;
+    localparam LOAD     = 2'd1;
+    localparam WAIT_OUT = 2'd2;
+    localparam DONE     = 2'd3;
+
+    reg [1:0] state, next_state;
+    reg [10:0] in_cnt;
+    reg [10:0] out_cnt;
+
+    wire        do_en;
+    wire [FFT_DATA_WIDTH-1:0] do_re;
+    wire [FFT_DATA_WIDTH-1:0] do_im;
+
+    always @(posedge aclk) begin
+        if (~aresetn) state <= IDLE;
+        else state <= next_state;
+    end
+
+    always @(*) begin
+        case (state)
+            IDLE:     if (fft_ctrl[0]) next_state = LOAD; else next_state = IDLE;
+            LOAD:     if (in_cnt == FFT_LEN - 1) next_state = WAIT_OUT; else next_state = LOAD;
+            WAIT_OUT: if (do_en && out_cnt == FFT_LEN - 1) next_state = DONE; else next_state = WAIT_OUT;
+            DONE:     next_state = IDLE;
+            default:  next_state = IDLE;
+        endcase
+    end
+
+    always @(posedge aclk) begin
+        if (~aresetn) begin
+            in_cnt  <= 0;
+            out_cnt <= 0;
+        end else if (state == IDLE) begin
+            in_cnt  <= 0;
+            out_cnt <= 0;
+        end else begin
+            if (state == LOAD) in_cnt <= in_cnt + 1;
+            if (do_en) out_cnt <= out_cnt + 1; 
+        end
+    end
+
+    // 更新寄存器与状态
+    always @(posedge aclk) begin
+        if (~aresetn) begin
+            fft_ctrl   <= 4'h0;
+            fft_status <= 4'h0;
+        end else begin
+            if (write_fft_csr) begin
+                fft_ctrl <= s_wdata[7:4];
+            end else if (state != IDLE) begin
+                fft_ctrl[0] <= 1'b0;
+            end
+
+            fft_status[0] <= (state != IDLE && state != DONE);
+
+            if (write_fft_csr && s_wdata[4]) begin
+                fft_status[1] <= 1'b0;
+            end else if (state == DONE) begin
+                fft_status[1] <= 1'b1;
+            end
+        end
+    end
+
+    assign fft_finish = fft_status[1];
+
+    // BRAM 接口连线
+    wire [FFT_DATA_WIDTH-1:0] in_re_dout;
+    wire [FFT_DATA_WIDTH-1:0] in_im_dout;
+    wire [FFT_DATA_WIDTH-1:0] out_re_dout;
+    wire [FFT_DATA_WIDTH-1:0] out_im_dout;
+    wire [31:0] out_re_sx = {{(32-FFT_DATA_WIDTH){out_re_dout[FFT_DATA_WIDTH-1]}}, out_re_dout};
+    wire [31:0] out_im_sx = {{(32-FFT_DATA_WIDTH){out_im_dout[FFT_DATA_WIDTH-1]}}, out_im_dout};
+
+    my_bram0 #(
+        .DATA_WIDTH (FFT_DATA_WIDTH),
+        .ADDR_WIDTH (10)
+    ) u_in0(
+        .clka   (aclk),
+        .ena    (w_active && hit_in_re),      // 由 burst写逻辑产生
+        .wea    (1'b1),               
+        .addra  (aw_addr_reg[11:2]),          // 取当前递增的突发写地址
+        .dina   (s_wdata[FFT_DATA_WIDTH-1:0]),
+
+        .clkb   (aclk),
+        .enb    (state == LOAD),
+        .addrb  (in_cnt[9:0]),
+        .doutb  (in_re_dout)
+    );
+
+    my_bram0 #(
+        .DATA_WIDTH (FFT_DATA_WIDTH),
+        .ADDR_WIDTH (10)
+    ) u_in1(
+        .clka   (aclk),
+        .ena    (w_active && hit_in_im),
+        .wea    (1'b1),
+        .addra  (aw_addr_reg[11:2]),
+        .dina   (s_wdata[FFT_DATA_WIDTH-1:0]),
+
+        .clkb   (aclk),
+        .enb    (state == LOAD),
+        .addrb  (in_cnt[9:0]),
+        .doutb  (in_im_dout)
+    );
+
+    // 对于输出 BRAM，采用原先的位反转（Bit-reverse）读取逻辑
+    wire [9:0] b_rd_addr = ar_addr_reg[11:2];
+    wire [9:0] bit_reversed_index = {
+        b_rd_addr[0], b_rd_addr[1], b_rd_addr[2], b_rd_addr[3], b_rd_addr[4], 
+        b_rd_addr[5], b_rd_addr[6], b_rd_addr[7], b_rd_addr[8], b_rd_addr[9]
+    };
+
+    my_bram0 #(
+        .DATA_WIDTH (FFT_DATA_WIDTH),
+        .ADDR_WIDTH (10)
+    ) u_out0(
+        .clka   (aclk),
+        .ena    (do_en),              
+        .wea    (1'b1),
+        .addra  (out_cnt[9:0]),
+        .dina   (do_re),
+
+        .clkb   (aclk),
+        .enb    (r_state != R_IDLE),  // 当处于读突发事务时始终使能 BRAM
+        .addrb  (bit_reversed_index),
+        .doutb  (out_re_dout)
+    );
+
+    my_bram0 #(
+        .DATA_WIDTH (FFT_DATA_WIDTH),
+        .ADDR_WIDTH (10)
+    ) u_out1(
+        .clka   (aclk),
+        .ena    (do_en),
+        .wea    (1'b1),
+        .addra  (out_cnt[9:0]),
+        .dina   (do_im),
+
+        .clkb   (aclk),
+        .enb    (r_state != R_IDLE),
+        .addrb  (bit_reversed_index),
+        .doutb  (out_im_dout)
+    );
+
+    // 支持 1 到 N 拍的读延迟，让 di_en 严格对齐 BRAM 的吐出数据
+    reg [3:0] di_en_shift;
+    always @(posedge aclk) begin
+        if (~aresetn) di_en_shift <= 0;
+        else di_en_shift <= {di_en_shift[2:0], (state == LOAD)};
+    end
+
+    wire di_en_r = (BRAM_RD_LATENCY == 1) ? di_en_shift[0] :
+                   (BRAM_RD_LATENCY == 2) ? di_en_shift[1] : 
+                   (BRAM_RD_LATENCY == 3) ? di_en_shift[2] : di_en_shift[3];
+
+    FFT #(
+        .WIDTH(FFT_DATA_WIDTH)
+    ) u_FFT (
+        .clock  (aclk),
+        .reset  (~aresetn),    
+        .di_en  (di_en_r),     
+        .di_re  (in_re_dout),
+        .di_im  (in_im_dout),
+        .do_en  (do_en),
+        .do_re  (do_re),
+        .do_im  (do_im)
+    );
+
+    // 读取返回数据选择
+    wire [31:0] rdata_d = 
+        (ar_addr_reg[15:0] == `FFT_CSR_ADDR) ? fft_csr     :
+        hit_out_re                           ? out_re_sx   :
+        hit_out_im                           ? out_im_sx   :
+        32'h0;
+
+    always @(*) begin
+        s_rdata = rdata_d;
+    end
+
+endmodule

rtl/ip/matmul/matmul_axi_slave.v

@@ -1,6 +1,9 @@
-// 3-stage pipelined multiplier (LUT-based, no DSP)
-// latency=3, throughput=1 result/cycle
-(* use_dsp = "no", use_dsp48 = "no", syn_multstyle = "logic" *)
+// ═══════════════════════════════════════════════════════
+//  3-stage pipelined multiplier (LUT-based, no DSP)
+//  latency=3, throughput=1 result/cycle
+// ═══════════════════════════════════════════════════════
+
+(* use_dsp = "no" *)
 module pipelined_mult_32x32 (
     input             clk,
     input             rstn,
@@ -9,23 +12,7 @@ module pipelined_mult_32x32 (
     output reg [63:0] p
 );
     reg [31:0] a_r, b_r;
-    (* use_dsp = "no", use_dsp48 = "no", syn_multstyle = "logic" *)
     reg [63:0] prod;
-
-    function automatic [63:0] lut_mul32;
-        input [31:0] lhs;
-        input [31:0] rhs;
-        integer bit_idx;
-        reg [63:0] acc;
-        begin
-            acc = 64'b0;
-            for (bit_idx = 0; bit_idx < 32; bit_idx = bit_idx + 1) begin
-                if (rhs[bit_idx])
-                    acc = acc + ({32'b0, lhs} << bit_idx);
-            end
-            lut_mul32 = acc;
-        end
-    endfunction
     
     always @(posedge clk) begin
         if (!rstn) begin
@@ -34,14 +21,16 @@ module pipelined_mult_32x32 (
         end else begin
             a_r  <= a;         // Stage 1: register inputs
             b_r  <= b;
-            prod <= lut_mul32(a_r, b_r);  // Stage 2: LUT-based multiply
+            prod <= a_r * b_r;  // Stage 2: LUT-based multiply
             p    <= prod;       // Stage 3: register output
         end
     end
 endmodule
 
 
-// AXI Burst Slave + Ping-Pong + Stream CRC32
+// ═══════════════════════════════════════════════════════
+//  矩阵乘法器顶层模块 (AXI Burst Slave + Ping-Pong + Stream CRC32)
+// ═══════════════════════════════════════════════════════
 module matmul_axi_slave (
     input             clk,
     input             resetn,
@@ -92,63 +81,38 @@ module matmul_axi_slave (
     output reg        s_axi_rvalid,
     input             s_axi_rready,
 
-    // AXI master port for autonomous matrix stream load/store
-    output reg [3:0]  m_axi_awid,
-    output reg [31:0] m_axi_awaddr,
-    output reg [7:0]  m_axi_awlen,
-    output reg [2:0]  m_axi_awsize,
-    output reg [1:0]  m_axi_awburst,
-    output reg        m_axi_awlock,
-    output reg [3:0]  m_axi_awcache,
-    output reg [2:0]  m_axi_awprot,
-    output reg        m_axi_awvalid,
-    input             m_axi_awready,
+    // CDMA local endpoint port
+    input             ep_wr_valid,
+    input      [3:0]  ep_wr_id,
+    input      [3:0]  ep_wr_bank,
+    input      [7:0]  ep_wr_word_addr,
+    input      [31:0] ep_wr_data,
+    output            ep_wr_ready,
 
-    output reg [31:0] m_axi_wdata,
-    output reg [3:0]  m_axi_wstrb,
-    output reg        m_axi_wlast,
-    output reg        m_axi_wvalid,
-    input             m_axi_wready,
+    input             ep_rd_valid,
+    input      [3:0]  ep_rd_id,
+    input      [3:0]  ep_rd_bank,
+    input      [7:0]  ep_rd_word_addr,
+    output reg [31:0] ep_rd_data,
+    output            ep_rd_ready,
 
-    input      [3:0]  m_axi_bid,
-    input      [1:0]  m_axi_bresp,
-    input             m_axi_bvalid,
-    output reg        m_axi_bready,
-
-    output reg [3:0]  m_axi_arid,
-    output reg [31:0] m_axi_araddr,
-    output reg [7:0]  m_axi_arlen,
-    output reg [2:0]  m_axi_arsize,
-    output reg [1:0]  m_axi_arburst,
-    output reg        m_axi_arlock,
-    output reg [3:0]  m_axi_arcache,
-    output reg [2:0]  m_axi_arprot,
-    output reg        m_axi_arvalid,
-    input             m_axi_arready,
-
-    input      [3:0]  m_axi_rid,
-    input      [31:0] m_axi_rdata,
-    input      [1:0]  m_axi_rresp,
-    input             m_axi_rlast,
-    input             m_axi_rvalid,
-    output reg        m_axi_rready,
+    // Direct control from the CDMA/matmul bridge
+    input             mat_start_valid,
+    input             mat_start_bank,
+    input             mat_done_clear,
+    input             mat_crc_clear,
+    output            mat_done,
 
     // Interrupt output (active high level, pulsed by calc_done)
     output            intr
 );
 
     // ==========================================
-    // Memory Map
+    // 内存地址映射 (Memory Map)
     // ==========================================
     localparam ADDR_CTRL    = 12'h000;
     localparam ADDR_STATUS  = 12'h004;
     localparam ADDR_CRC     = 12'h010;
-    localparam ADDR_DMA_SRC_BASE   = 12'h020;
-    localparam ADDR_DMA_DST_BASE   = 12'h024;
-    localparam ADDR_DMA_GROUPS     = 12'h028;
-    localparam ADDR_DMA_SRC_STRIDE = 12'h02C;
-    localparam ADDR_DMA_DST_STRIDE = 12'h030;
-    localparam ADDR_DMA_CYCLES     = 12'h034;
     
     localparam ADDR_B0_A    = 12'h100; 
     localparam ADDR_B0_B    = 12'h140; 
@@ -159,13 +123,12 @@ module matmul_axi_slave (
     localparam ADDR_B1_C    = 12'h380; 
 
     // ==========================================
-    // Registers and data buffers
+    // 寄存器与数据缓冲
     // ==========================================
     reg        req_0, req_1;
     reg        busy;
-    reg [1:0]  done_count;
+    reg        done;
     reg        error;
-    wire       done = (done_count != 2'd0);
     
     reg [31:0] b0_a [0:15];
     reg [31:0] b0_b [0:15];
@@ -175,73 +138,32 @@ module matmul_axi_slave (
     reg [31:0] b1_b [0:15];
     reg [65:0] b1_c [0:15];
 
-    reg [31:0] dma_src_base;
-    reg [31:0] dma_dst_base;
-    reg [31:0] dma_groups;
-    reg [31:0] dma_src_stride;
-    reg [31:0] dma_dst_stride;
-    // Full sys_clk cycles spent in dma_busy; held after DMA completion.
-    reg [31:0] dma_cycle_count;
-    reg        dma_busy;
-    reg        dma_done;
-    reg        dma_compute_complete;
-    reg [31:0] load_group;
-    reg [31:0] store_group;
-    reg [31:0] dma_next_rd_addr;
-    reg [31:0] dma_next_wr_addr;
-    reg [31:0] completed_groups;
-    reg [1:0]  bank_loaded;
-    reg [1:0]  bank_store_pending;
-    reg [1:0]  bank_storing;
-    reg [1:0]  bank_compute_pending;
-    reg        dma_compute_bank;
-    reg        dma_load_bank;
-    reg        dma_store_bank;
-    reg        dma_start_pulse;
-    reg        dma_done_clear_pulse;
-    reg        dma_req0_pulse;
-    reg        dma_req1_pulse;
+    assign ep_wr_ready = 1'b1;
+    assign ep_rd_ready = 1'b1;
+    assign mat_done = done;
 
-    function [3:0] c_elem_from_word;
-        input [5:0] word_idx;
-        begin
-            case (word_idx)
-                6'd0,  6'd1,  6'd2:  c_elem_from_word = 4'd0;
-                6'd3,  6'd4,  6'd5:  c_elem_from_word = 4'd1;
-                6'd6,  6'd7,  6'd8:  c_elem_from_word = 4'd2;
-                6'd9,  6'd10, 6'd11: c_elem_from_word = 4'd3;
-                6'd12, 6'd13, 6'd14: c_elem_from_word = 4'd4;
-                6'd15, 6'd16, 6'd17: c_elem_from_word = 4'd5;
-                6'd18, 6'd19, 6'd20: c_elem_from_word = 4'd6;
-                6'd21, 6'd22, 6'd23: c_elem_from_word = 4'd7;
-                6'd24, 6'd25, 6'd26: c_elem_from_word = 4'd8;
-                6'd27, 6'd28, 6'd29: c_elem_from_word = 4'd9;
-                6'd30, 6'd31, 6'd32: c_elem_from_word = 4'd10;
-                6'd33, 6'd34, 6'd35: c_elem_from_word = 4'd11;
-                6'd36, 6'd37, 6'd38: c_elem_from_word = 4'd12;
-                6'd39, 6'd40, 6'd41: c_elem_from_word = 4'd13;
-                6'd42, 6'd43, 6'd44: c_elem_from_word = 4'd14;
-                default:             c_elem_from_word = 4'd15;
-            endcase
-        end
-    endfunction
+    wire [3:0] ep_wr_idx = ep_wr_word_addr[3:0];
+    wire [7:0] ep_rd_elem_raw = ep_rd_word_addr / 8'd3;
+    wire [7:0] ep_rd_part_raw = ep_rd_word_addr % 8'd3;
+    wire [3:0] ep_rd_elem = ep_rd_elem_raw[3:0];
+    wire [1:0] ep_rd_part = ep_rd_part_raw[1:0];
+    wire [65:0] ep_rd_c0 = b0_c[ep_rd_elem];
+    wire [65:0] ep_rd_c1 = b1_c[ep_rd_elem];
 
-    function [1:0] c_part_from_word;
-        input [5:0] word_idx;
-        begin
-            case (word_idx)
-                6'd0,  6'd3,  6'd6,  6'd9,
-                6'd12, 6'd15, 6'd18, 6'd21,
-                6'd24, 6'd27, 6'd30, 6'd33,
-                6'd36, 6'd39, 6'd42, 6'd45: c_part_from_word = 2'd0;
-                6'd1,  6'd4,  6'd7,  6'd10,
-                6'd13, 6'd16, 6'd19, 6'd22,
-                6'd25, 6'd28, 6'd31, 6'd34,
-                6'd37, 6'd40, 6'd43, 6'd46: c_part_from_word = 2'd1;
-                default:                     c_part_from_word = 2'd2;
-            endcase
+    always @(*) begin
+        ep_rd_data = 32'b0;
+        if (ep_rd_word_addr < 8'd48) begin
+            if (ep_rd_bank[0] == 1'b0) begin
+                if (ep_rd_part == 2'd0)      ep_rd_data = ep_rd_c0[31:0];
+                else if (ep_rd_part == 2'd1) ep_rd_data = ep_rd_c0[63:32];
+                else                         ep_rd_data = {30'b0, ep_rd_c0[65:64]};
+            end else begin
+                if (ep_rd_part == 2'd0)      ep_rd_data = ep_rd_c1[31:0];
+                else if (ep_rd_part == 2'd1) ep_rd_data = ep_rd_c1[63:32];
+                else                         ep_rd_data = {30'b0, ep_rd_c1[65:64]};
+            end
         end
-    endfunction
+    end
 
     function [31:0] apply_wstrb;
         input [31:0] old_value;
@@ -258,71 +180,26 @@ module matmul_axi_slave (
 
     // ==========================================
     // CRC32 Engine (IEEE 802.3, polynomial 0xEDB88320)
-    //
-    // AXI-stream: single-cycle crc32_update_word (4 LUT lookup depth, ok for
-    //   AXI timing—the bus runs at or below internal compute rate).
-    // DMA-calc: two 6-byte CRC steps per 66-bit C-element.  A result FIFO
-    //   absorbs the 16-cycle compute burst so the recursive CRC state never
-    //   backpressures the multiplier under the normal DMA load cadence.
     // ==========================================
     reg [31:0] crc32_table [0:255];
     reg [31:0] crc_reg;
 
-    // ---- AXI-stream CRC (single-cycle) ----------------------------------
-    wire [31:0] crc_stream_data = s_axi_rdata;
-    wire        crc_axi_valid = (r_state == R_DATA) && s_axi_rvalid && s_axi_rready &&
-                                ((r_offset >= ADDR_B0_C && r_offset < (ADDR_B0_C + 12'h0C0)) ||
-                                 (r_offset >= ADDR_B1_C && r_offset < (ADDR_B1_C + 12'h0C0)));
-    wire        crc_stream_valid = crc_axi_valid;
-    wire [31:0] crc_next = crc32_update_word(crc_reg, crc_stream_data);
-
-    function [31:0] crc32_update_word;
+    function [31:0] crc32_word_next;
         input [31:0] crc_in;
         input [31:0] data_in;
-        reg [31:0] c0;
-        reg [31:0] c1;
-        reg [31:0] c2;
+        reg [31:0] t0, c0, t1, c1, t2, c2, t3;
         begin
-            c0 = crc32_table[(crc_in[7:0] ^ data_in[7:0])] ^ {8'h00, crc_in[31:8]};
-            c1 = crc32_table[(c0[7:0]     ^ data_in[15:8])] ^ {8'h00, c0[31:8]};
-            c2 = crc32_table[(c1[7:0]     ^ data_in[23:16])] ^ {8'h00, c1[31:8]};
-            crc32_update_word = crc32_table[(c2[7:0] ^ data_in[31:24])] ^ {8'h00, c2[31:8]};
+            t0 = crc32_table[(crc_in[7:0] ^ data_in[7:0])];
+            c0 = t0 ^ {8'h00, crc_in[31:8]};
+            t1 = crc32_table[(c0[7:0] ^ data_in[15:8])];
+            c1 = t1 ^ {8'h00, c0[31:8]};
+            t2 = crc32_table[(c1[7:0] ^ data_in[23:16])];
+            c2 = t2 ^ {8'h00, c1[31:8]};
+            t3 = crc32_table[(c2[7:0] ^ data_in[31:24])];
+            crc32_word_next = t3 ^ {8'h00, c2[31:8]};
         end
     endfunction
 
-    function [31:0] crc32_update_6bytes;
-        input [31:0] crc_in;
-        input [47:0] data_in;
-        reg [31:0] c;
-        integer byte_idx;
-        begin
-            c = crc_in;
-            for (byte_idx = 0; byte_idx < 6; byte_idx = byte_idx + 1)
-                c = crc32_table[(c[7:0] ^ data_in[byte_idx*8 +: 8])] ^
-                    {8'h00, c[31:8]};
-            crc32_update_6bytes = c;
-        end
-    endfunction
-
-    // ---- DMA result FIFO and two-cycle recursive CRC consumer -----------
-    localparam CRC_FIFO_DEPTH = 32;
-    reg [65:0] crc_fifo [0:CRC_FIFO_DEPTH-1];
-    reg [4:0]  crc_fifo_wr_ptr;
-    reg [4:0]  crc_fifo_rd_ptr;
-    reg [5:0]  crc_fifo_count;
-    reg        crc_c66_busy;
-    reg [65:0] crc_c66_data;
-    reg [31:0] crc_c66_half;
-
-    wire        crc_fifo_empty = (crc_fifo_count == 6'd0);
-    wire        crc_fifo_push = dma_busy && acc_valid_d4;
-    wire        crc_fifo_pop = !crc_c66_busy && !crc_fifo_empty;
-    wire [31:0] crc_c66_first_next =
-        crc32_update_6bytes(crc_reg, crc_fifo[crc_fifo_rd_ptr][47:0]);
-    wire [47:0] crc_c66_second_data = {30'b0, crc_c66_data[65:48]};
-    wire [31:0] crc_c66_final_next =
-        crc32_update_6bytes(crc_c66_half, crc_c66_second_data);
-
     initial begin
         crc32_table[0  ] = 32'h00000000; crc32_table[1  ] = 32'h77073096;
         crc32_table[2  ] = 32'hEE0E612C; crc32_table[3  ] = 32'h990951BA;
@@ -455,7 +332,7 @@ module matmul_axi_slave (
     end
 
     // ==========================================
-    // AXI Write (INCR Burst)
+    // AXI Write 通道逻辑 (支持 INCR Burst)
     // ==========================================
     localparam W_IDLE = 2'd0;
     localparam W_DATA = 2'd1;
@@ -471,40 +348,16 @@ module matmul_axi_slave (
     assign s_axi_bid   = w_id;
     assign s_axi_bresp = 2'b00;
 
+    // 前向声明引擎的状态
     localparam C_IDLE      = 2'd0;
     localparam C_RUN       = 2'd1;
     reg [1:0] state;
     reg       cur_bank;
     reg       calc_done_pulse;
-
-    localparam DMA_RD_IDLE = 2'd0;
-    localparam DMA_RD_ADDR = 2'd1;
-    localparam DMA_RD_DATA = 2'd2;
-    reg [1:0] dma_rd_state;
-    reg [7:0] dma_rd_count;
-    reg       dma_rd_bank;
-    wire [4:0] dma_rd_group_word_idx = dma_rd_count[4:0];
-    wire [3:0] dma_rd_word_idx = dma_rd_count[3:0];
-    wire       dma_rd_fill_bank = dma_rd_bank ^ dma_rd_count[5];
-    wire       dma_rd_commit = (dma_rd_state == DMA_RD_DATA) && m_axi_rvalid && m_axi_rready;
-    wire       dma_bank0_free = !bank_loaded[0] && !bank_compute_pending[0] && !req_0 &&
-                                !(state == C_RUN && cur_bank == 1'b0);
-    wire       dma_bank1_free = !bank_loaded[1] && !bank_compute_pending[1] && !req_1 &&
-                                !(state == C_RUN && cur_bank == 1'b1);
-    wire       dma_load_bank_free = dma_load_bank ? dma_bank1_free : dma_bank0_free;
-    wire       dma_rd_fill_bank_free = dma_rd_fill_bank ? dma_bank1_free : dma_bank0_free;
-    wire       dma_rd_next_bank_free = dma_rd_fill_bank ? dma_bank0_free : dma_bank1_free;
-
-    localparam DMA_WR_IDLE = 2'd0;
-    localparam DMA_WR_ADDR = 2'd1;
-    localparam DMA_WR_DATA = 2'd2;
-    localparam DMA_WR_RESP = 2'd3;
-    reg [1:0] dma_wr_state;
-    reg [5:0] dma_wr_count;
-
-    wire crc_clear_pulse = (w_state == W_DATA) && s_axi_wvalid && s_axi_wready && (w_offset == ADDR_CRC);
-    wire done_clear_pulse = (w_state == W_DATA) && s_axi_wvalid && s_axi_wready &&
-                            (w_offset == ADDR_STATUS) && s_axi_wdata[1];
+    
+    // 【修改点 1】单独引出一个写脉冲信号给 CRC 清零用
+    wire crc_clear_pulse = ((w_state == W_DATA) && s_axi_wvalid && s_axi_wready && (w_offset == ADDR_CRC)) ||
+                           mat_crc_clear;
 
     always @(posedge clk) begin
         if (!resetn) begin
@@ -514,37 +367,39 @@ module matmul_axi_slave (
             s_axi_bvalid  <= 1'b0;
             req_0         <= 1'b0;
             req_1         <= 1'b0;
-            done_count    <= 2'd0;
+            done          <= 1'b0;
             error         <= 1'b0;
-            dma_src_base   <= 32'd0;
-            dma_dst_base   <= 32'd0;
-            dma_groups     <= 32'd0;
-            dma_src_stride <= 32'd128;
-            dma_dst_stride <= 32'd192;
-            dma_start_pulse <= 1'b0;
-            dma_done_clear_pulse <= 1'b0;
         end else begin
-            dma_start_pulse <= 1'b0;
-            dma_done_clear_pulse <= 1'b0;
-
-            if (dma_rd_commit) begin
-                if (dma_rd_fill_bank == 1'b0) begin
-                    if (dma_rd_group_word_idx < 5'd16)
-                        b0_a[dma_rd_word_idx] <= m_axi_rdata;
-                    else
-                        b0_b[dma_rd_word_idx] <= m_axi_rdata;
-                end else begin
-                    if (dma_rd_group_word_idx < 5'd16)
-                        b1_a[dma_rd_word_idx] <= m_axi_rdata;
-                    else
-                        b1_b[dma_rd_word_idx] <= m_axi_rdata;
-                end
-            end
-
             if (req_0 && state == C_RUN && cur_bank == 1'b0) req_0 <= 1'b0;
             if (req_1 && state == C_RUN && cur_bank == 1'b1) req_1 <= 1'b0;
-            if (dma_req0_pulse) req_0 <= 1'b1;
-            if (dma_req1_pulse) req_1 <= 1'b1;
+
+            if (mat_start_valid) begin
+                if (mat_start_bank) req_1 <= 1'b1;
+                else                req_0 <= 1'b1;
+            end
+            
+            if (calc_done_pulse) begin
+                done <= 1'b1;
+            end
+
+            if (mat_done_clear) begin
+                done  <= 1'b0;
+                error <= 1'b0;
+            end
+
+            if (ep_wr_valid && ep_wr_ready) begin
+                if (ep_wr_word_addr < 8'd16) begin
+                    if (ep_wr_bank[0] == 1'b0)
+                        b0_a[ep_wr_idx] <= ep_wr_data;
+                    else
+                        b1_a[ep_wr_idx] <= ep_wr_data;
+                end else if (ep_wr_word_addr < 8'd32) begin
+                    if (ep_wr_bank[0] == 1'b0)
+                        b0_b[ep_wr_idx] <= ep_wr_data;
+                    else
+                        b1_b[ep_wr_idx] <= ep_wr_data;
+                end
+            end
             
             case (w_state)
                 W_IDLE: begin
@@ -563,23 +418,12 @@ module matmul_axi_slave (
                         if (w_offset == ADDR_CTRL) begin
                             if (s_axi_wdata[0]) req_0 <= 1'b1; 
                             if (s_axi_wdata[1]) req_1 <= 1'b1; 
-                            if (s_axi_wdata[8]) dma_start_pulse <= 1'b1;
                         end
                         else if (w_offset == ADDR_STATUS) begin
+                            if (s_axi_wdata[1]) done  <= 1'b0;
                             if (s_axi_wdata[2]) error <= 1'b0;
-                            if (s_axi_wdata[4]) dma_done_clear_pulse <= 1'b1;
                         end
-                        else if (w_offset == ADDR_DMA_SRC_BASE)
-                            dma_src_base <= apply_wstrb(dma_src_base, s_axi_wdata, s_axi_wstrb);
-                        else if (w_offset == ADDR_DMA_DST_BASE)
-                            dma_dst_base <= apply_wstrb(dma_dst_base, s_axi_wdata, s_axi_wstrb);
-                        else if (w_offset == ADDR_DMA_GROUPS)
-                            dma_groups <= apply_wstrb(dma_groups, s_axi_wdata, s_axi_wstrb);
-                        else if (w_offset == ADDR_DMA_SRC_STRIDE)
-                            dma_src_stride <= apply_wstrb(dma_src_stride, s_axi_wdata, s_axi_wstrb);
-                        else if (w_offset == ADDR_DMA_DST_STRIDE)
-                            dma_dst_stride <= apply_wstrb(dma_dst_stride, s_axi_wdata, s_axi_wstrb);
-                        // CRC register is now managed by the pipelined CRC engine
+                        // 【修改点 2】删除 else if (w_offset == ADDR_CRC) { crc_reg <= ... } 防止多重驱动
                         else if (w_offset >= ADDR_B0_A && w_offset < ADDR_B0_B)
                             b0_a[(w_offset - ADDR_B0_A) >> 2] <= apply_wstrb(b0_a[(w_offset - ADDR_B0_A) >> 2], s_axi_wdata, s_axi_wstrb);
                         else if (w_offset >= ADDR_B0_B && w_offset < ADDR_B0_C)
@@ -610,17 +454,11 @@ module matmul_axi_slave (
                 end
                 default: w_state <= W_IDLE;
             endcase
-
-            case ({calc_done_pulse, done_clear_pulse})
-                2'b10: if (done_count != 2'd3) done_count <= done_count + 2'd1;
-                2'b01: if (done_count != 2'd0) done_count <= done_count - 2'd1;
-                default: done_count <= done_count;
-            endcase
         end
     end
 
     // ==========================================
-    // AXI Read (INCR Burst)
+    // AXI Read 通道逻辑 (支持 INCR Burst)
     // ==========================================
     localparam R_IDLE = 2'd0;
     localparam R_DATA = 2'd1;
@@ -635,13 +473,13 @@ module matmul_axi_slave (
     assign s_axi_rresp = 2'b00;
 
     wire [5:0] c0_offset = (r_offset - ADDR_B0_C) >> 2;
-    wire [3:0] c0_elem   = c_elem_from_word(c0_offset);
-    wire [1:0] c0_part   = c_part_from_word(c0_offset);
+    wire [3:0] c0_elem   = c0_offset / 3;
+    wire [1:0] c0_part   = c0_offset % 3;
     wire [65:0] target_c0 = b0_c[c0_elem];
 
     wire [5:0] c1_offset = (r_offset - ADDR_B1_C) >> 2;
-    wire [3:0] c1_elem   = c_elem_from_word(c1_offset);
-    wire [1:0] c1_part   = c_part_from_word(c1_offset);
+    wire [3:0] c1_elem   = c1_offset / 3;
+    wire [1:0] c1_part   = c1_offset % 3;
     wire [65:0] target_c1 = b1_c[c1_elem];
 
     wire crc_read_en = (r_offset >= ADDR_B0_C && r_offset < (ADDR_B0_C + 12'h0C0)) ||
@@ -672,6 +510,7 @@ module matmul_axi_slave (
                 end
                 R_DATA: begin
                     if (s_axi_rvalid && s_axi_rready) begin
+                        // CRC is updated from completed compute results, not from C reads.
                         if (r_cnt == r_len) begin
                             s_axi_rvalid  <= 1'b0;
                             s_axi_rlast   <= 1'b0;
@@ -699,20 +538,7 @@ module matmul_axi_slave (
             else if (current_r_offset == ADDR_CRC)
                 s_axi_rdata = crc_reg ^ 32'hFFFFFFFF;
             else if (current_r_offset == ADDR_STATUS)
-                s_axi_rdata = {26'b0, (crc_c66_busy || !crc_fifo_empty),
-                               dma_done, dma_busy, error, done, busy};
-            else if (current_r_offset == ADDR_DMA_SRC_BASE)
-                s_axi_rdata = dma_src_base;
-            else if (current_r_offset == ADDR_DMA_DST_BASE)
-                s_axi_rdata = dma_dst_base;
-            else if (current_r_offset == ADDR_DMA_GROUPS)
-                s_axi_rdata = dma_groups;
-            else if (current_r_offset == ADDR_DMA_SRC_STRIDE)
-                s_axi_rdata = dma_src_stride;
-            else if (current_r_offset == ADDR_DMA_DST_STRIDE)
-                s_axi_rdata = dma_dst_stride;
-            else if (current_r_offset == ADDR_DMA_CYCLES)
-                s_axi_rdata = dma_cycle_count;
+                s_axi_rdata = {29'b0, error, done, busy};
             else if (current_r_offset >= ADDR_B0_A && current_r_offset < ADDR_B0_B)
                 s_axi_rdata = b0_a[(current_r_offset - ADDR_B0_A) >> 2];
             else if (current_r_offset >= ADDR_B0_B && current_r_offset < ADDR_B0_C)
@@ -735,7 +561,7 @@ module matmul_axi_slave (
     end
     
     // ==========================================
-    // Compute FSM
+    // 计算引擎 (Compute FSM)
     // ==========================================
     wire [63:0] mult_p    [0:3];
     reg  [31:0] m_in_a    [0:3];
@@ -759,66 +585,22 @@ module matmul_axi_slave (
     reg       acc_bank_d1, acc_bank_d2, acc_bank_d3, acc_bank_d4;
     reg       acc_valid_d1, acc_valid_d2, acc_valid_d3, acc_valid_d4;
     reg [4:0] pipe_cnt;
-    wire [65:0] acc_result = ({2'b0, mult_p[0]} + {2'b0, mult_p[1]}) +
-                             ({2'b0, mult_p[2]} + {2'b0, mult_p[3]});
-
-    // Leave eight entries for results already in the multiplier pipeline.
-    // Under the normal DMA cadence the FIFO stays well below this threshold.
-    wire dma_crc_issue_ready = !dma_busy || (crc_fifo_count < 6'd24);
-
-    // DMA CRC takes priority over the software-driven AXI read stream.
-    always @(posedge clk) begin
-        if (!resetn) begin
-            crc_reg         <= 32'hFFFFFFFF;
-            crc_fifo_wr_ptr <= 5'd0;
-            crc_fifo_rd_ptr <= 5'd0;
-            crc_fifo_count  <= 6'd0;
-            crc_c66_busy    <= 1'b0;
-            crc_c66_data    <= 66'd0;
-            crc_c66_half    <= 32'd0;
-        end else if (crc_clear_pulse) begin
-            crc_reg         <= 32'hFFFFFFFF;
-            crc_fifo_wr_ptr <= 5'd0;
-            crc_fifo_rd_ptr <= 5'd0;
-            crc_fifo_count  <= 6'd0;
-            crc_c66_busy    <= 1'b0;
-            crc_c66_data    <= 66'd0;
-            crc_c66_half    <= 32'd0;
-        end else begin
-            if (crc_fifo_push) begin
-                crc_fifo[crc_fifo_wr_ptr] <= acc_result;
-                crc_fifo_wr_ptr <= crc_fifo_wr_ptr + 5'd1;
-            end
-
-            case ({crc_fifo_push, crc_fifo_pop})
-                2'b10: crc_fifo_count <= crc_fifo_count + 6'd1;
-                2'b01: crc_fifo_count <= crc_fifo_count - 6'd1;
-                default: crc_fifo_count <= crc_fifo_count;
-            endcase
-
-            if (crc_c66_busy) begin
-                crc_reg <= crc_c66_final_next;
-                crc_c66_busy <= 1'b0;
-            end else if (crc_fifo_pop) begin
-                crc_c66_data <= crc_fifo[crc_fifo_rd_ptr];
-                crc_c66_half <= crc_c66_first_next;
-                crc_c66_busy <= 1'b1;
-                crc_fifo_rd_ptr <= crc_fifo_rd_ptr + 5'd1;
-            end else if (crc_stream_valid) begin
-                crc_reg <= crc_next;
-            end
-        end
-    end
+    wire [65:0] calc_c_result = ({2'b0, mult_p[0]} + {2'b0, mult_p[1]}) +
+                                ({2'b0, mult_p[2]} + {2'b0, mult_p[3]});
+    wire        calc_crc_valid = acc_valid_d4;
+    wire [31:0] crc_calc_0 = crc32_word_next(crc_reg, calc_c_result[31:0]);
+    wire [31:0] crc_calc_1 = crc32_word_next(crc_calc_0, calc_c_result[63:32]);
+    wire [31:0] crc_calc_2 = crc32_word_next(crc_calc_1, {30'b0, calc_c_result[65:64]});
 
     task start_calc_bank;
         input bank;
         begin
-            cur_bank    <= bank;
-            busy        <= 1'b1;
-            state       <= C_RUN;
-            pipe_cnt    <= 5'd1;
-            acc_idx_d1  <= 4'd0;
-            acc_bank_d1 <= bank;
+            cur_bank     <= bank;
+            busy         <= 1'b1;
+            state        <= C_RUN;
+            pipe_cnt     <= 5'd1;
+            acc_idx_d1   <= 4'd0;
+            acc_bank_d1  <= bank;
             acc_valid_d1 <= 1'b1;
             if (bank == 1'b0) begin
                 m_in_a[0] <= b0_a[4'd0]; m_in_b[0] <= b0_b[4'd0];
@@ -834,6 +616,17 @@ module matmul_axi_slave (
         end
     endtask
 
+    // CRC tracks completed C elements directly, independent of result writeback.
+    always @(posedge clk) begin
+        if (!resetn) begin
+            crc_reg <= 32'hFFFFFFFF;
+        end else if (crc_clear_pulse) begin
+            crc_reg <= 32'hFFFFFFFF;
+        end else if (calc_crc_valid) begin
+            crc_reg <= crc_calc_2;
+        end
+    end
+
     always @(posedge clk) begin
         if (!resetn) begin
             state           <= C_IDLE;
@@ -856,7 +649,7 @@ module matmul_axi_slave (
         end else begin
             calc_done_pulse <= 1'b0;
 
-            // Pipeline shift (4 cycles total)
+            // Pipeline shift: issue_idx → d1 → d2 → d3 → d4 (4 cycles total)
             acc_idx_d4  <= acc_idx_d3;
             acc_idx_d3  <= acc_idx_d2;
             acc_idx_d2  <= acc_idx_d1;
@@ -883,296 +676,49 @@ module matmul_axi_slave (
                 end
 
                 C_RUN: begin
-                    // Issue one C element per cycle unless the CRC FIFO is
-                    // approaching capacity.
+                    // Issue 4 new operands every cycle (pipe_cnt 0-15, 16 rounds)
                     if (pipe_cnt < 5'd16) begin
-                        if (dma_crc_issue_ready) begin
-                            acc_idx_d1   <= pipe_cnt[3:0];
-                            acc_bank_d1  <= cur_bank;
-                            acc_valid_d1 <= 1'b1;
-                            if (cur_bank == 1'b0) begin
-                                m_in_a[0] <= b0_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b0_b[{2'd0, pipe_cnt[1:0]}];
-                                m_in_a[1] <= b0_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b0_b[{2'd1, pipe_cnt[1:0]}];
-                                m_in_a[2] <= b0_a[{pipe_cnt[3:2], 2'd2}]; m_in_b[2] <= b0_b[{2'd2, pipe_cnt[1:0]}];
-                                m_in_a[3] <= b0_a[{pipe_cnt[3:2], 2'd3}]; m_in_b[3] <= b0_b[{2'd3, pipe_cnt[1:0]}];
-                            end else begin
-                                m_in_a[0] <= b1_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b1_b[{2'd0, pipe_cnt[1:0]}];
-                                m_in_a[1] <= b1_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b1_b[{2'd1, pipe_cnt[1:0]}];
-                                m_in_a[2] <= b1_a[{pipe_cnt[3:2], 2'd2}]; m_in_b[2] <= b1_b[{2'd2, pipe_cnt[1:0]}];
-                                m_in_a[3] <= b1_a[{pipe_cnt[3:2], 2'd3}]; m_in_b[3] <= b1_b[{2'd3, pipe_cnt[1:0]}];
-                            end
-                            pipe_cnt <= pipe_cnt + 5'd1;
+                        acc_idx_d1   <= pipe_cnt[3:0];
+                        acc_bank_d1  <= cur_bank;
+                        acc_valid_d1 <= 1'b1;
+                        if (cur_bank == 1'b0) begin
+                            m_in_a[0] <= b0_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b0_b[{2'd0, pipe_cnt[1:0]}];
+                            m_in_a[1] <= b0_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b0_b[{2'd1, pipe_cnt[1:0]}];
+                            m_in_a[2] <= b0_a[{pipe_cnt[3:2], 2'd2}]; m_in_b[2] <= b0_b[{2'd2, pipe_cnt[1:0]}];
+                            m_in_a[3] <= b0_a[{pipe_cnt[3:2], 2'd3}]; m_in_b[3] <= b0_b[{2'd3, pipe_cnt[1:0]}];
+                        end else begin
+                            m_in_a[0] <= b1_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b1_b[{2'd0, pipe_cnt[1:0]}];
+                            m_in_a[1] <= b1_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b1_b[{2'd1, pipe_cnt[1:0]}];
+                            m_in_a[2] <= b1_a[{pipe_cnt[3:2], 2'd2}]; m_in_b[2] <= b1_b[{2'd2, pipe_cnt[1:0]}];
+                            m_in_a[3] <= b1_a[{pipe_cnt[3:2], 2'd3}]; m_in_b[3] <= b1_b[{2'd3, pipe_cnt[1:0]}];
                         end
                     end
 
                     // Accumulate results from 4 cycles ago.
                     if (acc_valid_d4) begin
                         if (acc_bank_d4 == 1'b0)
-                            b0_c[acc_idx_d4] <= acc_result;
+                            b0_c[acc_idx_d4] <= calc_c_result;
                         else
-                            b1_c[acc_idx_d4] <= acc_result;
+                            b1_c[acc_idx_d4] <= calc_c_result;
                     end
 
                     if (acc_valid_d4 && acc_idx_d4 == 4'd15) begin
                         calc_done_pulse <= 1'b1;
                     end
 
-                    if (pipe_cnt >= 5'd16) begin
-                        if (dma_busy) begin
-                            if (acc_valid_d4 && acc_idx_d4 == 4'd15) begin
-                                if (cur_bank == 1'b0 && req_1)
-                                    start_calc_bank(1'b1);
-                                else if (cur_bank == 1'b1 && req_0)
-                                    start_calc_bank(1'b0);
-                                else begin
-                                    busy  <= 1'b0;
-                                    state <= C_IDLE;
-                                end
-                            end else begin
-                                pipe_cnt <= pipe_cnt + 5'd1;
-                            end
-                        end else if (cur_bank == 1'b0 && req_1) begin
-                            start_calc_bank(1'b1);
-                        end else if (cur_bank == 1'b1 && req_0) begin
-                            start_calc_bank(1'b0);
-                        end else if (acc_valid_d4 && acc_idx_d4 == 4'd15) begin
-                            busy  <= 1'b0;
-                            state <= C_IDLE;
-                        end else begin
-                            pipe_cnt <= pipe_cnt + 5'd1;
-                        end
-                    end
-                end
-            endcase
-        end
-    end
-
-    // ==========================================
-    // Autonomous AXI master loader with inline result CRC.
-    // ==========================================
-    always @(posedge clk) begin
-        if (!resetn) begin
-            dma_busy           <= 1'b0;
-            dma_done           <= 1'b0;
-            dma_compute_complete <= 1'b0;
-            dma_cycle_count    <= 32'd0;
-            load_group         <= 32'd0;
-            store_group        <= 32'd0;
-            dma_next_rd_addr   <= 32'd0;
-            dma_next_wr_addr   <= 32'd0;
-            completed_groups   <= 32'd0;
-            bank_loaded        <= 2'b00;
-            bank_store_pending <= 2'b00;
-            bank_storing       <= 2'b00;
-            bank_compute_pending <= 2'b00;
-            dma_compute_bank   <= 1'b0;
-            dma_load_bank      <= 1'b0;
-            dma_store_bank     <= 1'b0;
-            dma_rd_state       <= DMA_RD_IDLE;
-            dma_rd_count       <= 8'd0;
-            dma_rd_bank        <= 1'b0;
-            dma_wr_state       <= DMA_WR_IDLE;
-            dma_wr_count       <= 6'd0;
-
-            m_axi_arid         <= 4'd0;
-            m_axi_araddr       <= 32'd0;
-            m_axi_arlen        <= 8'd31;
-            m_axi_arsize       <= 3'd2;
-            m_axi_arburst      <= 2'b01;
-            m_axi_arlock       <= 1'b0;
-            m_axi_arcache      <= 4'b0;
-            m_axi_arprot       <= 3'b0;
-            m_axi_arvalid      <= 1'b0;
-            m_axi_rready       <= 1'b0;
-
-            m_axi_awid         <= 4'd0;
-            m_axi_awaddr       <= 32'd0;
-            m_axi_awlen        <= 8'd47;
-            m_axi_awsize       <= 3'd2;
-            m_axi_awburst      <= 2'b01;
-            m_axi_awlock       <= 1'b0;
-            m_axi_awcache      <= 4'b0;
-            m_axi_awprot       <= 3'b0;
-            m_axi_awvalid      <= 1'b0;
-            m_axi_wdata        <= 32'd0;
-            m_axi_wstrb        <= 4'hF;
-            m_axi_wlast        <= 1'b0;
-            m_axi_wvalid       <= 1'b0;
-            m_axi_bready       <= 1'b0;
-            dma_req0_pulse     <= 1'b0;
-            dma_req1_pulse     <= 1'b0;
-        end else begin
-            dma_req0_pulse <= 1'b0;
-            dma_req1_pulse <= 1'b0;
-
-            if (dma_done_clear_pulse)
-                dma_done <= 1'b0;
-
-            if (dma_start_pulse && !dma_busy && dma_groups != 32'd0) begin
-                dma_busy           <= 1'b1;
-                dma_done           <= 1'b0;
-                dma_compute_complete <= 1'b0;
-                dma_cycle_count    <= 32'd0;
-                load_group         <= 32'd0;
-                store_group        <= 32'd0;
-                dma_next_rd_addr   <= dma_src_base;
-                dma_next_wr_addr   <= dma_dst_base;
-                completed_groups   <= 32'd0;
-                bank_loaded        <= 2'b00;
-                bank_store_pending <= 2'b00;
-                bank_storing       <= 2'b00;
-                bank_compute_pending <= 2'b00;
-                dma_compute_bank   <= 1'b0;
-                dma_load_bank      <= 1'b0;
-                dma_store_bank     <= 1'b0;
-                dma_rd_state       <= DMA_RD_IDLE;
-                dma_wr_state       <= DMA_WR_IDLE;
-            end else if (dma_busy) begin
-                dma_cycle_count <= dma_cycle_count + 32'd1;
-            end
-
-            if (dma_busy) begin
-                if (state == C_RUN)
-                    bank_compute_pending[cur_bank] <= 1'b0;
-
-                if (bank_loaded[0] && !req_0 &&
-                    !bank_compute_pending[0] && !(state == C_RUN && cur_bank == 1'b0)) begin
-                    dma_req0_pulse <= 1'b1;
-                    bank_loaded[0] <= 1'b0;
-                    bank_compute_pending[0] <= 1'b1;
-                    dma_compute_bank <= 1'b0;
-                end else if (bank_loaded[1] && !req_1 &&
-                             !bank_compute_pending[1] && !(state == C_RUN && cur_bank == 1'b1)) begin
-                    dma_req1_pulse <= 1'b1;
-                    bank_loaded[1] <= 1'b0;
-                    bank_compute_pending[1] <= 1'b1;
-                    dma_compute_bank <= 1'b1;
-                end
-            end
-
-            if (calc_done_pulse && dma_busy) begin
-                store_group <= store_group + 32'd1;
-                completed_groups <= completed_groups + 32'd1;
-                if ((completed_groups + 32'd1) >= dma_groups)
-                    dma_compute_complete <= 1'b1;
-            end
-
-            if (dma_compute_complete && crc_fifo_empty && !crc_c66_busy) begin
-                dma_busy <= 1'b0;
-                dma_done <= 1'b1;
-                dma_compute_complete <= 1'b0;
-            end
-
-            case (dma_rd_state)
-                DMA_RD_IDLE: begin
-                    m_axi_arvalid <= 1'b0;
-                    m_axi_rready  <= 1'b0;
-                    if (dma_busy && load_group < dma_groups && dma_load_bank_free) begin
-                        dma_rd_bank   <= dma_load_bank;
-                        dma_rd_count  <= 8'd0;
-                        m_axi_araddr  <= dma_next_rd_addr;
-                        m_axi_arlen   <= ((dma_src_stride == 32'd128) &&
-                                          ((dma_groups - load_group) >= 32'd8)) ? 8'd255 : 8'd31;
-                        m_axi_arsize  <= 3'd2;
-                        m_axi_arburst <= 2'b01;
-                        m_axi_arvalid <= 1'b1;
-                        dma_rd_state  <= DMA_RD_ADDR;
-                    end
-                end
-                DMA_RD_ADDR: begin
-                    if (m_axi_arvalid && m_axi_arready) begin
-                        m_axi_arvalid <= 1'b0;
-                        m_axi_rready  <= 1'b1;
-                        dma_rd_state  <= DMA_RD_DATA;
-                    end
-                end
-                DMA_RD_DATA: begin
-                    if (!m_axi_rready && dma_rd_fill_bank_free)
-                        m_axi_rready <= 1'b1;
-
-                    if (m_axi_rvalid && m_axi_rready) begin
-                        // Present the next request one beat early so the SRAM
-                        // slave can accept it together with the current RLAST.
-                        if ((dma_rd_count == 8'd254) && dma_busy &&
-                            ((load_group + 32'd1) < dma_groups) && dma_rd_next_bank_free) begin
-                            m_axi_araddr  <= dma_next_rd_addr + dma_src_stride;
-                            m_axi_arlen   <= ((dma_src_stride == 32'd128) &&
-                                              ((dma_groups - (load_group + 32'd1)) >= 32'd8)) ?
-                                             8'd255 : 8'd31;
-                            m_axi_arvalid <= 1'b1;
-                        end
-
-                        if (dma_rd_group_word_idx == 5'd31) begin
-                            bank_loaded[dma_rd_fill_bank] <= 1'b1;
-                            load_group <= load_group + 32'd1;
-                            dma_next_rd_addr <= dma_next_rd_addr + dma_src_stride;
-                            dma_load_bank <= ~dma_load_bank;
-                        end
-
-                        if (m_axi_rlast) begin
-                            m_axi_rready <= 1'b0;
-                            if (dma_busy && ((load_group + 32'd1) < dma_groups) &&
-                                dma_rd_next_bank_free) begin
-                                dma_rd_bank   <= ~dma_rd_fill_bank;
-                                dma_rd_count  <= 8'd0;
-                                if (m_axi_arvalid && m_axi_arready) begin
-                                    m_axi_arvalid <= 1'b0;
-                                    m_axi_rready  <= 1'b1;
-                                    dma_rd_state  <= DMA_RD_DATA;
-                                end else begin
-                                    m_axi_araddr  <= dma_next_rd_addr + dma_src_stride;
-                                    m_axi_arlen   <= ((dma_src_stride == 32'd128) &&
-                                                      ((dma_groups - (load_group + 32'd1)) >= 32'd8)) ?
-                                                     8'd255 : 8'd31;
-                                    m_axi_arvalid <= 1'b1;
-                                    dma_rd_state  <= DMA_RD_ADDR;
-                                end
-                            end else begin
-                                m_axi_arvalid <= 1'b0;
-                                dma_rd_state <= DMA_RD_IDLE;
-                            end
-                        end else begin
-                            dma_rd_count <= dma_rd_count + 8'd1;
-                            if ((dma_rd_group_word_idx == 5'd31) && !dma_rd_next_bank_free)
-                                m_axi_rready <= 1'b0;
-                        end
-                    end
-                end
-                default: dma_rd_state <= DMA_RD_IDLE;
-            endcase
-
-            case (dma_wr_state)
-                DMA_WR_IDLE: begin
-                    m_axi_awvalid <= 1'b0;
-                    m_axi_wvalid  <= 1'b0;
-                    m_axi_bready  <= 1'b0;
-                end
-                DMA_WR_ADDR: begin
-                    m_axi_awvalid <= 1'b0;
-                    dma_wr_state  <= DMA_WR_DATA;
-                end
-                DMA_WR_DATA: begin
-                    m_axi_wvalid <= 1'b0;
-                    m_axi_wlast  <= 1'b0;
-                    if (dma_wr_count == 6'd47) begin
-                        bank_storing[dma_store_bank] <= 1'b0;
-                        dma_store_bank <= ~dma_store_bank;
-                        store_group <= store_group + 32'd1;
-                        completed_groups <= completed_groups + 32'd1;
-                        if ((completed_groups + 32'd1) >= dma_groups) begin
-                            dma_busy <= 1'b0;
-                            dma_done <= 1'b1;
-                        end
-                        dma_wr_state <= DMA_WR_IDLE;
+                    if (pipe_cnt < 5'd16) begin
+                        pipe_cnt <= pipe_cnt + 5'd1;
+                    end else if (cur_bank == 1'b0 && req_1) begin
+                        start_calc_bank(1'b1);
+                    end else if (cur_bank == 1'b1 && req_0) begin
+                        start_calc_bank(1'b0);
+                    end else if (acc_valid_d4 && acc_idx_d4 == 4'd15) begin
+                        busy            <= 1'b0;
+                        state           <= C_IDLE;
                     end else begin
-                        dma_wr_count <= dma_wr_count + 6'd1;
+                        pipe_cnt <= pipe_cnt + 5'd1;
                     end
                 end
-                DMA_WR_RESP: begin
-                    m_axi_bready <= 1'b0;
-                    dma_wr_state <= DMA_WR_IDLE;
-                end
-                default: dma_wr_state <= DMA_WR_IDLE;
             endcase
         end
     end

rtl/ip/mlkem/comp_decomp/comp_decomp_sync.v

@@ -1,8 +1,9 @@
 // comp_decomp_sync.v - ML-KEM coefficient compression/decompression
 //
-// Streaming: one coefficient per cycle through pipeline_reg.
+// Streaming valid/ready interface. The arithmetic is fixed-latency pipelined
+// so compression does not infer a long combinational divider/reducer.
 // mode=0: compress   — round((2^d * x) / Q) mod 2^d
-// mode=1: decompress — round((Q * x) / 2^d) mod Q
+// mode=1: decompress — round((Q * x) / 2^d)
 // Uses round-half-up (round(2.5)=3, round(3.5)=4).
 // Integer arithmetic:
 //   compress:   (x * 2^d + Q/2) / Q,  lower d bits as result
@@ -24,52 +25,175 @@ module comp_decomp_sync (
     input         ready_i
 );
 
-    // 2^d for d in {4,5,10,11}; fits in 12 bits (max 2048)
-    wire [11:0] two_pow_d;
-    assign two_pow_d = 12'd1 << d;
+    localparam [24:0] Q25 = 25'd`Q;
+    localparam [12:0] K13 = 13'd5039;   // floor(2^24 / 3329)
 
-    // Product: 12-bit * 12-bit = max 2048*3328 = 6,815,744 → 23 bits (use 24)
-    wire [23:0] product;
+    reg [11:0] data_r;
+    reg        valid_r;
 
-    // compress: x * 2^d;  decompress: x * Q
-    assign product = mode ? {12'b0, coeff_in} * {12'b0, 12'd3329}
-                          : {12'b0, coeff_in} * {12'b0, two_pow_d};
+    reg        mode_s0;
+    reg [4:0]  d_s0;
+    reg [11:0] coeff_s0;
+    reg        valid_s0;
 
-    // Rounding offset: compress→Q/2=1664; decompress→2^(d-1)
-    wire [11:0] round_off;
-    assign round_off = mode ? (two_pow_d >> 1) : 12'd1664;
+    reg        mode_s1;
+    reg [4:0]  d_s1;
+    reg [23:0] comp_dividend_s1;
+    reg [23:0] decomp_rounded_s1;
+    reg        valid_s1;
 
-    // Dividend = product + round_off  (max ~ 6,817,408 fits in 24 bits)
-    wire [23:0] dividend;
-    assign dividend = product + {12'b0, round_off};
+    reg        mode_s2;
+    reg [4:0]  d_s2;
+    reg [23:0] comp_dividend_s2;
+    (* use_dsp = "no" *) reg [36:0] comp_qprod_est_s2;
+    reg [23:0] decomp_rounded_s2;
+    reg        valid_s2;
 
-    // Divisor: compress→Q=3329; decompress→2^d
-    wire [11:0] divisor;
-    assign divisor = mode ? two_pow_d : 12'd3329;
+    reg        mode_s3;
+    reg [4:0]  d_s3;
+    reg [23:0] comp_dividend_s3;
+    reg [12:0] comp_q_est_s3;
+    reg [11:0] decomp_result_s3;
+    reg        valid_s3;
 
-    // Integer division (both ops positive → floor)
-    // Quotient is computed as 24b (widest operand) but fits in 12b
-    /* verilator lint_off WIDTH */
-    wire [11:0] div_result;
-    assign div_result = dividend / {12'b0, divisor};
-    /* verilator lint_on WIDTH */
+    reg        mode_s4;
+    reg [4:0]  d_s4;
+    reg [23:0] comp_dividend_s4;
+    reg [12:0] comp_q_est_s4;
+    (* use_dsp = "no" *) reg [24:0] comp_q_mul_q_s4;
+    reg [11:0] decomp_result_s4;
+    reg        valid_s4;
 
-    // Final modular reduction
-    // compress: lower d bits  (mask with 2^d - 1)
-    // decompress: result < Q always, but apply mod Q for safety
-    wire [11:0] mod_result;
-    assign mod_result = mode ? (div_result % 12'd3329) : (div_result & (two_pow_d - 1'b1));
+    reg        mode_s5;
+    reg [4:0]  d_s5;
+    reg [12:0] comp_q_est_s5;
+    reg [24:0] comp_rem_s5;
+    reg [11:0] decomp_result_s5;
+    reg        valid_s5;
 
-    // Pipeline through valid/ready stage
-    pipeline_reg #(.DW(12)) u_pipe (
-        .clk    (clk),
-        .rst_n  (rst_n),
-        .data_i (mod_result),
-        .valid_i(valid_i),
-        .ready_o(ready_o),
-        .data_o (coeff_out),
-        .valid_o(valid_o),
-        .ready_i(ready_i)
-    );
+    wire fire_i = valid_i && ready_o;
+
+    wire pipe_busy = valid_s0 | valid_s1 | valid_s2 | valid_s3 | valid_s4 | valid_s5;
+
+    // Fully pipelined: accept one coefficient per cycle. Every stage advances
+    // unconditionally (valid_sN <= valid_s(N-1)), and the sole consumer ties
+    // ready_i high, so the output register never needs to backpressure the
+    // pipeline. Streaming feeders (Encaps C1/C2, Decaps DECOMP) can therefore
+    // issue a new coeff every cycle instead of draining the 6-stage pipe each
+    // time. pipe_busy retained only for the legacy drain-based users' info.
+    assign ready_o   = 1'b1;
+    assign coeff_out = data_r;
+    assign valid_o   = valid_r;
+
+    wire [23:0] coeff_ext_s0 = {12'd0, coeff_s0};
+    wire [23:0] comp_dividend_next = (coeff_ext_s0 << d_s0) + 24'd1664;
+    (* use_dsp = "no" *) wire [23:0] decomp_product_next = coeff_s0 * 12'd`Q;
+    wire [23:0] decomp_round_next =
+        decomp_product_next + ((d_s0 == 5'd0) ? 24'd0 : (24'd1 << (d_s0 - 5'd1)));
+
+    wire [12:0] comp_q_corr1_s5 =
+        comp_q_est_s5 + ((comp_rem_s5 >= Q25) ? 13'd1 : 13'd0);
+    wire [24:0] comp_rem_corr1_s5 =
+        (comp_rem_s5 >= Q25) ? (comp_rem_s5 - Q25) : comp_rem_s5;
+    wire [12:0] comp_q_corr2_s5 =
+        comp_q_corr1_s5 + ((comp_rem_corr1_s5 >= Q25) ? 13'd1 : 13'd0);
+    wire [11:0] comp_mask_s5 =
+        (d_s5 == 5'd0) ? 12'd0 : (12'd1 << d_s5) - 12'd1;
+    wire [11:0] comp_result_s5 = comp_q_corr2_s5[11:0] & comp_mask_s5;
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            data_r <= 12'd0;
+            valid_r <= 1'b0;
+
+            mode_s0 <= 1'b0;
+            d_s0 <= 5'd0;
+            coeff_s0 <= 12'd0;
+            valid_s0 <= 1'b0;
+
+            mode_s1 <= 1'b0;
+            d_s1 <= 5'd0;
+            comp_dividend_s1 <= 24'd0;
+            decomp_rounded_s1 <= 24'd0;
+            valid_s1 <= 1'b0;
+
+            mode_s2 <= 1'b0;
+            d_s2 <= 5'd0;
+            comp_dividend_s2 <= 24'd0;
+            comp_qprod_est_s2 <= 37'd0;
+            decomp_rounded_s2 <= 24'd0;
+            valid_s2 <= 1'b0;
+
+            mode_s3 <= 1'b0;
+            d_s3 <= 5'd0;
+            comp_dividend_s3 <= 24'd0;
+            comp_q_est_s3 <= 13'd0;
+            decomp_result_s3 <= 12'd0;
+            valid_s3 <= 1'b0;
+
+            mode_s4 <= 1'b0;
+            d_s4 <= 5'd0;
+            comp_dividend_s4 <= 24'd0;
+            comp_q_est_s4 <= 13'd0;
+            comp_q_mul_q_s4 <= 25'd0;
+            decomp_result_s4 <= 12'd0;
+            valid_s4 <= 1'b0;
+
+            mode_s5 <= 1'b0;
+            d_s5 <= 5'd0;
+            comp_q_est_s5 <= 13'd0;
+            comp_rem_s5 <= 25'd0;
+            decomp_result_s5 <= 12'd0;
+            valid_s5 <= 1'b0;
+        end else begin
+            if (valid_r && ready_i)
+                valid_r <= 1'b0;
+
+            mode_s0 <= mode;
+            d_s0 <= d;
+            coeff_s0 <= coeff_in;
+            valid_s0 <= fire_i;
+
+            mode_s1 <= mode_s0;
+            d_s1 <= d_s0;
+            comp_dividend_s1 <= comp_dividend_next;
+            decomp_rounded_s1 <= decomp_round_next;
+            valid_s1 <= valid_s0;
+
+            mode_s2 <= mode_s1;
+            d_s2 <= d_s1;
+            comp_dividend_s2 <= comp_dividend_s1;
+            comp_qprod_est_s2 <= {13'd0, comp_dividend_s1} * K13;
+            decomp_rounded_s2 <= decomp_rounded_s1;
+            valid_s2 <= valid_s1;
+
+            mode_s3 <= mode_s2;
+            d_s3 <= d_s2;
+            comp_dividend_s3 <= comp_dividend_s2;
+            comp_q_est_s3 <= comp_qprod_est_s2[36:24];
+            decomp_result_s3 <= decomp_rounded_s2 >> d_s2;
+            valid_s3 <= valid_s2;
+
+            mode_s4 <= mode_s3;
+            d_s4 <= d_s3;
+            comp_dividend_s4 <= comp_dividend_s3;
+            comp_q_est_s4 <= comp_q_est_s3;
+            comp_q_mul_q_s4 <= comp_q_est_s3 * Q25;
+            decomp_result_s4 <= decomp_result_s3;
+            valid_s4 <= valid_s3;
+
+            mode_s5 <= mode_s4;
+            d_s5 <= d_s4;
+            comp_q_est_s5 <= comp_q_est_s4;
+            comp_rem_s5 <= {1'b0, comp_dividend_s4} - comp_q_mul_q_s4;
+            decomp_result_s5 <= decomp_result_s4;
+            valid_s5 <= valid_s4;
+
+            if (valid_s5) begin
+                data_r <= mode_s5 ? decomp_result_s5 : comp_result_s5;
+                valid_r <= 1'b1;
+            end
+        end
+    end
 
 endmodule

rtl/ip/mlkem/ntt/barrett_mul.v

@@ -6,6 +6,7 @@
 // Pure combinational, single-cycle latency.
 // All multiplication widths explicitly controlled to avoid Verilog truncation.
 
+
 (* use_dsp = "no" *)
 module barrett_mul (
     input  [11:0] a,
@@ -18,7 +19,7 @@ module barrett_mul (
 
     // Full product: a * b (both < 3329, product < 11,082,241 < 2^24)
     // Force 24-bit evaluation by extending operand
-    wire [23:0] p;
+    (* use_dsp = "no" *) wire [23:0] p;
     assign p = {12'd0, a} * b;
 
     // Extend p to 37 bits for multiplication with K
@@ -28,14 +29,14 @@ module barrett_mul (
     // Compute t_shifted = (p * K) >> 24
     // Use explicit wire for the product to control width
     /* verilator lint_off UNUSED */
-    wire [36:0] t_product;
+    (* use_dsp = "no" *) wire [36:0] t_product;
     /* verilator lint_on UNUSED */
     assign t_product = p_ext * K;
     wire [12:0] t_shifted;
     assign t_shifted = t_product[36:R];
 
     // q_approx = t_shifted * Q
-    wire [24:0] q_approx;
+    (* use_dsp = "no" *) wire [24:0] q_approx;
     assign q_approx = t_shifted * Q;
 
     // r = p - q_approx

rtl/ip/mlkem/ntt/barrett_mul_pipe.v

@@ -0,0 +1,73 @@
+// barrett_mul_pipe.v - DSP-friendly pipelined Barrett modular multiply
+//
+// Computes product = a * b mod Q with fixed latency. This module is used on
+// timing-critical NTT paths; the legacy barrett_mul remains combinational for
+// older users.
+
+(* use_dsp = "no" *)
+module barrett_mul_pipe (
+    input         clk,
+    input         rst_n,
+    input         valid_i,
+    input  [11:0] a,
+    input  [11:0] b,
+    output [11:0] product,
+    output        valid_o
+);
+    localparam [24:0] Q25 = 25'd3329;
+    localparam [12:0] K13 = 13'd5039;
+
+    (* use_dsp = "no" *) reg [23:0] p_s1;
+
+    reg [23:0] p_s2;
+    (* use_dsp = "no" *) reg [36:0] tk_s2;
+
+    reg [23:0] p_s3;
+    reg [12:0] q_s3;
+
+    reg [24:0] p_s4;
+    (* use_dsp = "no" *) reg [24:0] qprod_s4;
+
+    reg [24:0] r0_s5;
+    reg [24:0] r1_s6;
+    reg [11:0] product_r;
+    reg [6:0]  valid_sr;
+
+    assign product = product_r;
+    assign valid_o = valid_sr[6];
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            p_s1 <= 24'd0;
+            p_s2 <= 24'd0; tk_s2 <= 37'd0;
+            p_s3 <= 24'd0; q_s3 <= 13'd0;
+            p_s4 <= 25'd0; qprod_s4 <= 25'd0;
+            r0_s5 <= 25'd0; r1_s6 <= 25'd0;
+            product_r <= 12'd0;
+            valid_sr <= 7'd0;
+        end else begin
+            valid_sr <= {valid_sr[5:0], valid_i};
+
+            // S1: full product.
+            p_s1 <= {12'd0, a} * b;
+
+            // S2: quotient-estimate product.
+            p_s2  <= p_s1;
+            tk_s2 <= {13'd0, p_s1} * K13;
+
+            // S3: quotient estimate.
+            p_s3 <= p_s2;
+            q_s3 <= tk_s2[36:24];
+
+            // S4: q * Q.
+            p_s4     <= {1'b0, p_s3};
+            qprod_s4 <= q_s3 * Q25;
+
+            // S5/S6/S7: subtract q*Q and conditionally subtract Q twice.
+            r0_s5 <= p_s4 - qprod_s4;
+            r1_s6 <= (r0_s5 >= Q25) ? (r0_s5 - Q25) : r0_s5;
+            product_r <= (r1_s6 >= Q25) ? (r1_s6 - Q25) : r1_s6[11:0];
+        end
+    end
+
+endmodule

rtl/ip/mlkem/ntt/butterfly_unit_pipe.v

@@ -0,0 +1,89 @@
+// butterfly_unit_pipe.v - pipelined Cooley-Tukey / Gentleman-Sande butterfly
+//
+// Fixed-latency wrapper around barrett_mul_pipe. All arithmetic that used to
+// sit in one NTT cycle is now split by registers.
+
+module butterfly_unit_pipe (
+    input         clk,
+    input         rst_n,
+    input         valid_i,
+    input  [11:0] a,
+    input  [11:0] b,
+    input  [11:0] zeta,
+    input         mode,       // 0 = forward NTT, 1 = inverse NTT
+    output [11:0] a_out,
+    output [11:0] b_out,
+    output        valid_o
+);
+    localparam [11:0] Q12 = 12'd3329;
+    localparam [12:0] Q13 = 13'd3329;
+
+    // Plan A: register the inputs. Operands arrive combinationally from the
+    // coeff_bram read; without this stage the path coeff_bram-read -> diff ->
+    // first multiply stage sits in one cycle (the mlkem_clk critical path at
+    // 100 MHz). Registering here splits it into (BRAM read -> reg) and
+    // (reg -> diff -> multiply). Adds one pipeline cycle (absorbed by the NTT
+    // writeback delay line).
+    reg [11:0] a_r, b_r, zeta_r;
+    reg        mode_ri, vld_r;
+
+    wire [11:0] diff = (b_r >= a_r) ? (b_r - a_r) : (b_r - a_r + Q12);
+    wire [11:0] mul_data = mode_ri ? diff : b_r;
+
+    wire [11:0] mul_result;
+    wire        mul_valid;
+    barrett_mul_pipe u_barrett (
+        .clk(clk),
+        .rst_n(rst_n),
+        .valid_i(vld_r),
+        .a(zeta_r),
+        .b(mul_data),
+        .product(mul_result),
+        .valid_o(mul_valid)
+    );
+
+    // a/b/mode delay lines (fed from the REGISTERED inputs a_r/b_r/mode_ri so
+    // a_d6 aligns with mul_valid = valid_i delayed 8).
+    reg [11:0] a_d0, a_d1, a_d2, a_d3, a_d4, a_d5, a_d6;
+    reg [11:0] b_d0, b_d1, b_d2, b_d3, b_d4, b_d5, b_d6;
+    reg        mode_d0, mode_d1, mode_d2, mode_d3, mode_d4, mode_d5, mode_d6;
+
+    reg [11:0] a_out_r, b_out_r;
+    reg        valid_r;
+
+    wire [12:0] a_sum = {1'b0, a_d6} + {1'b0, (mode_d6 ? b_d6 : mul_result)};
+    wire [11:0] a_mod = (a_sum >= Q13) ? (a_sum[11:0] - Q12) : a_sum[11:0];
+    wire [11:0] b_sub = (a_d6 >= mul_result) ? (a_d6 - mul_result) :
+                                                 (a_d6 - mul_result + Q12);
+
+    assign a_out = a_out_r;
+    assign b_out = b_out_r;
+    assign valid_o = valid_r;
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            a_r <= 12'd0; b_r <= 12'd0; zeta_r <= 12'd0; mode_ri <= 1'b0; vld_r <= 1'b0;
+            a_d0 <= 12'd0; a_d1 <= 12'd0; a_d2 <= 12'd0; a_d3 <= 12'd0; a_d4 <= 12'd0; a_d5 <= 12'd0; a_d6 <= 12'd0;
+            b_d0 <= 12'd0; b_d1 <= 12'd0; b_d2 <= 12'd0; b_d3 <= 12'd0; b_d4 <= 12'd0; b_d5 <= 12'd0; b_d6 <= 12'd0;
+            mode_d0 <= 1'b0; mode_d1 <= 1'b0; mode_d2 <= 1'b0; mode_d3 <= 1'b0; mode_d4 <= 1'b0; mode_d5 <= 1'b0; mode_d6 <= 1'b0;
+            a_out_r <= 12'd0;
+            b_out_r <= 12'd0;
+            valid_r <= 1'b0;
+        end else begin
+            // input register stage
+            a_r <= a; b_r <= b; zeta_r <= zeta; mode_ri <= mode; vld_r <= valid_i;
+
+            a_d0 <= a_r;  a_d1 <= a_d0;    a_d2 <= a_d1;    a_d3 <= a_d2;    a_d4 <= a_d3;    a_d5 <= a_d4;    a_d6 <= a_d5;
+            b_d0 <= b_r;  b_d1 <= b_d0;    b_d2 <= b_d1;    b_d3 <= b_d2;    b_d4 <= b_d3;    b_d5 <= b_d4;    b_d6 <= b_d5;
+            mode_d0 <= mode_ri; mode_d1 <= mode_d0; mode_d2 <= mode_d1;
+            mode_d3 <= mode_d2; mode_d4 <= mode_d3; mode_d5 <= mode_d4; mode_d6 <= mode_d5;
+
+            valid_r <= mul_valid;
+            if (mul_valid) begin
+                a_out_r <= a_mod;
+                b_out_r <= mode_d6 ? mul_result : b_sub;
+            end
+        end
+    end
+
+endmodule

rtl/ip/mlkem/ntt/coeff_bram_4way.v

@@ -0,0 +1,113 @@
+// coeff_bram_4way.v - 4-way conflict-free banked storage for NTT coefficients
+//
+// Replaces the 256x12 LUT register file (reg [11:0] cr [0:255]) with 4 BRAM
+// banks (each 128x12 via sd_bram), removing the large multi-port LUT mux tree.
+//
+// Bank function: bank(a) = { a[0], ^a[7:1] }   (bit0 XOR parity of upper 7 bits)
+//   local(a)   = a[7:1]   (7-bit index into the 128-deep bank)
+//
+// This function makes a dual-butterfly's four simultaneous coefficient accesses
+// {j, j+1, j+len, j+1+len} land in four DISTINCT banks for every ML-KEM NTT
+// layer_len in {2,4,...,128}: j is even and len is even, so
+//   j        -> {0, P }
+//   j+1      -> {1, P }
+//   j+len    -> {0, P'}   (flipping bit m>=1 flips the upper-bits parity)
+//   j+1+len  -> {1, P'}
+// with P != P'. Four distinct banks => 4 conflict-free reads/cycle from four
+// single-read-port banks, and likewise 4 conflict-free writes/cycle. Each bank
+// therefore needs only 1 read + 1 write per cycle (an sd_bram), no ping-pong.
+//
+// Read latency is 1 cycle (sd_bram registered read): present rd_addr_k this
+// cycle, rd_data_k valid next cycle. Writes commit on the presenting cycle.
+//
+// NOTE: the caller must guarantee the four read addresses map to four distinct
+// banks (true for the NTT butterfly pattern) and the four write addresses too.
+// Sequential access (load/output) uses a single port and is always safe.
+
+module coeff_bram_4way (
+    input         clk, rst_n,
+    // Four read addresses (global 8-bit); data returns 1 cycle later.
+    input  [7:0]  rd_addr_0, rd_addr_1, rd_addr_2, rd_addr_3,
+    output [11:0] rd_data_0, rd_data_1, rd_data_2, rd_data_3,
+    // Four write ports.
+    input         wr_en_0, wr_en_1, wr_en_2, wr_en_3,
+    input  [7:0]  wr_addr_0, wr_addr_1, wr_addr_2, wr_addr_3,
+    input  [11:0] wr_data_0, wr_data_1, wr_data_2, wr_data_3
+);
+
+    // Bank id and local index for an address.
+    function [1:0] bank_id;
+        input [7:0] a;
+        bank_id = {a[0], ^a[7:1]};
+    endfunction
+
+    wire [1:0] rb0 = bank_id(rd_addr_0);
+    wire [1:0] rb1 = bank_id(rd_addr_1);
+    wire [1:0] rb2 = bank_id(rd_addr_2);
+    wire [1:0] rb3 = bank_id(rd_addr_3);
+
+    wire [1:0] wb0 = bank_id(wr_addr_0);
+    wire [1:0] wb1 = bank_id(wr_addr_1);
+    wire [1:0] wb2 = bank_id(wr_addr_2);
+    wire [1:0] wb3 = bank_id(wr_addr_3);
+
+    // Per-bank read-address crossbar: bank b reads the local index of whichever
+    // read port targets it (exactly one, by construction).
+    wire [6:0] bank_rd_local [0:3];
+    wire [6:0] bank_wr_local [0:3];
+    wire       bank_wr_en    [0:3];
+    wire [11:0] bank_wr_data  [0:3];
+    wire [11:0] bank_rd_data  [0:3];
+
+    genvar b;
+    generate
+        for (b = 0; b < 4; b = b + 1) begin : gen_xbar
+            // read address route (priority: 3>2>1>0; ties impossible for NTT)
+            assign bank_rd_local[b] =
+                (rb3 == b[1:0]) ? rd_addr_3[7:1] :
+                (rb2 == b[1:0]) ? rd_addr_2[7:1] :
+                (rb1 == b[1:0]) ? rd_addr_1[7:1] :
+                                  rd_addr_0[7:1];
+            // write route
+            wire m0 = wr_en_0 && (wb0 == b[1:0]);
+            wire m1 = wr_en_1 && (wb1 == b[1:0]);
+            wire m2 = wr_en_2 && (wb2 == b[1:0]);
+            wire m3 = wr_en_3 && (wb3 == b[1:0]);
+            assign bank_wr_en[b]   = m0 | m1 | m2 | m3;
+            assign bank_wr_local[b] =
+                m3 ? wr_addr_3[7:1] :
+                m2 ? wr_addr_2[7:1] :
+                m1 ? wr_addr_1[7:1] : wr_addr_0[7:1];
+            assign bank_wr_data[b] =
+                m3 ? wr_data_3 :
+                m2 ? wr_data_2 :
+                m1 ? wr_data_1 : wr_data_0;
+
+            sd_bram #(.W(12), .D(128), .A(7)) u_bank (
+                .clk(clk),
+                .rd_addr(bank_rd_local[b]),
+                .rd_data(bank_rd_data[b]),
+                .wr_en(bank_wr_en[b]),
+                .wr_addr(bank_wr_local[b]),
+                .wr_data(bank_wr_data[b])
+            );
+        end
+    endgenerate
+
+    // Register the read bank-ids to align with sd_bram's 1-cycle read latency,
+    // then route each bank's output back to the requesting read port.
+    reg [1:0] rb0_r, rb1_r, rb2_r, rb3_r;
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            rb0_r <= 2'd0; rb1_r <= 2'd0; rb2_r <= 2'd0; rb3_r <= 2'd0;
+        end else begin
+            rb0_r <= rb0; rb1_r <= rb1; rb2_r <= rb2; rb3_r <= rb3;
+        end
+    end
+
+    assign rd_data_0 = bank_rd_data[rb0_r];
+    assign rd_data_1 = bank_rd_data[rb1_r];
+    assign rd_data_2 = bank_rd_data[rb2_r];
+    assign rd_data_3 = bank_rd_data[rb3_r];
+
+endmodule

rtl/ip/mlkem/ntt/ntt_core.v

@@ -1,8 +1,18 @@
-// ntt_core.v - NTT core with individual coefficient registers
+// ntt_core.v - NTT core with 4-way banked BRAM coefficient storage
 //
-// Uses 256 individual 12-bit registers and generate-based muxing
-// to avoid any part-select simulation issues.
-// 3-cycle butterfly: SetAddr -> Read -> Compute+Write
+// Coefficient storage moved from a 256x12 LUT register file to coeff_bram_4way
+// (4 x 128x12 sd_bram, conflict-free banked). This removes the large multi-port
+// LUT mux tree. Two pipelined butterflies (R1) still issue one pair/cycle.
+//
+// Because BRAM reads are synchronous (1-cycle latency), the compute pipeline
+// gains one stage:
+//   READ (present rd addrs from j) -> FEED butterflies (t+1, rd_data valid)
+//   -> 8-stage Barrett butterfly -> WRITEBACK (t+9) into the write buffer.
+// Read and writeback hit disjoint banks (butterfly index sets in a layer are
+// disjoint), so each bank does 1 read + 1 write per cycle (sd_bram = 1R1W).
+//
+// LOAD/OUTPUT/OUT_SCALE stream through a single bank port with 1-cycle read
+// latency (ready_i is tied high by all NTT consumers, so no output backpressure).
 
 module ntt_core (
     input         clk, rst_n,
@@ -17,116 +27,270 @@ module ntt_core (
 );
     localparam N = 256, LAYERS = 7, DW = 12;
 
-    // Individual coefficient registers
-    reg [DW-1:0] cr [0:N-1];
-    integer ci;
+    localparam S_IDLE      = 4'd0;
+    localparam S_LOAD      = 4'd1;
+    localparam S_CMP_RUN   = 4'd2;
+    localparam S_CMP_DRAIN = 4'd3;
+    localparam S_OUT_PREP  = 4'd7;
+    localparam S_OUTPUT    = 4'd8;
+    localparam S_OUT_SCALE = 4'd9;
+    localparam S_DONE      = 4'd10;
 
-    // State machine
-    localparam S_IDLE=3'd0, S_LOAD=3'd1, S_CMP_A=3'd2, S_CMP_B=3'd3,
-               S_CMP_C=3'd4, S_OUTPUT=3'd5, S_DONE=3'd6;
-    reg [2:0] state, next_state;
+    reg [3:0] state, next_state;
 
-    reg [7:0] load_cnt, out_cnt;
+    reg [7:0] load_cnt;
+    reg [8:0] out_rptr;        // output read address pointer (0..256)
+    reg [8:0] out_cnt;         // output coeffs emitted (0..256)
+    reg [8:0] scale_rptr;      // scale read address pointer
+    reg [8:0] scale_issue_cnt; // coeffs fed to scale barrett
+    reg [8:0] scale_emit_cnt;  // coeffs emitted from scale barrett
     reg [7:0] j, start, layer_len;
     reg [6:0] zeta_idx;
     reg [2:0] layer;
-    reg bf_done;
+    reg       mode_r;
+    reg       layer_issue_done;
+    reg [5:0] bf_inflight;
 
-    // Pipeline registers
-    reg [DW-1:0] r_a, r_b;
-    reg [7:0] r_wa, r_wb;
+    reg       rd_fire_r;       // issue_fire delayed 1 (BRAM read latency) -> feed
+    // 9-deep writeback address delay lines (BRAM read + 8-stage butterfly).
+    reg [7:0] a0d[0:9]; reg [7:0] b0d[0:9];
+    reg [7:0] a1d[0:9]; reg [7:0] b1d[0:9];
+    integer k;
+
+    reg [DW-1:0] coeff_out_r;
+    reg          valid_o_r;
+    reg          scale_valid_i;
+    reg [DW-1:0] scale_a_i;
+    reg [DW-1:0] zeta_fed;     // zeta aligned to BRAM read data (1 cyc after present)
 
-    // Zeta
     wire [DW-1:0] zeta;
     zeta_rom u_z (.addr(zeta_idx), .zeta(zeta));
 
-    // Butterfly
-    wire [DW-1:0] bf_a_out, bf_b_out;
-    butterfly_unit u_bf (
-        .a(r_a), .b(r_b), .zeta(zeta), .mode(mode),
-        .a_out(bf_a_out), .b_out(bf_b_out));
+    wire [8:0] group_end        = {1'b0, start} + {1'b0, layer_len};
+    wire [8:0] next_group_start = {1'b0, start} + {1'b0, layer_len} + {1'b0, layer_len};
+    wire       issue_group_last = ({1'b0, j} + 9'd2 >= group_end);
+    wire       issue_layer_last = issue_group_last && (next_group_start >= 9'd256);
+    wire [7:0] next_layer_len   = mode_r ? (layer_len << 1) : (layer_len >> 1);
+    wire       issue_fire       = (state == S_CMP_RUN) && !layer_issue_done;
 
-    // Output scaling
-    wire [DW-1:0] coeff_scaled;
-    barrett_mul u_scl (.a(cr[out_cnt]), .b(12'd3303), .product(coeff_scaled));
-    assign coeff_out = mode ? coeff_scaled : cr[out_cnt];
+    // ---- coeff_bram_4way port muxing ----
+    // Read addr 0 is shared by compute (j), output (out_rptr), scale (scale_rptr).
+    wire [7:0] cmp_a0 = j;
+    wire [7:0] cmp_b0 = j + layer_len;
+    wire [7:0] cmp_a1 = j + 8'd1;
+    wire [7:0] cmp_b1 = j + 8'd1 + layer_len;
 
+    wire [7:0] rd_addr_0 = (state == S_OUT_PREP || state == S_OUTPUT) ? out_rptr[7:0]   :
+                           (state == S_OUT_SCALE)                     ? scale_rptr[7:0] : cmp_a0;
+    // Ports 1..3 carry the other three butterfly operands ONLY during compute;
+    // otherwise they must mirror port 0 so the read crossbar's per-bank priority
+    // arbitration doesn't route a stale compute address into port 0's bank.
+    wire cmp_rd = (state == S_CMP_RUN) || (state == S_CMP_DRAIN);
+    wire [7:0] rd_addr_1 = cmp_rd ? cmp_b0 : rd_addr_0;
+    wire [7:0] rd_addr_2 = cmp_rd ? cmp_a1 : rd_addr_0;
+    wire [7:0] rd_addr_3 = cmp_rd ? cmp_b1 : rd_addr_0;
+    wire [11:0] rd_data_0, rd_data_1, rd_data_2, rd_data_3;
 
-    assign ready_o = (state == S_IDLE) || (state == S_LOAD);
-    assign valid_o = (state == S_OUTPUT);
-    assign done_o  = (state == S_DONE);
+    // Butterflies fed from BRAM read data one cycle after the address (rd_fire_r).
+    wire [DW-1:0] bf0_a_out, bf0_b_out, bf1_a_out, bf1_b_out;
+    wire          bf0_valid, bf1_valid;
+    butterfly_unit_pipe u_bf0 (
+        .clk(clk), .rst_n(rst_n),
+        .valid_i(rd_fire_r),
+        .a(rd_data_0), .b(rd_data_1),
+        .zeta(zeta_fed), .mode(mode_r),
+        .a_out(bf0_a_out), .b_out(bf0_b_out), .valid_o(bf0_valid)
+    );
+    butterfly_unit_pipe u_bf1 (
+        .clk(clk), .rst_n(rst_n),
+        .valid_i(rd_fire_r),
+        .a(rd_data_2), .b(rd_data_3),
+        .zeta(zeta_fed), .mode(mode_r),
+        .a_out(bf1_a_out), .b_out(bf1_b_out), .valid_o(bf1_valid)
+    );
+    // zeta must align with the BRAM read data (1 cycle after presentation).
+
+    // Scale multiplier (inverse NTT final x3303).
+    wire [DW-1:0] scale_product;
+    wire          scale_valid_o;
+    barrett_mul_pipe u_scl (
+        .clk(clk), .rst_n(rst_n),
+        .valid_i(scale_valid_i),
+        .a(scale_a_i), .b(12'd3303),
+        .product(scale_product), .valid_o(scale_valid_o)
+    );
+
+    // ---- write ports ----
+    wire loading_we = (state == S_IDLE && valid_i) || (state == S_LOAD && valid_i);
+    wire [7:0] load_addr = (state == S_IDLE) ? 8'd0 : load_cnt;
+
+    wire wr_en_0 = loading_we | bf0_valid;
+    wire wr_en_1 = bf0_valid & ~loading_we;
+    wire wr_en_2 = bf0_valid & ~loading_we;
+    wire wr_en_3 = bf0_valid & ~loading_we;
+    wire [7:0]  wr_addr_0 = loading_we ? load_addr : a0d[9];
+    wire [7:0]  wr_addr_1 = b0d[9];
+    wire [7:0]  wr_addr_2 = a1d[9];
+    wire [7:0]  wr_addr_3 = b1d[9];
+    wire [11:0] wr_data_0 = loading_we ? coeff_in : bf0_a_out;
+    wire [11:0] wr_data_1 = bf0_b_out;
+    wire [11:0] wr_data_2 = bf1_a_out;
+    wire [11:0] wr_data_3 = bf1_b_out;
+
+    coeff_bram_4way u_cr (
+        .clk(clk), .rst_n(rst_n),
+        .rd_addr_0(rd_addr_0), .rd_addr_1(rd_addr_1),
+        .rd_addr_2(rd_addr_2), .rd_addr_3(rd_addr_3),
+        .rd_data_0(rd_data_0), .rd_data_1(rd_data_1),
+        .rd_data_2(rd_data_2), .rd_data_3(rd_data_3),
+        .wr_en_0(wr_en_0), .wr_en_1(wr_en_1), .wr_en_2(wr_en_2), .wr_en_3(wr_en_3),
+        .wr_addr_0(wr_addr_0), .wr_addr_1(wr_addr_1),
+        .wr_addr_2(wr_addr_2), .wr_addr_3(wr_addr_3),
+        .wr_data_0(wr_data_0), .wr_data_1(wr_data_1),
+        .wr_data_2(wr_data_2), .wr_data_3(wr_data_3)
+    );
+
+    assign ready_o   = (state == S_IDLE) || (state == S_LOAD);
+    // During forward OUTPUT, drive coeff_out straight from the BRAM read (1-cycle
+    // latency, matching the old combinational-read + 1 output reg). Scale path
+    // uses the registered barrett result.
+    assign coeff_out = (state == S_OUTPUT) ? rd_data_0 : coeff_out_r;
+    assign valid_o   = valid_o_r;
+    assign done_o    = (state == S_DONE);
 
     always @* begin
         next_state = state;
         case (state)
-            S_IDLE:  if (valid_i) next_state = S_LOAD;
-            S_LOAD:  if (load_cnt >= 255 && valid_i) next_state = S_CMP_A;
-            S_CMP_A: if (bf_done) next_state = S_OUTPUT; else next_state = S_CMP_B;
-            S_CMP_B: if (bf_done) next_state = S_OUTPUT; else next_state = S_CMP_C;
-            S_CMP_C: if (bf_done) next_state = S_OUTPUT; else next_state = S_CMP_A;
-            S_OUTPUT:if (out_cnt >= 255 && ready_i) next_state = S_DONE;
-            S_DONE:  next_state = S_IDLE;
-            default: next_state = S_IDLE;
+            S_IDLE:      if (valid_i) next_state = S_LOAD;
+            S_LOAD:      if (load_cnt >= 8'd255 && valid_i) next_state = S_CMP_RUN;
+            S_CMP_RUN:   if (layer_issue_done) next_state = S_CMP_DRAIN;
+            S_CMP_DRAIN: if (bf_inflight == 6'd0)
+                              next_state = (layer + 3'd1 >= LAYERS) ? S_OUT_PREP : S_CMP_RUN;
+            S_OUT_PREP:  next_state = mode_r ? S_OUT_SCALE : S_OUTPUT;
+            S_OUTPUT:    if (out_cnt >= 9'd256) next_state = S_DONE;
+            S_OUT_SCALE: if (scale_emit_cnt >= 9'd256) next_state = S_DONE;
+            S_DONE:      next_state = S_IDLE;
+            default:     next_state = S_IDLE;
         endcase
     end
 
     always @(posedge clk or negedge rst_n) begin
         if (!rst_n) begin
-            state<=S_IDLE; load_cnt<=0; out_cnt<=0; j<=0; start<=0; layer_len<=0;
-            zeta_idx<=0; layer<=0; bf_done<=0; r_a<=0; r_b<=0; r_wa<=0; r_wb<=0;
-            for (ci=0; ci<N; ci=ci+1) cr[ci] = 0;
+            state <= S_IDLE;
+            load_cnt <= 8'd0;
+            out_rptr <= 9'd0; out_cnt <= 9'd0;
+            scale_rptr <= 9'd0; scale_issue_cnt <= 9'd0; scale_emit_cnt <= 9'd0;
+            j <= 8'd0; start <= 8'd0; layer_len <= 8'd0;
+            zeta_idx <= 7'd0; zeta_fed <= 12'd0;
+            layer <= 3'd0; mode_r <= 1'b0;
+            layer_issue_done <= 1'b0; bf_inflight <= 6'd0;
+            rd_fire_r <= 1'b0;
+            for (k = 0; k <= 9; k = k + 1) begin
+                a0d[k] <= 8'd0; b0d[k] <= 8'd0; a1d[k] <= 8'd0; b1d[k] <= 8'd0;
+            end
+            coeff_out_r <= 12'd0; valid_o_r <= 1'b0;
+            scale_valid_i <= 1'b0; scale_a_i <= 12'd0;
         end else begin
             state <= next_state;
+            scale_valid_i <= 1'b0;
+
+            // read->feed pipeline register (BRAM latency) + zeta alignment
+            rd_fire_r <= issue_fire;
+            zeta_fed  <= zeta;
+
+            // writeback address delay lines: sample j-derived addrs at read cycle
+            a0d[0] <= cmp_a0; b0d[0] <= cmp_b0; a1d[0] <= cmp_a1; b1d[0] <= cmp_b1;
+            for (k = 1; k <= 9; k = k + 1) begin
+                a0d[k] <= a0d[k-1]; b0d[k] <= b0d[k-1];
+                a1d[k] <= a1d[k-1]; b1d[k] <= b1d[k-1];
+            end
+
+            // in-flight pair accounting: +1 on issue, -1 on writeback
+            if (issue_fire && !bf0_valid)      bf_inflight <= bf_inflight + 6'd1;
+            else if (!issue_fire && bf0_valid) bf_inflight <= bf_inflight - 6'd1;
+
+            if (state != S_OUTPUT && state != S_OUT_SCALE)
+                valid_o_r <= 1'b0;
 
             if (state == S_IDLE && valid_i) begin
-                cr[0] <= coeff_in;
-                load_cnt<=1; out_cnt<=0; j<=0; start<=0; layer<=0; bf_done<=0;
-                if (!mode) begin layer_len<=128; zeta_idx<=1; end
-                else       begin layer_len<=2;   zeta_idx<=127; end
+                load_cnt <= 8'd1;
+                out_rptr <= 9'd0; out_cnt <= 9'd0;
+                scale_rptr <= 9'd0; scale_issue_cnt <= 9'd0; scale_emit_cnt <= 9'd0;
+                j <= 8'd0; start <= 8'd0; layer <= 3'd0;
+                layer_issue_done <= 1'b0; bf_inflight <= 6'd0;
+                mode_r <= mode;
+                if (!mode) begin layer_len <= 8'd128; zeta_idx <= 7'd1; end
+                else       begin layer_len <= 8'd2;   zeta_idx <= 7'd127; end
             end
 
-            if (state == S_LOAD && valid_i) begin
-                cr[load_cnt] <= coeff_in;
-                load_cnt <= load_cnt + 8'd1;
-            end
+            if (state == S_LOAD && valid_i) load_cnt <= load_cnt + 8'd1;
 
-            // S_CMP_A: set read addresses (j, j+len)
-            if (state == S_CMP_A) begin
-                r_wa <= j;
-                r_wb <= j + layer_len;
-            end
-
-            // S_CMP_B: capture read data
-            if (state == S_CMP_B) begin
-                r_a <= cr[j];
-                r_b <= cr[j + layer_len];
-            end
-
-            // S_CMP_C: write butterfly results, advance counters
-            if (state == S_CMP_C) begin
-                cr[r_wa] <= bf_a_out;
-                cr[r_wb] <= bf_b_out;
-
-                j <= j + 8'd1;
-                if (j + 8'd1 >= start + layer_len) begin
-                    if (!mode) zeta_idx <= zeta_idx + 7'd1;
-                    else       zeta_idx <= zeta_idx - 7'd1;
-
-                    if ({1'b0,start} + {1'b0,layer_len} + {1'b0,layer_len} >= 256) begin
-                        layer <= layer + 3'd1;
-                        layer_len <= mode ? (layer_len<<1) : (layer_len>>1);
-                        start <= 0; j <= 0;
-                        if (layer + 3'd1 >= LAYERS) bf_done <= 1'b1;
-                    end else begin
-                        start <= start + layer_len + layer_len;
-                        j <= start + layer_len + layer_len;
-                    end
+            // ---- issue advance (read pointer j, step 2) ----
+            if (state == S_CMP_RUN && !layer_issue_done) begin
+                if (issue_group_last) begin
+                    if (!mode_r) zeta_idx <= zeta_idx + 7'd1;
+                    else         zeta_idx <= zeta_idx - 7'd1;
+                    if (issue_layer_last) layer_issue_done <= 1'b1;
+                    else begin start <= next_group_start[7:0]; j <= next_group_start[7:0]; end
+                end else begin
+                    j <= j + 8'd2;
                 end
             end
 
-            if (state == S_OUTPUT && ready_i)
-                out_cnt <= (out_cnt>=255) ? 0 : (out_cnt+8'd1);
+            // ---- layer advance after drain ----
+            if (state == S_CMP_DRAIN && bf_inflight == 6'd0) begin
+                if (layer + 3'd1 < LAYERS) begin
+                    layer <= layer + 3'd1;
+                    layer_len <= next_layer_len;
+                    start <= 8'd0; j <= 8'd0;
+                    layer_issue_done <= 1'b0;
+                end
+            end
+
+            // ---- OUT_PREP: reset output pointers ----
+            if (state == S_OUT_PREP) begin
+                out_rptr <= 9'd0; out_cnt <= 9'd0;
+                scale_rptr <= 9'd1; scale_issue_cnt <= 9'd0; scale_emit_cnt <= 9'd0;
+                // (scale first addr 0 is presented via out_rptr in this PREP cycle)
+            end
+
+            // ---- OUTPUT: stream coeffs. coeff_out is combinational rd_data_0;
+            // valid_o is a registered "presented a valid addr last cycle". Present
+            // addresses out_rptr = 0..255 (256), giving 256 valid outputs. ----
+            if (state == S_OUTPUT) begin
+                if (out_rptr < 9'd256) begin
+                    out_rptr  <= out_rptr + 9'd1;   // present rd_addr_0 = out_rptr
+                    valid_o_r <= 1'b1;              // data valid next cycle
+                end else begin
+                    valid_o_r <= 1'b0;
+                end
+                if (valid_o_r) out_cnt <= out_cnt + 9'd1;   // count emitted
+            end
+
+            // ---- OUT_SCALE: read coeff, x3303 via barrett, emit ----
+            if (state == S_OUT_SCALE) begin
+                if (scale_rptr < 9'd256) scale_rptr <= scale_rptr + 9'd1;
+                // feed barrett with the coeff that arrived this cycle
+                if (scale_issue_cnt < 9'd256) begin
+                    scale_valid_i <= 1'b1;
+                    scale_a_i <= rd_data_0;
+                    scale_issue_cnt <= scale_issue_cnt + 9'd1;
+                end
+                valid_o_r <= 1'b0;
+                if (scale_valid_o) begin
+                    coeff_out_r <= scale_product;
+                    valid_o_r <= 1'b1;
+                    scale_emit_cnt <= scale_emit_cnt + 9'd1;
+                end
+            end
+
+            if (state == S_DONE) begin
+                load_cnt <= 8'd0;
+                out_rptr <= 9'd0; out_cnt <= 9'd0;
+                scale_rptr <= 9'd0; scale_issue_cnt <= 9'd0; scale_emit_cnt <= 9'd0;
+                layer_issue_done <= 1'b0; bf_inflight <= 6'd0;
+                valid_o_r <= 1'b0;
+            end
         end
     end
-
 endmodule

rtl/ip/mlkem/poly_mul/basecase_mul_pipe.v

@@ -0,0 +1,144 @@
+// basecase_mul_pipe.v - pipelined NTT-domain degree-1 multiplication
+//
+// Fixed-latency replacement for the combinational basecase_mul hot path.
+// The shared ntt/barrett_mul remains combinational for NTT users; this module
+// keeps the extra registers local to poly_mul_sync.
+
+(* use_dsp = "no" *)
+module basecase_mul_pipe (
+    input         clk,
+    input         rst_n,
+    input         valid_i,
+    input  [11:0] a0, a1,
+    input  [11:0] b0, b1,
+    input  [11:0] zeta,
+    output [11:0] c0,
+    output [11:0] c1,
+    output        valid_o
+);
+    localparam [11:0] Q12 = 12'd3329;
+    localparam [12:0] K13 = 13'd5039;
+    localparam [24:0] Q25 = 25'd3329;
+
+    function [12:0] barrett_q;
+        input [23:0] p;
+        (* use_dsp = "no" *) reg [36:0] prod;
+        begin
+            prod = {13'd0, p} * K13;
+            barrett_q = prod[36:24];
+        end
+    endfunction
+
+    function [11:0] barrett_reduce;
+        input [23:0] p;
+        input [12:0] qe;
+        (* use_dsp = "no" *) reg [24:0] q_approx;
+        reg   [24:0] r0;
+        reg   [24:0] r1;
+        reg   [24:0] r2;
+        begin
+            q_approx = qe * Q12;
+            r0 = {1'b0, p} - q_approx;
+            r1 = (r0 >= Q25) ? (r0 - Q25) : r0;
+            r2 = (r1 >= Q25) ? (r1 - Q25) : r1;
+            barrett_reduce = r2[11:0];
+        end
+    endfunction
+
+    function [11:0] mod_add;
+        input [11:0] x;
+        input [11:0] y;
+        reg   [12:0] sum;
+        begin
+            sum = {1'b0, x} + {1'b0, y};
+            mod_add = (sum >= {1'b0, Q12}) ? (sum[11:0] - Q12) : sum[11:0];
+        end
+    endfunction
+
+    // Stage 1: first-level scalar products.
+    (* use_dsp = "no" *) reg [23:0] p10, p11, p12, p13;
+    reg [11:0] zeta_s1;
+
+    // Stage 2: Barrett quotient estimates for first-level products.
+    reg [23:0] p20, p21, p22, p23;
+    reg [12:0] q20, q21, q22, q23;
+    reg [11:0] zeta_s2;
+
+    // Stage 3: first-level reduced products.
+    reg [11:0] t1_s3, t2_s3, t3_s3, t4_s3;
+    reg [11:0] zeta_s3;
+
+    // Stage 4: zeta product for c0's second Barrett multiply.
+    reg [11:0] t1_s4, t3_s4, t4_s4;
+    (* use_dsp = "no" *) reg [23:0] pz_s4;
+
+    // Stage 5: Barrett quotient estimate for zeta product.
+    reg [11:0] t1_s5, t3_s5, t4_s5;
+    reg [23:0] pz_s5;
+    reg [12:0] qz_s5;
+
+    // Stage 6: reduced zeta product.
+    reg [11:0] t1_s6, t3_s6, t4_s6, tz_s6;
+
+    // Stage 7: final modular additions.
+    reg [11:0] c0_r, c1_r;
+    reg [6:0]  valid_sr;
+
+    assign c0 = c0_r;
+    assign c1 = c1_r;
+    assign valid_o = valid_sr[6];
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            p10 <= 24'd0; p11 <= 24'd0; p12 <= 24'd0; p13 <= 24'd0; zeta_s1 <= 12'd0;
+            p20 <= 24'd0; p21 <= 24'd0; p22 <= 24'd0; p23 <= 24'd0;
+            q20 <= 13'd0; q21 <= 13'd0; q22 <= 13'd0; q23 <= 13'd0; zeta_s2 <= 12'd0;
+            t1_s3 <= 12'd0; t2_s3 <= 12'd0; t3_s3 <= 12'd0; t4_s3 <= 12'd0; zeta_s3 <= 12'd0;
+            t1_s4 <= 12'd0; t3_s4 <= 12'd0; t4_s4 <= 12'd0; pz_s4 <= 24'd0;
+            t1_s5 <= 12'd0; t3_s5 <= 12'd0; t4_s5 <= 12'd0; pz_s5 <= 24'd0; qz_s5 <= 13'd0;
+            t1_s6 <= 12'd0; t3_s6 <= 12'd0; t4_s6 <= 12'd0; tz_s6 <= 12'd0;
+            c0_r <= 12'd0; c1_r <= 12'd0; valid_sr <= 7'd0;
+        end else begin
+            valid_sr <= {valid_sr[5:0], valid_i};
+
+            p10 <= {12'd0, a0} * b0;
+            p11 <= {12'd0, a1} * b1;
+            p12 <= {12'd0, a1} * b0;
+            p13 <= {12'd0, a0} * b1;
+            zeta_s1 <= zeta;
+
+            p20 <= p10; p21 <= p11; p22 <= p12; p23 <= p13;
+            q20 <= barrett_q(p10);
+            q21 <= barrett_q(p11);
+            q22 <= barrett_q(p12);
+            q23 <= barrett_q(p13);
+            zeta_s2 <= zeta_s1;
+
+            t1_s3 <= barrett_reduce(p20, q20);
+            t2_s3 <= barrett_reduce(p21, q21);
+            t3_s3 <= barrett_reduce(p22, q22);
+            t4_s3 <= barrett_reduce(p23, q23);
+            zeta_s3 <= zeta_s2;
+
+            t1_s4 <= t1_s3;
+            t3_s4 <= t3_s3;
+            t4_s4 <= t4_s3;
+            pz_s4 <= {12'd0, t2_s3} * zeta_s3;
+
+            t1_s5 <= t1_s4;
+            t3_s5 <= t3_s4;
+            t4_s5 <= t4_s4;
+            pz_s5 <= pz_s4;
+            qz_s5 <= barrett_q(pz_s4);
+
+            t1_s6 <= t1_s5;
+            t3_s6 <= t3_s5;
+            t4_s6 <= t4_s5;
+            tz_s6 <= barrett_reduce(pz_s5, qz_s5);
+
+            c0_r <= mod_add(t1_s6, tz_s6);
+            c1_r <= mod_add(t3_s6, t4_s6);
+        end
+    end
+
+endmodule