This repository has been archived on 2026-08-21 . You can view files and clone it. You cannot open issues or pull requests or push a commit.
69de12e79f411f50eb1931b672a8b25293d54127
Description
No description provided
Languages
Verilog
46.5%
C
27.8%
Assembly
20.5%
SystemVerilog
3.3%
Python
0.7%
Other
1.2%