remove dsp usage
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@@ -98,6 +98,9 @@ module cdma_matmul_bridge #(
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logic [1:0] bank_store_pending;
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logic [1:0] bank_store_active;
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logic [31:0] bank_group_idx [2];
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logic [31:0] load_next_src_addr;
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logic [31:0] load_next_dst_addr;
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logic [31:0] bank_dst_addr [2];
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logic rd_busy;
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logic wr_busy;
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@@ -250,6 +253,10 @@ module cdma_matmul_bridge #(
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bank_store_active <= 2'b00;
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bank_group_idx[0] <= 32'd0;
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bank_group_idx[1] <= 32'd0;
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load_next_src_addr <= 32'd0;
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load_next_dst_addr <= 32'd0;
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bank_dst_addr[0] <= 32'd0;
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bank_dst_addr[1] <= 32'd0;
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rd_busy <= 1'b0;
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wr_busy <= 1'b0;
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rd_active_bank <= 1'b0;
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@@ -302,6 +309,10 @@ module cdma_matmul_bridge #(
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bank_store_active <= 2'b00;
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bank_group_idx[0] <= 32'd0;
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bank_group_idx[1] <= 32'd0;
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load_next_src_addr <= seq_src_base;
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load_next_dst_addr <= seq_dst_base;
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bank_dst_addr[0] <= 32'd0;
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bank_dst_addr[1] <= 32'd0;
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rd_busy <= 1'b0;
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wr_busy <= 1'b0;
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compute_q <= 2'b00;
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@@ -344,7 +355,7 @@ module cdma_matmul_bridge #(
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end
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if (!rd_busy && !cdma_rd_req_valid && (load_next_idx < seq_groups) && load_target_free) begin
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cdma_rd_req_src <= seq_src_base + (load_next_idx * seq_src_stride);
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cdma_rd_req_src <= load_next_src_addr;
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cdma_rd_req_bytes <= MAT_AB_BYTES;
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cdma_rd_req_ep_id <= 4'd0;
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cdma_rd_req_ep_bank <= {3'b000, load_target_bank};
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@@ -354,11 +365,14 @@ module cdma_matmul_bridge #(
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rd_active_bank <= load_target_bank;
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bank_load_active[load_target_bank] <= 1'b1;
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bank_group_idx[load_target_bank] <= load_next_idx;
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bank_dst_addr[load_target_bank] <= load_next_dst_addr;
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load_next_src_addr <= load_next_src_addr + seq_src_stride;
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load_next_dst_addr <= load_next_dst_addr + seq_dst_stride;
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load_next_idx <= load_next_idx + 32'd1;
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end
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if (!seq_skip_writeback && !wr_busy && !cdma_wr_req_valid && store_ready_any) begin
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cdma_wr_req_dst <= seq_dst_base + (bank_group_idx[store_sel_bank] * seq_dst_stride);
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cdma_wr_req_dst <= bank_dst_addr[store_sel_bank];
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cdma_wr_req_bytes <= MAT_C_BYTES;
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cdma_wr_req_ep_id <= 4'd0;
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cdma_wr_req_ep_bank <= {3'b000, store_sel_bank};
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