FallenSigh
b2c8d6eaf3
Replace poly_mul_sync's two 256x12 LUT register arrays (mem_A/mem_B, ~8k LUT) with four sd_bram banks (A_even/A_odd/B_even/B_odd, 128x12). The base-case reads mem[2k] and mem[2k+1] together, so an even/odd split gives each bank a single read port. This removes the multi-port LUT mux and the long BRAM->register-file route that was the mlkem_clk critical path. sd_bram reads are synchronous (1-cycle); the existing 2-cycle issue cadence absorbs it (address on the gap cycle, data on the issue cycle), with a one-cycle priming gap at LOAD->RUN. Interface and behavior unchanged. Verified byte-exact vs NIST KAT: poly_mul standalone TB 11/11, Encaps 9/9, Decaps 9/9 (incl. reject + DECOMP), KeyGen, hello_world e2e — all PASS. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>