This repository has been archived on 2026-08-21. You can view files and clone it. You cannot open issues or pull requests or push a commit.

FallenSigh 27cdfb713a Optimize CDMA matmul bridge scheduling

2026-07-04 19:59:49 +08:00

doc

doc(mlkem): add mlkem user guide

2026-06-30 15:23:13 +08:00

fpga

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

rtl

Optimize CDMA matmul bridge scheduling

2026-07-04 19:59:49 +08:00

sdk

Compute matmul CRC before result store

2026-07-04 19:45:22 +08:00

sim

Fix SRAM model: level-sensitive write for burst support

2026-06-25 15:40:28 +08:00

tools

add test data

2026-06-26 21:36:55 +08:00

.gitignore

chore: gitignore AI agent config directories (.claude .codex .opencode .agents)

2026-06-26 17:56:28 +08:00

Description

No description provided

193 MiB

Languages

Verilog 46.5%

C 27.8%

Assembly 20.5%

SystemVerilog 3.3%

Python 0.7%

Other 1.2%