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FallenSigh 7b990966e0 doc: update system design report with figures, tables, and test results

2026-07-13 05:26:09 +08:00

doc

doc: update system design report with figures, tables, and test results

2026-07-13 05:26:09 +08:00

fpga

update reports & add mlkem cdc test result & update pll

2026-07-11 10:09:45 +08:00

rtl

update reports & add mlkem cdc test result & update pll

2026-07-11 10:09:45 +08:00

sdk

update reports & add mlkem cdc test result & update pll

2026-07-11 10:09:45 +08:00

sim

update test data and remove mif files

2026-07-05 20:16:13 +08:00

test_data

mlkem test diagnostics and allocator updates

2026-07-08 02:35:56 +08:00

tools

update test data and remove mif files

2026-07-05 20:16:13 +08:00

.gitignore

mlkem test diagnostics and allocator updates

2026-07-08 02:35:56 +08:00

Description

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193 MiB

Languages

Verilog 46.5%

C 27.8%

Assembly 20.5%

SystemVerilog 3.3%

Python 0.7%

Other 1.2%