95fe94063c
fix: revert UART FIFO batching — caused FIFO overflow + syserr on board
...
uart_puts(13B) + uart_puthex(8B) = 21 bytes without polling → FIFO overflow.
Board UART IP asserts AXI error → CPU syserr exception.
Simulation UART model is lenient, so sim passed but board failed.
Back to per-byte polling (safe).
2026-06-26 23:53:15 +08:00
9202327dd0
perf: batch UART FIFO writes — poll once per 16 bytes instead of per byte
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uart_puts: burst-write up to 16 chars before polling LSR
uart_puthex: write all 8 hex digits without polling (8 < 16 FIFO depth)
Reduces AXI register reads from ~50 to ~3 per CRC output.
Each saved poll: -1 uncached AXI read (~390ns)
2026-06-26 23:48:23 +08:00
52e85aa6fb
perf: drop stdint.h + picolibc — zero libc dependency
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dma.h: typedef u32 instead of uint32_t, no stdint.h include
dma.c: use u32 instead of uint32_t
user-sample.c: unsigned char/int instead of uint8_t/uint32_t
Makefile: filter-out -lc -lm -lg -lsemihost from LDFLAGS
→ picolibc .data section (2.1KB, 532 words) eliminated
→ startup data-copy loop: ~30000 → ~200 cycles
→ total start.S latency: ~44000 → ~14000 cycles (~0.42ms at 33MHz)
2026-06-26 22:34:26 +08:00
dd6053ab73
add test data
2026-06-26 21:36:55 +08:00
ac00518741
chore: untrack remaining agent config files (.claude/settings.json, .codex/config.toml)
2026-06-26 17:58:19 +08:00
c539182ecb
chore: gitignore AI agent config directories (.claude .codex .opencode .agents)
2026-06-26 17:56:28 +08:00
eed9a83b3e
chore: remove trellis infrastructure (agents, hooks, skills, tasks, spec)
2026-06-26 17:55:08 +08:00
ae89363227
perf(matmul): bypass printf — direct UART 16550 register writes
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Replace all printf() calls with direct UART THR register access:
- uart_tx(): poll LSR bit5, write byte to THR
- uart_puts(): null-terminated string output
- uart_puthex(): 8-digit lowercase hex for CRC32
Eliminates picolibc printf overhead: no format parsing, no FILE* I/O,
no locale, no buffering. UART runs at 115200 baud (~8.7μs/byte),
THR nearly always empty at 33MHz core → single poll iteration.
Output: MATMUL_START, MATMUL_CRC32=XXXXXXXX, MATMUL_DONE
2026-06-26 17:51:13 +08:00
f55e15af32
perf(matmul): remove all DMA TAG writes (hardware ignores TAG register)
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Each uncached TAG write costs ~810ns on the AXI bus. Removed:
- 2 TAG writes per main loop iteration (Ch1 store + Ch0 pre-fire)
- 2 TAG writes in prologue (group 0 load + pre-fire group 1)
- 1 TAG write in epilogue (final store)
Total: ~10,000 wasted AXI transactions eliminated for 5000 groups.
Estimated ~8% reduction in per-iteration time.
2026-06-26 17:49:39 +08:00
07b670b4c9
perf(matmul): strip ALL timing — zero get_ns() calls, zero TIME_* output
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Removed:
- confreg_time.h and common_func.h includes
- All get_ns() calls (6 in prologue/loop/epilogue boundaries)
- All timing variables (t_prologue, t_mainloop, t_epilogue)
- All TIME_* printf markers
- Unused extram pointer and stdbool.h
Only essential output remains: MATMUL_START, MATMUL_CRC32, MATMUL_DONE
2026-06-26 17:46:07 +08:00
6aab84bf4b
perf(matmul): remove diagnostic get_ns() calls from hot loop (v2 clean)
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Stripped all per-iteration timing instrumentation:
- Removed 16 get_ns() calls per iteration from main loop
- Removed pipeline diagnostic print section
- Removed timing accumulator variables
- Retained outer timing markers only (prologue/loop/epilogue)
Expected ~45% speedup from removing measurement overhead
(previous run: 179.6ms with diag → estimated ~100ms clean)
2026-06-26 17:44:13 +08:00
20611157c3
tools: add extract_cbor_uart.py — extract UART output from CBOR trace files
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Parses CBOR hardware trace format, extracts UART serial output bytes,
and optionally parses MATMUL timing markers + pipeline diagnostics.
Usage:
python3 tools/extract_cbor_uart.py <file.cbor> # full UART output
python3 tools/extract_cbor_uart.py <file.cbor> -s # timing summary
python3 tools/extract_cbor_uart.py <file.cbor> -o out # save to file
2026-06-26 17:40:20 +08:00
45731e05b7
perf(matmul): add pipeline timing diagnostics (v2.1)
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Measure per-phase wait times and stall counts to identify bottleneck:
- PIPE_WAIT_IP / DMA0 / DMA1: aggregate wait time per resource
- PIPE_FIRE_DMA / IP: register write overhead
- PIPE_STALL_*: iterations where each resource actually blocked
Output after standard markers, before MATMUL_DONE.
Allows data-driven decision on next optimization target:
wait_ip dominant → optimize IP (HW multiplier pipeline)
wait_dma0 dominant → pre-fire insufficient (wider bus/faster RAM)
wait_dma1 dominant → bank reuse delay (deeper buffering)
2026-06-26 03:54:20 +08:00
81c636fb56
perf(matmul): pre-fire DMA Ch0 load + inline wait/DMA start + XOR bank toggle
...
user-sample.c v2 optimizations:
- Pre-fire DMA Ch0 load at loop tail to overlap fully with IP compute
- Inline wait_matmul_done/wait_dma_done to eliminate function call overhead
- Inline DMA register writes, skip redundant STATUS_BUSY_BIT check
- Replace g%2 with XOR bank toggle (bank ^= 1)
- Cache volatile pointers in locals (ch0, ch1, mat_status, mat_ctrl)
Makefile: bump -O2 to -O3
2026-06-26 03:39:32 +08:00
a2b496ca8d
Restore timing + switch to polling + disable CPU interrupts (IE=0)
2026-06-26 01:01:48 +08:00
115466353d
Remove timing instrumentation from user-sample.c
2026-06-26 00:34:44 +08:00
8bc3d42ac6
Fix pipe_cnt range: issue 0-15 (16 rounds), acc 4-19, done at 20
2026-06-25 22:26:07 +08:00
db9997b473
Pipelined multiplier: 3-stage LUT-based replaces shift_add, FSM simplified to 2-state
2026-06-25 22:09:20 +08:00
b3c0db19b9
Fix CRC32: use combinational stream_valid (was stuck-high causing repeated processing)
2026-06-25 20:53:56 +08:00
f8459f2478
Hardware CRC32 engine in matmul IP: 4-byte/cycle combinational, register at 0x010
2026-06-25 20:40:08 +08:00
76b5f30c6b
Move MATMUL_DONE to last line
2026-06-25 20:11:45 +08:00
d9483a9d39
Add timing instrumentation for profiling (prologue/loop/epilogue/crc32)
2026-06-25 20:10:31 +08:00
956cd67773
Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines
2026-06-25 20:03:53 +08:00
57ba5d271d
Remove all debug and printf
2026-06-25 15:44:18 +08:00
b331301584
Fix SRAM model: level-sensitive write for burst support
2026-06-25 15:40:28 +08:00
a24b5cff6e
Add for writes to result region (addr 320-399)
2026-06-25 15:31:28 +08:00
a9958ee4fa
BURST_LEN 47->63 (64 beats)
2026-06-25 04:08:18 +08:00
4aba830a7d
Add for B1_C read channel
2026-06-25 04:04:18 +08:00
3cad98a811
Increase BURST_LEN to 47 (48 beats) to cover 192-byte C reads in one burst
2026-06-25 03:54:10 +08:00
b5ec0d2926
Fix escaped quotes in display
2026-06-25 03:45:18 +08:00
9c6b321d59
Add in read channel to debug C register readback
2026-06-25 03:44:54 +08:00
3fb93131e5
Simplify ACCUM debug: show expression value only
2026-06-25 03:43:46 +08:00
86eab428a7
Use parenthesized pairwise addition to prevent synthesis truncation
2026-06-25 03:41:58 +08:00
fba86b01a8
Add in C_ACCUM to debug accumulation sum
2026-06-25 03:38:26 +08:00
4e409f870c
Register mult_p before accumulation to prevent synthesis glitches
2026-06-25 03:27:51 +08:00
6c77fa2e38
Remove FFT controller, tie off slave 6
2026-06-25 03:16:40 +08:00
d9d03b16c6
Fix: wait for ALL 4 multipliers to finish before accumulation
2026-06-25 03:07:49 +08:00
54aa37adee
Add debug output for C[0][0]/C[1][1]/C[2][3] of groups 0,1
2026-06-25 03:03:10 +08:00
2e5d793bbf
Merge main (CRC32 fix)
2026-06-25 02:52:09 +08:00
9ecda4aa7a
Fix CRC32 table, remove debug output
2026-06-25 02:51:36 +08:00
ae8f2d1c2d
Merge main (AXI ports fix) into no-fft
2026-06-25 02:35:04 +08:00
a2b3f72c76
Fix matmul AXI: add missing awlock/cache/prot ports, remove placeholder
2026-06-25 02:34:50 +08:00
8e86d8693e
Increase DMA FIFO depth to 128 (512 bytes) for burst support
2026-06-25 01:54:07 +08:00
1e36883a7c
Fix CRC32 table entry 187
2026-06-25 01:26:53 +08:00
3962058592
Fix CRC32 table entry 187 again (0x5CB30A04 -> 0x5CB36A04)
2026-06-25 01:24:04 +08:00
31c2b53583
CRC32 on-the-fly from c_buf (bypass GCC volatile ExtRAM bug)
2026-06-25 01:19:57 +08:00
292d3c7abf
Remove placeholder comment
2026-06-25 00:53:42 +08:00
d3e1b5fda4
Add missing AXI4 ports: awlock/awcache/awprot/arlock/arcache/arprot
2026-06-25 00:53:28 +08:00
828612164a
Re-remove FFT module (leaked in from main merge)
2026-06-25 00:51:54 +08:00
acb158a392
Update matmul RTL, remove shift_add_mult.v
2026-06-25 00:47:43 +08:00
