ciciec2026

fallensigh/ciciec2026

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FallenSigh 52e85aa6fb perf: drop stdint.h + picolibc — zero libc dependency

dma.h: typedef u32 instead of uint32_t, no stdint.h include
dma.c: use u32 instead of uint32_t
user-sample.c: unsigned char/int instead of uint8_t/uint32_t

Makefile: filter-out -lc -lm -lg -lsemihost from LDFLAGS
  → picolibc .data section (2.1KB, 532 words) eliminated
  → startup data-copy loop: ~30000 → ~200 cycles
  → total start.S latency: ~44000 → ~14000 cycles (~0.42ms at 33MHz)

2026-06-26 22:34:26 +08:00

doc

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

fpga

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

rtl

Fix pipe_cnt range: issue 0-15 (16 rounds), acc 4-19, done at 20

2026-06-25 22:26:07 +08:00

sdk

perf: drop stdint.h + picolibc — zero libc dependency