Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines

.omo/run-continuation/ses_10239d2deffea8KLY07dbf73Xl.json

@@ -0,0 +1,10 @@
+{
+  "sessionID": "ses_10239d2deffea8KLY07dbf73Xl",
+  "updatedAt": "2026-06-25T07:55:55.876Z",
+  "sources": {
+    "background-task": {
+      "state": "idle",
+      "updatedAt": "2026-06-25T07:55:55.876Z"
+    }
+  }
+}

.omo/run-continuation/ses_10fa71838ffejKERYltTRb8Y0A.json

@@ -0,0 +1,10 @@
+{
+  "sessionID": "ses_10fa71838ffejKERYltTRb8Y0A",
+  "updatedAt": "2026-06-25T11:54:10.632Z",
+  "sources": {
+    "background-task": {
+      "state": "idle",
+      "updatedAt": "2026-06-25T11:54:10.632Z"
+    }
+  }
+}

rtl/ip/confreg/confreg.v

@@ -91,7 +91,6 @@ module confreg #(
     input      [3 :0] touch_btn,
 
     input             uart0_int,
-    input             dma_finish,
     input             fft_finish,
     output            confreg_int
 );
@@ -384,7 +383,7 @@ always @(posedge aclk) begin
     end
 end
 
-assign int_in = {24'b0, dma_finish, fft_finish, uart0_int, timer_int, touch_btn_data};
+assign int_in = {24'b0, 1'b0, fft_finish, uart0_int, timer_int, touch_btn_data};
 
 int_ctrl u_int_ctrl (
     .clk       (aclk),

rtl/ip/matmul/matmul_axi_slave.v

@@ -103,7 +103,10 @@ module matmul_axi_slave (
     output     [1:0]  s_axi_rresp,
     output reg        s_axi_rlast,
     output reg        s_axi_rvalid,
-    input             s_axi_rready
+    input             s_axi_rready,
+
+    // Interrupt output (active high level, pulsed by calc_done)
+    output            intr
 );
 
     // ==========================================
@@ -459,4 +462,7 @@ module matmul_axi_slave (
         end
     end
 
+    // Interrupt: driven by done, cleared when software writes STATUS[1]
+    assign intr = done;
+
 endmodule

rtl/soc_top.v

@@ -603,6 +603,7 @@ wire        axiOut_7_bvalid ;
 wire        axiOut_7_bready ;
 
 wire confreg_int;
+wire matmul_intr;
 
 AxiCrossbar_2x8  u_AxiCrossbar_2x8 (
     .clk                     ( sys_clk             ),
@@ -1031,10 +1032,11 @@ AxiCrossbar_2x8  u_AxiCrossbar_2x8 (
 
 );
 
-
+
 
 core_top u_cpu(
-    .intrpt          ({7'b0, confreg_int}), //high active
+    .intrpt          ({5'd0,  matmul_intr, dma_finish, confreg_int}), //high active
+    // intrpt[2]=matmul, intrpt[1]=dma, intrpt[0]=confreg
 
     .aclk            (cpu_clk ),
     .aresetn         (cpu_resetn ), //low active
@@ -1370,7 +1372,6 @@ confreg #(
 
     // 中断与状态信号
     .uart0_int  (uart0_int),        // UART0中断
-    .dma_finish (dma_finish),       // DMA完成信号
     .fft_finish (fft_finish),       // FFT完成信号
     .confreg_int(confreg_int)       // 输出中断给CPU 
 );
@@ -1436,7 +1437,7 @@ assign fft_arready = 1'b1;
 assign fft_awready = 1'b1;
 assign fft_wready  = 1'b1;
 
-//slave 7 - matmul accelerator
+//slave 7 - matmul accelerator
 matmul_axi_slave u_matmul_axi_slave (
     .clk            (sys_clk),
     .resetn         (sys_resetn),
@@ -1480,7 +1481,8 @@ matmul_axi_slave u_matmul_axi_slave (
     .s_axi_rresp    (axiOut_7_rresp ),
     .s_axi_rlast    (axiOut_7_rlast ),
     .s_axi_rvalid   (axiOut_7_rvalid),
-    .s_axi_rready   (axiOut_7_rready)
+    .s_axi_rready   (axiOut_7_rready),
+    .intr           (matmul_intr)
 );
 
 wire [31:0] cdma_s_awaddr;

sdk/software/bsp/env/trap_handler.S

@@ -153,12 +153,18 @@ handle_hwi0:
 
     b trap_jump_exit
 
-# HWI1 处理程序
+# HWI1 处理程序 - DMA完成
 handle_hwi1:
+
+    bl DMA_IntrHandler
+
     b trap_jump_exit
 
-# HWI2 处理程序
+# HWI2 处理程序 - Matmul完成
 handle_hwi2:
+
+    bl MATMUL_IntrHandler
+
     b trap_jump_exit
 
 # HWI3 处理程序
@@ -186,3 +192,13 @@ handle_hwi7:
 HWI0_IntrHandler:
 1:
   b 1b
+
+.weak DMA_IntrHandler
+DMA_IntrHandler:
+1:
+  b 1b
+
+.weak MATMUL_IntrHandler
+MATMUL_IntrHandler:
+1:
+  b 1b

sdk/software/examples/asm/user-sample.c

@@ -99,16 +99,43 @@ static const uint32_t crc32_table[256] = {
     0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
 };
 
-/* ─── Poll IP STATUS until done and clear it (W1C) ────────────────── */
-static void wait_matmul_done(void)
+static volatile int matmul_done_flag = 0;
+static volatile int dma0_done_flag   = 0;
+static volatile int dma1_done_flag   = 0;
+
+void MATMUL_IntrHandler(void)
 {
-    uint32_t status;
-    do {
-        status = REG_RD(MATMUL_STATUS);
-    } while (!(status & (STATUS_DONE | STATUS_ERROR)));
-    
-    // Write 1 to Clear the DONE bit
-    REG_WR(MATMUL_STATUS, STATUS_DONE);
+    matmul_done_flag = 1;
+    REG_WR(MATMUL_STATUS, STATUS_DONE);  // W1C: deassert intr
+}
+
+void DMA_IntrHandler(void)
+{
+    if (DMA_CH(0)->STATUS & STATUS_DONE_BIT) {
+        dma0_done_flag = 1;
+        DMA_CH(0)->STATUS = STATUS_DONE_BIT;
+    }
+    if (DMA_CH(1)->STATUS & STATUS_DONE_BIT) {
+        dma1_done_flag = 1;
+        DMA_CH(1)->STATUS = STATUS_DONE_BIT;
+    }
+}
+
+static void wait_matmul_done_intr(void)
+{
+    while (!matmul_done_flag) { }
+    matmul_done_flag = 0;
+}
+
+static void wait_dma_done_intr(int ch)
+{
+    if (ch == 0) {
+        while (!dma0_done_flag) { }
+        dma0_done_flag = 0;
+    } else {
+        while (!dma1_done_flag) { }
+        dma1_done_flag = 0;
+    }
 }
 
 /* ─── CRC32 over ExtRAM result region ─────────────────────────────── */
@@ -152,7 +179,7 @@ int main(void)
     /* ── Prologue: 第0组数据初始化 ────────────────────────── */
     // DMA Ch0: 从 ExtRAM 将 Group 0 的 A、B (128 bytes) 搬入 IP 的 Bank 0
     dma_start_transfer(0, EXTRAM_PHYS_AB(0), phys_bank_AB[0], 128, 10);
-    dma_wait_polling(0); // 必须等待首个数据加载完成
+    wait_dma_done_intr(0);
     
     // 启动 IP Bank 0 计算
     REG_WR(MATMUL_CTRL, ctrl_start[0]);
@@ -170,30 +197,30 @@ int main(void)
         dma_start_transfer(0, EXTRAM_PHYS_AB(g), phys_bank_AB[cur_bank], 128, 10);
 
         // 2. 等待上一组在 IP 中的计算完成
-        wait_matmul_done();
+        wait_matmul_done_intr();
 
         // 3. 确保上一次的结果写回 (Channel 1) 已经空闲
         if (g > 1) {
-            dma_wait_polling(1);
+            wait_dma_done_intr(1);
         }
 
         // 4. 发起写回刚才计算完成的结果 (Channel 1: IP -> Memory)
         dma_start_transfer(1, phys_bank_C[prev_bank], EXTRAM_PHYS_C(g - 1), 192, 20);
 
         // 5. 确保当前要计算的输入数据 (Channel 0) 已经加载完毕
-        dma_wait_polling(0);
+        wait_dma_done_intr(0);
 
         // 6. 立即启动当前组在 IP 中的计算
         REG_WR(MATMUL_CTRL, ctrl_start[cur_bank]);
     }
 
     /* ── Epilogue: 收尾最后一组 ───────────────────────────── */
-    wait_matmul_done(); // 等待最后一次计算完成
-    dma_wait_polling(1); // 确保之前的 DMA CH1 空闲
+    wait_matmul_done_intr(); // 等待最后一次计算完成
+    wait_dma_done_intr(1);   // 确保之前的 DMA CH1 空闲
     
     // DMA CH1 将最后一组结果写回
     dma_start_transfer(1, phys_bank_C[(MATMUL_GROUP_NUM - 1) % 2], EXTRAM_PHYS_C(MATMUL_GROUP_NUM - 1), 192, 20);
-    dma_wait_polling(1); // 必须等待最后一组写回完成
+    wait_dma_done_intr(1);
 
     /* ── CRC32 over result region ─────────────────────────────── */
     crc = compute_crc32(extram);