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FallenSigh 54aa37adee Add debug output for C[0][0]/C[1][1]/C[2][3] of groups 0,1

2026-06-25 03:03:10 +08:00

.agents/skills

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.claude

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.codex

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.opencode

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.trellis

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

doc

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

fpga

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

rtl

Merge main (AXI ports fix) into no-fft

2026-06-25 02:35:04 +08:00

sdk

Add debug output for C[0][0]/C[1][1]/C[2][3] of groups 0,1

2026-06-25 03:03:10 +08:00

sim

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

tools

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

.gitignore

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

AGENTS.md

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

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193 MiB

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