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FallenSigh 20611157c3 tools: add extract_cbor_uart.py — extract UART output from CBOR trace files ...

Parses CBOR hardware trace format, extracts UART serial output bytes,
and optionally parses MATMUL timing markers + pipeline diagnostics.

Usage:
  python3 tools/extract_cbor_uart.py <file.cbor>          # full UART output
  python3 tools/extract_cbor_uart.py <file.cbor> -s       # timing summary
  python3 tools/extract_cbor_uart.py <file.cbor> -o out   # save to file

2026-06-26 17:40:20 +08:00

.agents/skills

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.claude

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.codex

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.omo/run-continuation

Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines

2026-06-25 20:03:53 +08:00

.opencode

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.trellis

Pipelined multiplier: 3-stage LUT-based replaces shift_add, FSM simplified to 2-state

2026-06-25 22:09:20 +08:00

doc

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

fpga

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

rtl

Fix pipe_cnt range: issue 0-15 (16 rounds), acc 4-19, done at 20

2026-06-25 22:26:07 +08:00

sdk

perf(matmul): add pipeline timing diagnostics (v2.1)

2026-06-26 03:54:20 +08:00

sim

Fix SRAM model: level-sensitive write for burst support

2026-06-25 15:40:28 +08:00

tools

tools: add extract_cbor_uart.py — extract UART output from CBOR trace files

2026-06-26 17:40:20 +08:00

.gitignore

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

AGENTS.md

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

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