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FallenSigh 45731e05b7 perf(matmul): add pipeline timing diagnostics (v2.1) ...

Measure per-phase wait times and stall counts to identify bottleneck:
- PIPE_WAIT_IP / DMA0 / DMA1: aggregate wait time per resource
- PIPE_FIRE_DMA / IP: register write overhead
- PIPE_STALL_*: iterations where each resource actually blocked

Output after standard markers, before MATMUL_DONE.
Allows data-driven decision on next optimization target:
  wait_ip dominant → optimize IP (HW multiplier pipeline)
  wait_dma0 dominant → pre-fire insufficient (wider bus/faster RAM)
  wait_dma1 dominant → bank reuse delay (deeper buffering)

2026-06-26 03:54:20 +08:00

.agents/skills

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.claude

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.codex

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.omo/run-continuation

Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines

2026-06-25 20:03:53 +08:00

.opencode

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.trellis

Pipelined multiplier: 3-stage LUT-based replaces shift_add, FSM simplified to 2-state

2026-06-25 22:09:20 +08:00

doc

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

fpga

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

rtl

Fix pipe_cnt range: issue 0-15 (16 rounds), acc 4-19, done at 20

2026-06-25 22:26:07 +08:00

sdk

perf(matmul): add pipeline timing diagnostics (v2.1)

2026-06-26 03:54:20 +08:00

sim

Fix SRAM model: level-sensitive write for burst support

2026-06-25 15:40:28 +08:00

tools

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

.gitignore

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

AGENTS.md

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

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