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FallenSigh eed9a83b3e chore: remove trellis infrastructure (agents, hooks, skills, tasks, spec)

2026-06-26 17:55:08 +08:00

.claude

chore: remove trellis infrastructure (agents, hooks, skills, tasks, spec)

2026-06-26 17:55:08 +08:00

.codex

chore: remove trellis infrastructure (agents, hooks, skills, tasks, spec)

2026-06-26 17:55:08 +08:00

doc

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

fpga

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

rtl

Fix pipe_cnt range: issue 0-15 (16 rounds), acc 4-19, done at 20

2026-06-25 22:26:07 +08:00

sdk

perf(matmul): bypass printf — direct UART 16550 register writes

2026-06-26 17:51:13 +08:00

sim

Fix SRAM model: level-sensitive write for burst support

2026-06-25 15:40:28 +08:00

tools

tools: add extract_cbor_uart.py — extract UART output from CBOR trace files

2026-06-26 17:40:20 +08:00

.gitignore

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

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