Commit Graph

Select branches

Hide Pull Requests

main

main-cdc

main-nocdc

matmul-crc-only

matmul-dma-master

v0.1

Mono Color

• c028c72aab docs: add timing violation regret to competition summary main FallenSigh 2026-08-21 20:13:29 +08:00
• 24c129d18d docs: add competition summary and reorganize reports FallenSigh 2026-08-21 19:47:46 +08:00
• 9642413e31 update reports FallenSigh 2026-07-15 18:43:30 +08:00
• d6873b5aed update reports FallenSigh 2026-07-15 18:22:17 +08:00
• 62a4e07037 delete generated pll sim files FallenSigh 2026-07-15 11:29:58 +08:00
• af65503947 remove reports FallenSigh 2026-07-15 11:10:28 +08:00
• fe20f28a72 update system design report FallenSigh 2026-07-15 11:09:57 +08:00
• c4d36515cc fix samples ntt bugs & set PLL & optimize matmul FallenSigh 2026-07-15 10:36:38 +08:00
• fc91511950 feat: optimize sram controller FallenSigh 2026-07-15 10:03:39 +08:00
• d45646342b test: add board FFT validation and VCD capture FallenSigh 2026-07-15 04:13:15 +08:00
• 2359e7976c docs: rebuild system report and test workflow FallenSigh 2026-07-15 03:48:19 +08:00
• 2e4817fea6 set sysclk to 60Mhz matmul-crc-only FallenSigh 2026-07-14 22:50:44 +08:00
• c4f34426e6 fix: typo FallenSigh 2026-07-14 22:50:34 +08:00
• 459d08fa65 Update matmul fast-start software image FallenSigh 2026-07-14 20:43:02 +08:00
• 0d0c6d0376 Optimize matmul DMA with chained 256-beat bursts FallenSigh 2026-07-14 20:40:43 +08:00
• f3af271788 Optimize matmul CRC pipeline and expose DMA cycles FallenSigh 2026-07-14 18:21:45 +08:00
• 1b51f28263 doc: add backend design report with screenshots main-cdc FallenSigh 2026-07-13 08:23:34 +08:00
• 7c60da78cb optimize FallenSigh 2026-07-13 07:10:30 +08:00
• 82f3c3d700 doc: reorganize reports into mlkem_ip/ and system/ directories FallenSigh 2026-07-13 06:48:50 +08:00
• 7b990966e0 doc: update system design report with figures, tables, and test results FallenSigh 2026-07-13 05:26:09 +08:00
• 6d4239ea7f doc: update ML-KEM IP report (NTT architecture, clock, compares) and system design report FallenSigh 2026-07-12 01:33:31 +08:00
• 1d7e974c28 doc: update ML-KEM IP design report with latest timing and test data FallenSigh 2026-07-11 10:10:18 +08:00
• 4857016b42 update reports & add mlkem cdc test result & update pll FallenSigh 2026-07-11 10:09:45 +08:00
• 760bcddccc Merge branch 'main-cdc' main-nocdc FallenSigh 2026-07-11 09:26:38 +08:00
• e30a65bd72 perf(mlkem): pipeline CBD->bank write to cut 100 MHz critical path FallenSigh 2026-07-11 07:42:35 +08:00
• 4538ec496f perf(mlkem): register butterfly inputs to cut the 100 MHz NTT critical path FallenSigh 2026-07-11 07:05:12 +08:00
• b2c8d6eaf3 perf(mlkem): move poly_mul coeff storage to even/odd banked BRAM FallenSigh 2026-07-11 05:41:27 +08:00
• 78ccc34578 perf(mlkem): move NTT coeff storage to 4-way banked BRAM FallenSigh 2026-07-11 05:16:58 +08:00
• be2e54c8ab revert(mlkem): drop poly_mul ping-pong (B2) to reclaim ~7k LUT FallenSigh 2026-07-11 03:48:50 +08:00
• 454c3e559d perf(mlkem): dual-butterfly NTT core (R1) — ~12% fewer Encaps cycles FallenSigh 2026-07-11 03:05:35 +08:00
• 975903000e perf(mlkem): ping-pong poly_mul + decoupled MAC load/accumulate (B2) FallenSigh 2026-07-11 02:37:28 +08:00
• ce40a6df42 perf(mlkem): stream compress feed (B1) — ~27% fewer Encaps cycles FallenSigh 2026-07-11 02:00:03 +08:00
• 6faaa8abd8 doc: update ML-KEM IP design report with cover page, design evaluation, and comparisons FallenSigh 2026-07-10 05:10:06 +08:00
• b052b12885 update vivado reports FallenSigh 2026-07-10 04:47:36 +08:00
• 03b3415e76 add mlkem_test result FallenSigh 2026-07-10 00:26:43 +08:00
• 5f9cb1c883 remove mlkem CDC; mlkem can now run at 50MHz FallenSigh 2026-07-08 17:52:16 +08:00
• 6a1b374bc1 set mlkem_clk to 50Mhz FallenSigh 2026-07-08 17:01:46 +08:00
• ab4751bfd3 doc: add ML-KEM IP design report with figures FallenSigh 2026-07-08 04:42:11 +08:00
• 3d2917a807 add examples/mlkem_hello FallenSigh 2026-07-08 04:41:37 +08:00
• 5a3529d09b update vivado reports FallenSigh 2026-07-08 04:20:27 +08:00
• 4229652659 fix: add use_dsp=no to FFT Multiply and fft_mlkem_axi_slave FallenSigh 2026-07-08 03:57:39 +08:00
• f676fc6e60 add vivado reports FallenSigh 2026-07-08 03:48:37 +08:00
• b003fc057f fix(mlkem): verilator lint fixes — BLKLOOPINIT and UNUSEDSIGNAL FallenSigh 2026-07-08 03:36:52 +08:00
• 1b494fe44d add use_dsp=no for matmul FallenSigh 2026-07-08 03:20:34 +08:00
• 94f8f443d3 add mlkem test results FallenSigh 2026-07-08 03:18:19 +08:00
• 83473b66aa remove dsp usage FallenSigh 2026-07-08 03:18:10 +08:00
• 0c85a20b4e mlkem test diagnostics and allocator updates FallenSigh 2026-07-08 02:35:56 +08:00
• 886ae8ad3f Sync fast SRAM read burst controller FallenSigh 2026-07-06 00:19:25 +08:00
• 4c0646a514 Optimize asm matmul crc software path FallenSigh 2026-07-06 00:16:23 +08:00
• 93d2fbd935 Optimize asm matmul dma software path matmul-dma-master FallenSigh 2026-07-06 00:13:01 +08:00
• 65607badd2 add vivado reports v0.1 FallenSigh 2026-07-06 00:03:57 +08:00
• 34ce639f69 test(fft): update fft_dma example FallenSigh 2026-07-05 23:25:51 +08:00
• 088a9bd5b8 fix(fft): update SdfUnit, Twiddle, and axi wrapper FallenSigh 2026-07-05 23:25:51 +08:00
• e8893a28dd mlkem_test: add mlkem-native FallenSigh 2026-07-05 21:26:39 +08:00
• cd039e2e2e mlkem_test: add mlkem-native FallenSigh 2026-07-05 21:26:19 +08:00
• b8ddb2ef08 c program: use prng FallenSigh 2026-07-05 21:04:42 +08:00
• 54ec54d421 feat: add prng FallenSigh 2026-07-05 21:04:25 +08:00
• 19751b9d18 add no dsp hint for FFT FallenSigh 2026-07-05 20:37:19 +08:00
• 4eca83bd3d Add MLKEM DMA comparison test FallenSigh 2026-07-05 20:23:58 +08:00
• 69de12e79f update test data and remove mif files FallenSigh 2026-07-05 20:16:13 +08:00
• ca1472d859 Stop tracking generated binary images FallenSigh 2026-07-05 20:12:56 +08:00
• 2b7c43edcb Add DMA-friendly MLKEM windows FallenSigh 2026-07-05 20:07:14 +08:00
• d13f7933d8 Optimize FFT test input generation FallenSigh 2026-07-05 19:48:16 +08:00
• 7e72bd455a feat: add fft module FallenSigh 2026-07-05 19:30:51 +08:00
• 48072c5ecb remove all the LF FallenSigh 2026-07-05 18:23:23 +08:00
• 264e65f8d9 optimize uart output FallenSigh 2026-07-05 17:59:31 +08:00
• 7281df356f feat: optimize startup and linking FallenSigh 2026-07-05 17:27:26 +08:00
• 423ff32b49 feat: optimize sram read channel FallenSigh 2026-07-05 17:12:38 +08:00
• f735f789d6 remove dsp usage FallenSigh 2026-07-04 21:20:32 +08:00
• d3a08b1f9d Split CDMA matmul endpoint engines FallenSigh 2026-07-04 20:42:31 +08:00
• 2725f6eb57 Reduce CDMA matmul bridge request latency FallenSigh 2026-07-04 20:12:45 +08:00
• 27cdfb713a Optimize CDMA matmul bridge scheduling FallenSigh 2026-07-04 19:59:49 +08:00
• c37f493bcb Compute matmul CRC before result store FallenSigh 2026-07-04 19:45:22 +08:00
• bf6051c8c6 Add standalone CDMA matmul bridge FallenSigh 2026-07-04 19:35:42 +08:00
• b7553418fa Add direct CDMA matmul path FallenSigh 2026-07-04 19:15:34 +08:00
• 3f7c9b7a37 feat: optimize sram write channel FallenSigh 2026-07-04 18:54:05 +08:00
• 58f99d82ba chore: typo FallenSigh 2026-07-04 18:53:23 +08:00
• 1540087071 Optimize matmul CRC-only path FallenSigh 2026-07-04 16:13:26 +08:00
• 094157ff05 Outputting LF instead of CRLF ,resulted in a 0.25ms improvement FallenSigh 2026-07-02 01:26:51 +08:00
• 297b93b828 优化sram的写路径，待验证 FallenSigh 2026-07-02 00:36:59 +08:00
• ed2876b3a8 Pipeline external SRAM reads FallenSigh 2026-07-02 00:23:57 +08:00
• baf3f6f696 Avoid DSP in matmul master path FallenSigh 2026-07-01 23:30:11 +08:00
• fd03aaaaa1 Add matmul AXI master path FallenSigh 2026-07-01 23:13:28 +08:00
• 2b6e29f761 Pipeline matmul bank chaining FallenSigh 2026-07-01 22:41:31 +08:00
• ceff12eaf1 Fix CDMA sequencer declaration order FallenSigh 2026-07-01 22:15:31 +08:00
• dd8d9c8f5f Add CDMA matmul sequencer FallenSigh 2026-07-01 21:59:57 +08:00
• 2080a700e9 chore(sdk): update axi_ram.mif and mlkem_test.bin FallenSigh 2026-07-01 21:18:05 +08:00
• c7b052b5dd test(mlkem): update test vectors for golden-vector verification FallenSigh 2026-07-01 21:18:00 +08:00
• dde6a46b49 fix(asm): add uart_putdec and confreg_time.h to user-sample FallenSigh 2026-07-01 21:17:55 +08:00
• 38f2051f04 fix: typo FallenSigh 2026-07-01 21:03:46 +08:00
• d72cda97b9 Fix CDMA channel start timing FallenSigh 2026-07-01 20:34:33 +08:00
• 09fc1aeb44 Add CDMA endpoint path for matmul transfers FallenSigh 2026-07-01 20:15:55 +08:00
• 3d39fc2f5e doc(mlkem): add mlkem user guide FallenSigh 2026-06-30 15:23:13 +08:00
• 29313653a9 fix(mlkem): replace Barrett division with direct / and % in comp_decomp_sync FallenSigh 2026-06-30 03:20:42 +08:00
• 3617ee7656 fix: change <= to = in array for loops for verilator BLKLOOPINIT FallenSigh 2026-06-30 02:15:14 +08:00
• 99e6c884d7 chore: untrack auto-generated PLL files, add .gitignore FallenSigh 2026-06-30 02:10:29 +08:00
• 542495cb52 fix: replace UNUSEDPARAM/UNUSEDSIGNAL with UNUSED for verilator lint FallenSigh 2026-06-30 02:10:07 +08:00
• 92777efd30 fix: drive dbg_dk_idx_i only during full-dk readback FallenSigh 2026-06-30 02:00:50 +08:00
• c5072d7170 feat: add ML-KEM accelerator with AXI slave wrapper FallenSigh 2026-06-30 01:39:35 +08:00
• 95fe94063c fix: revert UART FIFO batching — caused FIFO overflow + syserr on board FallenSigh 2026-06-26 23:53:15 +08:00