This repository has been archived on 2026-08-21. You can view files and clone it. You cannot open issues or pull requests or push a commit.

FallenSigh d9483a9d39 Add timing instrumentation for profiling (prologue/loop/epilogue/crc32)

2026-06-25 20:10:31 +08:00

.agents/skills

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.claude

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.codex

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.omo/run-continuation

Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines

2026-06-25 20:03:53 +08:00

.opencode

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.trellis

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

doc

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

fpga

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

rtl

Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines

2026-06-25 20:03:53 +08:00

sdk

Add timing instrumentation for profiling (prologue/loop/epilogue/crc32)

2026-06-25 20:10:31 +08:00

sim

Fix SRAM model: level-sensitive write for burst support

2026-06-25 15:40:28 +08:00

tools

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

.gitignore

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

AGENTS.md

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

Description

No description provided

193 MiB

Languages

Verilog 46.5%

C 27.8%

Assembly 20.5%

SystemVerilog 3.3%

Python 0.7%

Other 1.2%