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main c028c72aab · docs: add timing violation regret to competition summary · Updated 2026-08-21 20:13:29 +08:00

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matmul-crc-only 2e4817fea6 · set sysclk to 60Mhz · Updated 2026-07-14 22:50:44 +08:00    fallensigh	63 23	Compare	ZIP  TAR.GZ
main-cdc 1b51f28263 · doc: add backend design report with screenshots · Updated 2026-07-13 08:23:34 +08:00    fallensigh	11 0	Included	ZIP  TAR.GZ
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matmul-dma-master 93d2fbd935 · Optimize asm matmul dma software path · Updated 2026-07-06 00:13:01 +08:00    fallensigh	63 15	Compare	ZIP  TAR.GZ