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FallenSigh f55e15af32 perf(matmul): remove all DMA TAG writes (hardware ignores TAG register) ...

Each uncached TAG write costs ~810ns on the AXI bus. Removed:
- 2 TAG writes per main loop iteration (Ch1 store + Ch0 pre-fire)
- 2 TAG writes in prologue (group 0 load + pre-fire group 1)
- 1 TAG write in epilogue (final store)

Total: ~10,000 wasted AXI transactions eliminated for 5000 groups.
Estimated ~8% reduction in per-iteration time.

2026-06-26 17:49:39 +08:00

.agents/skills

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.claude

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.codex

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.omo/run-continuation

Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines

2026-06-25 20:03:53 +08:00

.opencode

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

.trellis

Pipelined multiplier: 3-stage LUT-based replaces shift_add, FSM simplified to 2-state

2026-06-25 22:09:20 +08:00

doc

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

fpga

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

rtl

Fix pipe_cnt range: issue 0-15 (16 rounds), acc 4-19, done at 20

2026-06-25 22:26:07 +08:00

sdk

perf(matmul): remove all DMA TAG writes (hardware ignores TAG register)

2026-06-26 17:49:39 +08:00

sim

Fix SRAM model: level-sensitive write for burst support

2026-06-25 15:40:28 +08:00

tools

tools: add extract_cbor_uart.py — extract UART output from CBOR trace files

2026-06-26 17:40:20 +08:00

.gitignore

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

AGENTS.md

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

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