d4c3fc86fc
feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules
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Add file-based vector testbenches ( + ) for:
- mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync
- s_bram/sd_bram, sha3_chain_top
- ntt_core, poly_mul_sync
- sample_cbd_sync, sample_ntt_sync
Each module includes:
- tb_<module>_xsim.v: Vivado XSIM testbench
- gen_vectors.py: Python vector generator (stdlib only)
- vectors/<module>_input.hex: test input vectors
- xsim_run.tcl: compile + elaborate + simulate script
2026-06-25 20:48:38 +08:00
ae5f0ca048
feat(sha3_chain): add simple SHA3_G integration test
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Phase 3.2: Verifies module chaining works.
- sha3_chain_top.v: 3-state FSM (IDLE→BUSY→DONE), feeds d_in→sha3_top(G)
- Captures rho[255:0] and sigma[511:256] from SHA3-512 output
- Verified: 3/3 bit-exact vs Python G(d||k=2) reference
KG full-path FSM (~11 module chain) deferred — too complex for single dispatch.
2026-06-25 00:22:08 +08:00
a369a421b7
feat(phase3): implement storage BRAMs and Compress/Decompress
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Phase 3.1 + 3.3:
- sd_bram.v: simple dual-port RAM (behavioral, auto-infer to BRAM)
- s_bram.v: single-port RAM (rd_en/wr_en, write priority)
- comp_decomp_sync.v: streaming compress/decompress with round-half-up
Verified: storage 5/5, comp_decomp 60/60 all PASS
2026-06-24 23:28:06 +08:00
209ca90fb1
feat(poly_arith): implement synchronous PolyAdd/PolySub streaming module
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Phase 2.3: Polynomial modular addition and subtraction.
- poly_arith_sync.v: mode=0 add (a+b mod Q), mode=1 sub (a-b mod Q)
- Pure streaming (1 coeff/cycle, no BRAM needed)
- Uses pipeline_reg for valid/ready handshake
Verified: 10/10 vectors bit-exact vs Python reference
2026-06-24 23:12:59 +08:00
39dd36994b
feat(poly_mul): implement synchronous PolyMul with base-case multiply
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Phase 2.2: NTT-domain polynomial pointwise multiplication.
- basecase_mul.v: degree-1 base-case multiply (c0,c1) with Barrett
- poly_mul_zeta_rom.v: 128-entry zeta ROM for PolyMul
- poly_mul_sync.v: FSM (IDLE→LOAD 256 cycles→COMPUTE 256 cycles→DONE)
Verified: 5/5 vectors bit-exact vs Python PolyMul reference
2026-06-24 23:10:18 +08:00
c4cd10c2c1
feat(ntt): implement synchronous NTT core with Barrett modular reduction
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Phase 2.1: Merged Path00+Path01 NTT engine.
- barrett_mul.v: Barrett modular multiplication (a·b mod 3329)
- butterfly_unit.v: Cooley-Tukey/Gentleman-Sande butterfly
- zeta_rom.v: 128-entry ROM with bit-reversed roots of unity
- ntt_core.v: 7-layer NTT FSM, 256×12-bit register file
- ntt_sync.v: valid/ready streaming wrapper
Verified: 13/13 vectors bit-exact vs Python NTT/NTTInverse
2026-06-24 22:51:14 +08:00
5941fee980
feat(phase1): implement RNG, SampleCBD, SampleNTT modules + xsim TBs
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Phase 1 complete — all 4 leaf modules verified:
- rng_sync.v: 256-bit Galois LFSR PRNG (10/10 PASS)
- sample_cbd_sync.v: CBD sampler with keccak_core PRF (2560/2560 PASS)
- sample_ntt_sync.v: SHAKE-128 rejection sampling for A matrix (1536/1536 PASS)
- xsim Verilog TBs for sha3 module (tb_sha3_xsim.v, tb_sha3_xsim_simple.v, tb_keccak_core_xsim.v)
2026-06-24 21:32:53 +08:00
453bc899fc
feat(sha3): implement synchronous Keccak-f[1600] core with G/H/J modes
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Phase 1.1 of ML-KEM sync rewrite.
- keccak_round.v: combinational theta/rho/pi/chi/iota
- keccak_core.v: 24-round pipeline, valid/ready
- sha3_top.v: sponge FSM, modes G(SHA3-512)/H(SHA3-256)/J(SHAKE-256)
- Verilator C++ TB + Python vector gen against reference
- Verified: 25/25 vectors bit-exact vs Python G()/H()/J()
2026-06-24 20:33:44 +08:00
94783441b4
chore: add .gitignore, remove build artifacts and pycache from tracking
2026-06-24 19:43:46 +08:00
a293e20d51
chore: add .gitignore, remove build artifacts from tracking
2026-06-24 19:43:40 +08:00
8fdf944555
feat: init mlkem project with Verilator test framework
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- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready)
- sync_rtl/mod_add/: modular adder example with Verilator C++ TB
- test_framework/: Python-driven Verilator compile/sim/compare pipeline
- test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS
- .trellis/spec/: RTL and test_framework conventions documented
2026-06-24 19:43:29 +08:00
