fallensigh/mlkem-sync
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  • 2fb1cd67e3 revert comp_decomp_sync.v main FallenSigh 2026-06-30 03:17:55 +08:00
  • b7eb59fb5b add design report and timing analysis report FallenSigh 2026-06-30 02:49:40 +08:00
  • faf15ee113 docs: 新增 mlkem_top RTL 结构图 (SVG) FallenSigh 2026-06-30 02:42:31 +08:00
  • 717a9929b6 fix(rtl,scripts): replace combinational divider with Barrett multiplication, add synthesis include_dirs, set 50MHz clock FallenSigh 2026-06-30 00:23:43 +08:00
  • ebf1182b6d fix(scripts): add missing RTL files to create_project.tcl, switch default sim to hello_world FallenSigh 2026-06-29 23:24:03 +08:00
  • 92dafc9696 fix(rtl): add use_dsp="no" attributes, fix duplicate wire declaration FallenSigh 2026-06-29 23:23:58 +08:00
  • ffe2e1e0c8 delete image.png FallenSigh 2026-06-29 23:11:10 +08:00
  • f22165d29e chore: gitignore + untrack AI agent tooling (.claude/.opencode/.trellis/AGENTS.md) FallenSigh 2026-06-29 23:07:54 +08:00
  • 5ac7a59289 chore: 删除无用的 mod_add 模块 FallenSigh 2026-06-29 22:55:06 +08:00
  • 971ce97d50 chore: 删除无用测试文件与 ml-kem-r 痕迹 FallenSigh 2026-06-29 22:42:49 +08:00
  • df4d5cd572 refactor: 把 run_hello.sh 合并进 run_tb.sh 的 'hello' 模块 FallenSigh 2026-06-29 22:34:36 +08:00
  • 6b99e5abba docs: 重写 README，覆盖 KeyGen/Encaps/Decaps 全功能微架构与 mlkem_top I/O FallenSigh 2026-06-29 22:26:01 +08:00
  • ee2bf1cda8 test(top): two-instance hello_world TB (genenc + dec split) FallenSigh 2026-06-29 22:15:39 +08:00
  • f27922270a test(top): hardware hello_world TB (full KeyGen+Encaps+Decaps protocol) FallenSigh 2026-06-29 22:06:32 +08:00
  • 2b70431923 feat(dec): Decaps D7 - implicit-reject compare + end-to-end KAT FallenSigh 2026-06-29 21:56:07 +08:00
  • a734eb2cad feat(dec): Decaps D6 - c' = K-PKE.Encrypt(ek_pke, m', r') FallenSigh 2026-06-29 21:19:38 +08:00
  • 189411e8d1 feat(dec): Decaps D5 - (K',r')=G(m'||h) + K-bar=J(z||c) FallenSigh 2026-06-29 20:37:03 +08:00
  • 7f519fe826 feat(dec): Decaps D3+D4 - w = v'-INTT(s.u_hat) + m' recovery FallenSigh 2026-06-29 18:57:29 +08:00
  • 940946f30c feat(dec): Decaps D2 - s_hat=byteDecode12(dk_pke) + u_hat=NTT(u') FallenSigh 2026-06-29 18:00:44 +08:00
  • ecc00d6dd5 feat(dec): Decaps D1 - byteDecode_d + Decompress -> u'/v' FallenSigh 2026-06-29 17:32:03 +08:00
  • e46d2258d9 chore(tb): remove Verilator TBs + framework; parallelize XSIM runs FallenSigh 2026-06-29 16:05:06 +08:00
  • 030931d4e5 feat(dec): Decaps D0 - op_i widen + dk/c load + parse FallenSigh 2026-06-29 15:22:34 +08:00
  • 4091fd0676 chore(enc): merge run_enc.sh into run_tb.sh; TB dumps hardware ct FallenSigh 2026-06-29 12:32:29 +08:00
  • 7228bebb78 feat(enc): Encaps E7 - c2 = byteEncode_dv(Compress_dv(v)) + end-to-end KAT FallenSigh 2026-06-29 11:18:58 +08:00
  • e114bec5ee feat(enc): Encaps E6 - v = INTT(sum t_hat o y_hat) + e2 + mu FallenSigh 2026-06-29 11:03:33 +08:00
  • 4fee8bded3 fix(enc): compile comp_decomp_sync + pipeline_reg in KeyGen tcl FallenSigh 2026-06-29 03:06:11 +08:00
  • 3bc46f9640 feat(enc): Encaps E5 - c1 = byteEncode_du(Compress_du(u)) FallenSigh 2026-06-29 02:59:12 +08:00
  • ee875d2ff7 feat(enc): Encaps E4 - u = INTT(sum A^T o y_hat) + e1 FallenSigh 2026-06-29 02:26:01 +08:00
  • 8ed4d59546 feat(enc): Encaps E3 - y_hat = NTT(y) in place FallenSigh 2026-06-29 02:01:37 +08:00
  • cdc5ce25b1 feat(enc): Encaps E2 - sample y/e1/e2 (CBD eta1/eta2, r seed) FallenSigh 2026-06-29 01:55:47 +08:00
  • 31c967c8a4 feat(enc): Encaps E1 - rho load + A regen + byteDecode12 t_hat FallenSigh 2026-06-29 01:44:50 +08:00
  • 0a8b3dae69 feat(enc): Encaps E0 - op_i/msg_i/ek-load scaffold + H(ek)+G(m||H(ek)) FallenSigh 2026-06-29 01:00:47 +08:00
  • c4669480d1 test(top): add ml-kem-r cross-validation script (xcheck_mlkemr.py) FallenSigh 2026-06-28 23:54:08 +08:00
  • af9ecb20b7 test(top): dump KeyGen d/z inputs and ek/dk outputs per case FallenSigh 2026-06-28 22:08:50 +08:00
  • a38c41a1f5 refactor(kg): bank_se -> sd_bram instance; Phase 2 complete (polymem all BRAM) FallenSigh 2026-06-28 22:00:41 +08:00
  • 5cfe8c74ca refactor(kg): bank_t -> sd_bram instance (1R+1W RMW, real BRAM) FallenSigh 2026-06-28 21:41:51 +08:00
  • d1b409f65f refactor(kg): bank_a -> sd_bram instance (1R+1W, real BRAM) FallenSigh 2026-06-28 21:26:35 +08:00
  • 4afa3a4998 refactor(kg): registered single-port read for ST_E byteEncode (bank_se/bank_t) FallenSigh 2026-06-28 21:13:39 +08:00
  • 0fa7f48ed4 build(vivado): add sd_bram to create_project.tcl, fix run instructions FallenSigh 2026-06-28 17:14:14 +08:00
  • f4493966ac test(top): stream raw xsim output to terminal (tee to log) FallenSigh 2026-06-28 16:52:27 +08:00
  • 74d8f021c9 test(top): add fast single-K / single-case runner to run_tb.sh FallenSigh 2026-06-28 16:46:33 +08:00
  • 75c350c1e4 refactor(kg): registered read-ahead for ST_M accumulate (bank_se/bank_t) FallenSigh 2026-06-28 16:37:07 +08:00
  • 9c08273c5f refactor(kg): registered read-ahead for ST_M load (bank_a + bank_se) FallenSigh 2026-06-28 16:27:00 +08:00
  • 45e07c28e8 refactor(kg): registered read-ahead for ST_N (bank_se NTT load) FallenSigh 2026-06-28 16:17:30 +08:00
  • 4d3adc6b57 refactor(kg): split polymem into 3 banks {a, se, t} (async, stage 2a) FallenSigh 2026-06-28 15:55:26 +08:00
  • 4f46c1cd02 build(vivado): point create_project.tcl at shared keccak_core variants FallenSigh 2026-06-28 15:36:36 +08:00
  • 460a6ed70c refactor(kg): share a single keccak_core across G/H, SampleNTT, CBD (4->1) FallenSigh 2026-06-28 15:35:55 +08:00
  • 851630f73c refactor(kg): merge G/H into single shared sha3_top (4->3 keccak_core) FallenSigh 2026-06-28 15:22:28 +08:00
  • 5a7d5d6a47 refactor(kg): move ek/dk_pke byte storage into BRAM (sd_bram) FallenSigh 2026-06-28 14:49:05 +08:00
  • 8774e03a0e build(vivado): rewrite create_project.tcl for current KeyGen flow FallenSigh 2026-06-28 03:43:56 +08:00
  • 3a53993754 refactor(kg): make ML-KEM K a runtime input k_i instead of a parameter FallenSigh 2026-06-28 03:24:58 +08:00
  • b7e4fd9323 test(top): add kat_k2_* vectors with uniform prefix for parametric TB FallenSigh 2026-06-28 03:06:41 +08:00
  • b2bf798454 feat(mlkem_top): parameterize K in {2,3,4} (ML-KEM 512/768/1024) FallenSigh 2026-06-28 02:59:58 +08:00
  • 2f46c0790f test(top): add xsim_run.tcl so run_tb.sh top runs KeyGen KAT 0..4 FallenSigh 2026-06-28 02:29:58 +08:00
  • 42d3748ab6 test(mlkem_top): KeyGen verified vs NIST KAT count=0..4 FallenSigh 2026-06-28 02:23:18 +08:00
  • 9824ed8f2c feat(mlkem_top): KeyGen stage 4 - H(ek) + full dk, end-to-end KAT pass FallenSigh 2026-06-28 02:18:52 +08:00
  • 17914911c3 feat(mlkem_top): KeyGen stage 2f (byteEncode12 -> ek, dk_pke) FallenSigh 2026-06-28 02:03:03 +08:00
  • a9e50ebc0c feat(mlkem_top): KeyGen stage 2e (matrix accumulate t_hat) FallenSigh 2026-06-28 01:53:23 +08:00
  • 4c692e570a feat(mlkem_top): KeyGen stage 2d (forward NTT of s/e) FallenSigh 2026-06-28 01:47:54 +08:00
  • 2f206a6bc5 feat(mlkem_top): KeyGen stages 2a-2c (G, SampleNTT A_hat, CBD s/e) FallenSigh 2026-06-28 01:41:44 +08:00
  • 6db3c7cc5e fix(sample_ntt): suppress spurious 257th valid_o after last_o FallenSigh 2026-06-28 01:35:35 +08:00
  • 106b2925a8 feat(sha3): multi-block SHA3-256 absorb for H(ek); KeyGen golden vectors FallenSigh 2026-06-27 23:37:23 +08:00
  • 4997657d7e test(comp_decomp): add ML-KEM-1024 d=11/d=5 compress/decompress cases FallenSigh 2026-06-27 21:04:57 +08:00
  • 4d7ce69405 fix(sample_ntt,sha3): FIPS-203 SHAKE-128 squeeze + self-checking sha3 TBs FallenSigh 2026-06-27 17:23:28 +08:00
  • 5d86000231 add docs and test data FallenSigh 2026-06-27 03:53:53 +08:00
  • 1cace51649 delete mlkem_top FallenSigh 2026-06-27 03:20:52 +08:00
  • 038ba8ecf2 fix(kg): byte-reverse d_reg before sha3_chain to match FIPS 203 FallenSigh 2026-06-27 03:01:34 +08:00
  • 0b7c76283b feat(create_project): add kg/en/de testbenches to Vivado project FallenSigh 2026-06-27 02:33:37 +08:00
  • 030d032657 chore(task): archive 06-27-kg-en-de-separate-tb FallenSigh 2026-06-27 02:27:28 +08:00
  • f211dc3c55 feat(tb): add independent KG/EN/DE testbenches FallenSigh 2026-06-27 02:27:22 +08:00
  • 6721c3c0c1 fix(create_project): replace -cd with -tclbatch pre-simulation vector copy FallenSigh 2026-06-27 02:19:22 +08:00
  • 9ef6d96117 fix(create_project): set xsim working directory to project root FallenSigh 2026-06-27 02:12:40 +08:00
  • d7e65e2cf8 chore(task): archive 06-27-vivado-project-tcl FallenSigh 2026-06-27 01:51:46 +08:00
  • ed83ef9da2 feat(tcl): add create_project.tcl for automatic Vivado project setup FallenSigh 2026-06-27 01:51:42 +08:00
  • d61efc96c3 chore(task): archive 06-27-fix-tb-strict-compare FallenSigh 2026-06-27 01:48:14 +08:00
  • 5e0ba7ad77 fix(tb): strict numerical pass/fail — FSM completion without value match now counts as FAIL FallenSigh 2026-06-27 01:46:35 +08:00
  • e3470c92e1 chore(task): archive 06-27-fix-kg-compute FallenSigh 2026-06-27 01:38:45 +08:00
  • 3284aa443f fix(kg): implement t_hat computation and pk/sk output in mlkem_top FallenSigh 2026-06-27 01:38:38 +08:00
  • 880e87daad fix(run_tb): allow digits in TCL variable names (e.g. SHA3_DIR) FallenSigh 2026-06-27 01:13:58 +08:00
  • 09efbef423 chore(task): archive 06-27-mlkem-top-tb FallenSigh 2026-06-27 01:07:40 +08:00
  • 0e6798beb5 feat(tb): add KAT testbench for mlkem_top (ML-KEM-512) FallenSigh 2026-06-27 01:07:34 +08:00
  • e3e02fc7ee chore(task): archive 06-26-mlkem-top-integration FallenSigh 2026-06-26 03:35:47 +08:00
  • 03b4707879 feat(top): add shared keccak variants, arbiter, and mlkem_top integration FallenSigh 2026-06-26 03:35:37 +08:00
  • 1983d840a7 docs: add comprehensive README.md FallenSigh 2026-06-26 00:41:52 +08:00
  • 92f851da84 chore: record journal FallenSigh 2026-06-25 22:23:15 +08:00
  • 37c4df2582 chore(task): archive 06-25-fix-tb-failures FallenSigh 2026-06-25 22:23:08 +08:00
  • f5365c9cf5 fix(tb): fix Vivado 2019.2 compilation and TB timing bugs FallenSigh 2026-06-25 21:32:19 +08:00
  • 06d771f4bc chore: record journal FallenSigh 2026-06-25 20:59:39 +08:00
  • 171ffd91d3 chore(task): archive 06-25-vivado-verilog-tb FallenSigh 2026-06-25 20:59:32 +08:00
  • db0a559826 fix(tb): fix run_tb.sh TCL variable extraction FallenSigh 2026-06-25 20:57:30 +08:00
  • 79653ac3a5 fix(tb): fix Vivado 2019.2 compatibility and add run_tb.sh FallenSigh 2026-06-25 20:53:47 +08:00
  • 52c625b3ef docs(spec): add XSIM testbench conventions to RTL spec FallenSigh 2026-06-25 20:48:44 +08:00
  • d4c3fc86fc feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules FallenSigh 2026-06-25 20:48:38 +08:00
  • ae5f0ca048 feat(sha3_chain): add simple SHA3_G integration test FallenSigh 2026-06-25 00:22:08 +08:00
  • a369a421b7 feat(phase3): implement storage BRAMs and Compress/Decompress FallenSigh 2026-06-24 23:28:06 +08:00
  • 209ca90fb1 feat(poly_arith): implement synchronous PolyAdd/PolySub streaming module FallenSigh 2026-06-24 23:12:59 +08:00
  • 39dd36994b feat(poly_mul): implement synchronous PolyMul with base-case multiply FallenSigh 2026-06-24 23:10:18 +08:00
  • c4cd10c2c1 feat(ntt): implement synchronous NTT core with Barrett modular reduction FallenSigh 2026-06-24 22:51:14 +08:00
  • 5941fee980 feat(phase1): implement RNG, SampleCBD, SampleNTT modules + xsim TBs FallenSigh 2026-06-24 21:32:53 +08:00
  • 453bc899fc feat(sha3): implement synchronous Keccak-f[1600] core with G/H/J modes FallenSigh 2026-06-24 20:33:44 +08:00