9 Commits

Author SHA1 Message Date
717a9929b6 fix(rtl,scripts): replace combinational divider with Barrett multiplication, add synthesis include_dirs, set 50MHz clock
- Replace / and % operators in comp_decomp_sync with Barrett multiply-by-reciprocal
  (dividend * 5039 >> 24) + correction step. Eliminates ~100 CARRY4 divider chain.
- Add include_dirs for sources_1 fileset so Windows Vivado synthesis finds defines.vh.
- Change CLK_PERIOD from 10.0 (100MHz) to 40.0 (50MHz) to reflect actual target.
2026-06-30 00:23:43 +08:00
ebf1182b6d fix(scripts): add missing RTL files to create_project.tcl, switch default sim to hello_world
- Add sync_rtl/common/pipeline_reg.v and sync_rtl/comp_decomp/comp_decomp_sync.v
  (were missing vs xsim_run.tcl, would cause elaboration failure)
- Change default top module from tb_mlkem_kg_katK_xsim to tb_mlkem_hello_world_xsim
- Remove unused SIM_KP/SIM_CASE variables and pre-compile KAT copy hook
2026-06-29 23:24:03 +08:00
0fa7f48ed4 build(vivado): add sd_bram to create_project.tcl, fix run instructions
mlkem_top instantiates sd_bram (ek/dk byte buffers) but create_project.tcl
was missing it -- elaboration would fail. Add sync_rtl/storage/sd_bram.v to
match xsim_run.tcl exactly. Also clarify the run flow: runtime=all means
launch_simulation runs to the TB $finish; a manual 'run all' afterwards trips
the 120ms watchdog and prints a spurious timeout.

Verified: vivado -mode batch builds the project (0 errors) and the simulation
prints 'K=2 CASE 0 PASS: ek==pk, dk==sk'.
2026-06-28 17:14:14 +08:00
4f46c1cd02 build(vivado): point create_project.tcl at shared keccak_core variants
Match the sim flow: use sha3_top_shared + sample_*_sync_shared so the Vivado
project synthesises the single-keccak_core datapath.
2026-06-28 15:36:36 +08:00
8774e03a0e build(vivado): rewrite create_project.tcl for current KeyGen flow
The old script referenced 5 non-existent files (keccak_arbiter,
sha3_chain_top_shared, tb_mlkem_top_xsim, tb_kg/en/de) and stale
vectors, so read_verilog/elaborate failed outright.

Rewrite to mirror the verified XSIM flow (sync_rtl/top/TB/xsim_run.tcl):
  - load exactly the 14 sources mlkem_top depends on
  - sim top = tb_mlkem_kg_katK_xsim, runtime K via generic KP, case via
    -testplusarg CASE
  - copy KAT vectors into the xsim working dir via xsim.compile.tcl.pre
    (the only hook in 2019.2 that runs before $readmemh; an appended
    -tclbatch runs after Vivado's own 'run all', too late)
  - drop duplicate --relax (XSim adds it; passing again is an error)

Verified through the actual Vivado batch project flow:
  K=2 CASE 0 -> PASS (21403 cyc), K=4 CASE 2 -> PASS (54059 cyc),
  0 file-not-found warnings. gitignore the generated vivado_prj/.

Also rewrite README.md in Chinese documenting the mlkem_top workflow
and test flow.
2026-06-28 03:43:56 +08:00
0b7c76283b feat(create_project): add kg/en/de testbenches to Vivado project 2026-06-27 02:33:37 +08:00
6721c3c0c1 fix(create_project): replace -cd with -tclbatch pre-simulation vector copy
Vivado 2019.2 xsim does not support -cd flag. Instead:
- Generate copy_vectors_pre.tcl that copies hex files
- Pass via -tclbatch for pre-simulation execution
-  can then find vectors relative to xsim work dir
2026-06-27 02:19:22 +08:00
9ef6d96117 fix(create_project): set xsim working directory to project root
Add -cd flag so  finds vector files when running
from Vivado GUI (simulation dir ≠ project root)
2026-06-27 02:12:40 +08:00
ed83ef9da2 feat(tcl): add create_project.tcl for automatic Vivado project setup
Creates Vivado simulation project with all 25 RTL source files,
shared keccak variants, mlkem_top, and tb_mlkem_top_xsim.

Usage: vivado -mode batch -source create_project.tcl
2026-06-27 01:51:42 +08:00