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build(vivado): add sd_bram to create_project.tcl, fix run instructions

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mlkem_top instantiates sd_bram (ek/dk byte buffers) but create_project.tcl
was missing it -- elaboration would fail. Add sync_rtl/storage/sd_bram.v to
match xsim_run.tcl exactly. Also clarify the run flow: runtime=all means
launch_simulation runs to the TB $finish; a manual 'run all' afterwards trips
the 120ms watchdog and prints a spurious timeout.

Verified: vivado -mode batch builds the project (0 errors) and the simulation
prints 'K=2 CASE 0 PASS: ek==pk, dk==sk'.
This commit is contained in:
FallenSigh
2026-06-28 17:14:14 +08:00
parent f4493966ac
commit 0fa7f48ed4
1 changed files with 12 additions and 3 deletions
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15
create_project.tcl
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@@ -2,7 +2,7 @@
# 顶层 mlkem_top 及其全部叶子算子与参数化 KAT testbench。
#
# 与已验证的 XSIM 流程（sync_rtl/top/TB/xsim_run.tcl）保持一致：
# - 仅加载 mlkem_top 实际依赖的 14 个源文件
# - 加载 mlkem_top 实际依赖的全部 RTL 源文件（含 sd_bram 存储）
# - 顶层仿真模块 = tb_mlkem_kg_katK_xsim
# - 运行时安全等级由 generic KP（2/3/4）选择，用例号由 +CASE 选择
#
@@ -30,7 +30,7 @@ create_project -force ${PROJECT_NAME} ${PROJECT_DIR}/vivado_prj
set_property target_simulator XSim [current_project]
# ===================================================================
# RTL 源文件 —— 与 xsim_run.tcl 完全一致的 14 个文件
# RTL 源文件 —— 与 xsim_run.tcl 完全一致
# ===================================================================
# ── SHA3 / Keccak ──
@@ -53,6 +53,9 @@ read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/basecase_mul.v
read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/poly_mul_zeta_rom.v
read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/poly_mul_sync.v
# ── 存储（ek/dk 字节缓冲，registered-read BRAM）──
read_verilog -sv ${PROJECT_DIR}/sync_rtl/storage/sd_bram.v
# ── 顶层 KeyGen 集成 ──
read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/mlkem_top.v
@@ -107,7 +110,13 @@ set_property -name {xsim.simulate.xsim.more_options} \
puts "========================================"
puts " Project created: ${PROJECT_DIR}/vivado_prj/${PROJECT_NAME}.xpr"
puts " 仿真配置: ML-KEM K=${SIM_KP}, KAT CASE=${SIM_CASE}"
puts " 运行仿真: launch_simulation; run all"
puts ""
puts " 运行仿真（runtime=all，会自动跑到 TB 的 \$finish）："
puts " - GUI: 打开工程后点 Run Simulation，或 Tcl Console: launch_simulation"
puts " - batch: vivado -mode batch -source create_project.tcl 后，"
puts " 另开: open_project vivado_prj/mlkem.xpr; launch_simulation"
puts " （勿在 launch_simulation 后再手动 run all —— 仿真已到 \$finish，"
puts " 再 run 会触发 TB 的 120ms 看门狗误报 timeout）"
puts " 期望输出: K=${SIM_KP} CASE ${SIM_CASE} PASS: ek==pk, dk==sk"
puts ""
puts " 切换配置（如 K=4）：编辑脚本顶部 SIM_KP/SIM_CASE 重跑本脚本，"