FallenSigh
9ef6d96117
Add -cd flag so finds vector files when running from Vivado GUI (simulation dir ≠ project root)
84 lines
3.2 KiB
Tcl
84 lines
3.2 KiB
Tcl
# create_project.tcl — 自动创建 Vivado 工程，添加所有 RTL 源文件和 testbench
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#
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# Usage:
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# cd ~/Dev/mlkem
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# vivado -mode batch -source create_project.tcl
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#
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# Or in Vivado Tcl Console:
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# source create_project.tcl
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set PROJECT_NAME mlkem
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set PROJECT_DIR [file normalize [file dirname [info script]]]
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# Create project (simulation-only, no FPGA part needed)
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create_project -force ${PROJECT_NAME} ${PROJECT_DIR}/vivado_prj
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# Set top-level testbench
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set_property top tb_mlkem_top_xsim [current_fileset -simset]
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set_property target_simulator XSim [current_project]
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# ── Common infrastructure ──
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read_verilog -sv [glob ${PROJECT_DIR}/sync_rtl/common/*.v]
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# ── SHA3 / Keccak ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/keccak_round.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/keccak_core.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/sha3_top.v
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# ── SHA3 Chain (shared variant for top-level integration) ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3_chain/sha3_chain_top_shared.v
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# ── RNG ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/rng/rng_sync.v
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# ── NTT ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/zeta_rom.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/barrett_mul.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/butterfly_unit.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/ntt_core.v
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# ── Polynomial Arithmetic ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_arith/poly_arith_sync.v
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# ── Polynomial Multiplication ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/poly_mul_zeta_rom.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/basecase_mul.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/poly_mul_sync.v
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# ── Sampling ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/sample_cbd/sample_cbd_sync_shared.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/sample_ntt/sample_ntt_sync_shared.v
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# ── Compression & Modular Arithmetic ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/comp_decomp/comp_decomp_sync.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/mod_add/mod_add_sync.v
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# ── Storage (BRAM) ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/storage/s_bram.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/storage/sd_bram.v
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# ── Top-level Integration ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/keccak_arbiter.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/mlkem_top.v
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# ── Testbench ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/TB/tb_mlkem_top_xsim.v
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# ── Include path for `include directives ──
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set_property include_dirs ${PROJECT_DIR} [current_fileset -simset]
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# ── Simulation settings ──
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set_property -name {xsim.simulate.runtime} -value {all} -objects [get_filesets sim_1]
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set_property -name {xsim.elaborate.xelab.more_options} -value {--timescale 1ns/1ps} -objects [get_filesets sim_1]
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# Set simulation working directory to project root (for $readmemh to find vectors/)
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set_property -name {xsim.simulate.xsim.more_options} -value "-cd ${PROJECT_DIR}" -objects [get_filesets sim_1]
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# Save project
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puts "========================================"
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puts " Project created: ${PROJECT_DIR}/vivado_prj/${PROJECT_NAME}.xpr"
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puts " Run simulation:"
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puts " launch_simulation"
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puts " run all"
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puts "========================================"
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