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fix(rtl,scripts): replace combinational divider with Barrett multiplication, add synthesis include_dirs, set 50MHz clock

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- Replace / and % operators in comp_decomp_sync with Barrett multiply-by-reciprocal
  (dividend * 5039 >> 24) + correction step. Eliminates ~100 CARRY4 divider chain.
- Add include_dirs for sources_1 fileset so Windows Vivado synthesis finds defines.vh.
- Change CLK_PERIOD from 10.0 (100MHz) to 40.0 (50MHz) to reflect actual target.
This commit is contained in:
FallenSigh
2026-06-30 00:23:43 +08:00
parent ebf1182b6d
commit 717a9929b6
3 changed files with 57 additions and 35 deletions
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3
create_project.tcl
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@@ -66,8 +66,9 @@ read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/TB/tb_mlkem_hello_world_xsim.v
set_property top tb_mlkem_hello_world_xsim [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
# `include "sync_rtl/common/defines.vh" 的包含路径（相对工程根）
# `include "sync_rtl/common/defines.vh" 的包含路径（同时用于仿真和综合）
set_property include_dirs ${PROJECT_DIR} [get_filesets sim_1]
set_property include_dirs ${PROJECT_DIR} [get_filesets sources_1]
# hello_world TB 使用 localparam KP=2（硬编码），无 generic 传入
# 切换 K 值需编辑 tb_mlkem_hello_world_xsim.v 中的 KP 参数后重跑