Wrap mlkem_top in an AXI4 burst slave (mlkem_axi_slave) mapped to the
freed FFT slot 6 at 0x1f400000 (virtual 0xbf400000). The core runs on
sys_clk/2 (25 MHz); the wrapper handles the clock-domain crossing:
start toggle->pulse, wait-stated byte-preload handshake, busy/done
sync, and direct readback taps (ek/dk/ct/ss). CPU drives it via a
register map (CTRL/STATUS/CONFIG, d/z/msg, preload + readback windows).
Wire into soc_top on the existing axiOut_6 nets (no crossbar change),
add mlkem_intr on intrpt[3]. Add sdk mlkem_test example running a
KeyGen->Encaps->Decaps self-consistency round trip.
uart_puts(13B) + uart_puthex(8B) = 21 bytes without polling → FIFO overflow.
Board UART IP asserts AXI error → CPU syserr exception.
Simulation UART model is lenient, so sim passed but board failed.
Back to per-byte polling (safe).
uart_puts: burst-write up to 16 chars before polling LSR
uart_puthex: write all 8 hex digits without polling (8 < 16 FIFO depth)
Reduces AXI register reads from ~50 to ~3 per CRC output.
Each saved poll: -1 uncached AXI read (~390ns)
Each uncached TAG write costs ~810ns on the AXI bus. Removed:
- 2 TAG writes per main loop iteration (Ch1 store + Ch0 pre-fire)
- 2 TAG writes in prologue (group 0 load + pre-fire group 1)
- 1 TAG write in epilogue (final store)
Total: ~10,000 wasted AXI transactions eliminated for 5000 groups.
Estimated ~8% reduction in per-iteration time.
Removed:
- confreg_time.h and common_func.h includes
- All get_ns() calls (6 in prologue/loop/epilogue boundaries)
- All timing variables (t_prologue, t_mainloop, t_epilogue)
- All TIME_* printf markers
- Unused extram pointer and stdbool.h
Only essential output remains: MATMUL_START, MATMUL_CRC32, MATMUL_DONE
- 5000 groups (N_GROUPS=5000), group 0 all-zero as required
- MATMUL_START before computation, MATMUL_DONE after CRC
- IEEE CRC32 over 960000-byte result region (little-endian words)
- MATMUL_CRC32=XXXXXXXX format, 8 hex digits, no 0x prefix
- Uncached ExtRAM access (0xA0000000 segment)
- Removed all debug output for minimal UART traffic
The open-la500 core has USE_CACHE enabled. Writes to 0x1c400000
go to the write-back data cache and never reach the SRAM model
before the testbench checks ExtRAM. Use the 0xA0000000 uncached
segment (same pattern as fft_dma/main.c).
The open-la500 CPU maps 0xbfxx_xxxx to the peripheral address space
(crossbar sees 0x1fxx_xxxx). FFT uses 0xbf400000, CONFREG uses
0xbf20f100, UART uses 0xbf000000. Matmul must follow the same
convention.
