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FallenSigh c37f493bcb Compute matmul CRC before result store

2026-07-04 19:45:22 +08:00

..

software

Compute matmul CRC before result store

2026-07-04 19:45:22 +08:00

axi_ram.mif

Add direct CDMA matmul path

2026-07-04 19:15:34 +08:00

fft_dma.bin

Remove all debug and printf

2026-06-25 15:44:18 +08:00

fft.bin

Remove all debug and printf

2026-06-25 15:44:18 +08:00

hello_world.bin

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

mlkem_test.bin

fix: replace UNUSEDPARAM/UNUSEDSIGNAL with UNUSED for verilator lint

2026-06-30 02:10:07 +08:00

toolchains

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

user-sample.bin

Add direct CDMA matmul path

2026-07-04 19:15:34 +08:00