This repository has been archived on 2026-08-21. You can view files and clone it. You cannot open issues or pull requests or push a commit.

FallenSigh b8a4fcc30b Fix matmul_base address: 0x1f500000 -> 0xbf500000 ...

The open-la500 CPU maps 0xbfxx_xxxx to the peripheral address space
(crossbar sees 0x1fxx_xxxx). FFT uses 0xbf400000, CONFREG uses
0xbf20f100, UART uses 0xbf000000. Matmul must follow the same
convention.

2026-06-24 01:58:29 +08:00

..

software

Fix matmul_base address: 0x1f500000 -> 0xbf500000

2026-06-24 01:58:29 +08:00

axi_ram.mif

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

hello_world.bin

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

toolchains

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00