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FallenSigh 95fe94063c fix: revert UART FIFO batching — caused FIFO overflow + syserr on board ...

uart_puts(13B) + uart_puthex(8B) = 21 bytes without polling → FIFO overflow.
Board UART IP asserts AXI error → CPU syserr exception.
Simulation UART model is lenient, so sim passed but board failed.

Back to per-byte polling (safe).

2026-06-26 23:53:15 +08:00

..

software

fix: revert UART FIFO batching — caused FIFO overflow + syserr on board

2026-06-26 23:53:15 +08:00

axi_ram.mif

perf(matmul): pre-fire DMA Ch0 load + inline wait/DMA start + XOR bank toggle

2026-06-26 03:39:32 +08:00

fft_dma.bin

Remove all debug and printf

2026-06-25 15:44:18 +08:00

fft.bin

Remove all debug and printf

2026-06-25 15:44:18 +08:00

hello_world.bin

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

toolchains

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

user-sample.bin

perf(matmul): pre-fire DMA Ch0 load + inline wait/DMA start + XOR bank toggle

2026-06-26 03:39:32 +08:00