fix(rtl): add use_dsp="no" attributes, fix duplicate wire declaration
Add (* use_dsp = "no" *) to all modules containing multiplication operators to force LUT-based multiplication instead of DSP inference: - barrett_mul.v (3 multipliers x 7 instances = 21 ops) - comp_decomp_sync.v, sample_ntt_sync*.v, mlkem_top.v Also fix duplicate wire declaration of ct_bytes_rt in mlkem_top.v.
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@@ -10,6 +10,7 @@
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`include "sync_rtl/common/defines.vh"
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(* use_dsp = "no" *)
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module comp_decomp_sync (
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input clk,
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input rst_n,
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@@ -6,6 +6,7 @@
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// Pure combinational, single-cycle latency.
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// All multiplication widths explicitly controlled to avoid Verilog truncation.
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(* use_dsp = "no" *)
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module barrett_mul (
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input [11:0] a,
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input [11:0] b,
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@@ -31,6 +31,7 @@
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`include "sync_rtl/common/defines.vh"
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/* verilator lint_off UNUSEDPARAM */
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(* use_dsp = "no" *)
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module sample_ntt_sync #(parameter K = 4) (
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/* verilator lint_on UNUSEDPARAM */
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input clk,
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@@ -44,6 +44,7 @@
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`include "sync_rtl/common/defines.vh"
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/* verilator lint_off UNUSEDPARAM */
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(* use_dsp = "no" *)
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module sample_ntt_sync_shared #(parameter K = 4) (
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/* verilator lint_on UNUSEDPARAM */
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input clk,
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@@ -22,6 +22,7 @@
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`include "sync_rtl/common/defines.vh"
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(* use_dsp = "no" *)
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module mlkem_top #(
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parameter KMAX = 4 // storage sizing (worst case = ML-KEM-1024)
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) (
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@@ -133,7 +134,6 @@ module mlkem_top #(
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wire [11:0] c1_bytes_rt = 12'd32 * {7'b0, du_rt} * {9'b0, k_r}; // 640/960/1408
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wire [11:0] c2_bytes_rt = 12'd32 * {7'b0, dv_rt}; // 128/128/160
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wire [11:0] ct_bytes_rt = c1_bytes_rt + c2_bytes_rt; // 768/1088/1568
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wire [11:0] ct_bytes_rt = c1_bytes_rt + c2_bytes_rt; // 768/1088/1568
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// Shared secret out: Encaps drives ss_r = K directly. Decaps implicit reject:
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// ss = (c' == c) ? K' : K-bar. K' is in ss_r, K-bar in kbar_r; dec_reject is
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// the latched c' != c flag from D7 (0 for KeyGen/Encaps, so ss_r passes through).
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