fallensigh/mlkem-sync
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  • db0a559826 fix(tb): fix run_tb.sh TCL variable extraction FallenSigh 2026-06-25 20:57:30 +08:00
  • 79653ac3a5 fix(tb): fix Vivado 2019.2 compatibility and add run_tb.sh FallenSigh 2026-06-25 20:53:47 +08:00
  • 52c625b3ef docs(spec): add XSIM testbench conventions to RTL spec FallenSigh 2026-06-25 20:48:44 +08:00
  • d4c3fc86fc feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules FallenSigh 2026-06-25 20:48:38 +08:00
  • ae5f0ca048 feat(sha3_chain): add simple SHA3_G integration test FallenSigh 2026-06-25 00:22:08 +08:00
  • a369a421b7 feat(phase3): implement storage BRAMs and Compress/Decompress FallenSigh 2026-06-24 23:28:06 +08:00
  • 209ca90fb1 feat(poly_arith): implement synchronous PolyAdd/PolySub streaming module FallenSigh 2026-06-24 23:12:59 +08:00
  • 39dd36994b feat(poly_mul): implement synchronous PolyMul with base-case multiply FallenSigh 2026-06-24 23:10:18 +08:00
  • c4cd10c2c1 feat(ntt): implement synchronous NTT core with Barrett modular reduction FallenSigh 2026-06-24 22:51:14 +08:00
  • 5941fee980 feat(phase1): implement RNG, SampleCBD, SampleNTT modules + xsim TBs FallenSigh 2026-06-24 21:32:53 +08:00
  • 453bc899fc feat(sha3): implement synchronous Keccak-f[1600] core with G/H/J modes FallenSigh 2026-06-24 20:33:44 +08:00
  • 94783441b4 chore: add .gitignore, remove build artifacts and pycache from tracking FallenSigh 2026-06-24 19:43:46 +08:00
  • a293e20d51 chore: add .gitignore, remove build artifacts from tracking FallenSigh 2026-06-24 19:43:40 +08:00
  • 8fdf944555 feat: init mlkem project with Verilator test framework FallenSigh 2026-06-24 19:43:29 +08:00