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4
.gitignore
vendored
4
.gitignore
vendored
@@ -17,6 +17,10 @@ webtalk*.jou
|
||||
*.str
|
||||
vivado_pid*.txt
|
||||
*.bit
|
||||
*_netlist.v
|
||||
*_netlist.vhdl
|
||||
*_stub.v
|
||||
*_stub.vhdl
|
||||
|
||||
# ========================================
|
||||
# Generated binary / AXI images
|
||||
|
||||
39
README.md
Normal file
39
README.md
Normal file
@@ -0,0 +1,39 @@
|
||||
# 2026年全国大学生集成电路创新创业大赛 - 龙芯中科杯
|
||||
|
||||
本仓库为 2026年全国大学生集成电路创新创业大赛（CICC） “龙芯中科”企业命题的参赛代码仓库。
|
||||
|
||||
## 团队信息
|
||||
|
||||
- 队伍编号：CICC1008439
|
||||
- 队伍名称：碳基生物
|
||||
- 参赛赛道：龙芯中科企业命题
|
||||
|
||||
## 项目简介
|
||||
|
||||
本项目基于龙芯指令集架构（Loongson Architecture），针对特定应用场景（如数字信号处理/嵌入式系统优化）设计了一套高性能的系统级芯片（SoC）或核心外设子系统。旨在充分发挥龙芯架构的优势，通过自定义硬件加速器和高效的总线管理提升系统整体效能。
|
||||
|
||||
## 已完成功能模块
|
||||
|
||||
- 外部中断控制器
|
||||
- FFT 硬件加速器
|
||||
- 8-channel mm2mm/mm2ep/ep2mm DMA 控制器
|
||||
- 4x4矩阵加速器
|
||||
- MLKEM算法加速器
|
||||
|
||||
## 目录结构
|
||||
|
||||
```
|
||||
.
|
||||
├── fpga/ # Vivado工程文件与Tcl自动化构建脚本
|
||||
├── doc/ # 参赛技术文档、设计说明书及测试报告
|
||||
├── rtl/ # 硬件源代码 (龙芯核、中断控制器、FFT、DMA等)
|
||||
├── sdk/ # 嵌入式软件开发 (针对龙芯架构的C语言驱动与应用)
|
||||
├── sim/ # 仿真验证环境 (Testbench与仿真脚本)
|
||||
└── README.md # 项目总体说明与快速上手指南
|
||||
```
|
||||
|
||||
## 参考文献
|
||||
|
||||
[1] nelsoncsc. verilaxi[EB/OL]. https://github.com/nelsoncsc/verilaxi, 2026-05-05.
|
||||
|
||||
[2] alexforencich. verilog-axi[EB/OL]. https://github.com/alexforencich/verilog-axi, 2026-05-05.
|
||||
@@ -1,262 +0,0 @@
|
||||
# ML-KEM AXI Slave 寄存器参考手册
|
||||
|
||||
## 概述
|
||||
|
||||
`mlkem_axi_slave` 是 ML-KEM 硬件加速器的 AXI4 Slave 总线接口。它封装 `mlkem_top` 核心，提供完整的寄存器映射用于软件控制 KeyGen / Encaps / Decaps 操作。
|
||||
|
||||
### 关键特性
|
||||
|
||||
- **总线**: AXI4 (支持 INCR burst read/write)
|
||||
- **基址**: `0xbf400000`（LoongArch 虚地址）
|
||||
- **时钟域**: sys_clk (50 MHz) → mlkem_clk (25 MHz)，跨域通过 toggle 握手同步
|
||||
- **支持参数**: k=2 (ML-KEM-512), k=3 (ML-KEM-768), k=4 (ML-KEM-1024)
|
||||
- **中断**: `intr` 信号，当 done 标志锁存时电平有效高
|
||||
|
||||
---
|
||||
|
||||
## 寄存器映射
|
||||
|
||||
所有寄存器为 32-bit 对齐。偏移量相对于基址 `0xbf400000`。
|
||||
|
||||
| 偏移 | 名称 | 访问 | 复位值 | 描述 |
|
||||
|------|------|------|--------|------|
|
||||
| `0x000` | **CTRL** | W | `0x00000000` | 控制寄存器：写 bit0=1 启动操作 |
|
||||
| `0x004` | **STATUS** | R/W1C | `0x00000000` | 状态寄存器 |
|
||||
| `0x008` | **CONFIG** | RW | `0x00000004` | 配置寄存器：k 值和操作码 |
|
||||
| `0x010`–`0x02C` | **D[0..7]** | RW | `0x00000000` | KeyGen 种子 d（256-bit，8字） |
|
||||
| `0x030`–`0x04C` | **Z[0..7]** | RW | `0x00000000` | KeyGen 隐式拒绝种子 z（256-bit，8字） |
|
||||
| `0x050`–`0x06C` | **MSG[0..7]** | RW | `0x00000000` | Encaps 消息 m（256-bit，8字） |
|
||||
| `0x070`–`0x08C` | **SS[0..7]** | R | — | 共享密钥输出（256-bit，8字，只读） |
|
||||
| `0x100` | **PRELOAD_SEL** | RW | `0x00000000` | 预载端口选择 |
|
||||
| `0x104` | **PRELOAD_ADDR** | RW | `0x00000000` | 预载字节地址（写入后自动递增） |
|
||||
| `0x108` | **PRELOAD_DATA** | W | — | 预载数据字节（写低 8-bit，自动 wait-state） |
|
||||
| `0x10C` | **READBACK_SEL** | RW | `0x00000000` | 回读端口选择 |
|
||||
| `0x110` | **READBACK_ADDR** | RW | `0x00000000` | 回读字节索引（无自动递增） |
|
||||
| `0x114` | **READBACK_DATA** | R | — | 回读数据字节（低 8-bit 有效） |
|
||||
|
||||
---
|
||||
|
||||
## 寄存器详情
|
||||
|
||||
### CTRL (0x000) — 控制寄存器，只写
|
||||
|
||||
| Bits | 名称 | 描述 |
|
||||
|------|------|------|
|
||||
| `0` | **start** | 写 `1` 启动当前 CONFIG 中配置的操作。写 `0` 无效。 |
|
||||
|
||||
- 写 start 后，STATUS.busy 立即置位，done 清零。
|
||||
- 操作完成前不可再次启动。
|
||||
- CTRL 本身不可读（读返回 0）。
|
||||
|
||||
---
|
||||
|
||||
### STATUS (0x004) — 状态寄存器，读/写1清零
|
||||
|
||||
| Bits | 名称 | 访问 | 描述 |
|
||||
|------|------|------|------|
|
||||
| `0` | **busy** | R | 核心正在执行操作（KeyGen/Encaps/Decaps） |
|
||||
| `1` | **done** | R/W1C | 操作已完成。写 `1` 清除（写 `0` 无效）。启动新操作时自动清除 |
|
||||
| `2` | **preload_busy** | R | 预载数据传输正在进行中（跨域字节握手未完成） |
|
||||
| `31:3` | — | — | 保留，读为 0 |
|
||||
|
||||
**注意**:
|
||||
- `done` 是**锁存**标志：操作完成后保持为 1，直到软件写 1 清零或启动新操作。
|
||||
- `busy` 和 `done` **不互斥**：在 done 置位的同一周期 busy 清零，两者可能同时为 1（短暂窗口）。
|
||||
- `preload_busy` 为 1 时，写入 PRELOAD_DATA 会被 wait-state 直到传输完成。
|
||||
|
||||
---
|
||||
|
||||
### CONFIG (0x008) — 配置寄存器，读写
|
||||
|
||||
| Bits | 名称 | 复位值 | 描述 |
|
||||
|------|------|--------|------|
|
||||
| `2:0` | **k** | `3'b100` (4) | ML-KEM 参数：`2`=ML-KEM-512, `3`=ML-KEM-768, `4`=ML-KEM-1024 |
|
||||
| `4` | — | `0` | 保留 |
|
||||
| `5:4` | **op** | `2'b00` | 操作码：`0`=KeyGen, `1`=Encaps, `2`=Decaps |
|
||||
| `31:6` | — | `0` | 保留 |
|
||||
|
||||
**约束**:
|
||||
- 修改 CONFIG 应在启动操作之前完成。启动后修改可能导致未定义行为。
|
||||
- k 必须为 2、3 或 4。
|
||||
|
||||
---
|
||||
|
||||
### D[0..7] (0x010–0x02C) — KeyGen 种子 d，读写
|
||||
|
||||
256-bit 种子 `d`，用于 KeyGen 操作。存储为 8 个 32-bit 字，小端序：
|
||||
|
||||
| 字偏移 | 地址 | 包含字节 |
|
||||
|--------|------|---------|
|
||||
| D[0] | `0x010` | d[3:0]（字节 3 在 bit[31:24]，字节 0 在 bit[7:0]） |
|
||||
| D[1] | `0x014` | d[7:4] |
|
||||
| ... | ... | ... |
|
||||
| D[7] | `0x02C` | d[31:28] |
|
||||
|
||||
核心看到的 256-bit 总线为 `{D[7], D[6], ..., D[0]}`，其中 `d_i[7:0]` = D[0][7:0]。
|
||||
|
||||
支持 AXI wstrb 按字节写入。
|
||||
|
||||
---
|
||||
|
||||
### Z[0..7] (0x030–0x04C) — 隐式拒绝种子 z，读写
|
||||
|
||||
256-bit 种子 `z`，用于 KeyGen。布局与 D 相同。
|
||||
|
||||
---
|
||||
|
||||
### MSG[0..7] (0x050–0x06C) — Encaps 消息 m，读写
|
||||
|
||||
256-bit 消息 `m`，用于 Encaps。布局与 D 相同。
|
||||
|
||||
---
|
||||
|
||||
### SS[0..7] (0x070–0x08C) — 共享密钥，只读
|
||||
|
||||
256-bit 共享密钥输出。KeyGen 和 Encaps 操作完成后在此处提供结果。
|
||||
|
||||
| 字偏移 | 地址 | 内容 |
|
||||
|--------|------|------|
|
||||
| SS[0] | `0x070` | ss[31:0] |
|
||||
| SS[1] | `0x074` | ss[63:32] |
|
||||
| ... | ... | ... |
|
||||
| SS[7] | `0x08C` | ss[255:224] |
|
||||
|
||||
---
|
||||
|
||||
### PRELOAD_SEL (0x100) — 预载端口选择，读写
|
||||
|
||||
| Bits | 名称 | 描述 |
|
||||
|------|------|------|
|
||||
| `1:0` | **sel** | 预载目标端口：`0`=ek, `1`=dk, `2`=c（密文） |
|
||||
| `31:2` | — | 保留 |
|
||||
|
||||
设置后，随后写入 PRELOAD_DATA 的字节将流向所选端口。
|
||||
|
||||
---
|
||||
|
||||
### PRELOAD_ADDR (0x104) — 预载字节地址，读写
|
||||
|
||||
| Bits | 名称 | 描述 |
|
||||
|------|------|------|
|
||||
| `11:0` | **addr** | 预载端口内的字节偏移地址。每次 PRELOAD_DATA 写入成功后自动递增 |
|
||||
| `31:12` | — | 保留 |
|
||||
|
||||
写入 PRELOAD_DATA 前必须先设置好 PRELOAD_SEL 和 PRELOAD_ADDR（通常 addr=0）。
|
||||
|
||||
---
|
||||
|
||||
### PRELOAD_DATA (0x108) — 预载数据字节，只写
|
||||
|
||||
| Bits | 名称 | 描述 |
|
||||
|------|------|------|
|
||||
| `7:0` | **byte** | 写入所选预载端口的字节数据 |
|
||||
| `31:8` | — | 忽略 |
|
||||
|
||||
此寄存器**自动 wait-state**：写入后 AXI 总线暂停，直到跨域握手完成（字节被 mlkem 核心采样）。然后 PRELOAD_ADDR 自动递增 1。
|
||||
|
||||
**重要**: 每个字节需要一次 AXI 写事务。对于大数据量（ek=800B, dk=1632B），建议使用 INCR burst 写，burst 长度设为字节数。
|
||||
|
||||
---
|
||||
|
||||
### READBACK_SEL (0x10C) — 回读端口选择，读写
|
||||
|
||||
| Bits | 名称 | 描述 |
|
||||
|------|------|------|
|
||||
| `1:0` | **sel** | 回读源：`0`=ek, `1`=dk_pke, `2`=完整 dk, `3`=密文 |
|
||||
| `31:2` | — | 保留 |
|
||||
|
||||
---
|
||||
|
||||
### READBACK_ADDR (0x110) — 回读字节索引，读写
|
||||
|
||||
| Bits | 名称 | 描述 |
|
||||
|------|------|------|
|
||||
| `11:0` | **addr** | 待读取字节在回读端口中的索引。**无自动递增** |
|
||||
| `31:12` | — | 保留 |
|
||||
|
||||
每个字节的读取流程：写 READBACK_ADDR → 读 READBACK_DATA。
|
||||
|
||||
---
|
||||
|
||||
### READBACK_DATA (0x114) — 回读数据字节，只读
|
||||
|
||||
| Bits | 名称 | 描述 |
|
||||
|------|------|------|
|
||||
| `7:0` | **byte** | 所选回读端口中 READBACK_ADDR 索引处的字节 |
|
||||
| `31:24` | — | 读为 0 |
|
||||
|
||||
---
|
||||
|
||||
## 操作流程
|
||||
|
||||
### 1. KeyGen: (d, z) → ek, dk
|
||||
|
||||
```
|
||||
1. 写 CONFIG: op=0 (KeyGen), k=2/3/4
|
||||
2. 写 D[0..7] ← 种子 d (256-bit)
|
||||
3. 写 Z[0..7] ← 种子 z (256-bit)
|
||||
4. 写 CTRL: bit0=1 → 启动
|
||||
5. 轮询 STATUS.done == 1（或等待 intr）
|
||||
6. 通过 READBACK 读取 ek 和 dk:
|
||||
a. RDB_SEL=0, 逐个字节读 ADDR=0..799 → ek (800 B for k=2)
|
||||
b. RDB_SEL=2, 逐个字节读 ADDR=0..1631 → dk (1632 B for k=2)
|
||||
7. 读 SS[0..7] → 共享密钥（可选）
|
||||
8. 写 STATUS: bit1=1 → 清除 done
|
||||
```
|
||||
|
||||
### 2. Encaps: (ek, m) → (ss, ct)
|
||||
|
||||
```
|
||||
1. 写 CONFIG: op=1 (Encaps), k=2/3/4
|
||||
2. 通过 PRELOAD 预载 ek:
|
||||
a. PRE_SEL=0, PRE_ADR=0
|
||||
b. 逐个字节写 PRE_DAT (800 B for k=2)
|
||||
3. 写 MSG[0..7] ← 消息 m (256-bit)
|
||||
4. 写 CTRL: bit0=1 → 启动
|
||||
5. 轮询 STATUS.done == 1
|
||||
6. 读 SS[0..7] → 共享密钥
|
||||
7. 通过 READBACK 读取 ct:
|
||||
a. RDB_SEL=3, 逐个字节读 ADDR=0..767 → ct (768 B for k=2)
|
||||
```
|
||||
|
||||
### 3. Decaps: (dk, ct) → ss
|
||||
|
||||
```
|
||||
1. 写 CONFIG: op=2 (Decaps), k=2/3/4
|
||||
2. 通过 PRELOAD 预载 dk 和 ct:
|
||||
a. PRE_SEL=1, PRE_ADR=0, 逐个字节写 PRE_DAT (1632 B for k=2)
|
||||
b. PRE_SEL=2, PRE_ADR=0, 逐个字节写 PRE_DAT (768 B for k=2)
|
||||
3. 写 CTRL: bit0=1 → 启动
|
||||
4. 轮询 STATUS.done == 1
|
||||
5. 读 SS[0..7] → 共享密钥
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## 数据尺寸参考
|
||||
|
||||
| 参数 | k=2 (ML-KEM-512) | k=3 (ML-KEM-768) | k=4 (ML-KEM-1024) |
|
||||
|------|-------------------|-------------------|---------------------|
|
||||
| ek 字节数 | 800 | 1184 | 1568 |
|
||||
| dk_pke 字节数 | 768 | 1152 | 1536 |
|
||||
| dk 总字节数 | 1632 | 2400 | 3168 |
|
||||
| ct 字节数 | 768 | 1088 | 1568 |
|
||||
|
||||
---
|
||||
|
||||
## 中断
|
||||
|
||||
- `intr` 信号在 `STATUS.done == 1` 时保持高电平。
|
||||
- 清除中断：写 `STATUS` 的 bit1=1（W1C）或启动新操作。
|
||||
- `intr` 是电平触发（非脉冲），连接到 LoongArch 的 HWI 输入。
|
||||
|
||||
---
|
||||
|
||||
## 注意事项
|
||||
|
||||
1. **时钟域**: 核心运行在 sys_clk/2 (25 MHz)。PRELOAD_DATA 写入自动 wait-state，软件无需处理跨域延迟。
|
||||
2. **启动时序**: 确保在写 CTRL.start 之前，config/seeds/preload 数据已全部写入且稳定。
|
||||
3. **PRELOAD_ADDR 自动递增**: 连续写 PRELOAD_DATA 时地址自动递增，无需手动更新 PRELOAD_ADDR（除非切换端口）。
|
||||
4. **READBACK_ADDR 无自动递增**: 每次读 READBACK_DATA 前必须手动写 READBACK_ADDR。
|
||||
5. **done 标志**: 是锁存的，启动新操作时自动清除。连续执行多个操作时，每次启动前先确认 busy==0，然后清 done。
|
||||
6. **STATUS 读取时机**: done 标志在操作完成的 mlkem_clk 周期后，需经 2 级同步器（~40ns）才能在 sys_clk 域看到。
|
||||
@@ -1,45 +0,0 @@
|
||||
# ML-KEM Test Results Summary
|
||||
|
||||
## Test Setup
|
||||
|
||||
- Platform: LoongArch bare-metal target
|
||||
- Test mode: `STATIC_KAT_COUNT_0`
|
||||
- Levels: `k=2,3,4`
|
||||
- Repeat count: `100`
|
||||
- ML-KEM software allocator: `MLK_CONFIG_CUSTOM_ALLOC_FREE`
|
||||
- Verification sources: KAT count 0 expected values
|
||||
|
||||
## Correctness
|
||||
|
||||
All three paths passed in isolated testing:
|
||||
|
||||
- `SW_ONLY_FAILS=0`
|
||||
- `CPU_ONLY_FAILS=0`
|
||||
- `DMA_ONLY_FAILS=0`
|
||||
|
||||
Final result for the isolated diagnostic run:
|
||||
|
||||
- `MLKEM512_RESULT=PASS`
|
||||
- `MLKEM768_RESULT=PASS`
|
||||
- `MLKEM1024_RESULT=PASS`
|
||||
- `MLKEM_RESULT=PASS`
|
||||
|
||||
## Performance
|
||||
|
||||
The following results are from isolated per-level runs. Each level was tested
|
||||
for 100 iterations with software-only, CPU register path, and DMA path separated.
|
||||
|
||||
| Level | SW avg cycles | CPU avg cycles | DMA avg cycles | CPU vs SW | DMA vs SW | DMA vs CPU |
|
||||
|---|---:|---:|---:|---:|---:|---:|
|
||||
| k=2 / ML-KEM-512 | 2,587,784 | 352,684 | 185,671 | 7.34x | 13.94x | 1.90x |
|
||||
| k=3 / ML-KEM-768 | 4,056,378 | 523,656 | 279,588 | 7.75x | 14.51x | 1.87x |
|
||||
| k=4 / ML-KEM-1024 | 6,025,486 | 718,672 | 388,959 | 8.38x | 15.49x | 1.85x |
|
||||
|
||||
## Notes
|
||||
|
||||
- CPU/DMA hardware paths were stable across 100 iterations for all levels.
|
||||
- Software, CPU register path, and DMA path all passed 100 iterations for k=2, k=3, and k=4.
|
||||
- The DMA path is 13.94x to 15.49x faster than software across the tested levels.
|
||||
- The CPU register path is 7.34x to 8.38x faster than software across the tested levels.
|
||||
- The DMA path is about 1.85x to 1.90x faster than the CPU register path.
|
||||
- The hardware advantage increases slightly as k grows, because the accelerated computation grows faster than the fixed software control overhead.
|
||||
Binary file not shown.
@@ -60,7 +60,7 @@
|
||||
\fontsize{14pt}{22pt}\selectfont
|
||||
报告类型：\uline{\hfill 后端设计实践报告\hfill} \\[18pt]
|
||||
参赛杯赛：\uline{\hfill 龙芯中科杯\hfill} \\[18pt]
|
||||
作品名称：\uline{\hfill 基于龙芯SoC的后量子密码与矩阵运算加速系统芯片后端设计\hfill} \\[18pt]
|
||||
作品名称：\uline{\hfill 基于LoongArch SoC 的后量子密码与矩阵运算加速系统\hfill} \\[18pt]
|
||||
队伍编号：\uline{\hfill CICC1008439\hfill} \\[18pt]
|
||||
团队名称：\uline{\hfill 碳基生物\hfill}
|
||||
\end{flushleft}
|
||||
|
||||
28
doc/reports/defense/README.md
Normal file
28
doc/reports/defense/README.md
Normal file
@@ -0,0 +1,28 @@
|
||||
# 答辩材料
|
||||
|
||||
本目录包含十分钟系统设计答辩材料：
|
||||
|
||||
- `ppt_template.pptx`：大赛官方答辩模板，生成时作为母版使用。
|
||||
- `defense_presentation.pptx`：18页主讲内容、1页结束页和3页答疑备用内容。
|
||||
- `defense_presentation.pdf`：用于快速审阅排版的导出版本。
|
||||
- `defense_speech.md`：逐页演讲稿、时间分配和常见追问速答。
|
||||
- `build_defense_ppt.py`：可重复生成PPTX的脚本。
|
||||
|
||||
当前数据基线为系统设计报告 evidence `d456463`，日期为2026-07-15。Matmul最终评测完成5000组运算，用时4.911765 ms，CRC32 `0x0417d761`匹配，得分100.00%。PPT保留官方模板的母版、主题、背景素材和嵌入字体。
|
||||
|
||||
重新生成PPTX需要Python 3、`python-pptx`和Pillow：
|
||||
|
||||
```bash
|
||||
python3 -m pip install python-pptx Pillow
|
||||
python3 doc/reports/defense/build_defense_ppt.py
|
||||
```
|
||||
|
||||
可使用LibreOffice生成审阅PDF：
|
||||
|
||||
```bash
|
||||
libreoffice --headless --convert-to pdf \
|
||||
--outdir doc/reports/defense \
|
||||
doc/reports/defense/defense_presentation.pptx
|
||||
```
|
||||
|
||||
更新性能数据时，需要同时修改系统报告指标、PPT生成脚本和演讲稿，以保持证据口径一致。
|
||||
863
doc/reports/defense/build_defense_ppt.py
Normal file
863
doc/reports/defense/build_defense_ppt.py
Normal file
@@ -0,0 +1,863 @@
|
||||
#!/usr/bin/env python3
|
||||
"""Build the defense deck from the official CICIEC PPT template."""
|
||||
|
||||
from __future__ import annotations
|
||||
|
||||
import sys
|
||||
from io import BytesIO
|
||||
from pathlib import Path
|
||||
from zipfile import ZipFile
|
||||
|
||||
try:
|
||||
from pptx import Presentation
|
||||
except ModuleNotFoundError:
|
||||
sys.path.insert(0, "/tmp/codex_pptx")
|
||||
from pptx import Presentation
|
||||
|
||||
from PIL import Image
|
||||
from pptx.dml.color import RGBColor
|
||||
from pptx.enum.shapes import MSO_SHAPE
|
||||
from pptx.enum.text import MSO_ANCHOR, PP_ALIGN
|
||||
from pptx.util import Inches, Pt
|
||||
|
||||
|
||||
ROOT = Path(__file__).resolve().parents[3]
|
||||
HERE = Path(__file__).resolve().parent
|
||||
SYSTEM = ROOT / "doc/reports/system"
|
||||
MLKEM = ROOT / "doc/reports/mlkem_ip"
|
||||
TEMPLATE = HERE / "ppt_template.pptx"
|
||||
OUTPUT = HERE / "defense_presentation.pptx"
|
||||
|
||||
W = 13.333
|
||||
H = 7.5
|
||||
|
||||
# Template typefaces and palette.
|
||||
FONT = "HarmonyOS Sans SC"
|
||||
TITLE_FONT = "Alimama ShuHeiTi Bold"
|
||||
LATIN_FONT = "Arial"
|
||||
INK = "202533"
|
||||
MUTED = "667085"
|
||||
BLUE = "142DA8"
|
||||
ACCENT_BLUE = "4874CB"
|
||||
ORANGE = "EE822F"
|
||||
YELLOW = "F2BA02"
|
||||
GREEN = "75BD42"
|
||||
TEAL = "30C0B4"
|
||||
RED = "E54C5E"
|
||||
WHITE = "FFFFFF"
|
||||
PALE_BLUE = "EDF3FF"
|
||||
PALE_ORANGE = "FFF3E9"
|
||||
PALE_TEAL = "EAF9F7"
|
||||
PALE_GRAY = "F5F7FA"
|
||||
LINE = "D7DEEA"
|
||||
|
||||
|
||||
def color(value: str) -> RGBColor:
|
||||
return RGBColor.from_string(value)
|
||||
|
||||
|
||||
with ZipFile(TEMPLATE) as archive:
|
||||
MEDIA = {
|
||||
name.rsplit("/", 1)[-1]: archive.read(name)
|
||||
for name in archive.namelist()
|
||||
if name.startswith("ppt/media/") and not name.endswith("/")
|
||||
}
|
||||
|
||||
|
||||
prs = Presentation(str(TEMPLATE))
|
||||
while len(prs.slides):
|
||||
sld_id = prs.slides._sldIdLst[0]
|
||||
prs.part.drop_rel(sld_id.rId)
|
||||
del prs.slides._sldIdLst[0]
|
||||
blank = prs.slide_layouts[6]
|
||||
|
||||
|
||||
def add_template_image(slide, media_name, x, y, w, h):
|
||||
return slide.shapes.add_picture(
|
||||
BytesIO(MEDIA[media_name]), Inches(x), Inches(y), Inches(w), Inches(h)
|
||||
)
|
||||
|
||||
|
||||
def add_rect(slide, x, y, w, h, fill=WHITE, line=None, radius=False):
|
||||
shape_type = MSO_SHAPE.ROUNDED_RECTANGLE if radius else MSO_SHAPE.RECTANGLE
|
||||
shape = slide.shapes.add_shape(shape_type, Inches(x), Inches(y), Inches(w), Inches(h))
|
||||
shape.fill.solid()
|
||||
shape.fill.fore_color.rgb = color(fill)
|
||||
if line:
|
||||
shape.line.color.rgb = color(line)
|
||||
shape.line.width = Pt(1)
|
||||
else:
|
||||
shape.line.fill.background()
|
||||
if radius:
|
||||
try:
|
||||
shape.adjustments[0] = 0.06
|
||||
except Exception:
|
||||
pass
|
||||
return shape
|
||||
|
||||
|
||||
def add_text(
|
||||
slide,
|
||||
text,
|
||||
x,
|
||||
y,
|
||||
w,
|
||||
h,
|
||||
size=17,
|
||||
fill=INK,
|
||||
bold=False,
|
||||
font=FONT,
|
||||
align=PP_ALIGN.LEFT,
|
||||
valign=MSO_ANCHOR.TOP,
|
||||
margin=0.02,
|
||||
line_spacing=1.05,
|
||||
):
|
||||
shape = slide.shapes.add_textbox(Inches(x), Inches(y), Inches(w), Inches(h))
|
||||
frame = shape.text_frame
|
||||
frame.clear()
|
||||
frame.margin_left = frame.margin_right = Inches(margin)
|
||||
frame.margin_top = frame.margin_bottom = Inches(margin)
|
||||
frame.vertical_anchor = valign
|
||||
para = frame.paragraphs[0]
|
||||
para.text = text
|
||||
para.alignment = align
|
||||
para.space_after = Pt(0)
|
||||
para.line_spacing = line_spacing
|
||||
para.font.name = font
|
||||
para.font.size = Pt(size)
|
||||
para.font.bold = bold
|
||||
para.font.color.rgb = color(fill)
|
||||
return shape
|
||||
|
||||
|
||||
def add_rich(slide, runs, x, y, w, h, align=PP_ALIGN.LEFT):
|
||||
shape = slide.shapes.add_textbox(Inches(x), Inches(y), Inches(w), Inches(h))
|
||||
frame = shape.text_frame
|
||||
frame.clear()
|
||||
frame.margin_left = frame.margin_right = Inches(0.02)
|
||||
frame.margin_top = frame.margin_bottom = Inches(0.02)
|
||||
para = frame.paragraphs[0]
|
||||
para.alignment = align
|
||||
for text, size, bold, fill, font in runs:
|
||||
run = para.add_run()
|
||||
run.text = text
|
||||
run.font.name = font
|
||||
run.font.size = Pt(size)
|
||||
run.font.bold = bold
|
||||
run.font.color.rgb = color(fill)
|
||||
return shape
|
||||
|
||||
|
||||
def add_bullets(slide, items, x, y, w, h, size=15, fill=INK, gap=5, accent=BLUE):
|
||||
shape = slide.shapes.add_textbox(Inches(x), Inches(y), Inches(w), Inches(h))
|
||||
frame = shape.text_frame
|
||||
frame.clear()
|
||||
frame.margin_left = frame.margin_right = Inches(0.02)
|
||||
frame.margin_top = frame.margin_bottom = Inches(0.02)
|
||||
for index, item in enumerate(items):
|
||||
para = frame.paragraphs[0] if index == 0 else frame.add_paragraph()
|
||||
para.text = "• " + item
|
||||
para.font.name = FONT
|
||||
para.font.size = Pt(size)
|
||||
para.font.color.rgb = color(fill)
|
||||
para.space_after = Pt(gap)
|
||||
para.line_spacing = 1.06
|
||||
return shape
|
||||
|
||||
|
||||
def add_arrow(slide, x, y, w, h, fill=BLUE):
|
||||
shape = slide.shapes.add_shape(MSO_SHAPE.RIGHT_ARROW, Inches(x), Inches(y), Inches(w), Inches(h))
|
||||
shape.fill.solid()
|
||||
shape.fill.fore_color.rgb = color(fill)
|
||||
shape.line.fill.background()
|
||||
return shape
|
||||
|
||||
|
||||
def add_line(slide, x, y, w, h=0.02, fill=LINE):
|
||||
return add_rect(slide, x, y, w, h, fill)
|
||||
|
||||
|
||||
def add_image_contain(slide, path: Path, x, y, w, h, frame=True):
|
||||
if frame:
|
||||
add_rect(slide, x - 0.03, y - 0.03, w + 0.06, h + 0.06, WHITE, LINE)
|
||||
with Image.open(path) as image:
|
||||
iw, ih = image.size
|
||||
scale = min(w / iw, h / ih)
|
||||
pw, ph = iw * scale, ih * scale
|
||||
return slide.shapes.add_picture(
|
||||
str(path), Inches(x + (w - pw) / 2), Inches(y + (h - ph) / 2), Inches(pw), Inches(ph)
|
||||
)
|
||||
|
||||
|
||||
def set_cell(cell, text, size=12, bold=False, fill=INK, bg=None, align=PP_ALIGN.LEFT):
|
||||
if bg:
|
||||
cell.fill.solid()
|
||||
cell.fill.fore_color.rgb = color(bg)
|
||||
frame = cell.text_frame
|
||||
frame.clear()
|
||||
frame.margin_left = frame.margin_right = Inches(0.07)
|
||||
frame.margin_top = frame.margin_bottom = Inches(0.03)
|
||||
frame.vertical_anchor = MSO_ANCHOR.MIDDLE
|
||||
para = frame.paragraphs[0]
|
||||
para.text = text
|
||||
para.alignment = align
|
||||
para.font.name = LATIN_FONT if "seed" in text else FONT
|
||||
para.font.size = Pt(size)
|
||||
para.font.bold = bold
|
||||
para.font.color.rgb = color(fill)
|
||||
|
||||
|
||||
def add_table(slide, rows, x, y, w, h, widths=None, size=12):
|
||||
shape = slide.shapes.add_table(len(rows), len(rows[0]), Inches(x), Inches(y), Inches(w), Inches(h))
|
||||
table = shape.table
|
||||
if widths:
|
||||
for index, width in enumerate(widths):
|
||||
table.columns[index].width = Inches(width)
|
||||
for r, row in enumerate(rows):
|
||||
for c, value in enumerate(row):
|
||||
set_cell(
|
||||
table.cell(r, c),
|
||||
value,
|
||||
size=size,
|
||||
bold=r == 0,
|
||||
fill=WHITE if r == 0 else INK,
|
||||
bg=BLUE if r == 0 else (PALE_GRAY if r % 2 == 0 else WHITE),
|
||||
align=PP_ALIGN.CENTER if c else PP_ALIGN.LEFT,
|
||||
)
|
||||
return table
|
||||
|
||||
|
||||
def add_metric(slide, value, label, x, y, w, accent=BLUE, suffix=""):
|
||||
add_rich(
|
||||
slide,
|
||||
[(value, 24, True, accent, TITLE_FONT), (suffix, 13, False, accent, LATIN_FONT)],
|
||||
x,
|
||||
y,
|
||||
w,
|
||||
0.45,
|
||||
PP_ALIGN.CENTER,
|
||||
)
|
||||
add_text(slide, label, x, y + 0.48, w, 0.45, 11, MUTED, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
def add_number_badge(slide, number, x, y, fill=BLUE):
|
||||
add_rect(slide, x, y, 0.47, 0.47, fill, radius=True)
|
||||
add_text(slide, number, x, y + 0.08, 0.47, 0.22, 12, WHITE, True, font=LATIN_FONT, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
def new_content_slide(title, number, subtitle=None):
|
||||
slide = prs.slides.add_slide(blank)
|
||||
add_template_image(slide, "image1.png", 0, 0, W, H)
|
||||
add_template_image(slide, "image2.png", 0.28, -0.02, 1.82, 1.12)
|
||||
add_text(slide, title, 2.4, 0.48, 8.55, 0.55, 24, BLUE, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
add_rect(slide, 6.17, 1.17, 0.98, 0.07, ORANGE)
|
||||
if subtitle:
|
||||
add_text(slide, subtitle, 10.9, 0.53, 1.9, 0.28, 9.5, MUTED, align=PP_ALIGN.RIGHT)
|
||||
add_text(slide, str(number), 12.35, 6.98, 0.72, 0.3, 9, MUTED, font=LATIN_FONT, align=PP_ALIGN.LEFT)
|
||||
return slide
|
||||
|
||||
|
||||
def new_preview_slide(number, label):
|
||||
slide = prs.slides.add_slide(blank)
|
||||
add_template_image(slide, "image1.png", 0, 0, W, H)
|
||||
add_template_image(slide, "image2.png", 0.3, -0.02, 1.82, 1.12)
|
||||
add_text(slide, "作品重要亮点预览页", 3.2, 0.48, 6.95, 0.56, 25, BLUE, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
add_rect(slide, 6.17, 1.17, 0.98, 0.07, ORANGE)
|
||||
add_text(slide, label, 10.85, 0.53, 1.95, 0.28, 10, ORANGE, True, align=PP_ALIGN.RIGHT)
|
||||
add_text(slide, str(number), 12.35, 6.98, 0.72, 0.3, 9, MUTED, font=LATIN_FONT, align=PP_ALIGN.LEFT)
|
||||
return slide
|
||||
|
||||
|
||||
# 1. Cover
|
||||
slide = prs.slides.add_slide(blank)
|
||||
add_template_image(slide, "image3.png", 0, 0, W, H)
|
||||
add_template_image(slide, "image4.png", 5.93, 0.65, 1.48, 1.48)
|
||||
add_text(slide, "第十届全国大学生集成电路创新创业大赛", 1.15, 2.2, 11.05, 0.48, 24, BLUE, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
add_text(slide, "基于龙芯SoC的后量子密码与矩阵运算加速系统", 1.1, 2.82, 11.15, 0.78, 30, BLUE, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
add_rect(slide, 4.2, 3.9, 4.93, 0.62, BLUE, radius=True)
|
||||
add_text(slide, "龙芯中科杯 · 系统设计答辩", 4.33, 4.05, 4.67, 0.26, 16, WHITE, True, align=PP_ALIGN.CENTER)
|
||||
add_text(slide, "作品编号：CICC1008439 · 团队：碳基生物", 4.25, 5.25, 4.85, 0.34, 13, INK, True, align=PP_ALIGN.CENTER)
|
||||
add_text(slide, "证据版本 d456463 · 2026-07-15", 4.4, 5.72, 4.55, 0.3, 11, MUTED, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
# 2. Team introduction
|
||||
slide = new_content_slide("团队介绍：围绕完整系统形成协同分工", 2, "团队与项目")
|
||||
add_text(slide, "团队名称：碳基生物", 0.88, 1.48, 4.2, 0.36, 16, BLUE, True)
|
||||
roles = [
|
||||
(0.82, BLUE, PALE_BLUE, "系统架构与SoC集成", ["OpenLA500平台集成", "AXI、DMA与多时钟域", "SRAM控制器优化"]),
|
||||
(4.52, TEAL, PALE_TEAL, "密码算法与RTL实现", ["全参数ML-KEM架构", "Keccak、NTT与多项式算子", "常量时间解封装"]),
|
||||
(8.22, ORANGE, PALE_ORANGE, "软件验证、测试与文档", ["板级驱动与测试程序", "分层仿真和证据采集", "系统报告与答辩材料"]),
|
||||
]
|
||||
for x, accent, pale, title, items in roles:
|
||||
add_rect(slide, x, 2.08, 3.35, 3.72, pale, accent, radius=True)
|
||||
add_text(slide, title, x + 0.18, 2.38, 2.99, 0.36, 17, accent, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
add_bullets(slide, items, x + 0.32, 3.12, 2.72, 1.85, size=13, gap=10)
|
||||
add_rect(slide, 1.0, 6.18, 11.15, 0.55, PALE_GRAY, LINE)
|
||||
add_text(slide, "以统一接口、可重复测试和版本化证据贯通硬件、软件与文档。", 1.2, 6.34, 10.75, 0.24, 13, INK, True, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
# 3. Contents
|
||||
slide = prs.slides.add_slide(blank)
|
||||
add_template_image(slide, "image3.png", 0, 0, W, H)
|
||||
add_text(slide, "目录", 0.82, 0.48, 1.6, 0.55, 29, BLUE, True, TITLE_FONT)
|
||||
add_text(slide, "CONTENTS", 0.91, 1.15, 1.5, 0.22, 11, MUTED, font=LATIN_FONT)
|
||||
contents = [
|
||||
("1", "项目与系统方案", "开发过程、设计目标与系统数据流", BLUE),
|
||||
("2", "自主计算IP", "Matmul流水与全参数ML-KEM", ORANGE),
|
||||
("3", "验证与实现结果", "分层验证、资源时序与最终性能", TEAL),
|
||||
("4", "心得与后续工作", "工程认识、设计取舍与优化路线", GREEN),
|
||||
]
|
||||
for i, (num, title, sub, accent) in enumerate(contents):
|
||||
y = 1.75 + i * 1.2
|
||||
add_rect(slide, 2.25, y, 0.58, 0.58, accent)
|
||||
add_text(slide, num, 2.25, y + 0.13, 0.58, 0.24, 15, WHITE, True, align=PP_ALIGN.CENTER)
|
||||
add_text(slide, title, 3.18, y - 0.02, 4.35, 0.34, 17, INK, True)
|
||||
add_text(slide, sub, 3.18, y + 0.42, 5.1, 0.3, 12, MUTED)
|
||||
|
||||
|
||||
# 4. Preview: architecture and contributions
|
||||
slide = new_preview_slide(4, "系统方案")
|
||||
add_rect(slide, 0.78, 1.52, 7.75, 4.8, WHITE, LINE)
|
||||
add_image_contain(slide, SYSTEM / "system_arch.png", 0.94, 1.7, 7.43, 4.45, frame=False)
|
||||
add_text(slide, "OpenLA500 + DMA数据面 + 三个自主计算IP", 0.95, 6.4, 7.4, 0.3, 13, BLUE, True, align=PP_ALIGN.CENTER)
|
||||
highlights = [
|
||||
("01", "硬件自治", "五千组 Matmul 任务一次启动完成", BLUE),
|
||||
("02", "存储优化", "SRAM连续突发达到1 beat/cycle", ORANGE),
|
||||
("03", "全参数密码", "单比特流覆盖三等级、三操作", TEAL),
|
||||
("04", "异步协同", "三时钟域通过全五通道AXI FIFO连接", GREEN),
|
||||
]
|
||||
for i, (num, title, desc, accent) in enumerate(highlights):
|
||||
y = 1.62 + i * 1.18
|
||||
add_number_badge(slide, num, 8.85, y, accent)
|
||||
add_text(slide, title, 9.48, y - 0.02, 2.55, 0.3, 15, accent, True)
|
||||
add_text(slide, desc, 9.48, y + 0.37, 2.85, 0.48, 11.5, INK)
|
||||
add_rect(slide, 8.78, 6.25, 3.72, 0.58, PALE_BLUE, BLUE)
|
||||
add_text(slide, "全系统 0 DSP · 三时钟域零违例", 8.92, 6.42, 3.44, 0.24, 12, BLUE, True, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
# 5. Preview: measured results
|
||||
slide = new_preview_slide(5, "关键结果")
|
||||
metrics = [
|
||||
("4.911765", "Matmul 5000组最终时间", BLUE, " ms"),
|
||||
("827.80", "FFT DMA相对软件加速", ORANGE, "×"),
|
||||
("48.95–53.33", "ML-KEM DMA相对软件加速", TEAL, "×"),
|
||||
("0", "DSP48E1使用量", GREEN, " DSP"),
|
||||
]
|
||||
for i, (value, label, accent, suffix) in enumerate(metrics):
|
||||
x = 0.72 + i * 3.12
|
||||
add_rect(slide, x, 1.62, 2.77, 1.2, WHITE, accent, radius=True)
|
||||
add_metric(slide, value, label, x + 0.12, 1.77, 2.53, accent, suffix)
|
||||
add_table(
|
||||
slide,
|
||||
[
|
||||
["验证对象", "测试规模", "结果"],
|
||||
["ML-KEM主路径KAT", "3等级 × 3操作 × 1000", "9000 / 9000"],
|
||||
["Decaps隐式拒绝", "3等级 × 100", "300 / 300"],
|
||||
["ML-KEM板级诊断", "3等级 × 3路径 × 100", "900次零失败"],
|
||||
["Matmul最终评测", "5000组 · seed a3772ec8", "4.911765 ms · 满分"],
|
||||
["FFT板级验证", "CPU / DMA各3次", "误差Re=1、Im=2"],
|
||||
],
|
||||
0.92,
|
||||
3.18,
|
||||
7.2,
|
||||
3.05,
|
||||
widths=[2.25, 2.9, 2.05],
|
||||
size=11.5,
|
||||
)
|
||||
add_rect(slide, 8.5, 3.18, 3.88, 3.05, PALE_ORANGE, ORANGE, radius=True)
|
||||
add_text(slide, "实现质量", 8.82, 3.48, 3.2, 0.34, 18, ORANGE, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
add_metric(slide, "55,066", "Slice LUT · 41.16%", 8.85, 4.04, 1.45, BLUE)
|
||||
add_metric(slide, "29.5", "BRAM Tile · 8.08%", 10.48, 4.04, 1.45, TEAL)
|
||||
add_metric(slide, "88,843", "时序端点", 8.85, 5.2, 1.45, GREEN)
|
||||
add_metric(slide, "+0.070", "全系统最小WNS / ns", 10.48, 5.2, 1.45, ORANGE)
|
||||
|
||||
|
||||
# 6. Development process
|
||||
slide = new_content_slide("开发过程：以端到端证据驱动迭代", 6, "项目与系统方案")
|
||||
stages = [
|
||||
("1", "基础SoC跑通", "完成处理器取指、串口及总线外设联调", BLUE),
|
||||
("2", "计算IP接入", "实现Matmul、CRC32、FFT与全参数ML-KEM", TEAL),
|
||||
("3", "数据通路优化", "引入DMA端点、双Bank调度和SRAM连续突发", ORANGE),
|
||||
("4", "时钟与复位收敛", "完成PLL分域、AXI CDC和复位顺序验证", GREEN),
|
||||
("5", "分层验证闭环", "建立叶模块、IP、SoC与板级四层证据", BLUE),
|
||||
("6", "最终性能迭代", "压缩启动与稳态空闲，Matmul评测达到100分", ORANGE),
|
||||
]
|
||||
for i, (num, title, desc, accent) in enumerate(stages):
|
||||
col, row = i % 3, i // 3
|
||||
x, y = 0.78 + col * 4.12, 1.55 + row * 2.35
|
||||
add_rect(slide, x, y, 3.68, 1.75, WHITE, accent, radius=True)
|
||||
add_number_badge(slide, num, x + 0.2, y + 0.25, accent)
|
||||
add_text(slide, title, x + 0.88, y + 0.23, 2.55, 0.3, 15, accent, True)
|
||||
add_text(slide, desc, x + 0.25, y + 0.82, 3.18, 0.68, 11.2, INK, align=PP_ALIGN.CENTER)
|
||||
if i < 2 or 3 <= i < 5:
|
||||
add_arrow(slide, x + 3.75, y + 0.74, 0.25, 0.17, accent)
|
||||
add_rect(slide, 1.0, 6.35, 11.15, 0.44, PALE_TEAL, TEAL)
|
||||
add_text(slide, "每轮迭代同时检查功能正确性、总线可观测性、时序与板级端到端时间。", 1.22, 6.48, 10.7, 0.2, 12.5, INK, True, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
# 7. Contest requirements
|
||||
slide = new_content_slide("赛题要求与设计响应", 7, "项目与系统方案")
|
||||
add_text(slide, "赛题不是孤立IP设计，而是完整SoC中的端到端实现。", 0.82, 1.48, 8.3, 0.34, 13, MUTED)
|
||||
add_table(
|
||||
slide,
|
||||
[
|
||||
["赛题要求 / 工程约束", "本系统的设计响应"],
|
||||
["基于OpenLA500构建完整SoC", "双主八从AXI架构；CPU、系统、ML-KEM三个异步时钟域"],
|
||||
["5000组4×4矩阵乘法，禁止DSP", "全LUT乘加、双Bank序列器、在线CRC32与快速通道"],
|
||||
["实现FIPS 203 ML-KEM", "单比特流覆盖三等级、三操作；KAT与隐式拒绝验证"],
|
||||
["提高端到端性能", "四通道DMA、端点传输、SRAM连续突发与硬件自主调度"],
|
||||
],
|
||||
0.85,
|
||||
1.98,
|
||||
11.6,
|
||||
3.85,
|
||||
widths=[4.0, 7.6],
|
||||
size=13,
|
||||
)
|
||||
add_rect(slide, 0.9, 6.15, 11.5, 0.58, PALE_TEAL, TEAL)
|
||||
add_text(slide, "答辩主线：赛题约束 → 系统架构 → 数据流与自主IP → 分层验证 → 实测结果", 1.1, 6.32, 11.1, 0.24, 14, INK, True, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
# 8. Architecture and ownership
|
||||
slide = new_content_slide("总体架构与自主设计边界", 8, "项目与系统方案")
|
||||
add_image_contain(slide, SYSTEM / "system_arch.png", 0.7, 1.48, 8.0, 5.15)
|
||||
add_rect(slide, 9.02, 1.5, 3.45, 3.78, WHITE, TEAL, radius=True)
|
||||
add_text(slide, "自主实现", 9.25, 1.78, 3.0, 0.34, 18, TEAL, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
add_bullets(
|
||||
slide,
|
||||
[
|
||||
"四通道DMA与加速器端点",
|
||||
"Matmul、批量序列器、CRC32",
|
||||
"1024点Radix-2² SDF FFT",
|
||||
"全参数ML-KEM硬件IP",
|
||||
"两级AXI跨时钟域桥",
|
||||
"SRAM控制器突发流水化",
|
||||
],
|
||||
9.28,
|
||||
2.35,
|
||||
2.95,
|
||||
2.55,
|
||||
size=13.2,
|
||||
gap=5,
|
||||
)
|
||||
add_rect(slide, 9.02, 5.5, 3.45, 1.1, PALE_GRAY, LINE, radius=True)
|
||||
add_text(slide, "赛事基础平台", 9.25, 5.72, 2.95, 0.28, 14, MUTED, True, align=PP_ALIGN.CENTER)
|
||||
add_text(slide, "OpenLA500、板级SRAM器件、UART及基础外设", 9.25, 6.08, 2.95, 0.36, 11, INK, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
# 9. Data movement, clocks and SRAM
|
||||
slide = new_content_slide("数据搬运、SRAM与三时钟域协同", 9, "项目与系统方案")
|
||||
clock_info = [
|
||||
(0.8, BLUE, "CPU域 · 33.333 MHz", "OpenLA500 / Cache / AXI主端"),
|
||||
(5.0, TEAL, "系统域 · 50 MHz", "Crossbar / DMA / SRAM / Matmul / FFT"),
|
||||
(9.2, ORANGE, "ML-KEM域 · 76.923 MHz", "AXI前端 / Keccak / NTT / FSM"),
|
||||
]
|
||||
for x, accent, title, desc in clock_info:
|
||||
add_rect(slide, x, 1.5, 3.3, 0.85, WHITE, accent, radius=True)
|
||||
add_text(slide, title, x + 0.1, 1.68, 3.1, 0.28, 13.5, accent, True, align=PP_ALIGN.CENTER)
|
||||
add_text(slide, desc, x + 0.1, 2.02, 3.1, 0.2, 9.5, MUTED, align=PP_ALIGN.CENTER)
|
||||
add_arrow(slide, 4.26, 1.78, 0.5, 0.25, BLUE)
|
||||
add_arrow(slide, 8.46, 1.78, 0.5, 0.25, TEAL)
|
||||
add_text(slide, "AXI双时钟FIFO", 3.84, 2.34, 1.35, 0.2, 9, MUTED, align=PP_ALIGN.CENTER)
|
||||
add_text(slide, "AXI双时钟FIFO", 8.04, 2.34, 1.35, 0.2, 9, MUTED, align=PP_ALIGN.CENTER)
|
||||
|
||||
add_rect(slide, 0.82, 2.85, 5.7, 3.45, WHITE, BLUE, radius=True)
|
||||
add_text(slide, "硬件数据通路", 1.05, 3.08, 5.2, 0.3, 17, BLUE, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
flow = [("CPU配置", BLUE), ("DMA", TEAL), ("ExtRAM", YELLOW), ("加速器", ORANGE)]
|
||||
x = 1.05
|
||||
for index, (name, accent) in enumerate(flow):
|
||||
add_rect(slide, x, 3.72, 1.03, 0.58, PALE_GRAY, accent)
|
||||
add_text(slide, name, x, 3.88, 1.03, 0.22, 11, accent, True, align=PP_ALIGN.CENTER)
|
||||
if index < 3:
|
||||
add_arrow(slide, x + 1.08, 3.9, 0.35, 0.18, accent)
|
||||
x += 1.43
|
||||
add_text(slide, "CPU只配置任务，DMA、SRAM与加速器完成批量搬运和计算。", 1.02, 4.65, 5.25, 0.5, 12, INK, align=PP_ALIGN.CENTER)
|
||||
add_text(slide, "复位顺序：sys → mlkem → cpu；释放前AXI valid保持为0。", 1.02, 5.42, 5.25, 0.38, 11, MUTED, align=PP_ALIGN.CENTER)
|
||||
|
||||
add_rect(slide, 6.82, 2.85, 5.65, 3.45, WHITE, ORANGE, radius=True)
|
||||
add_text(slide, "SRAM连续突发优化", 7.05, 3.08, 5.2, 0.3, 17, ORANGE, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
add_text(slide, "优化前", 7.12, 3.63, 0.75, 0.24, 10.5, MUTED, True)
|
||||
for i in range(4):
|
||||
accent = BLUE if i % 2 == 0 else "E3E7EF"
|
||||
add_rect(slide, 8.08 + i * 0.72, 3.58, 0.42, 0.36, accent)
|
||||
add_text(slide, "优化后", 7.12, 4.18, 0.75, 0.24, 10.5, ORANGE, True)
|
||||
for i in range(4):
|
||||
add_rect(slide, 8.08 + i * 0.48, 4.13, 0.42, 0.36, TEAL)
|
||||
add_metric(slide, "200", "理论单向带宽", 7.15, 4.82, 2.0, ORANGE, " MB/s")
|
||||
add_metric(slide, "1", "无反压连续读写", 9.52, 4.82, 2.0, TEAL, " beat/cycle")
|
||||
add_text(slide, "读数据寄存保持R通道稳定；Bank选择随事务锁存。", 7.12, 5.9, 5.0, 0.32, 11, INK, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
# 10. Matmul
|
||||
slide = new_content_slide("Matmul：一次启动完成5000组流水任务", 10, "自主计算IP")
|
||||
add_image_contain(slide, SYSTEM / "matmul_dataflow_gantt.png", 0.65, 1.5, 9.55, 5.3)
|
||||
add_rect(slide, 10.45, 1.5, 2.02, 5.3, WHITE, BLUE, radius=True)
|
||||
add_text(slide, "关键节拍", 10.65, 1.78, 1.62, 0.3, 17, BLUE, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
for y, value, label, accent in [
|
||||
(2.26, "128 B", "每组A/B读取", BLUE),
|
||||
(3.18, "≈22 cyc", "单Bank乘加延迟", GREEN),
|
||||
(4.10, "2×6 B", "每元素CRC更新", ORANGE),
|
||||
(5.02, "0 B", "快速模式结果写回", TEAL),
|
||||
]:
|
||||
add_text(slide, value, 10.66, y, 1.62, 0.3, 18, accent, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
add_text(slide, label, 10.66, y + 0.34, 1.62, 0.26, 10, MUTED, align=PP_ALIGN.CENTER)
|
||||
add_text(slide, "最后一组退休后仍等待CRC FIFO排空，再产生DONE。", 10.7, 6.03, 1.55, 0.5, 10.5, INK, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
# 11. ML-KEM architecture
|
||||
slide = new_content_slide("ML-KEM：单比特流覆盖三等级与三操作", 11, "自主计算IP")
|
||||
add_image_contain(slide, MLKEM / "mlkem_modules.png", 0.65, 1.48, 8.05, 4.8)
|
||||
add_rect(slide, 9.0, 1.5, 3.45, 3.95, WHITE, TEAL, radius=True)
|
||||
add_text(slide, "运行时配置", 9.25, 1.8, 2.95, 0.3, 18, TEAL, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
add_metric(slide, "3", "512 / 768 / 1024", 9.27, 2.28, 1.3, TEAL)
|
||||
add_metric(slide, "3", "KeyGen / Encaps / Decaps", 10.78, 2.28, 1.35, ORANGE)
|
||||
add_bullets(
|
||||
slide,
|
||||
[
|
||||
"参数在start时锁存",
|
||||
"存储按KMAX=4静态分配",
|
||||
"控制、算子、BRAM三级组织",
|
||||
"公钥/私钥/密文支持AXI突发窗口",
|
||||
"无需按安全等级重新综合",
|
||||
],
|
||||
9.28,
|
||||
3.38,
|
||||
2.95,
|
||||
1.72,
|
||||
size=11.8,
|
||||
gap=4,
|
||||
)
|
||||
add_rect(slide, 0.82, 6.36, 11.47, 0.46, PALE_TEAL, TEAL)
|
||||
add_text(slide, "KeyGen 生成 ek/dk", 1.45, 6.49, 2.45, 0.2, 12, BLUE, True, align=PP_ALIGN.CENTER)
|
||||
add_arrow(slide, 4.02, 6.5, 0.48, 0.17, BLUE)
|
||||
add_text(slide, "Encaps 生成 c/ss", 4.62, 6.49, 2.45, 0.2, 12, TEAL, True, align=PP_ALIGN.CENTER)
|
||||
add_arrow(slide, 7.18, 6.5, 0.48, 0.17, TEAL)
|
||||
add_text(slide, "Decaps 恢复或拒绝 ss", 7.78, 6.49, 3.05, 0.2, 12, ORANGE, True, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
# 12. ML-KEM key designs
|
||||
slide = new_content_slide("ML-KEM关键设计：复用、并行与常量时间", 12, "自主计算IP")
|
||||
panels = [
|
||||
(0.72, BLUE, PALE_BLUE, "共享Keccak"),
|
||||
(4.52, TEAL, PALE_TEAL, "双蝶形NTT"),
|
||||
(8.32, ORANGE, PALE_ORANGE, "Decaps复用"),
|
||||
]
|
||||
for x, accent, pale, title in panels:
|
||||
add_rect(slide, x, 1.55, 3.5, 4.95, pale, accent, radius=True)
|
||||
add_text(slide, title, x + 0.2, 1.84, 3.1, 0.34, 18, accent, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
|
||||
# Shared Keccak panel
|
||||
for i, name in enumerate(["G/H/J哈希", "SampleNTT", "CBD采样"]):
|
||||
add_rect(slide, 0.98, 2.55 + i * 0.62, 1.15, 0.38, WHITE, LINE)
|
||||
add_text(slide, name, 0.98, 2.66 + i * 0.62, 1.15, 0.16, 9.5, INK, align=PP_ALIGN.CENTER)
|
||||
add_arrow(slide, 2.22, 2.67 + i * 0.62, 0.36, 0.16, BLUE)
|
||||
add_rect(slide, 2.65, 2.83, 1.25, 1.0, WHITE, BLUE)
|
||||
add_text(slide, "单一\nKeccak-f[1600]", 2.72, 3.08, 1.12, 0.45, 11, BLUE, True, align=PP_ALIGN.CENTER)
|
||||
add_text(slide, "避免两份额外实例\n约节省10.6k LUT", 1.05, 4.85, 2.82, 0.6, 13, BLUE, True, align=PP_ALIGN.CENTER)
|
||||
|
||||
# NTT panel
|
||||
add_rect(slide, 4.92, 2.6, 1.1, 1.3, WHITE, TEAL)
|
||||
for i in range(4):
|
||||
add_rect(slide, 5.08, 2.75 + i * 0.24, 0.78, 0.14, TEAL if i % 2 == 0 else ACCENT_BLUE)
|
||||
add_arrow(slide, 6.15, 3.08, 0.4, 0.2, TEAL)
|
||||
add_rect(slide, 6.65, 2.6, 1.08, 1.3, WHITE, TEAL)
|
||||
add_text(slide, "BU0\nBU1", 6.72, 2.99, 0.94, 0.42, 14, TEAL, True, align=PP_ALIGN.CENTER)
|
||||
add_text(slide, "4路BRAM无冲突供数\n读-算-写三级调度", 4.95, 4.28, 2.75, 0.58, 12, INK, align=PP_ALIGN.CENTER)
|
||||
add_text(slide, "4 coeff/cycle · 0 DSP", 4.98, 5.14, 2.72, 0.32, 15, TEAL, True, align=PP_ALIGN.CENTER)
|
||||
|
||||
# Decaps panel
|
||||
for i, (name, accent) in enumerate([("D1–D5 解密恢复", BLUE), ("D6 复用Encaps", TEAL), ("D7 常量时间比较", ORANGE)]):
|
||||
add_rect(slide, 8.7, 2.5 + i * 0.82, 2.75, 0.5, WHITE, accent)
|
||||
add_text(slide, name, 8.82, 2.64 + i * 0.82, 2.51, 0.2, 11, accent, True, align=PP_ALIGN.CENTER)
|
||||
if i < 2:
|
||||
down = slide.shapes.add_shape(MSO_SHAPE.DOWN_ARROW, Inches(9.88), Inches(3.04 + i * 0.82), Inches(0.38), Inches(0.2))
|
||||
down.fill.solid(); down.fill.fore_color.rgb = color(accent); down.line.fill.background()
|
||||
add_text(slide, "Accept与Reject路径\n总周期数完全相等", 8.86, 5.25, 2.44, 0.52, 13, ORANGE, True, align=PP_ALIGN.CENTER)
|
||||
|
||||
add_text(slide, "设计取舍：以资源共享和运行时可配置性换取更低的面积与部署复杂度。", 1.0, 6.68, 11.3, 0.28, 13, INK, True, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
# 13. Verification
|
||||
slide = new_content_slide("四层验证：从算子正确到板级闭环", 13, "验证与实现结果")
|
||||
bands = [
|
||||
(1.55, 1.35, 8.25, "板级系统", "真实FPGA、CPU软件、DMA与串口日志", ORANGE),
|
||||
(2.55, 1.95, 7.05, "SoC集成", "AXI解码、CDC、复位释放、SRAM取指", TEAL),
|
||||
(3.55, 2.55, 5.85, "IP集成", "Matmul / FFT / DMA / ML-KEM端到端", BLUE),
|
||||
(4.55, 3.15, 4.65, "叶模块", "Keccak、NTT、蝶形、FIFO、CRC32", GREEN),
|
||||
]
|
||||
for y, x, width, title, desc, accent in bands:
|
||||
add_rect(slide, x, y, width, 0.7, WHITE, accent, radius=True)
|
||||
add_text(slide, title, x + 0.18, y + 0.17, 1.2, 0.24, 13, accent, True)
|
||||
add_text(slide, desc, x + 1.45, y + 0.16, width - 1.65, 0.26, 11.5, INK, align=PP_ALIGN.CENTER)
|
||||
add_rect(slide, 9.88, 1.55, 2.5, 4.75, PALE_ORANGE, ORANGE, radius=True)
|
||||
add_text(slide, "验证结果", 10.15, 1.82, 1.96, 0.3, 17, ORANGE, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
for i, (value, label, accent) in enumerate([
|
||||
("9000", "主路径KAT", BLUE),
|
||||
("300", "隐式拒绝向量", ORANGE),
|
||||
("900", "ML-KEM板级运行", TEAL),
|
||||
("100%", "Matmul最终得分", GREEN),
|
||||
("6", "FFT板级测试", YELLOW),
|
||||
]):
|
||||
y = 2.28 + i * 0.76
|
||||
add_text(slide, value, 10.05, y, 0.95, 0.28, 16, accent, True, TITLE_FONT, PP_ALIGN.RIGHT)
|
||||
add_text(slide, label, 11.12, y + 0.03, 1.05, 0.26, 10, INK)
|
||||
add_rect(slide, 1.0, 5.75, 8.55, 0.58, PALE_TEAL, TEAL)
|
||||
add_text(slide, "算法逐字节比对；板级以零失败、CRC匹配和误差阈值为判据。", 1.18, 5.92, 8.2, 0.24, 12.5, INK, True, align=PP_ALIGN.CENTER)
|
||||
add_text(slide, "全部通过", 9.98, 6.48, 2.25, 0.36, 20, GREEN, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
# 14. Resources and timing
|
||||
slide = new_content_slide("实现结果：资源可控，三个时钟域全部收敛", 14, "验证与实现结果")
|
||||
add_rect(slide, 0.78, 1.5, 5.72, 4.85, WHITE, BLUE, radius=True)
|
||||
add_text(slide, "FPGA资源利用", 1.05, 1.78, 5.18, 0.3, 17, BLUE, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
resource_data = [
|
||||
("Slice LUT", 41.16, "55,066", BLUE),
|
||||
("Registers", 11.58, "31,000", TEAL),
|
||||
("BRAM Tile", 8.08, "29.5", YELLOW),
|
||||
("DSP48E1", 0.0, "0", ORANGE),
|
||||
]
|
||||
for i, (label, percent, absolute, accent) in enumerate(resource_data):
|
||||
y = 2.45 + i * 0.75
|
||||
add_text(slide, label, 1.02, y, 1.1, 0.24, 11, INK)
|
||||
add_rect(slide, 2.2, y + 0.02, 2.55, 0.22, "E5E9F1")
|
||||
if percent:
|
||||
add_rect(slide, 2.2, y + 0.02, 2.55 * percent / 50, 0.22, accent)
|
||||
add_text(slide, f"{percent:.2f}%", 4.85, y - 0.02, 0.68, 0.26, 10.5, accent, True, align=PP_ALIGN.RIGHT)
|
||||
add_text(slide, absolute, 5.6, y - 0.02, 0.55, 0.26, 10, MUTED, align=PP_ALIGN.RIGHT)
|
||||
add_text(slide, "xc7a200tfbg676-1 · 布局布线100%完成", 1.1, 5.72, 5.08, 0.28, 11.5, MUTED, align=PP_ALIGN.CENTER)
|
||||
|
||||
add_rect(slide, 6.82, 1.5, 5.62, 4.85, WHITE, TEAL, radius=True)
|
||||
add_text(slide, "布局布线后时序", 7.08, 1.78, 5.1, 0.3, 17, TEAL, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
add_table(
|
||||
slide,
|
||||
[
|
||||
["时钟域", "频率", "Setup WNS", "端点"],
|
||||
["cpu_clk", "33.333 MHz", "+0.737 ns", "17,197"],
|
||||
["sys_clk", "50.000 MHz", "+0.125 ns", "22,307"],
|
||||
["mlkem_clk", "76.923 MHz", "+0.070 ns", "31,646"],
|
||||
],
|
||||
7.08,
|
||||
2.35,
|
||||
5.1,
|
||||
2.35,
|
||||
widths=[1.15, 1.35, 1.35, 1.25],
|
||||
size=10.5,
|
||||
)
|
||||
add_metric(slide, "88,843", "时序端点", 7.15, 5.0, 1.45, TEAL)
|
||||
add_metric(slide, "0", "建立/保持违例", 8.95, 5.0, 1.45, GREEN)
|
||||
add_metric(slide, "+0.070", "全系统最小WNS / ns", 10.72, 5.0, 1.45, ORANGE)
|
||||
add_rect(slide, 1.0, 6.58, 11.2, 0.35, PALE_BLUE, BLUE)
|
||||
add_text(slide, "ML-KEM独立高速时钟域隔离了系统总线布线压力。", 1.2, 6.66, 10.8, 0.18, 11.5, BLUE, True, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
# 15. Performance
|
||||
slide = new_content_slide("最终性能：Matmul满分与端到端加速", 15, "验证与实现结果")
|
||||
for i, (value, label, accent, suffix) in enumerate([
|
||||
("4.911765", "Matmul 5000组最终时间", BLUE, " ms"),
|
||||
("827.80", "FFT DMA相对软件加速", ORANGE, "×"),
|
||||
("48.95–53.33", "ML-KEM DMA相对软件加速", TEAL, "×"),
|
||||
]):
|
||||
x = 0.85 + i * 4.05
|
||||
add_rect(slide, x, 1.5, 3.55, 1.05, WHITE, accent, radius=True)
|
||||
add_metric(slide, value, label, x + 0.15, 1.66, 3.25, accent, suffix)
|
||||
|
||||
add_rect(slide, 0.78, 2.92, 7.2, 3.55, WHITE, ORANGE, radius=True)
|
||||
add_text(slide, "ML-KEM三路径完整往返加速比", 1.02, 3.17, 6.72, 0.3, 16, ORANGE, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
levels = ["512", "768", "1024"]
|
||||
cpu = [13.04, 13.84, 15.05]
|
||||
dma = [48.95, 50.41, 53.33]
|
||||
for i, level in enumerate(levels):
|
||||
y = 3.74 + i * 0.72
|
||||
add_text(slide, f"ML-KEM-{level}", 1.0, y + 0.16, 1.15, 0.22, 10.5, INK)
|
||||
add_rect(slide, 2.25, y, cpu[i] / 60 * 4.65, 0.23, BLUE)
|
||||
add_rect(slide, 2.25, y + 0.31, dma[i] / 60 * 4.65, 0.23, ORANGE)
|
||||
add_text(slide, f"{cpu[i]:.2f}×", 2.33 + cpu[i] / 60 * 4.65, y - 0.02, 0.62, 0.2, 8.5, BLUE, True)
|
||||
add_text(slide, f"{dma[i]:.2f}×", 2.33 + dma[i] / 60 * 4.65, y + 0.29, 0.62, 0.2, 8.5, ORANGE, True)
|
||||
add_rect(slide, 2.15, 6.04, 0.15, 0.15, BLUE)
|
||||
add_text(slide, "CPU寄存器路径", 2.4, 6.02, 1.25, 0.2, 9, MUTED)
|
||||
add_rect(slide, 3.9, 6.04, 0.15, 0.15, ORANGE)
|
||||
add_text(slide, "DMA窗口路径", 4.15, 6.02, 1.25, 0.2, 9, MUTED)
|
||||
|
||||
add_rect(slide, 8.28, 2.92, 4.15, 3.55, PALE_TEAL, TEAL, radius=True)
|
||||
add_text(slide, "结果解释", 8.55, 3.18, 3.6, 0.3, 16, TEAL, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
add_bullets(
|
||||
slide,
|
||||
[
|
||||
"Matmul CRC32 0x0417d761匹配",
|
||||
"FFT DMA延迟296.73 μs，误差Re=1、Im=2",
|
||||
"ML-KEM-512 DMA往返约1.605 ms",
|
||||
"SRAM连续突发理论带宽200 MB/s",
|
||||
],
|
||||
8.55,
|
||||
3.78,
|
||||
3.55,
|
||||
1.85,
|
||||
size=12,
|
||||
gap=6,
|
||||
)
|
||||
add_text(slide, "随机种子0xa3772ec8 · 最终得分100.00%", 8.55, 5.92, 3.55, 0.34, 10.5, ORANGE, True, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
# 16. Lessons learned
|
||||
slide = new_content_slide("项目心得：从单点优化走向系统工程", 16, "心得与后续工作")
|
||||
lessons = [
|
||||
("端到端优先", "计算核延迟不是唯一指标；启动、搬运、调度和校验共同决定评测时间。", BLUE),
|
||||
("先正确再加速", "先建立CRC、状态寄存器和分层测试等可观测手段，再压缩流水空闲。", ORANGE),
|
||||
("取舍必须显式", "Keccak复用、双蝶形NTT和零DSP策略是在面积、吞吐与部署复杂度间的选择。", TEAL),
|
||||
("证据需要版本化", "报告、软件、RTL和实测日志必须共享同一数据基线，才能保证结论可复现。", GREEN),
|
||||
]
|
||||
for i, (title, desc, accent) in enumerate(lessons):
|
||||
col, row = i % 2, i // 2
|
||||
x, y = 0.82 + col * 6.0, 1.55 + row * 2.45
|
||||
add_rect(slide, x, y, 5.55, 1.85, WHITE, accent, radius=True)
|
||||
add_number_badge(slide, f"0{i+1}", x + 0.25, y + 0.28, accent)
|
||||
add_text(slide, title, x + 0.95, y + 0.27, 4.2, 0.32, 16, accent, True)
|
||||
add_text(slide, desc, x + 0.35, y + 0.9, 4.85, 0.58, 12, INK, align=PP_ALIGN.CENTER)
|
||||
add_rect(slide, 1.0, 6.38, 11.15, 0.42, PALE_ORANGE, ORANGE)
|
||||
add_text(slide, "最终满分来自软硬件协同，而不是单一模块参数的堆叠。", 1.2, 6.5, 10.75, 0.2, 13, INK, True, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
# 17. Future work
|
||||
slide = new_content_slide("后续工作：沿性能、验证与工程化继续演进", 17, "心得与后续工作")
|
||||
future = [
|
||||
(BLUE, "ML-KEM并行度", "增加Keccak并行路径，扩展NTT蝶形单元并评估面积收益比。"),
|
||||
(ORANGE, "存储专项验证", "补充SRAM随机反压、跨Bank边界与持续带宽微基准。"),
|
||||
(TEAL, "实现与功耗证据", "完善I/O约束，使用SAIF/VCD活动率回标提高功耗估计可信度。"),
|
||||
(GREEN, "版本与回归体系", "统一RTL、软件、测试向量和报告指标，形成自动化回归基线。"),
|
||||
]
|
||||
for i, (accent, title, desc) in enumerate(future):
|
||||
y = 1.48 + i * 1.22
|
||||
add_number_badge(slide, f"0{i+1}", 0.92, y, accent)
|
||||
add_text(slide, title, 1.65, y + 0.07, 2.15, 0.3, 15, accent, True)
|
||||
add_text(slide, desc, 3.92, y + 0.06, 7.85, 0.4, 13, INK)
|
||||
add_line(slide, 0.95, y + 0.76, 11.15, 0.012, LINE)
|
||||
add_rect(slide, 1.0, 6.45, 11.15, 0.35, PALE_TEAL, TEAL)
|
||||
add_text(slide, "目标：在不牺牲标准完整性和可验证性的前提下继续提高系统吞吐。", 1.2, 6.55, 10.75, 0.18, 12.5, INK, True, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
# 18. Summary
|
||||
slide = new_content_slide("总结：完成从算法IP到板级系统的闭环", 18, "总结与展望")
|
||||
summary = [
|
||||
("01", "系统", "构建CPU、DMA、存储与三个计算加速器协同的异构SoC", BLUE),
|
||||
("02", "数据流", "以SRAM连续突发、DMA端点和双Bank调度降低搬运开销", ORANGE),
|
||||
("03", "密码IP", "单比特流覆盖ML-KEM三等级、三操作和常量时间拒绝", TEAL),
|
||||
("04", "工程验证", "零DSP、三个时钟域收敛，并通过仿真与板级分层验证", GREEN),
|
||||
]
|
||||
for i, (num, tag, desc, accent) in enumerate(summary):
|
||||
y = 1.52 + i * 1.08
|
||||
add_number_badge(slide, num, 0.95, y, accent)
|
||||
add_text(slide, tag, 1.65, y + 0.08, 1.0, 0.28, 15, accent, True)
|
||||
add_text(slide, desc, 2.75, y + 0.08, 8.95, 0.36, 14, INK)
|
||||
add_line(slide, 0.95, y + 0.72, 11.2, 0.012, LINE)
|
||||
add_rect(slide, 0.92, 6.02, 11.3, 0.62, PALE_ORANGE, ORANGE)
|
||||
add_rich(
|
||||
slide,
|
||||
[
|
||||
("最终结果：", 12.5, True, INK, FONT),
|
||||
("5000", 12.5, True, INK, LATIN_FONT),
|
||||
("组 Matmul 用时4.911765 ms · CRC32匹配 · 得分100.00%", 12.5, True, INK, FONT),
|
||||
],
|
||||
1.12,
|
||||
6.2,
|
||||
10.9,
|
||||
0.3,
|
||||
PP_ALIGN.CENTER,
|
||||
)
|
||||
|
||||
|
||||
# 19. End
|
||||
slide = prs.slides.add_slide(blank)
|
||||
add_template_image(slide, "image3.png", 0, 0, W, H)
|
||||
add_template_image(slide, "image4.png", 5.92, 0.7, 1.48, 1.48)
|
||||
add_text(slide, "感谢聆听", 3.45, 2.55, 6.45, 0.75, 34, BLUE, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
add_rect(slide, 4.63, 3.65, 4.08, 0.72, BLUE, radius=True)
|
||||
add_text(slide, "Q&A", 4.75, 3.83, 3.84, 0.3, 22, WHITE, True, LATIN_FONT, PP_ALIGN.CENTER)
|
||||
add_text(slide, "中国集成电路未来之星从这里起步！", 3.2, 5.2, 6.95, 0.42, 17, INK, True, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
# 20. Backup: address space
|
||||
slide = new_content_slide("备用：地址空间与软件控制流程", 20, "答疑备用")
|
||||
add_table(
|
||||
slide,
|
||||
[
|
||||
["AXI从端", "基地址", "功能"],
|
||||
["S0", "0x1c00_0000", "BaseRAM / ExtRAM，共8 MB"],
|
||||
["S5", "0x1f30_0000", "DMA与矩阵批量序列器"],
|
||||
["S6", "0x1f40_0000", "FFT / ML-KEM共享窗口"],
|
||||
["S7", "0x1f50_0000", "Matmul控制与数据Bank"],
|
||||
],
|
||||
0.8,
|
||||
1.55,
|
||||
6.2,
|
||||
3.75,
|
||||
widths=[1.0, 2.0, 3.2],
|
||||
size=12,
|
||||
)
|
||||
add_rect(slide, 7.4, 1.55, 4.8, 3.75, WHITE, TEAL, radius=True)
|
||||
add_text(slide, "软件控制流程", 7.7, 1.83, 4.2, 0.3, 17, TEAL, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
for i, text in enumerate(["写配置寄存器", "配置DMA窗口", "启动硬件", "轮询done", "读取结果 / CRC"]):
|
||||
y = 2.35 + i * 0.56
|
||||
add_rect(slide, 8.05, y, 3.5, 0.38, PALE_GRAY, TEAL if i < 3 else BLUE)
|
||||
add_text(slide, text, 8.15, y + 0.1, 3.3, 0.17, 10.5, INK, True, align=PP_ALIGN.CENTER)
|
||||
add_rect(slide, 0.92, 5.75, 11.25, 0.62, PALE_TEAL, TEAL)
|
||||
add_text(slide, "快速路径中CPU不参与逐组Matmul调度；ML-KEM DMA路径只进行少量批量窗口配置。", 1.15, 5.93, 10.8, 0.26, 12.5, INK, True, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
# 21. Backup: KeyGen timing
|
||||
slide = new_content_slide("备用：ML-KEM-512 KeyGen逐状态周期分解", 21, "答疑备用")
|
||||
states = [
|
||||
("G哈希", 27, YELLOW),
|
||||
("SampleNTT矩阵A", 3213, ORANGE),
|
||||
("CBD采样", 1229, TEAL),
|
||||
("NTT", 4172, BLUE),
|
||||
("多项式基乘", 2096, GREEN),
|
||||
("密钥编码", 2081, RED),
|
||||
]
|
||||
for i, (name, cycles, accent) in enumerate(states):
|
||||
y = 1.52 + i * 0.72
|
||||
add_text(slide, name, 0.9, y + 0.1, 1.55, 0.22, 11, INK)
|
||||
add_rect(slide, 2.5, y + 0.1, 6.45, 0.25, "E5E9F1")
|
||||
add_rect(slide, 2.5, y + 0.1, 6.45 * cycles / 4500, 0.25, accent)
|
||||
add_text(slide, f"{cycles:,} cyc", 9.1, y + 0.06, 1.0, 0.25, 10, accent, True, align=PP_ALIGN.RIGHT)
|
||||
add_rect(slide, 10.45, 1.55, 2.0, 4.3, PALE_ORANGE, ORANGE, radius=True)
|
||||
add_text(slide, "主要瓶颈", 10.7, 1.88, 1.5, 0.3, 16, ORANGE, True, TITLE_FONT, PP_ALIGN.CENTER)
|
||||
add_text(slide, "NTT\n30.2%", 10.73, 2.5, 1.45, 0.65, 19, BLUE, True, align=PP_ALIGN.CENTER)
|
||||
add_text(slide, "SampleNTT\n23.3%", 10.68, 3.55, 1.55, 0.65, 16, ORANGE, True, align=PP_ALIGN.CENTER)
|
||||
add_text(slide, "两者合计\n53.5%", 10.72, 4.65, 1.48, 0.65, 15, INK, True, align=PP_ALIGN.CENTER)
|
||||
add_rect(slide, 0.92, 6.25, 11.25, 0.58, PALE_ORANGE, ORANGE)
|
||||
add_text(slide, "优化优先级：增加采样路径Keccak并行度，其次扩展NTT蝶形单元数量。", 1.12, 6.42, 10.85, 0.24, 12.5, INK, True, align=PP_ALIGN.CENTER)
|
||||
|
||||
|
||||
# 22. Backup: tradeoffs
|
||||
slide = new_content_slide("备用：设计取舍与优化路线", 22, "答疑备用")
|
||||
add_table(
|
||||
slide,
|
||||
[
|
||||
["维度", "当前选择", "优势", "代价"],
|
||||
["安全等级", "运行时k=2/3/4", "单比特流部署", "地址与控制逻辑增加"],
|
||||
["Keccak", "单核时分复用", "节省约10.6k LUT", "状态间无法重叠"],
|
||||
["NTT", "双蝶形、4 coeff/cycle", "BRAM无冲突、0 DSP", "吞吐低于多BU实现"],
|
||||
["控制", "30状态硬连线FSM", "行为清晰、易验证", "串行调度限制性能"],
|
||||
],
|
||||
0.72,
|
||||
1.48,
|
||||
11.85,
|
||||
3.62,
|
||||
widths=[1.4, 3.05, 3.35, 4.05],
|
||||
size=11.3,
|
||||
)
|
||||
add_text(slide, "优化路线", 0.92, 5.42, 1.45, 0.3, 17, ORANGE, True, TITLE_FONT)
|
||||
roadmap = [
|
||||
("1", "双Keccak或专用采样核", "预计KeyGen下降15%–20%", ORANGE),
|
||||
("2", "扩展多BU NTT", "提高至8 coeff/cycle", TEAL),
|
||||
("3", "完善约束与活动率回标", "提高时序与功耗结论置信度", BLUE),
|
||||
]
|
||||
for i, (num, title, desc, accent) in enumerate(roadmap):
|
||||
x = 0.95 + i * 4.05
|
||||
add_number_badge(slide, num, x, 5.88, accent)
|
||||
add_text(slide, title, x + 0.62, 5.86, 2.95, 0.28, 12, accent, True)
|
||||
add_text(slide, desc, x + 0.62, 6.23, 2.95, 0.4, 10.5, INK)
|
||||
|
||||
|
||||
prs.save(OUTPUT)
|
||||
print(f"Wrote {OUTPUT} from {TEMPLATE}")
|
||||
BIN
doc/reports/defense/defense_presentation.pdf
Normal file
BIN
doc/reports/defense/defense_presentation.pdf
Normal file
Binary file not shown.
BIN
doc/reports/defense/defense_presentation.pptx
Normal file
BIN
doc/reports/defense/defense_presentation.pptx
Normal file
Binary file not shown.
115
doc/reports/defense/defense_speech.md
Normal file
115
doc/reports/defense/defense_speech.md
Normal file
@@ -0,0 +1,115 @@
|
||||
# 系统设计答辩演讲稿
|
||||
|
||||
预计主讲时间：9分45秒。第1至18页为主讲内容，第19页结束，第20至22页仅用于答疑。
|
||||
|
||||
## 第1页：封面（0:00—0:15）
|
||||
|
||||
各位评委老师好。我们的作品是“基于龙芯SoC的后量子密码与矩阵运算加速系统”。系统以OpenLA500为控制核心，在Artix-7 FPGA上集成DMA、矩阵乘法、FFT和全参数ML-KEM硬件IP。
|
||||
|
||||
## 第2页：团队介绍（0:15—0:35）
|
||||
|
||||
团队围绕完整系统形成三类协同分工：系统架构与SoC集成负责AXI、DMA、多时钟域和SRAM；密码算法与RTL实现负责ML-KEM及其关键算子；软件验证、测试与文档负责板级程序、分层回归和证据整理。三部分通过统一接口和可重复测试共同迭代。
|
||||
|
||||
## 第3页：目录（0:35—0:45）
|
||||
|
||||
下面从项目与系统方案、自主计算IP、验证与实现结果，以及心得和后续工作四部分进行汇报。
|
||||
|
||||
## 第4页：作品亮点预览——系统方案（0:45—1:15）
|
||||
|
||||
系统的核心思路是让CPU负责配置与判断，让硬件负责数据搬运和计算。OpenLA500与DMA构成两个AXI主设备，Matmul、FFT和ML-KEM作为独立外设接入。一次启动可以完成5000组Matmul任务；SRAM连续突发在无反压时达到每周期一个数据拍；单一ML-KEM比特流覆盖三等级、三操作；三个异步时钟域由完整AXI双时钟FIFO连接。全系统DSP使用量为零。
|
||||
|
||||
## 第5页：作品亮点预览——关键结果（1:15—1:45）
|
||||
|
||||
先给出最终结果。5000组Matmul官方评测用时4.911765毫秒，CRC32期望值与上报值均为0x0417d761，得分100%。FFT的DMA模式相对软件加速827.80倍；ML-KEM的DMA路径相对软件加速48.95到53.33倍。ML-KEM通过9000个主路径KAT、300个隐式拒绝向量和900次板级运行。系统覆盖88843个时序端点且无时序违例。
|
||||
|
||||
## 第6页：开发过程总结（1:45—2:10）
|
||||
|
||||
开发过程分为六个阶段：先跑通基础SoC和串口，再接入各计算IP；随后以DMA端点、双Bank和SRAM连续突发优化数据通路；再完成PLL分域、AXI跨时钟域和复位验证；最后用叶模块、IP、SoC和板级四层证据持续回归。Matmul从阶段性正确结果迭代到最终满分，说明性能优化必须同时观察功能、总线状态、时序和端到端时间。
|
||||
|
||||
## 第7页：赛题要求与设计响应（2:10—2:40）
|
||||
|
||||
赛题要求的不是孤立计算核，而是能够运行和验证的完整SoC。针对5000组矩阵计算和零DSP约束，我们设计全LUT乘加核心、双Bank序列器和在线CRC32。针对FIPS 203，实现单比特流三等级、三操作的ML-KEM。针对端到端性能，扩展四通道DMA、加速器端点和SRAM连续突发，使CPU不再逐字搬运，也不参与逐组任务调度。
|
||||
|
||||
## 第8页：总体架构与自主设计边界（2:40—3:20）
|
||||
|
||||
系统采用双主八从AXI架构。CPU负责程序执行、参数配置和结果判断，DMA负责内存与加速器之间的批量传输，三个加速器具有独立地址空间。
|
||||
|
||||
这里明确自主设计边界。OpenLA500、板级SRAM器件、UART及基础外设来自赛事平台。我们完成四通道DMA扩展、Matmul与批量序列器、FFT、ML-KEM、两级AXI跨时钟域桥，以及基础SRAM控制器的突发流水化改造。工作重点是自主计算IP和贯穿SoC的数据通路。
|
||||
|
||||
## 第9页：数据搬运、SRAM与三时钟域（3:20—4:05）
|
||||
|
||||
CPU域为33.333兆赫；AXI互连、DMA、SRAM、Matmul和FFT位于50兆赫系统域；ML-KEM核心独立运行在76.923兆赫。CPU到系统、系统到ML-KEM的AXI五通道均通过双时钟FIFO跨域。复位按系统域、ML-KEM域、CPU域顺序释放，复位前AXI有效信号保持为零。
|
||||
|
||||
我们通过下一地址预驱动、读数据寄存和连续写握手，消除SRAM读数据拍之间的固定空闲周期，实现无反压时每周期一个32位数据拍。50兆赫下理论单向带宽为200 MB每秒。这个数值是接口节拍上限，不作为独立微基准实测值。
|
||||
|
||||
## 第10页：Matmul批量流水（4:05—4:50）
|
||||
|
||||
CPU只配置源地址、组数和跨步，序列器随后接管5000组任务。每组由CDMA读取128字节A、B矩阵并交替装入两个Bank；一个Bank计算时，另一个Bank可加载下一组。
|
||||
|
||||
计算核心使用四个32位无符号乘法器和加法树得到66位结果，稳定后每周期产生一个C元素。结果进入CRC FIFO，FIFO吸收乘加和递归CRC32之间的速率差。快速模式跳过192字节结果写回，但不会跳过计算和CRC。最后一组退休后仍等待CRC完全排空才产生DONE，因此最终CRC覆盖全部逻辑结果。
|
||||
|
||||
## 第11页：ML-KEM总体架构（4:50—5:30）
|
||||
|
||||
ML-KEM分为控制调度层、算子层和BRAM存储层。算子层包含Keccak、NTT、多项式乘法、采样和压缩解压缩。安全等级k和操作类型在start时锁存，存储按最大等级静态分配，循环边界和地址由k运行时推导。因此同一比特流支持ML-KEM-512、768、1024，以及KeyGen、Encaps和Decaps，无需重新综合。
|
||||
|
||||
## 第12页：ML-KEM关键设计（5:30—6:15）
|
||||
|
||||
第一，G、H、J哈希、SampleNTT和CBD处于互斥阶段，因此共享一个Keccak-f核，约节省10600个LUT。第二，NTT采用四路Banked BRAM和两个蝶形流水线，四个Bank无冲突提供两对系数，达到每周期四个系数且不使用DSP。第三，Decaps重加密直接复用Encaps状态序列，密文比较逐字节执行且不提前退出，Accept和Reject路径总周期完全相等。设计优先保证全参数支持、标准完整性和面积可控。
|
||||
|
||||
## 第13页：四层验证（6:15—6:55）
|
||||
|
||||
验证采用四层递进结构。叶模块层将Keccak、NTT、蝶形、FIFO和CRC32与参考模型比较；IP层验证完整控制流；SoC层验证AXI解码、跨时钟域、复位和SRAM取指；板级层由真实CPU软件形成闭环。
|
||||
|
||||
ML-KEM通过9000个主路径KAT和300个隐式拒绝向量，板级三等级、三路径共900次运行零失败。FFT在CPU和DMA模式下共运行六次。Matmul最终评测完成5000组随机输入，CRC32匹配并达到满分。
|
||||
|
||||
## 第14页：资源与时序（6:55—7:30）
|
||||
|
||||
系统在xc7a200tfbg676-1上完成布局布线。使用55066个LUT，占41.16%；31000个寄存器，占11.58%；29.5个BRAM Tile，占8.08%；DSP为零。CPU、系统和ML-KEM域的建立时间WNS分别为正0.737、正0.125和正0.070纳秒，没有建立或保持违例。独立ML-KEM时钟域隔离了系统总线的布线压力。
|
||||
|
||||
## 第15页：最终板级性能（7:30—8:20）
|
||||
|
||||
Matmul最终评测的随机种子为0xa3772ec8，5000组运行用时4.911765毫秒，平均每组约0.982微秒；在50兆赫系统时钟下约为49.12周期每组，CRC32完全匹配并获得100分。与阶段验证的6.944404毫秒中位值相比，最终时间降低约29.27%，收益来自启动、搬运、调度、计算和CRC全链路协同。
|
||||
|
||||
FFT DMA模式延迟296.73微秒，相对软件加速827.80倍，最大误差为实部1、虚部2。ML-KEM改用DMA窗口后，相对软件加速48.95到53.33倍，其中512等级完整往返约1.605毫秒。
|
||||
|
||||
## 第16页：项目心得体会（8:20—8:55）
|
||||
|
||||
本项目形成四点认识。第一，端到端性能比孤立计算核延迟更重要。第二，必须先建立CRC、状态寄存器和分层测试等可观测手段，再进行激进优化。第三，资源共享和并行度是明确的工程取舍。第四，报告、软件、RTL和实测日志必须共享版本化数据基线。最终满分来自软硬件协同，而不是单一参数堆叠。
|
||||
|
||||
## 第17页：后续工作（8:55—9:20）
|
||||
|
||||
后续从四方面推进：增加Keccak并行路径并扩展NTT蝶形单元；补充SRAM随机反压、跨Bank边界和持续带宽专项测试；使用SAIF或VCD活动率回标提高功耗结论可信度；统一RTL、软件、测试向量和报告指标，形成自动化回归基线。优化仍以标准完整性和可验证性为前提。
|
||||
|
||||
## 第18页：总结（9:20—9:45）
|
||||
|
||||
本项目构建了CPU、DMA、共享存储器与三个加速器协同的异构SoC；以SRAM连续突发、DMA端点和双Bank调度优化数据流；实现单比特流三等级、三操作的ML-KEM；并以零DSP完成布局布线和分层验证。最终5000组Matmul用时4.911765毫秒，CRC32匹配，得分100%。我的汇报完毕，谢谢各位老师。
|
||||
|
||||
## 常见追问速答
|
||||
|
||||
### 为什么设计三个时钟域？
|
||||
|
||||
CPU、外部SRAM和ML-KEM算法核心的时序能力不同。分域使ML-KEM运行在76.923 MHz，同时保持SRAM和系统总线在50 MHz可靠工作；跨域由五通道AXI双时钟FIFO完成。
|
||||
|
||||
### 200 MB/s是否为实测带宽？
|
||||
|
||||
不是。它是50 MHz乘以32位得到的连续传输理论单向上限。板级业务间接验证了连续突发正确性，但当前报告没有独立SRAM微基准。
|
||||
|
||||
### 快速模式不写回结果，如何保证正确性？
|
||||
|
||||
矩阵核心仍计算全部66位结果，并按标准字节序进入CRC32。DONE只在最后一组退休且CRC FIFO完全排空后产生，因此官方CRC覆盖全部逻辑结果序列。
|
||||
|
||||
### Matmul为何能从6.94毫秒降至4.91毫秒？
|
||||
|
||||
优化不只发生在乘加核心，而是同时减少软件启动开销、批量调度空闲和SRAM突发间隙，并保持计算与CRC消费重叠。最终每组从约69.4个系统周期降到约49.12个周期。
|
||||
|
||||
### 为什么ML-KEM慢于部分论文？
|
||||
|
||||
本设计支持单比特流三等级、三种完整操作、SoC接口和零DSP。部分论文针对固定等级或单一操作综合，并使用更多蝶形单元或DSP。当前单Keccak和双蝶形NTT是主要性能限制。
|
||||
|
||||
### 如何保证复位前没有操作？
|
||||
|
||||
各时钟域采用异步置位、同步撤离，并按sys、mlkem、cpu顺序释放。复位期间AXI valid、加速器start和DMA请求保持为零，系统仿真检查了首次取指前的事务状态。
|
||||
|
||||
### 为什么全系统不用DSP？
|
||||
|
||||
Matmul零DSP是赛题约束。为了统一资源策略，FFT和ML-KEM乘法也映射到LUT和进位链。这增加LUT消耗，但保证全系统DSP使用量为零。
|
||||
BIN
doc/reports/defense/ppt_template.pdf
Normal file
BIN
doc/reports/defense/ppt_template.pdf
Normal file
Binary file not shown.
BIN
doc/reports/defense/ppt_template.pptx
Normal file
BIN
doc/reports/defense/ppt_template.pptx
Normal file
Binary file not shown.
Binary file not shown.
@@ -81,7 +81,6 @@
|
||||
|
||||
\end{titlepage}
|
||||
|
||||
\maketitle
|
||||
\tableofcontents
|
||||
\newpage
|
||||
|
||||
|
||||
24
doc/reports/system/evidence/README.md
Normal file
24
doc/reports/system/evidence/README.md
Normal file
@@ -0,0 +1,24 @@
|
||||
# Report evidence
|
||||
|
||||
Generated logs and Vivado reports used by `system_design_report.tex` live here:
|
||||
|
||||
- `soc/`: short SoC simulation evidence; `reset_window.vcd` records reset and pre-reset transaction signals
|
||||
- `build/`: software build logs for the five selected examples
|
||||
- `vivado/`: timing, utilization, DRC, route and power reports
|
||||
- `board/`: official matmul evaluation plus FFT and ML-KEM board UART logs
|
||||
|
||||
The report currently consumes these board filenames:
|
||||
|
||||
- `fft_1.log`, `fft_2.log`, `fft_3.log`
|
||||
- `fft_dma_1.log`, `fft_dma_2.log`, `fft_dma_3.log`
|
||||
- `mlkem_test_512.log`, `mlkem_test_768.log`, `mlkem_test_1024.log`
|
||||
- `mlkem_hello.log`
|
||||
- `matmul_official.log` (three complete official runs in one file)
|
||||
|
||||
Reset screenshots derived from `soc/reset_window.vcd` belong in `../figures/` as
|
||||
`reset_release.png` and `reset_no_transaction.png`.
|
||||
|
||||
Run `../tools/run_report_tests.sh refresh` after replacing evidence. Large generated
|
||||
artifacts such as `.wdb`, `.jou`, `.str`, implementation checkpoints and bitstreams do
|
||||
not belong in Git. The short reset VCD may be retained as report evidence; avoid tracing
|
||||
the complete SoC for long software runs because the result can grow to several GB.
|
||||
390
doc/reports/system/evidence/vivado/cdc.rpt
Normal file
390
doc/reports/system/evidence/vivado/cdc.rpt
Normal file
@@ -0,0 +1,390 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||
| Date : Wed Jul 15 05:09:36 2026
|
||||
| Host : Roc_Wang running 64-bit major release (build 9200)
|
||||
| Command : report_cdc -details -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/cdc.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200t-fbg676
|
||||
| Speed File : -1 PRODUCTION 1.23 2018-06-13
|
||||
------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
CDC Report
|
||||
|
||||
ID Severity Count Description
|
||||
------ -------- ----- -------------------------------------------------------
|
||||
CDC-3 Info 1 1-bit synchronized with ASYNC_REG property
|
||||
CDC-6 Warning 20 Multi-bit synchronized with ASYNC_REG property
|
||||
CDC-7 Critical 1 Asynchronous reset unknown CDC circuitry
|
||||
CDC-9 Info 3 Asynchronous reset synchronized with ASYNC_REG property
|
||||
CDC-11 Critical 2 Fan-out from launch flop to destination clock
|
||||
CDC-15 Warning 313 Clock enable controlled CDC structure detected
|
||||
|
||||
Source Clock: sys_clk
|
||||
Destination Clock: cpu_clk
|
||||
CDC Type: User Ignored
|
||||
|
||||
Row ID Severity Description Depth Exception Source (From) Destination (To)
|
||||
--- ------ -------- ---------------------------------------------- ----- ------------------- ---------------------------------------------- ------------------------------------------------------------
|
||||
1 CDC-11 Critical Fan-out from launch flop to destination clock 2 Asynch Clock Groups pll_clk.u_rst_sys/delay_reg[1]/C pll_clk.u_rst_cpu/delay_reg[0]/CLR
|
||||
2 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2:0]/C u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D
|
||||
3 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2:0]/C u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D
|
||||
4 CDC-11 Critical Fan-out from launch flop to destination clock 2 Asynch Clock Groups pll_clk.u_rst_sys/delay_reg[1]/C u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR
|
||||
5 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2:0]/C u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D
|
||||
6 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D
|
||||
7 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D
|
||||
8 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D
|
||||
9 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D
|
||||
10 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D
|
||||
11 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D
|
||||
12 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D
|
||||
13 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D
|
||||
14 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D
|
||||
15 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D
|
||||
16 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D
|
||||
17 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D
|
||||
18 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D
|
||||
19 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D
|
||||
20 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D
|
||||
21 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D
|
||||
22 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D
|
||||
23 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D
|
||||
24 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D
|
||||
25 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D
|
||||
26 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D
|
||||
27 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D
|
||||
28 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D
|
||||
29 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D
|
||||
30 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D
|
||||
31 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D
|
||||
32 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D
|
||||
33 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D
|
||||
34 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D
|
||||
35 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D
|
||||
36 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D
|
||||
37 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D
|
||||
38 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D
|
||||
39 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D
|
||||
40 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3:0]/C u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3:0]/D
|
||||
41 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3:0]/C u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3:0]/D
|
||||
42 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_confreg/int_out_or_q2_reg/C u_cpu/u_csr/csr_estat_reg[2]/D
|
||||
43 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_cdma_matmul_bridge/seq_done_flag_reg/C u_cpu/u_csr/csr_estat_reg[3]/D
|
||||
44 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_matmul_axi_slave/done_reg/C u_cpu/u_csr/csr_estat_reg[4]/D
|
||||
45 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C u_cpu/u_csr/csr_estat_reg[5]/D
|
||||
|
||||
Source Clock: sys_clk
|
||||
Destination Clock: mlkem_clk
|
||||
CDC Type: User Ignored
|
||||
|
||||
Row ID Severity Description Depth Exception Source (From) Destination (To)
|
||||
--- ------ -------- ------------------------------------------------------- ----- ------------------- -------------------------------------------------------------------------- ----------------------------------------------------------------------------------------
|
||||
1 CDC-7 Critical Asynchronous reset unknown CDC circuitry 0 Asynch Clock Groups pll_clk.u_rst_sys/delay_reg[1]/C pll_clk.u_rst_mlkem/delay_reg[0]/CLR
|
||||
2 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D
|
||||
3 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D
|
||||
4 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D
|
||||
5 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D
|
||||
6 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/D
|
||||
7 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/D
|
||||
8 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D
|
||||
9 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D
|
||||
10 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/D
|
||||
11 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/D
|
||||
12 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/D
|
||||
13 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[11]/D
|
||||
14 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D
|
||||
15 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D
|
||||
16 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D
|
||||
17 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D
|
||||
18 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/D
|
||||
19 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/D
|
||||
20 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/D
|
||||
21 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D
|
||||
22 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D
|
||||
23 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/D
|
||||
24 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/D
|
||||
25 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D
|
||||
26 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/D
|
||||
27 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/D
|
||||
28 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D
|
||||
29 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/D
|
||||
30 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/D
|
||||
31 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D
|
||||
32 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D
|
||||
33 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D
|
||||
34 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/D
|
||||
35 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/D
|
||||
36 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/D
|
||||
37 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/D
|
||||
38 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/D
|
||||
39 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[5]/D
|
||||
40 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/D
|
||||
41 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D
|
||||
42 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/D
|
||||
43 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D
|
||||
44 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/D
|
||||
45 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D
|
||||
46 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[12]/D
|
||||
47 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D
|
||||
48 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/D
|
||||
49 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/D
|
||||
50 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/D
|
||||
51 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/D
|
||||
52 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D
|
||||
53 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/D
|
||||
54 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D
|
||||
55 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D
|
||||
56 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/D
|
||||
57 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 Asynch Clock Groups pll_clk.u_rst_sys/delay_reg[1]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR
|
||||
58 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D
|
||||
59 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D
|
||||
60 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3:0]/D
|
||||
61 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/D
|
||||
62 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D
|
||||
63 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/D
|
||||
64 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3]/D
|
||||
65 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/D
|
||||
66 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/D
|
||||
67 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D
|
||||
68 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D
|
||||
69 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8]/D
|
||||
70 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/D
|
||||
71 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[10]/D
|
||||
72 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/D
|
||||
73 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D
|
||||
74 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D
|
||||
75 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/D
|
||||
76 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/D
|
||||
77 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/D
|
||||
78 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17]/D
|
||||
79 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/D
|
||||
80 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D
|
||||
81 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D
|
||||
82 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D
|
||||
83 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D
|
||||
84 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D
|
||||
85 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D
|
||||
86 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D
|
||||
87 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/D
|
||||
88 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/D
|
||||
89 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/D
|
||||
90 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/D
|
||||
91 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D
|
||||
92 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D
|
||||
93 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[32]/D
|
||||
94 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/D
|
||||
95 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/D
|
||||
96 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/D
|
||||
97 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/D
|
||||
98 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3:0]/D
|
||||
|
||||
Source Clock: cpu_clk
|
||||
Destination Clock: sys_clk
|
||||
CDC Type: User Ignored
|
||||
|
||||
Row ID Severity Description Depth Exception Source (From) Destination (To)
|
||||
--- ------ -------- ------------------------------------------------------- ----- ------------------- ---------------------------------------------- ------------------------------------------------------------
|
||||
1 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D
|
||||
2 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[1]/D
|
||||
3 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/D
|
||||
4 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D
|
||||
5 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/D
|
||||
6 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/D
|
||||
7 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D
|
||||
8 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D
|
||||
9 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D
|
||||
10 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D
|
||||
11 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D
|
||||
12 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[11]/D
|
||||
13 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D
|
||||
14 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/D
|
||||
15 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[14]/D
|
||||
16 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/D
|
||||
17 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[16]/D
|
||||
18 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[17]/D
|
||||
19 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D
|
||||
20 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/D
|
||||
21 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[20]/D
|
||||
22 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/D
|
||||
23 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D
|
||||
24 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D
|
||||
25 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D
|
||||
26 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D
|
||||
27 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[26]/D
|
||||
28 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[27]/D
|
||||
29 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[28]/D
|
||||
30 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/D
|
||||
31 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/D
|
||||
32 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/D
|
||||
33 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/D
|
||||
34 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/D
|
||||
35 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[34]/D
|
||||
36 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/D
|
||||
37 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D
|
||||
38 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[38]/D
|
||||
39 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[39]/D
|
||||
40 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[40]/D
|
||||
41 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/D
|
||||
42 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D
|
||||
43 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[43]/D
|
||||
44 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D
|
||||
45 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/D
|
||||
46 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D
|
||||
47 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[47]/D
|
||||
48 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/D
|
||||
49 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D
|
||||
50 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[50]/D
|
||||
51 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[51]/D
|
||||
52 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[52]/D
|
||||
53 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[53]/D
|
||||
54 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2:0]/C u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D
|
||||
55 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/D
|
||||
56 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/D
|
||||
57 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/D
|
||||
58 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D
|
||||
59 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[4]/D
|
||||
60 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/D
|
||||
61 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D
|
||||
62 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D
|
||||
63 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D
|
||||
64 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[9]/D
|
||||
65 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[10]/D
|
||||
66 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[11]/D
|
||||
67 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/D
|
||||
68 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/D
|
||||
69 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[14]/D
|
||||
70 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[15]/D
|
||||
71 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[16]/D
|
||||
72 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[17]/D
|
||||
73 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D
|
||||
74 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D
|
||||
75 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[20]/D
|
||||
76 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/D
|
||||
77 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/D
|
||||
78 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[23]/D
|
||||
79 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/D
|
||||
80 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/D
|
||||
81 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[26]/D
|
||||
82 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[27]/D
|
||||
83 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[28]/D
|
||||
84 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[29]/D
|
||||
85 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/D
|
||||
86 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D
|
||||
87 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/D
|
||||
88 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D
|
||||
89 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[34]/D
|
||||
90 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/D
|
||||
91 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/D
|
||||
92 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[38]/D
|
||||
93 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/D
|
||||
94 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[40]/D
|
||||
95 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/D
|
||||
96 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D
|
||||
97 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/D
|
||||
98 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/D
|
||||
99 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D
|
||||
100 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[46]/D
|
||||
101 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/D
|
||||
102 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/D
|
||||
103 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/D
|
||||
104 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[50]/D
|
||||
105 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/D
|
||||
106 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[52]/D
|
||||
107 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/D
|
||||
108 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 Asynch Clock Groups pll_clk.u_rst_cpu/delay_reg[1]/C u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR
|
||||
109 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2:0]/C u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D
|
||||
110 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2:0]/C u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D
|
||||
111 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3:0]/C u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3:0]/D
|
||||
112 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D
|
||||
113 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D
|
||||
114 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/D
|
||||
115 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[3]/D
|
||||
116 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[4]/D
|
||||
117 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[5]/D
|
||||
118 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/D
|
||||
119 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D
|
||||
120 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/D
|
||||
121 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[9]/D
|
||||
122 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/D
|
||||
123 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[11]/D
|
||||
124 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D
|
||||
125 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D
|
||||
126 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/D
|
||||
127 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[15]/D
|
||||
128 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D
|
||||
129 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[17]/D
|
||||
130 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D
|
||||
131 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/D
|
||||
132 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[20]/D
|
||||
133 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[21]/D
|
||||
134 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/D
|
||||
135 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D
|
||||
136 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D
|
||||
137 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/D
|
||||
138 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[26]/D
|
||||
139 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/D
|
||||
140 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/D
|
||||
141 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/D
|
||||
142 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/D
|
||||
143 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D
|
||||
144 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[32]/D
|
||||
145 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[33]/D
|
||||
146 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/D
|
||||
147 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[35]/D
|
||||
148 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D
|
||||
149 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3:0]/C u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3:0]/D
|
||||
|
||||
Source Clock: mlkem_clk
|
||||
Destination Clock: sys_clk
|
||||
CDC Type: User Ignored
|
||||
|
||||
Row ID Severity Description Depth Exception Source (From) Destination (To)
|
||||
--- ------ -------- ------------------------------------------------------- ----- ------------------- ------------------------------------------------------------------------- ----------------------------------------------------------------------------------------
|
||||
1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D
|
||||
2 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D
|
||||
3 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D
|
||||
4 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D
|
||||
5 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 Asynch Clock Groups pll_clk.u_rst_mlkem/delay_reg[1]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR
|
||||
6 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D
|
||||
7 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D
|
||||
8 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D
|
||||
9 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D
|
||||
10 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D
|
||||
11 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D
|
||||
12 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D
|
||||
13 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D
|
||||
14 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D
|
||||
15 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D
|
||||
16 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D
|
||||
17 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D
|
||||
18 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D
|
||||
19 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D
|
||||
20 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D
|
||||
21 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D
|
||||
22 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D
|
||||
23 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D
|
||||
24 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D
|
||||
25 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D
|
||||
26 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D
|
||||
27 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D
|
||||
28 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D
|
||||
29 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D
|
||||
30 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D
|
||||
31 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D
|
||||
32 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D
|
||||
33 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D
|
||||
34 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D
|
||||
35 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D
|
||||
36 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D
|
||||
37 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D
|
||||
38 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D
|
||||
39 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D
|
||||
40 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D
|
||||
41 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D
|
||||
42 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D
|
||||
43 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D
|
||||
44 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D
|
||||
45 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D
|
||||
46 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D
|
||||
47 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3:0]/D
|
||||
48 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3:0]/D
|
||||
|
||||
28
doc/reports/system/evidence/vivado/clock_interaction.rpt
Normal file
28
doc/reports/system/evidence/vivado/clock_interaction.rpt
Normal file
@@ -0,0 +1,28 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||
| Date : Wed Jul 15 05:09:35 2026
|
||||
| Host : Roc_Wang running 64-bit major release (build 9200)
|
||||
| Command : report_clock_interaction -delay_type min_max -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/clock_interaction.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200t-fbg676
|
||||
| Speed File : -1 PRODUCTION 1.23 2018-06-13
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Clock Interaction Report
|
||||
|
||||
Clock Interaction Table
|
||||
-----------------------
|
||||
|
||||
WNS TNS Failing TNS Total WNS Path WHS THS Failing THS Total WHS Path Clock-Pair Inter-Clock
|
||||
From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Clock Edges WHS(ns) THS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints
|
||||
---------------- ---------------- ----------- ------- ------- ----------- ----------- --------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- -------------------
|
||||
cpu_clk cpu_clk rise - rise 0.74 0.00 0 17264 30.00 rise - rise 0.04 0.00 0 17264 0.00 Clean Timed
|
||||
cpu_clk sys_clk 0 162 0 162 Ignored Asynchronous Groups
|
||||
mlkem_clk mlkem_clk rise - rise 0.07 0.00 0 48386 13.00 rise - rise 0.06 0.00 0 48386 0.00 Clean Timed
|
||||
mlkem_clk sys_clk 0 61 0 61 Ignored Asynchronous Groups
|
||||
sys_clk cpu_clk 0 59 0 59 Ignored Asynchronous Groups
|
||||
sys_clk mlkem_clk 0 112 0 112 Ignored Asynchronous Groups
|
||||
sys_clk sys_clk rise - rise 0.12 0.00 0 23193 20.00 rise - rise 0.02 0.00 0 23193 0.00 Clean Timed
|
||||
|
||||
|
||||
@@ -1,87 +1,76 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
<<<<<<< Updated upstream
|
||||
| Date : Fri Jul 10 04:14:54 2026
|
||||
=======
|
||||
| Date : Sat Jul 11 09:20:56 2026
|
||||
>>>>>>> Stashed changes
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_clocks -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/clocks.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200t-fbg676
|
||||
| Speed File : -1 PRODUCTION 1.23 2018-06-13
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Clock Report
|
||||
|
||||
|
||||
Attributes
|
||||
P: Propagated
|
||||
G: Generated
|
||||
A: Auto-derived
|
||||
R: Renamed
|
||||
V: Virtual
|
||||
I: Inverted
|
||||
S: Pin phase-shifted with Latency mode
|
||||
|
||||
Clock Period(ns) Waveform(ns) Attributes Sources
|
||||
clk 20.000 {0.000 10.000} P {clk}
|
||||
clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
|
||||
<<<<<<< Updated upstream
|
||||
cpu_clk 30.323 {0.000 15.161} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
|
||||
=======
|
||||
cpu_clk 30.000 {0.000 15.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
|
||||
mlkem_clk 13.000 {0.000 6.500} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
|
||||
>>>>>>> Stashed changes
|
||||
sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
|
||||
|
||||
|
||||
====================================================
|
||||
Generated Clocks
|
||||
====================================================
|
||||
|
||||
Generated Clock : clkfbout_clk_pll
|
||||
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Master Clock : clk
|
||||
Multiply By : 1
|
||||
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
|
||||
|
||||
Generated Clock : cpu_clk
|
||||
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Master Clock : clk
|
||||
Edges : {1 2 3}
|
||||
Edge Shifts(ns) : {0.000 5.000 10.000}
|
||||
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
|
||||
|
||||
<<<<<<< Updated upstream
|
||||
=======
|
||||
Generated Clock : mlkem_clk
|
||||
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Master Clock : clk
|
||||
Edges : {1 2 3}
|
||||
Edge Shifts(ns) : {0.000 -3.500 -7.000}
|
||||
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
|
||||
|
||||
>>>>>>> Stashed changes
|
||||
Generated Clock : sys_clk
|
||||
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Master Clock : clk
|
||||
Multiply By : 1
|
||||
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
|
||||
|
||||
|
||||
|
||||
====================================================
|
||||
User Uncertainty
|
||||
====================================================
|
||||
|
||||
|
||||
|
||||
====================================================
|
||||
User Jitter
|
||||
====================================================
|
||||
|
||||
Clock Jitter(ns)
|
||||
clk 0.200
|
||||
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||
| Date : Wed Jul 15 05:09:25 2026
|
||||
| Host : Roc_Wang running 64-bit major release (build 9200)
|
||||
| Command : report_clocks -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/clocks.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200t-fbg676
|
||||
| Speed File : -1 PRODUCTION 1.23 2018-06-13
|
||||
---------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Clock Report
|
||||
|
||||
|
||||
Attributes
|
||||
P: Propagated
|
||||
G: Generated
|
||||
A: Auto-derived
|
||||
R: Renamed
|
||||
V: Virtual
|
||||
I: Inverted
|
||||
S: Pin phase-shifted with Latency mode
|
||||
|
||||
Clock Period(ns) Waveform(ns) Attributes Sources
|
||||
clk 20.000 {0.000 10.000} P {clk}
|
||||
clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
|
||||
cpu_clk 30.000 {0.000 15.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
|
||||
mlkem_clk 13.000 {0.000 6.500} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
|
||||
sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
|
||||
|
||||
|
||||
====================================================
|
||||
Generated Clocks
|
||||
====================================================
|
||||
|
||||
Generated Clock : clkfbout_clk_pll
|
||||
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Master Clock : clk
|
||||
Multiply By : 1
|
||||
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
|
||||
|
||||
Generated Clock : cpu_clk
|
||||
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Master Clock : clk
|
||||
Edges : {1 2 3}
|
||||
Edge Shifts(ns) : {0.000 5.000 10.000}
|
||||
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
|
||||
|
||||
Generated Clock : mlkem_clk
|
||||
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Master Clock : clk
|
||||
Edges : {1 2 3}
|
||||
Edge Shifts(ns) : {0.000 -3.500 -7.000}
|
||||
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
|
||||
|
||||
Generated Clock : sys_clk
|
||||
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Master Clock : clk
|
||||
Multiply By : 1
|
||||
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
|
||||
|
||||
|
||||
|
||||
====================================================
|
||||
User Uncertainty
|
||||
====================================================
|
||||
|
||||
|
||||
|
||||
====================================================
|
||||
User Jitter
|
||||
====================================================
|
||||
|
||||
Clock Jitter(ns)
|
||||
clk 0.200
|
||||
|
||||
@@ -1,18 +1,14 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
<<<<<<< Updated upstream
|
||||
| Date : Fri Jul 10 04:14:40 2026
|
||||
=======
|
||||
| Date : Sat Jul 11 09:20:47 2026
|
||||
>>>>>>> Stashed changes
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_drc -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/drc.rpt
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||
| Date : Wed Jul 15 05:09:39 2026
|
||||
| Host : Roc_Wang running 64-bit major release (build 9200)
|
||||
| Command : report_drc -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/drc.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200tfbg676-1
|
||||
| Speed File : -1
|
||||
| Design State : Fully Routed
|
||||
----------------------------------------------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report DRC
|
||||
|
||||
@@ -1,18 +1,14 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
<<<<<<< Updated upstream
|
||||
| Date : Fri Jul 10 04:14:46 2026
|
||||
=======
|
||||
| Date : Sat Jul 11 09:20:51 2026
|
||||
>>>>>>> Stashed changes
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_methodology -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/methodology.rpt
|
||||
-------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||
| Date : Wed Jul 15 05:09:49 2026
|
||||
| Host : Roc_Wang running 64-bit major release (build 9200)
|
||||
| Command : report_methodology -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/methodology.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200tfbg676-1
|
||||
| Speed File : -1
|
||||
| Design State : Fully Routed
|
||||
--------------------------------------------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report Methodology
|
||||
|
||||
@@ -27,24 +23,15 @@ Table of Contents
|
||||
Floorplan: impl_1
|
||||
Design limits: <entire design considered>
|
||||
Max violations: <unlimited>
|
||||
<<<<<<< Updated upstream
|
||||
Violations found: 107
|
||||
=======
|
||||
Violations found: 115
|
||||
>>>>>>> Stashed changes
|
||||
+-----------+----------+-------------------------------------------------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+-----------+----------+-------------------------------------------------------------------+------------+
|
||||
| LUTAR-1 | Warning | LUT drives async reset alert | 1 |
|
||||
| SYNTH-5 | Warning | Mapped onto distributed RAM because of timing constraints | 8 |
|
||||
<<<<<<< Updated upstream
|
||||
| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 9 |
|
||||
| SYNTH-16 | Warning | Address collision | 8 |
|
||||
=======
|
||||
| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 6 |
|
||||
| SYNTH-16 | Warning | Address collision | 16 |
|
||||
| TIMING-9 | Warning | Unknown CDC Logic | 1 |
|
||||
>>>>>>> Stashed changes
|
||||
| TIMING-10 | Warning | Missing property on synchronizer | 1 |
|
||||
| TIMING-18 | Warning | Missing input or output delay | 76 |
|
||||
| TIMING-47 | Warning | False path or asynchronous clock group between synchronous clocks | 4 |
|
||||
@@ -56,11 +43,7 @@ Table of Contents
|
||||
-----------------
|
||||
LUTAR-1#1 Warning
|
||||
LUT drives async reset alert
|
||||
<<<<<<< Updated upstream
|
||||
LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 24656 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
=======
|
||||
LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 15633 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
>>>>>>> Stashed changes
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-5#1 Warning
|
||||
@@ -105,71 +88,32 @@ Related violations: <none>
|
||||
|
||||
SYNTH-6#1 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
<<<<<<< Updated upstream
|
||||
The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
=======
|
||||
The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
>>>>>>> Stashed changes
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#2 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
<<<<<<< Updated upstream
|
||||
The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
=======
|
||||
The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
>>>>>>> Stashed changes
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#3 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
<<<<<<< Updated upstream
|
||||
The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
=======
|
||||
The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
>>>>>>> Stashed changes
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#4 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
<<<<<<< Updated upstream
|
||||
The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
=======
|
||||
The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
>>>>>>> Stashed changes
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#5 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
<<<<<<< Updated upstream
|
||||
The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
=======
|
||||
The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
>>>>>>> Stashed changes
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#6 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
<<<<<<< Updated upstream
|
||||
The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#7 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#8 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#9 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
=======
|
||||
The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
>>>>>>> Stashed changes
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-16#1 Warning
|
||||
@@ -665,15 +609,15 @@ Related violations: <none>
|
||||
XDCC-1#1 Warning
|
||||
Scoped Clock constraint overwritten with the same name
|
||||
A new clock constraint create_clock overrides a previous scoped clock constraint with the same name. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors.
|
||||
New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/constraints/soc.xdc (Line: 4))
|
||||
Previous: create_clock -period 20.000 [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56))
|
||||
New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: c:/Users/11747/Desktop/ciciec2026/fpga/constraints/soc.xdc (Line: 4))
|
||||
Previous: create_clock -period 20.000 [get_ports clk] (Source: c:/Users/11747/Desktop/ciciec2026/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56))
|
||||
Related violations: <none>
|
||||
|
||||
XDCC-7#1 Warning
|
||||
Scoped Clock constraint overwritten on the same source
|
||||
A new clock constraint create_clock overrides a previous scoped clock constraint defined on the same source. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors.
|
||||
New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/constraints/soc.xdc (Line: 4))
|
||||
Previous: create_clock -period 20.000 [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56))
|
||||
New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: c:/Users/11747/Desktop/ciciec2026/fpga/constraints/soc.xdc (Line: 4))
|
||||
Previous: create_clock -period 20.000 [get_ports clk] (Source: c:/Users/11747/Desktop/ciciec2026/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56))
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
@@ -1,261 +1,188 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
<<<<<<< Updated upstream
|
||||
| Date : Fri Jul 10 04:15:05 2026
|
||||
=======
|
||||
| Date : Sat Jul 11 09:21:02 2026
|
||||
>>>>>>> Stashed changes
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_power -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/power.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200tfbg676-1
|
||||
| Design State : routed
|
||||
| Grade : commercial
|
||||
| Process : typical
|
||||
| Characterization : Production
|
||||
--------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Power Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
1.1 On-Chip Components
|
||||
1.2 Power Supply Summary
|
||||
1.3 Confidence Level
|
||||
2. Settings
|
||||
2.1 Environment
|
||||
2.2 Clock Constraints
|
||||
3. Detailed Reports
|
||||
3.1 By Hierarchy
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+--------------------------+--------------+
|
||||
<<<<<<< Updated upstream
|
||||
| Total On-Chip Power (W) | 0.686 |
|
||||
| Design Power Budget (W) | Unspecified* |
|
||||
| Power Budget Margin (W) | NA |
|
||||
| Dynamic (W) | 0.545 |
|
||||
| Device Static (W) | 0.141 |
|
||||
| Effective TJA (C/W) | 1.9 |
|
||||
| Max Ambient (C) | 83.7 |
|
||||
| Junction Temperature (C) | 26.3 |
|
||||
=======
|
||||
| Total On-Chip Power (W) | 0.779 |
|
||||
| Design Power Budget (W) | Unspecified* |
|
||||
| Power Budget Margin (W) | NA |
|
||||
| Dynamic (W) | 0.637 |
|
||||
| Device Static (W) | 0.142 |
|
||||
| Effective TJA (C/W) | 1.9 |
|
||||
| Max Ambient (C) | 83.5 |
|
||||
| Junction Temperature (C) | 26.5 |
|
||||
>>>>>>> Stashed changes
|
||||
| Confidence Level | Low |
|
||||
| Setting File | --- |
|
||||
| Simulation Activity File | --- |
|
||||
| Design Nets Matched | NA |
|
||||
+--------------------------+--------------+
|
||||
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
|
||||
|
||||
|
||||
1.1 On-Chip Components
|
||||
----------------------
|
||||
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
| On-Chip | Power (W) | Used | Available | Utilization (%) |
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
<<<<<<< Updated upstream
|
||||
| Clocks | 0.056 | 6 | --- | --- |
|
||||
| Slice Logic | 0.109 | 133224 | --- | --- |
|
||||
| LUT as Logic | 0.102 | 75460 | 133800 | 56.40 |
|
||||
| CARRY4 | 0.003 | 3546 | 33450 | 10.60 |
|
||||
| LUT as Distributed RAM | 0.002 | 628 | 46200 | 1.36 |
|
||||
| Register | 0.001 | 39690 | 267600 | 14.83 |
|
||||
| LUT as Shift Register | <0.001 | 1175 | 46200 | 2.54 |
|
||||
| F7/F8 Muxes | <0.001 | 6085 | 133800 | 4.55 |
|
||||
| Others | 0.000 | 289 | --- | --- |
|
||||
| Signals | 0.194 | 93202 | --- | --- |
|
||||
| Block RAM | 0.019 | 25.5 | 365 | 6.99 |
|
||||
| PLL | 0.137 | 1 | 10 | 10.00 |
|
||||
| I/O | 0.029 | 202 | 400 | 50.50 |
|
||||
| Static Power | 0.141 | | | |
|
||||
| Total | 0.686 | | | |
|
||||
=======
|
||||
| Clocks | 0.060 | 7 | --- | --- |
|
||||
| Slice Logic | 0.137 | 103629 | --- | --- |
|
||||
| LUT as Logic | 0.128 | 53158 | 133800 | 39.73 |
|
||||
| CARRY4 | 0.005 | 3669 | 33450 | 10.97 |
|
||||
| Register | 0.002 | 31000 | 267600 | 11.58 |
|
||||
| LUT as Distributed RAM | 0.001 | 740 | 46200 | 1.60 |
|
||||
| LUT as Shift Register | <0.001 | 1168 | 46200 | 2.53 |
|
||||
| F7/F8 Muxes | <0.001 | 2449 | 133800 | 1.83 |
|
||||
| Others | 0.000 | 333 | --- | --- |
|
||||
| Signals | 0.284 | 78815 | --- | --- |
|
||||
| Block RAM | 0.027 | 29.5 | 365 | 8.08 |
|
||||
| PLL | 0.102 | 1 | 10 | 10.00 |
|
||||
| I/O | 0.027 | 202 | 400 | 50.50 |
|
||||
| Static Power | 0.142 | | | |
|
||||
| Total | 0.779 | | | |
|
||||
>>>>>>> Stashed changes
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
|
||||
|
||||
1.2 Power Supply Summary
|
||||
------------------------
|
||||
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
<<<<<<< Updated upstream
|
||||
| Vccint | 1.000 | 0.423 | 0.391 | 0.032 |
|
||||
| Vccaux | 1.800 | 0.101 | 0.070 | 0.031 |
|
||||
=======
|
||||
| Vccint | 1.000 | 0.545 | 0.512 | 0.033 |
|
||||
| Vccaux | 1.800 | 0.085 | 0.054 | 0.031 |
|
||||
>>>>>>> Stashed changes
|
||||
| Vcco33 | 3.300 | 0.013 | 0.008 | 0.005 |
|
||||
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccbram | 1.000 | 0.003 | 0.002 | 0.001 |
|
||||
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
|
||||
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
|
||||
|
||||
1.3 Confidence Level
|
||||
--------------------
|
||||
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| User Input Data | Confidence | Details | Action |
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| Design implementation state | High | Design is routed | |
|
||||
| Clock nodes activity | High | User specified more than 95% of clocks | |
|
||||
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
|
||||
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
|
||||
| Device models | High | Device models are Production | |
|
||||
| | | | |
|
||||
| Overall confidence level | Low | | |
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
2. Settings
|
||||
-----------
|
||||
|
||||
2.1 Environment
|
||||
---------------
|
||||
|
||||
+-----------------------+--------------------------+
|
||||
| Ambient Temp (C) | 25.0 |
|
||||
| ThetaJA (C/W) | 1.9 |
|
||||
| Airflow (LFM) | 250 |
|
||||
| Heat Sink | medium (Medium Profile) |
|
||||
| ThetaSA (C/W) | 3.4 |
|
||||
| Board Selection | medium (10"x10") |
|
||||
| # of Board Layers | 12to15 (12 to 15 Layers) |
|
||||
| Board Temperature (C) | 25.0 |
|
||||
+-----------------------+--------------------------+
|
||||
|
||||
|
||||
2.2 Clock Constraints
|
||||
---------------------
|
||||
|
||||
<<<<<<< Updated upstream
|
||||
+------------------+-----------------------------------------+-----------------+
|
||||
| Clock | Domain | Constraint (ns) |
|
||||
+------------------+-----------------------------------------+-----------------+
|
||||
| clk | clk | 20.0 |
|
||||
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
|
||||
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 |
|
||||
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
|
||||
+------------------+-----------------------------------------+-----------------+
|
||||
=======
|
||||
+------------------+------------------------------------------+-----------------+
|
||||
| Clock | Domain | Constraint (ns) |
|
||||
+------------------+------------------------------------------+-----------------+
|
||||
| clk | clk | 20.0 |
|
||||
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
|
||||
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.0 |
|
||||
| mlkem_clk | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 13.0 |
|
||||
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
|
||||
+------------------+------------------------------------------+-----------------+
|
||||
>>>>>>> Stashed changes
|
||||
|
||||
|
||||
3. Detailed Reports
|
||||
-------------------
|
||||
|
||||
3.1 By Hierarchy
|
||||
----------------
|
||||
|
||||
+----------------------------+-----------+
|
||||
| Name | Power (W) |
|
||||
+----------------------------+-----------+
|
||||
<<<<<<< Updated upstream
|
||||
| soc_top | 0.545 |
|
||||
| pll_clk.u_clk_pll | 0.138 |
|
||||
| inst | 0.138 |
|
||||
| u_Axi_CDC | 0.003 |
|
||||
| u_axi_uart_controller | 0.002 |
|
||||
| u_cpu | 0.025 |
|
||||
| addr_trans | 0.002 |
|
||||
| tlb_entry | 0.002 |
|
||||
| btb | 0.003 |
|
||||
| dcache | 0.006 |
|
||||
| icache | 0.005 |
|
||||
| u_csr | 0.001 |
|
||||
| u_mul | 0.004 |
|
||||
| u_fft_mlkem_axi_slave | 0.251 |
|
||||
| u_fft_controller | 0.030 |
|
||||
| u_FFT | 0.027 |
|
||||
| u_out0 | 0.001 |
|
||||
| u_out1 | 0.001 |
|
||||
| u_mlkem_axi_slave | 0.221 |
|
||||
| u_mlkem | 0.218 |
|
||||
| u_matmul_axi_slave | 0.081 |
|
||||
=======
|
||||
| soc_top | 0.637 |
|
||||
| pll_clk.u_clk_pll | 0.103 |
|
||||
| inst | 0.103 |
|
||||
| u_Axi_CDC | 0.002 |
|
||||
| u_axi_uart_controller | 0.002 |
|
||||
| uart0 | 0.001 |
|
||||
| regs | 0.001 |
|
||||
| u_cdma_matmul_bridge | 0.001 |
|
||||
| u_confreg | 0.001 |
|
||||
| u_cpu | 0.027 |
|
||||
| addr_trans | 0.002 |
|
||||
| tlb_entry | 0.002 |
|
||||
| btb | 0.003 |
|
||||
| dcache | 0.004 |
|
||||
| icache | 0.005 |
|
||||
| u_csr | 0.001 |
|
||||
| u_mul | 0.008 |
|
||||
| u_fft_mlkem_axi_slave | 0.373 |
|
||||
| u_fft_controller | 0.031 |
|
||||
| u_FFT | 0.028 |
|
||||
| u_out0 | 0.001 |
|
||||
| u_out1 | 0.001 |
|
||||
| u_mlkem_axi_cdc | 0.003 |
|
||||
| wFifo | 0.001 |
|
||||
| u_mlkem_axi_slave | 0.339 |
|
||||
| u_mlkem | 0.332 |
|
||||
| u_matmul_axi_slave | 0.077 |
|
||||
>>>>>>> Stashed changes
|
||||
| mult_inst[0].u_mult | 0.003 |
|
||||
| mult_inst[1].u_mult | 0.002 |
|
||||
| mult_inst[2].u_mult | 0.002 |
|
||||
| mult_inst[3].u_mult | 0.002 |
|
||||
| u_snix_axil_cdma_mux_8ch | 0.008 |
|
||||
| u_core_engine | 0.004 |
|
||||
| axis_fifo_u0 | 0.002 |
|
||||
+----------------------------+-----------+
|
||||
|
||||
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||
| Date : Wed Jul 15 05:09:34 2026
|
||||
| Host : Roc_Wang running 64-bit major release (build 9200)
|
||||
| Command : report_power -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/power.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200tfbg676-1
|
||||
| Design State : routed
|
||||
| Grade : commercial
|
||||
| Process : typical
|
||||
| Characterization : Production
|
||||
-------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Power Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
1.1 On-Chip Components
|
||||
1.2 Power Supply Summary
|
||||
1.3 Confidence Level
|
||||
2. Settings
|
||||
2.1 Environment
|
||||
2.2 Clock Constraints
|
||||
3. Detailed Reports
|
||||
3.1 By Hierarchy
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+--------------------------+--------------+
|
||||
| Total On-Chip Power (W) | 0.779 |
|
||||
| Design Power Budget (W) | Unspecified* |
|
||||
| Power Budget Margin (W) | NA |
|
||||
| Dynamic (W) | 0.637 |
|
||||
| Device Static (W) | 0.142 |
|
||||
| Effective TJA (C/W) | 1.9 |
|
||||
| Max Ambient (C) | 83.5 |
|
||||
| Junction Temperature (C) | 26.5 |
|
||||
| Confidence Level | Low |
|
||||
| Setting File | --- |
|
||||
| Simulation Activity File | --- |
|
||||
| Design Nets Matched | NA |
|
||||
+--------------------------+--------------+
|
||||
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
|
||||
|
||||
|
||||
1.1 On-Chip Components
|
||||
----------------------
|
||||
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
| On-Chip | Power (W) | Used | Available | Utilization (%) |
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
| Clocks | 0.060 | 7 | --- | --- |
|
||||
| Slice Logic | 0.137 | 103629 | --- | --- |
|
||||
| LUT as Logic | 0.128 | 53158 | 133800 | 39.73 |
|
||||
| CARRY4 | 0.005 | 3669 | 33450 | 10.97 |
|
||||
| Register | 0.002 | 31000 | 267600 | 11.58 |
|
||||
| LUT as Distributed RAM | 0.001 | 740 | 46200 | 1.60 |
|
||||
| LUT as Shift Register | <0.001 | 1168 | 46200 | 2.53 |
|
||||
| F7/F8 Muxes | <0.001 | 2449 | 133800 | 1.83 |
|
||||
| Others | 0.000 | 333 | --- | --- |
|
||||
| Signals | 0.284 | 78815 | --- | --- |
|
||||
| Block RAM | 0.027 | 29.5 | 365 | 8.08 |
|
||||
| PLL | 0.102 | 1 | 10 | 10.00 |
|
||||
| I/O | 0.027 | 202 | 400 | 50.50 |
|
||||
| Static Power | 0.142 | | | |
|
||||
| Total | 0.779 | | | |
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
|
||||
|
||||
1.2 Power Supply Summary
|
||||
------------------------
|
||||
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Vccint | 1.000 | 0.545 | 0.512 | 0.033 |
|
||||
| Vccaux | 1.800 | 0.085 | 0.054 | 0.031 |
|
||||
| Vcco33 | 3.300 | 0.013 | 0.008 | 0.005 |
|
||||
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccbram | 1.000 | 0.003 | 0.002 | 0.001 |
|
||||
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
|
||||
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
|
||||
|
||||
1.3 Confidence Level
|
||||
--------------------
|
||||
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| User Input Data | Confidence | Details | Action |
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| Design implementation state | High | Design is routed | |
|
||||
| Clock nodes activity | High | User specified more than 95% of clocks | |
|
||||
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
|
||||
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
|
||||
| Device models | High | Device models are Production | |
|
||||
| | | | |
|
||||
| Overall confidence level | Low | | |
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
2. Settings
|
||||
-----------
|
||||
|
||||
2.1 Environment
|
||||
---------------
|
||||
|
||||
+-----------------------+--------------------------+
|
||||
| Ambient Temp (C) | 25.0 |
|
||||
| ThetaJA (C/W) | 1.9 |
|
||||
| Airflow (LFM) | 250 |
|
||||
| Heat Sink | medium (Medium Profile) |
|
||||
| ThetaSA (C/W) | 3.4 |
|
||||
| Board Selection | medium (10"x10") |
|
||||
| # of Board Layers | 12to15 (12 to 15 Layers) |
|
||||
| Board Temperature (C) | 25.0 |
|
||||
+-----------------------+--------------------------+
|
||||
|
||||
|
||||
2.2 Clock Constraints
|
||||
---------------------
|
||||
|
||||
+------------------+------------------------------------------+-----------------+
|
||||
| Clock | Domain | Constraint (ns) |
|
||||
+------------------+------------------------------------------+-----------------+
|
||||
| clk | clk | 20.0 |
|
||||
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
|
||||
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.0 |
|
||||
| mlkem_clk | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 13.0 |
|
||||
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
|
||||
+------------------+------------------------------------------+-----------------+
|
||||
|
||||
|
||||
3. Detailed Reports
|
||||
-------------------
|
||||
|
||||
3.1 By Hierarchy
|
||||
----------------
|
||||
|
||||
+----------------------------+-----------+
|
||||
| Name | Power (W) |
|
||||
+----------------------------+-----------+
|
||||
| soc_top | 0.637 |
|
||||
| pll_clk.u_clk_pll | 0.103 |
|
||||
| inst | 0.103 |
|
||||
| u_Axi_CDC | 0.002 |
|
||||
| u_axi_uart_controller | 0.002 |
|
||||
| uart0 | 0.001 |
|
||||
| regs | 0.001 |
|
||||
| u_cdma_matmul_bridge | 0.001 |
|
||||
| u_confreg | 0.001 |
|
||||
| u_cpu | 0.027 |
|
||||
| addr_trans | 0.002 |
|
||||
| tlb_entry | 0.002 |
|
||||
| btb | 0.003 |
|
||||
| dcache | 0.004 |
|
||||
| icache | 0.005 |
|
||||
| u_csr | 0.001 |
|
||||
| u_mul | 0.008 |
|
||||
| u_fft_mlkem_axi_slave | 0.373 |
|
||||
| u_fft_controller | 0.031 |
|
||||
| u_FFT | 0.028 |
|
||||
| u_out0 | 0.001 |
|
||||
| u_out1 | 0.001 |
|
||||
| u_mlkem_axi_cdc | 0.003 |
|
||||
| wFifo | 0.001 |
|
||||
| u_mlkem_axi_slave | 0.339 |
|
||||
| u_mlkem | 0.332 |
|
||||
| u_matmul_axi_slave | 0.077 |
|
||||
| mult_inst[0].u_mult | 0.003 |
|
||||
| mult_inst[1].u_mult | 0.002 |
|
||||
| mult_inst[2].u_mult | 0.002 |
|
||||
| mult_inst[3].u_mult | 0.002 |
|
||||
| u_snix_axil_cdma_mux_8ch | 0.008 |
|
||||
| u_core_engine | 0.004 |
|
||||
| axis_fifo_u0 | 0.002 |
|
||||
+----------------------------+-----------+
|
||||
|
||||
|
||||
5
doc/reports/system/evidence/vivado/revision.txt
Normal file
5
doc/reports/system/evidence/vivado/revision.txt
Normal file
@@ -0,0 +1,5 @@
|
||||
Evidence generated from implemented design.
|
||||
Vivado version: 2019.2
|
||||
Project: C:/Users/11747/Desktop/ciciec2026/fpga/project/Loongson_Soc.xpr
|
||||
Git revision: d45646342b79cefbc30775b5045e34c1f0d26ad6
|
||||
Generated at: 2026-07-15 05:09:50 +0800
|
||||
@@ -1,21 +1,12 @@
|
||||
Design Route Status
|
||||
: # nets :
|
||||
------------------------------------------- : ----------- :
|
||||
<<<<<<< Updated upstream
|
||||
# of logical nets.......................... : 144034 :
|
||||
# of nets not needing routing.......... : 50823 :
|
||||
# of internally routed nets........ : 50442 :
|
||||
# of nets with no loads............ : 381 :
|
||||
# of routable nets..................... : 93211 :
|
||||
# of fully routed nets............. : 93211 :
|
||||
=======
|
||||
# of logical nets.......................... : 114880 :
|
||||
# of nets not needing routing.......... : 36054 :
|
||||
# of internally routed nets........ : 35589 :
|
||||
# of nets with no loads............ : 465 :
|
||||
# of routable nets..................... : 78826 :
|
||||
# of fully routed nets............. : 78826 :
|
||||
>>>>>>> Stashed changes
|
||||
# of nets with routing errors.......... : 0 :
|
||||
------------------------------------------- : ----------- :
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,17 +1,13 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
<<<<<<< Updated upstream
|
||||
| Date : Fri Jul 10 04:14:47 2026
|
||||
=======
|
||||
| Date : Sat Jul 11 09:20:51 2026
|
||||
>>>>>>> Stashed changes
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_utilization -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/utilization.rpt
|
||||
-------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||
| Date : Wed Jul 15 05:09:26 2026
|
||||
| Host : Roc_Wang running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/utilization.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200tfbg676-1
|
||||
| Design State : Routed
|
||||
--------------------------------------------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
@@ -35,18 +31,6 @@ Table of Contents
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
<<<<<<< Updated upstream
|
||||
| Slice LUTs | 71196 | 0 | 133800 | 53.21 |
|
||||
| LUT as Logic | 69453 | 0 | 133800 | 51.91 |
|
||||
| LUT as Memory | 1743 | 0 | 46200 | 3.77 |
|
||||
| LUT as Distributed RAM | 628 | 0 | | |
|
||||
| LUT as Shift Register | 1115 | 0 | | |
|
||||
| Slice Registers | 39690 | 0 | 267600 | 14.83 |
|
||||
| Register as Flip Flop | 39690 | 0 | 267600 | 14.83 |
|
||||
| Register as Latch | 0 | 0 | 267600 | 0.00 |
|
||||
| F7 Muxes | 4565 | 0 | 66900 | 6.82 |
|
||||
| F8 Muxes | 1520 | 0 | 33450 | 4.54 |
|
||||
=======
|
||||
| Slice LUTs | 55066 | 0 | 133800 | 41.16 |
|
||||
| LUT as Logic | 53158 | 0 | 133800 | 39.73 |
|
||||
| LUT as Memory | 1908 | 0 | 46200 | 4.13 |
|
||||
@@ -57,7 +41,6 @@ Table of Contents
|
||||
| Register as Latch | 0 | 0 | 267600 | 0.00 |
|
||||
| F7 Muxes | 2130 | 0 | 66900 | 3.18 |
|
||||
| F8 Muxes | 319 | 0 | 33450 | 0.95 |
|
||||
>>>>>>> Stashed changes
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
|
||||
|
||||
@@ -74,15 +57,9 @@ Table of Contents
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 24 | Yes | - | Set |
|
||||
<<<<<<< Updated upstream
|
||||
| 26562 | Yes | - | Reset |
|
||||
| 139 | Yes | Set | - |
|
||||
| 12965 | Yes | Reset | - |
|
||||
=======
|
||||
| 17683 | Yes | - | Reset |
|
||||
| 126 | Yes | Set | - |
|
||||
| 13167 | Yes | Reset | - |
|
||||
>>>>>>> Stashed changes
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
@@ -92,30 +69,6 @@ Table of Contents
|
||||
+--------------------------------------------+-------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+--------------------------------------------+-------+-------+-----------+-------+
|
||||
<<<<<<< Updated upstream
|
||||
| Slice | 21289 | 0 | 33450 | 63.64 |
|
||||
| SLICEL | 13965 | 0 | | |
|
||||
| SLICEM | 7324 | 0 | | |
|
||||
| LUT as Logic | 69453 | 0 | 133800 | 51.91 |
|
||||
| using O5 output only | 2 | | | |
|
||||
| using O6 output only | 57661 | | | |
|
||||
| using O5 and O6 | 11790 | | | |
|
||||
| LUT as Memory | 1743 | 0 | 46200 | 3.77 |
|
||||
| LUT as Distributed RAM | 628 | 0 | | |
|
||||
| using O5 output only | 0 | | | |
|
||||
| using O6 output only | 60 | | | |
|
||||
| using O5 and O6 | 568 | | | |
|
||||
| LUT as Shift Register | 1115 | 0 | | |
|
||||
| using O5 output only | 47 | | | |
|
||||
| using O6 output only | 1008 | | | |
|
||||
| using O5 and O6 | 60 | | | |
|
||||
| Slice Registers | 39690 | 0 | 267600 | 14.83 |
|
||||
| Register driven from within the Slice | 24917 | | | |
|
||||
| Register driven from outside the Slice | 14773 | | | |
|
||||
| LUT in front of the register is unused | 6243 | | | |
|
||||
| LUT in front of the register is used | 8530 | | | |
|
||||
| Unique Control Sets | 1278 | | 33450 | 3.82 |
|
||||
=======
|
||||
| Slice | 17126 | 0 | 33450 | 51.20 |
|
||||
| SLICEL | 11119 | 0 | | |
|
||||
| SLICEM | 6007 | 0 | | |
|
||||
@@ -138,7 +91,6 @@ Table of Contents
|
||||
| LUT in front of the register is unused | 5924 | | | |
|
||||
| LUT in front of the register is used | 8408 | | | |
|
||||
| Unique Control Sets | 930 | | 33450 | 2.78 |
|
||||
>>>>>>> Stashed changes
|
||||
+--------------------------------------------+-------+-------+-----------+-------+
|
||||
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
|
||||
|
||||
@@ -149,19 +101,11 @@ Table of Contents
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
<<<<<<< Updated upstream
|
||||
| Block RAM Tile | 25.5 | 0 | 365 | 6.99 |
|
||||
| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 |
|
||||
| RAMB36E1 only | 10 | | | |
|
||||
| RAMB18 | 31 | 0 | 730 | 4.25 |
|
||||
| RAMB18E1 only | 31 | | | |
|
||||
=======
|
||||
| Block RAM Tile | 29.5 | 0 | 365 | 8.08 |
|
||||
| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 |
|
||||
| RAMB36E1 only | 10 | | | |
|
||||
| RAMB18 | 39 | 0 | 730 | 5.34 |
|
||||
| RAMB18E1 only | 39 | | | |
|
||||
>>>>>>> Stashed changes
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
@@ -209,7 +153,7 @@ Table of Contents
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 3 | 0 | 32 | 9.38 |
|
||||
| BUFGCTRL | 4 | 0 | 32 | 12.50 |
|
||||
| BUFIO | 0 | 0 | 40 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| PLLE2_ADV | 1 | 0 | 10 | 10.00 |
|
||||
@@ -243,24 +187,6 @@ Table of Contents
|
||||
+-----------+-------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+-----------+-------+---------------------+
|
||||
<<<<<<< Updated upstream
|
||||
| LUT6 | 37981 | LUT |
|
||||
| FDCE | 26562 | Flop & Latch |
|
||||
| FDRE | 12965 | Flop & Latch |
|
||||
| LUT5 | 12781 | LUT |
|
||||
| LUT4 | 10316 | LUT |
|
||||
| LUT3 | 10135 | LUT |
|
||||
| LUT2 | 9228 | LUT |
|
||||
| MUXF7 | 4565 | MuxFx |
|
||||
| CARRY4 | 3546 | CarryLogic |
|
||||
| MUXF8 | 1520 | MuxFx |
|
||||
| SRLC32E | 992 | Distributed Memory |
|
||||
| RAMD32 | 892 | Distributed Memory |
|
||||
| LUT1 | 802 | LUT |
|
||||
| RAMS32 | 272 | Distributed Memory |
|
||||
| SRL16E | 183 | Distributed Memory |
|
||||
| FDSE | 139 | Flop & Latch |
|
||||
=======
|
||||
| LUT6 | 26800 | LUT |
|
||||
| FDCE | 17683 | Flop & Latch |
|
||||
| FDRE | 13167 | Flop & Latch |
|
||||
@@ -277,7 +203,6 @@ Table of Contents
|
||||
| MUXF8 | 319 | MuxFx |
|
||||
| SRL16E | 224 | Distributed Memory |
|
||||
| FDSE | 126 | Flop & Latch |
|
||||
>>>>>>> Stashed changes
|
||||
| IBUF | 104 | IO |
|
||||
| OBUF | 98 | IO |
|
||||
| OBUFT | 66 | IO |
|
||||
@@ -285,11 +210,7 @@ Table of Contents
|
||||
| RAMD64E | 32 | Distributed Memory |
|
||||
| FDPE | 24 | Flop & Latch |
|
||||
| RAMB36E1 | 10 | Block Memory |
|
||||
<<<<<<< Updated upstream
|
||||
| BUFG | 3 | Clock |
|
||||
=======
|
||||
| BUFG | 4 | Clock |
|
||||
>>>>>>> Stashed changes
|
||||
| PLLE2_ADV | 1 | Clock |
|
||||
+-----------+-------+---------------------+
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sat Jul 11 09:20:51 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_utilization -hierarchical -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/utilization_hier.rpt
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||
| Date : Wed Jul 15 05:09:25 2026
|
||||
| Host : Roc_Wang running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -hierarchical -hierarchical_depth 4 -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/utilization_hierarchical.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200tfbg676-1
|
||||
| Design State : Routed
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
@@ -105,15 +105,7 @@ Table of Contents
|
||||
| (regs) | uart_regs | 118 | 118 | 0 | 0 | 155 | 0 | 0 | 0 |
|
||||
| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| receiver | uart_receiver | 229 | 221 | 8 | 0 | 124 | 0 | 0 | 0 |
|
||||
| (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 |
|
||||
| fifo_rx | uart_rfifo | 161 | 153 | 8 | 0 | 70 | 0 | 0 | 0 |
|
||||
| (fifo_rx) | uart_rfifo | 143 | 143 | 0 | 0 | 62 | 0 | 0 | 0 |
|
||||
| rfifo | raminfr_57 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
||||
| transmitter | uart_transmitter | 83 | 75 | 8 | 0 | 56 | 0 | 0 | 0 |
|
||||
| (transmitter) | uart_transmitter | 41 | 41 | 0 | 0 | 35 | 0 | 0 | 0 |
|
||||
| fifo_tx | uart_tfifo | 43 | 35 | 8 | 0 | 21 | 0 | 0 | 0 |
|
||||
| (fifo_tx) | uart_tfifo | 24 | 24 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_cdma_matmul_bridge | cdma_matmul_bridge | 248 | 248 | 0 | 0 | 578 | 0 | 0 | 0 |
|
||||
| u_confreg | confreg | 390 | 390 | 0 | 0 | 476 | 0 | 0 | 0 |
|
||||
| (u_confreg) | confreg | 230 | 230 | 0 | 0 | 399 | 0 | 0 | 0 |
|
||||
@@ -170,43 +162,10 @@ Table of Contents
|
||||
| (u_fft_controller) | fft_controller | 118 | 118 | 0 | 0 | 100 | 0 | 0 | 0 |
|
||||
| u_FFT | FFT | 6782 | 5742 | 0 | 1040 | 983 | 8 | 0 | 0 |
|
||||
| SU1 | SdfUnit | 2144 | 1376 | 0 | 768 | 197 | 2 | 0 | 0 |
|
||||
| (SU1) | SdfUnit | 39 | 39 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_34 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_35 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer | 624 | 112 | 0 | 512 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized0 | 320 | 64 | 0 | 256 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_36 | 610 | 610 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle_37 | 543 | 543 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU2 | SdfUnit__parameterized0 | 1567 | 1375 | 0 | 192 | 197 | 2 | 0 | 0 |
|
||||
| (SU2) | SdfUnit__parameterized0 | 38 | 38 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_30 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_31 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_32 | 612 | 612 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle_33 | 541 | 541 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU3 | SdfUnit__parameterized1 | 1416 | 1368 | 0 | 48 | 197 | 2 | 0 | 0 |
|
||||
| (SU3) | SdfUnit__parameterized1 | 35 | 35 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_26 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_27 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized4 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_28 | 610 | 610 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle_29 | 539 | 539 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU4 | SdfUnit__parameterized2 | 1397 | 1365 | 0 | 32 | 197 | 2 | 0 | 0 |
|
||||
| (SU4) | SdfUnit__parameterized2 | 34 | 34 | 0 | 0 | 133 | 0 | 0 | 0 |
|
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| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
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| BF2 | Butterfly__parameterized0_25 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
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| DB1 | DelayBuffer__parameterized5 | 128 | 112 | 0 | 16 | 32 | 0 | 0 | 0 |
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| DB2 | DelayBuffer__parameterized6 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
|
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| MU | Multiply | 611 | 611 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle | 536 | 536 | 0 | 0 | 0 | 2 | 0 | 0 |
|
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| SU5 | SdfUnit__parameterized3 | 258 | 258 | 0 | 0 | 195 | 0 | 0 | 0 |
|
||||
| (SU5) | SdfUnit__parameterized3 | 34 | 34 | 0 | 0 | 99 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
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| BF2 | Butterfly__parameterized0 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
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| DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 |
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| DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 |
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| u_in0 | my_bram0 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
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| u_in1 | my_bram0_21 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
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| u_out0 | my_bram0_22 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
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@@ -249,27 +208,7 @@ Table of Contents
|
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| u_ek_bram | sd_bram_8 | 304 | 304 | 0 | 0 | 0 | 0 | 1 | 0 |
|
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| u_keccak | keccak_core | 5258 | 5258 | 0 | 0 | 1618 | 0 | 0 | 0 |
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| u_ntt | ntt_core | 1900 | 1817 | 0 | 83 | 1062 | 0 | 4 | 0 |
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| (u_ntt) | ntt_core | 281 | 249 | 0 | 32 | 215 | 0 | 0 | 0 |
|
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| u_bf0 | butterfly_unit_pipe | 675 | 650 | 0 | 25 | 321 | 0 | 0 | 0 |
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| (u_bf0) | butterfly_unit_pipe | 264 | 239 | 0 | 25 | 112 | 0 | 0 | 0 |
|
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| u_barrett | barrett_mul_pipe_18 | 411 | 411 | 0 | 0 | 209 | 0 | 0 | 0 |
|
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| u_bf1 | butterfly_unit_pipe_12 | 487 | 462 | 0 | 25 | 307 | 0 | 0 | 0 |
|
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| (u_bf1) | butterfly_unit_pipe_12 | 89 | 65 | 0 | 24 | 96 | 0 | 0 | 0 |
|
||||
| u_barrett | barrett_mul_pipe_17 | 398 | 397 | 0 | 1 | 211 | 0 | 0 | 0 |
|
||||
| u_cr | coeff_bram_4way | 208 | 208 | 0 | 0 | 8 | 0 | 4 | 0 |
|
||||
| (u_cr) | coeff_bram_4way | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| gen_xbar[0].u_bank | sd_bram__parameterized3_13 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| gen_xbar[1].u_bank | sd_bram__parameterized3_14 | 89 | 89 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| gen_xbar[2].u_bank | sd_bram__parameterized3_15 | 16 | 16 | 0 | 0 | 0 | 0 | 1 | 0 |
|
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| gen_xbar[3].u_bank | sd_bram__parameterized3_16 | 82 | 82 | 0 | 0 | 0 | 0 | 1 | 0 |
|
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| u_scl | barrett_mul_pipe | 252 | 251 | 0 | 1 | 211 | 0 | 0 | 0 |
|
||||
| u_pmul | poly_mul_sync | 2058 | 2021 | 0 | 37 | 584 | 0 | 4 | 0 |
|
||||
| (u_pmul) | poly_mul_sync | 634 | 634 | 0 | 0 | 121 | 0 | 0 | 0 |
|
||||
| u_a_even | sd_bram__parameterized3 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_a_odd | sd_bram__parameterized3_9 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_b_even | sd_bram__parameterized3_10 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_b_odd | sd_bram__parameterized3_11 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_bc | basecase_mul_pipe | 1423 | 1386 | 0 | 37 | 463 | 0 | 0 | 0 |
|
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| u_sha3 | sha3_top_shared | 1955 | 1955 | 0 | 0 | 2378 | 0 | 0 | 0 |
|
||||
| u_snt | sample_ntt_sync_shared | 2109 | 2109 | 0 | 0 | 1669 | 0 | 0 | 0 |
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| u_matmul_axi_slave | matmul_axi_slave | 9879 | 9697 | 176 | 6 | 3243 | 0 | 0 | 0 |
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|
||||
<rect x="600" y="-17" width="28" height="20" class="crc"/><text x="638" y="0" class="small">CRC缓冲与更新</text>
|
||||
<rect x="835" y="-17" width="28" height="20" class="disabled"/><text x="873" y="0" class="small">快速模式禁用路径</text>
|
||||
<text x="1160" y="0" class="small" fill="#52606d">系统时钟：50 MHz</text>
|
||||
</g>
|
||||
</svg>
|
||||
|
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|
Before Width: | Height: | Size: 1.4 MiB After Width: | Height: | Size: 1.3 MiB |
104
doc/reports/system/modules/00_clock_domains.md
Normal file
104
doc/reports/system/modules/00_clock_domains.md
Normal file
@@ -0,0 +1,104 @@
|
||||
# 时钟域、复位与跨时钟域设计说明
|
||||
|
||||
## 1. 时钟拓扑
|
||||
|
||||
板级输入 `clk` 的周期为 20 ns，即 50 MHz。硬件路径由 `clk_pll` 产生 CPU、系统总线和
|
||||
ML-KEM 三个时钟。当前实现报告记录的周期和频率如下。
|
||||
|
||||
| 时钟 | 周期 | 频率 | 主要负载 |
|
||||
|---|---:|---:|---|
|
||||
| `cpu_clk` | 30 ns | 33.333 MHz | OpenLA500 CPU、CPU 侧缓存和 AXI 主接口 |
|
||||
| `sys_clk` | 20 ns | 50 MHz | Crossbar、SRAM、UART、DMA、FFT、matmul 和系统寄存器 |
|
||||
| `mlkem_clk` | 13 ns | 76.923 MHz | ML-KEM AXI 从端、算法总控、Keccak、NTT 和多项式算子 |
|
||||
|
||||
三个时钟均由同一个 PLL 产生，但 `soc.xdc` 使用 `set_clock_groups -asynchronous` 将三者
|
||||
划入独立异步组。工程含义是任何跨域逻辑都不能依赖固定相位关系，静态时序分析也不会把
|
||||
普通组合路径当作同步时序路径检查。跨域正确性必须由双时钟 FIFO、同步器、握手协议和
|
||||
专门的 CDC 验证保证。
|
||||
|
||||
## 2. 模块归属
|
||||
|
||||
CPU 核及其 AXI 主端属于 CPU 域。CPU 发出的 AW、W、AR 通道在进入 Crossbar 前跨到
|
||||
SYS 域，B 和 R 响应反向跨回 CPU 域。Crossbar 的两个主端、八个从端、外部 SRAM、
|
||||
DMA、FFT、矩阵序列器和矩阵乘法器全部属于 SYS 域，这些模块之间是同步连接。
|
||||
|
||||
FFT/ML-KEM 共享从端的地址选择和 FFT 分支属于 SYS 域。ML-KEM 分支的完整 AXI 接口
|
||||
跨到 ML-KEM 域后，`mlkem_axi_slave`、`mlkem_top` 及其所有叶子算子均在
|
||||
`mlkem_clk` 下工作。密码核心内部没有第二个计算时钟。
|
||||
|
||||
## 3. CPU--SYS AXI 跨域
|
||||
|
||||
`u_Axi_CDC` 为 AXI 的 AW、W、B、AR 和 R 五个通道分别设置双时钟 FIFO。AW、W 和 AR
|
||||
在 CPU 域写入 FIFO、在 SYS 域读出；B 和 R 在 SYS 域写入、在 CPU 域读出。FIFO 将
|
||||
valid/ready 反压限制在各自时钟域，并连同地址、ID、burst 属性、数据、WSTRB、响应和
|
||||
RLAST/WLAST 一起跨域。
|
||||
|
||||
该结构不对多位 AXI payload 逐位使用两级同步器，而是在写时钟域稳定写入存储，使用同步
|
||||
后的读写指针传递所有权，再在读时钟域读取。这是多位总线跨域的必要条件。AW 和 W 仍为
|
||||
独立通道，下游从端必须按 AXI 规则处理两者不同拍到达，不能假设跨域 FIFO 会自动配对。
|
||||
|
||||
CPU--SYS 路径的延迟包含 FIFO 入队、指针同步和出队，不应通过 CPU 与 SYS 周期的简单
|
||||
比例估算。端到端软件周期已经包含该延迟。
|
||||
|
||||
## 4. SYS--ML-KEM AXI 跨域
|
||||
|
||||
`fft_mlkem_axi_slave` 在 SYS 域锁存目标选择。FFT 请求保持在 SYS 域；ML-KEM 请求进入
|
||||
第二个 `Axi_CDC`，再由 ML-KEM 域的 `mlkem_axi_slave` 处理。该跨域同样覆盖 AXI 五个
|
||||
通道，而不是只同步 start/done。因此配置寄存器、批量密钥窗口和读回数据都遵循统一的
|
||||
AXI CDC 语义。
|
||||
|
||||
ML-KEM 完成中断在 `mlkem_clk` 域产生，先通过两级 `mlkem_intr_sync` 同步到 SYS 域。
|
||||
由于完成状态保持到软件 W1C，接收端观察的是电平而不是单周期脉冲，避免因频率差异丢失
|
||||
事件。软件读取 STATUS 获得最终完成语义，中断只负责通知。
|
||||
|
||||
## 5. 中断到 CPU 的边界
|
||||
|
||||
当前 `soc_top` 将 `confreg_int`、DMA done、matmul done 和 ML-KEM done 组合后直接连接
|
||||
到 CPU 的 `intrpt` 输入。其中 DMA 和 matmul 状态产生于 SYS 域；ML-KEM 状态虽已同步到
|
||||
SYS 域，仍需跨入 CPU 域。它们均为保持到清除的电平信号，因此相较单拍脉冲更不易漏采，
|
||||
但当前顶层没有为项目新增的三路中断显式实例化 CPU 域两级同步器。
|
||||
|
||||
严谨的前端实现应在 `cpu_clk` 域对每路异步电平增加两级 `ASYNC_REG` 同步，或把中断状态
|
||||
放入已有的 CPU--SYS 握手寄存器。同步前的电平必须保持不少于两个 CPU 周期，清除语义也
|
||||
应以 CPU 可观察到状态后再执行。该项属于时钟域实现风险，不能仅以板级轮询程序通过替代
|
||||
结构验证。
|
||||
|
||||
## 6. 复位生成与释放顺序
|
||||
|
||||
`rst_sync` 包含两个串联寄存器。输入复位有效时通过异步低电平立即把两级清零；输入复位
|
||||
撤销后，逻辑 1 在本时钟域连续两个上升沿移入，形成异步断言、同步撤销的低有效复位。
|
||||
|
||||
硬件路径中，外部 reset 先复位 PLL。PLL `locked` 进入 SYS 域复位同步器，产生
|
||||
`sys_resetn`；随后 `sys_resetn` 分别作为 CPU 和 ML-KEM 复位同步器输入，产生
|
||||
`cpu_resetn` 和 `mlkem_resetn`。因此 SYS 域先释放，CPU 和 ML-KEM 域至少再等待各自两个
|
||||
有效时钟边沿。CDC 两侧在各自复位释放前不得发送 valid，也不得保留上一轮 FIFO 所有权。
|
||||
|
||||
行为仿真 `SIMULATION=1` 不实例化 PLL。testbench 的 50 MHz 时钟直接作为 `sys_clk`，
|
||||
内部 30 ns 周期时钟作为 `cpu_clk`，`mlkem_clk` 暂等于 `sys_clk`。此模式可验证复位顺序
|
||||
和零事务，但不能验证真实 13 ns ML-KEM 时钟的相位、PLL 锁定过程或异步 FIFO 的全部
|
||||
频率组合。
|
||||
|
||||
当前 20 us XSIM VCD 中，外部 reset 在 2.000 us 撤销，`sys_resetn`、`mlkem_resetn` 和
|
||||
`cpu_resetn` 分别约在 2.030、2.070 和 2.085 us 释放。第一个 CPU ARVALID 约在
|
||||
2.205 us 出现，复位释放前 UART、AXI、DMA 请求和加速器 start 均没有高电平。
|
||||
|
||||
## 7. 跨域信号设计规则
|
||||
|
||||
单比特静态状态可以采用两级同步器，但源端必须保持足够长时间。单周期脉冲需要 toggle、
|
||||
脉冲展宽或 request/ack 握手，不能直接送入另一个时钟域。多位配置和数据必须通过异步
|
||||
FIFO、握手后稳定保持的影子寄存器或双口存储传递，禁止逐位同步后重新组合。
|
||||
|
||||
复位也是跨域信号。每个时钟域必须使用本地同步释放的 resetn，不能用另一个域同步器的
|
||||
输出直接复位本域大量寄存器。所有 CDC 结构的两侧复位关系必须保证复位期间不会把残留
|
||||
valid 解释为新事务。
|
||||
|
||||
## 8. 时序与验证方法
|
||||
|
||||
单域时序分别在 `cpu_clk`、`sys_clk` 和 `mlkem_clk` 路径组内检查 setup 和 hold。由于
|
||||
时钟组被声明为异步，跨域路径不应以普通 WNS 作为正确性依据。验证应包括 CDC 结构审查、
|
||||
同步寄存器属性检查、异步 FIFO 满空边界、随机相位/频率仿真、复位任意时刻进入，以及
|
||||
valid/ready 双向反压。
|
||||
|
||||
板级功能测试证明常用任务能够跨域完成，但不能观察亚稳态。报告中的时钟域结论应分别
|
||||
引用时钟报告、单域时序报告、复位波形和 CDC 结构说明，避免用单一板级 PASS 替代这些
|
||||
不同层次的证据。
|
||||
77
doc/reports/system/modules/01_soc_integration.md
Normal file
77
doc/reports/system/modules/01_soc_integration.md
Normal file
@@ -0,0 +1,77 @@
|
||||
# SoC 集成与时钟复位技术说明
|
||||
|
||||
## 1. 模块定位
|
||||
|
||||
`rtl/soc_top.v` 是项目的系统集成顶层。该文件不重新实现 CPU、UART 或 SRAM 控制器，
|
||||
而是将 OpenLA500 处理器、存储器、外设、DMA 和三个计算加速器组织为统一的 AXI 系统。
|
||||
项目相关的集成工作包括扩展 Crossbar 从端口、增加 DMA 主端口、划分加速器地址窗口、
|
||||
建立 CPU--SYS 和 SYS--ML-KEM 时钟边界，以及将完成状态接入中断系统。
|
||||
|
||||
系统采用 CPU 控制、DMA 搬运、加速器计算的职责划分。CPU 通过寄存器完成参数配置和
|
||||
任务启动；DMA 作为第二个 AXI 主机访问存储器与外设；FFT、ML-KEM 和矩阵乘法器作为
|
||||
被控计算单元。矩阵批处理序列器位于 DMA 控制窗口内，可脱离 CPU 的逐组调度执行长任务。
|
||||
|
||||
## 2. 地址空间与互连
|
||||
|
||||
系统 Crossbar 具有两个主端和八个从端。主端 0 接收经 `Axi_CDC` 转换后的 CPU AXI
|
||||
事务，主端 1 接收 DMA 发起的 AXI 事务。与本项目直接相关的从端如下。
|
||||
|
||||
| 物理地址 | 模块 | 作用 |
|
||||
|---|---|---|
|
||||
| `0x1f30_0000` | DMA 控制窗口 | 通道寄存器位于 `0x000--0x1ff`，矩阵序列器位于 `0x200--0x21f` |
|
||||
| `0x1f40_0000` | FFT/ML-KEM 共享窗口 | ML-KEM 使用低 `0x0000--0x3fff`，FFT 使用 `0x8000--0xcfff` |
|
||||
| `0x1f50_0000` | 矩阵乘法器 | 控制状态、CRC32、双 Bank 输入和结果窗口 |
|
||||
|
||||
CPU 软件使用高位映射访问未缓存地址，例如物理地址 `0x1f40_0000` 对应
|
||||
`0xbf40_0000`。DMA 始终使用物理地址，软件在提交描述符前需要去除 CPU 虚拟地址的
|
||||
高位映射。该约定避免 DMA 错把虚拟地址送入 Crossbar。
|
||||
|
||||
DMA 控制从端原始接口为 AXI4，经 `axi_axil_adapter` 转换为 AXI-Lite。地址偏移
|
||||
`0x200` 的访问在顶层被路由到 `cdma_matmul_bridge`，其余访问进入通用 DMA 通道寄存器。
|
||||
写地址的目标选择在 AW 握手后保持到 B 响应返回，读地址选择保持到 R 响应返回，从而
|
||||
避免响应阶段再次依赖变化中的地址信号。
|
||||
|
||||
## 3. 时钟结构
|
||||
|
||||
硬件实现使用 50 MHz 外部时钟驱动 PLL，产生三个逻辑时钟域。当前实现报告中的目标
|
||||
频率为 CPU 33.333 MHz、系统总线 50 MHz 和 ML-KEM 76.923 MHz。CPU 核及其 AXI 侧
|
||||
逻辑工作在 `cpu_clk`；Crossbar、DMA、FFT、矩阵乘法器和外设工作在 `sys_clk`；
|
||||
ML-KEM 核心工作在 `mlkem_clk`。
|
||||
|
||||
CPU AXI 五个通道通过 `Axi_CDC` 跨入系统时钟域。ML-KEM 的配置、批量数据窗口和完成
|
||||
响应通过第二个完整 AXI CDC 跨越 SYS--ML-KEM 边界；`mlkem_axi_slave` 内部的
|
||||
toggle/ack 负责把寄存器动作转换为单次事件。FFT 与矩阵乘法器均位于系统时钟域，不需要
|
||||
额外的计算域 CDC。
|
||||
|
||||
完整的时钟归属、异步时钟组约束、AXI 双时钟 FIFO 和中断边界见
|
||||
[时钟域、复位与跨时钟域设计说明](00_clock_domains.md)。本文件只说明顶层集成关系。
|
||||
|
||||
行为仿真中 `SIMULATION=1`，PLL 被可控仿真时钟替代：`sys_clk` 使用 50 MHz testbench
|
||||
时钟，`cpu_clk` 使用约 33.333 MHz 时钟，`mlkem_clk` 暂与 `sys_clk` 相同。该模式用于
|
||||
功能验证，不用于推导硬件 PLL 的锁定时间或跨域相位关系。
|
||||
|
||||
## 4. 复位结构
|
||||
|
||||
硬件路径中，PLL 的 `locked` 信号首先送入系统域 `rst_sync`。`sys_resetn` 释放后，CPU
|
||||
域和 ML-KEM 域的复位同步器再分别产生 `cpu_resetn` 和 `mlkem_resetn`。各同步器采用
|
||||
异步断言、同步撤销原则，使复位可立即进入有效状态，而退出复位只能发生在本时钟域的
|
||||
有效边沿。
|
||||
|
||||
复位约束不仅要求状态机回到初始状态，还要求复位释放前不产生外部可见事务。当前短时
|
||||
XSIM 证据记录了 UART 写使能、CPU AXI AW/W/AR valid、DMA 读写请求、矩阵启动和
|
||||
ML-KEM 启动。VCD 中 `sys_resetn`、`mlkem_resetn` 和 `cpu_resetn` 分别约在 2.030 us、
|
||||
2.070 us 和 2.085 us 释放；第一个 CPU 读请求出现在约 2.205 us，晚于 CPU 复位释放。
|
||||
|
||||
## 5. 中断与完成状态
|
||||
|
||||
DMA 的通道完成标志归并为 `cdma_dma_finish`，矩阵序列器另有 `cdma_matmul_seq_irq`。
|
||||
矩阵乘法器输出电平型 `matmul_intr`，ML-KEM 前端输出 `mlkem_intr`，FFT 完成状态接入
|
||||
原有 `confreg` 中断路径。性能测试程序主要采用轮询，以减少短任务的中断现场开销；
|
||||
中断信号仍保留给功能软件和后续异步调度使用。
|
||||
|
||||
## 6. 验证重点
|
||||
|
||||
顶层验证应覆盖地址译码互斥性、CPU 与 DMA 并发访问、AW/W 分离到达、复位前零事务、
|
||||
各域复位释放顺序以及完成状态的置位和清除。板级功能通过 FFT、ML-KEM 和矩阵乘法
|
||||
程序分别验证；时钟频率、时序裕量和资源使用以实现后报告为准。行为仿真不能替代 PLL
|
||||
实现检查，单个应用通过也不能证明所有地址空洞和并发组合均已覆盖。
|
||||
83
doc/reports/system/modules/02_dma_subsystem.md
Normal file
83
doc/reports/system/modules/02_dma_subsystem.md
Normal file
@@ -0,0 +1,83 @@
|
||||
# 通用 DMA 子系统技术说明
|
||||
|
||||
## 1. 功能与组成
|
||||
|
||||
DMA 子系统位于 `rtl/ip/cdma/`，对软件提供四个逻辑通道，对系统提供一个 32 位 AXI4
|
||||
主端，并对矩阵乘法器提供 32 位本地 endpoint。当前顶层实例参数为 `PORTS=4`、
|
||||
`DATA_WIDTH=32`、`FIFO_DEPTH=64`。源码中的“8 通道”实例名和注释是历史名称，实际
|
||||
综合配置应以参数值四通道为准。
|
||||
|
||||
子系统由三部分组成。`snix_axil_cdma_mux` 实现通道寄存器、轮询仲裁、传输模式选择和
|
||||
AXI 主端复用；`snix_axi_mm2mm` 实现普通内存到内存的 burst 搬运；本地 endpoint 状态机
|
||||
实现内存与矩阵双 Bank 之间的数据传递。同步 FIFO 和 AXIS FIFO 用于隔离 AXI 读、写
|
||||
通道的反压。
|
||||
|
||||
## 2. 软件接口
|
||||
|
||||
每个通道占用 `0x40` 字节，通道 `n` 的偏移基址为 `n*0x40`。
|
||||
|
||||
| 偏移 | 名称 | 说明 |
|
||||
|---|---|---|
|
||||
| `0x00` | SRC_ADDR | 源物理地址 |
|
||||
| `0x04` | DST_ADDR | 目的物理地址 |
|
||||
| `0x08` | LENGTH | 传输字节数 |
|
||||
| `0x0c` | TAG | 软件标记，硬件不解释 |
|
||||
| `0x10` | CTRL | bit 0 启动，bits 5:3 为 AxSIZE，bits 13:6 为 AxLEN |
|
||||
| `0x14` | STATUS | bit 0 busy，bit 1 done；done 采用 W1C |
|
||||
| `0x18` | MODE | 0 为 mem2mem，1 为 mem2ep，2 为 ep2mem |
|
||||
| `0x1c` | EP_CFG | bits 3:0 Bank，bits 15:8 word offset，bits 19:16 endpoint ID |
|
||||
|
||||
通道处于 busy 时，源地址、目的地址、长度、模式和 endpoint 配置不再接受修改。新启动
|
||||
请求会清除旧 done，硬件完成与软件 W1C 同周期发生时以硬件置位优先，避免丢失完成事件。
|
||||
所有地址均为物理地址，长度以字节计。
|
||||
|
||||
## 3. 通道仲裁
|
||||
|
||||
`snix_axil_cdma_mux` 为四个通道维护独立的请求位和完成位，但共享一个实际搬运引擎。
|
||||
仲裁器从 `rr_ptr` 开始循环检查待处理通道，选中后锁存 `cur_ch`，在 START 状态发出单拍
|
||||
`engine_start`，在 RUN 状态等待对应引擎完成。完成后设置该通道 done，并将轮询指针
|
||||
移动到下一通道。该结构保证长期存在的请求不会固定占用最低编号优先级。
|
||||
|
||||
共享引擎意味着四个通道可以独立排队，但不能同时占用 AXI 主端。多通道的主要收益是
|
||||
减少软件串行配置依赖并提供公平排队，而不是形成四路并行 AXI 数据流。
|
||||
|
||||
## 4. 内存到内存路径
|
||||
|
||||
`snix_axi_mm2mm` 的控制状态依次为 IDLE、PREP1、PREP2、AR、READ、AW、WRITE 和
|
||||
WAIT_BRESP。引擎先计算本次 burst 的实际长度，发出 INCR 读请求，将 R 通道数据写入
|
||||
FIFO，再发出对应写请求并从 FIFO 驱动 W 通道。最后一个写响应返回后，若仍有剩余字节，
|
||||
引擎更新源地址和目的地址并处理下一 burst。
|
||||
|
||||
读数据只在 READ 状态接收，写数据只在 WRITE 状态发送。该门控防止非活动状态下的
|
||||
AXI beat 被误计数。末尾不足一个数据宽度时由 `WSTRB` 屏蔽无效字节。当前 SoC 数据宽度
|
||||
为 32 bit，常用配置为 AxSIZE=2，即每 beat 4 字节。
|
||||
|
||||
## 5. 本地 endpoint 路径
|
||||
|
||||
mem2ep 模式从 AXI 地址读取数据，并逐字送往 `ep_wr_valid/ready`；ep2mem 模式通过
|
||||
`ep_rd_valid/ready` 读取本地结果，再发出 AXI 写事务。endpoint 接口附带 endpoint ID、
|
||||
Bank 号和字地址，因此无需把矩阵双 Bank 映射回 Crossbar，也避免每个 32 位字再次经过
|
||||
从端地址译码。
|
||||
|
||||
矩阵批处理序列器还可通过 `ext_rd_req_*` 和 `ext_wr_req_*` 直接提交一次外部请求。这组
|
||||
请求优先占用 AXI 主端，并在通用通道引擎空闲时接收。读请求完成后产生单拍
|
||||
`ext_rd_req_done`，写请求在 B 响应返回后产生 `ext_wr_req_done`。该接口用于流水调度，
|
||||
减少序列器重复写入通道 CSR 的延迟。
|
||||
|
||||
## 6. 复位与反压
|
||||
|
||||
当前集成的 DMA 通道寄存器、仲裁器、mem2mem 引擎、endpoint 引擎和 AXI 主端均工作在
|
||||
`sys_clk`，内部不存在活动的异步时钟边界。仓库保留的 `snix_async_fifo` 未被当前
|
||||
`soc_top` 层次实例化；实际数据 FIFO 为同一 SYS 域内的同步 FIFO。
|
||||
|
||||
所有控制状态、通道请求和完成位在 `rst_n=0` 时清零。AXI 与 endpoint 均遵循
|
||||
valid/ready 规则：发送端在握手前保持数据和控制字段，接收端可通过 ready 插入反压。
|
||||
目前 endpoint 只按 32 位数据宽度实现，字节数不是 4 的整数倍时不应使用该路径。
|
||||
|
||||
## 7. 验证方法与限制
|
||||
|
||||
DMA 验证至少应覆盖不同 burst 长度、末尾非满 beat、四通道公平性、R/W 反压、
|
||||
mem2mem、mem2ep、ep2mem 和 W1C 竞态。当前板级 FFT DMA 和 ML-KEM DMA 测试证明了
|
||||
普通外设窗口搬运路径，矩阵评测证明了外部请求与本地 endpoint 路径。当前实现未设置
|
||||
总线超时和错误恢复状态，若 AXI 从端永久不响应，通道会保持 busy；因此系统集成时必须
|
||||
保证目标地址有效，或在后续版本增加 watchdog 和错误码。
|
||||
70
doc/reports/system/modules/03_matmul_batch_sequencer.md
Normal file
70
doc/reports/system/modules/03_matmul_batch_sequencer.md
Normal file
@@ -0,0 +1,70 @@
|
||||
# 矩阵批处理序列器技术说明
|
||||
|
||||
## 1. 模块职责
|
||||
|
||||
`cdma_matmul_bridge` 将一次软件启动扩展为多组矩阵的完整硬件调度。模块位于 DMA 控制
|
||||
窗口偏移 `0x200`，通过通用 DMA 的外部请求接口搬运输入和可选结果，通过本地控制信号
|
||||
启动矩阵乘法器。该结构消除了 CPU 对 5000 组任务逐组配置、轮询和切换 Bank 的开销。
|
||||
|
||||
序列器、通用 DMA 外部请求接口和矩阵本地控制接口全部工作在 `sys_clk`，因此 Bank 状态、
|
||||
request/done 和 start 信号之间为同步路径。CPU 对序列器寄存器的访问在到达本模块前已由
|
||||
CPU--SYS `Axi_CDC` 完成跨域。
|
||||
|
||||
每组输入由两个 4x4、32 位无符号矩阵组成，共 32 个字，即 128 字节。每组结果包含
|
||||
16 个 66 位元素，以每元素三个 32 位字存储，共 192 字节。序列器使用可配置 stride，
|
||||
因此数据可以连续排列，也可嵌入更大的记录结构。
|
||||
|
||||
## 2. 寄存器接口
|
||||
|
||||
| 绝对偏移 | 名称 | 说明 |
|
||||
|---|---|---|
|
||||
| `0x200` | CTRL | bit 0 启动，bit 1 跳过结果写回 |
|
||||
| `0x204` | STATUS | bit 0 busy，bit 1 done；done 为 W1C |
|
||||
| `0x208` | SRC_BASE | 第一组 A/B 的物理地址 |
|
||||
| `0x20c` | DST_BASE | 第一组 C 的物理地址 |
|
||||
| `0x210` | GROUPS | 任务组数 |
|
||||
| `0x214` | MAT_BASE | 软件兼容字段，当前直接 endpoint 路径不使用 |
|
||||
| `0x218` | SRC_STRIDE | 相邻输入组地址间隔，默认 128 字节 |
|
||||
| `0x21c` | DST_STRIDE | 相邻结果组地址间隔，默认 192 字节 |
|
||||
|
||||
配置寄存器只在序列器空闲时接受写入。启动时模块锁存是否跳过写回，清除旧完成状态，
|
||||
清零矩阵 CRC，并初始化组计数、地址计数和两个 Bank 的占用状态。`GROUPS=0` 不产生计算。
|
||||
|
||||
## 3. 双 Bank 调度模型
|
||||
|
||||
序列器为两个 Bank 分别维护 load active、A/B valid、compute active、store pending 和
|
||||
store active 五类状态。一个 Bank 只有在上述状态均为零时才能接收下一组输入。输入组
|
||||
按组号奇偶映射到 Bank 0/1，并在 `bank_group_idx` 中记录所属组号。
|
||||
|
||||
调度过程包含三个可重叠阶段。装载阶段提交 128 字节 mem2ep 请求；计算阶段在 A/B
|
||||
有效后发出 `mat_start_valid` 和 Bank 号；存储阶段在计算完成后提交 192 字节 ep2mem
|
||||
请求。只要另一 Bank 可用，下一组装载可以与当前组计算或结果写回交叠。
|
||||
|
||||
当两个 Bank 均具备计算条件时，序列器选择组号较小者，保持提交顺序。计算 Bank 被放入
|
||||
两项深度的 `compute_q`，用于把矩阵乘法器的电平 done 事件对应回具体 Bank。done 通过
|
||||
边沿检测转化为单次完成事件，防止电平保持期间重复退休同一任务。
|
||||
|
||||
## 4. 完成与快速路径
|
||||
|
||||
正常模式下，一组任务在结果写回的 B 响应完成后退休。快速模式设置
|
||||
`skip_result_writeback`，计算完成即退休，不再把 192 字节结果写入 ExtRAM。矩阵乘法器
|
||||
在计算结果产生时直接更新整批 CRC32，因此跳过写回不会跳过正确性判定。该模式适用于
|
||||
官方评测只检查最终 CRC、无需读取全部结果矩阵的场景。
|
||||
|
||||
当 `groups_retired` 达到配置组数，且没有活动的装载、计算和存储任务时，序列器清除
|
||||
busy、置位 done 并拉高 `seq_done_irq`。软件通过 STATUS 的 W1C 位确认并清除完成状态。
|
||||
|
||||
## 5. 关键不变量
|
||||
|
||||
同一 Bank 不得同时被装载和计算，也不得在结果尚未消费时覆盖。组号只在输入请求被接受
|
||||
后递增，退休计数只响应写回完成或快速模式下的计算完成。输入和结果地址分别按 stride
|
||||
递增，不从 Bank 号反推地址。CRC 只在整批启动时清零，不在 Bank 切换时清零。
|
||||
|
||||
这些不变量是验证的核心。若仅检查最终 done，无法发现 Bank 覆盖、组号乱序或重复退休。
|
||||
测试平台应同时观察每个 Bank 的状态向量、DMA 请求握手、矩阵 start/done 和退休计数。
|
||||
|
||||
## 6. 当前验证范围
|
||||
|
||||
区域赛证据包含三次 5000 组官方板级运行，三次均收到完成标志并通过 CRC。该结果验证了
|
||||
长序列快速模式的主要数据流，但不等价于覆盖所有边界。模块级回归仍应包含组数 1、2、3，
|
||||
两种写回模式，不同 stride，DMA 读写反压，以及 done W1C 后立即启动下一批等场景。
|
||||
82
doc/reports/system/modules/04_matmul_accelerator.md
Normal file
82
doc/reports/system/modules/04_matmul_accelerator.md
Normal file
@@ -0,0 +1,82 @@
|
||||
# 4x4 矩阵乘法加速器技术说明
|
||||
|
||||
## 1. 计算规格
|
||||
|
||||
`matmul_axi_slave` 计算两个 4x4 无符号整数矩阵的乘积。输入元素宽度为 32 bit，输出
|
||||
元素满足
|
||||
|
||||
`C[i][j] = sum(A[i][k] * B[k][j]), k=0..3`。
|
||||
|
||||
单个乘积为 64 bit，四项相加的最坏情况需要 66 bit，因此结果存储宽度固定为 66 bit。
|
||||
每个输出元素通过三个 32 位字传输：低 32 位、高 32 位以及最高 2 位。该布局使 AXI 和
|
||||
DMA 数据宽度保持 32 bit，同时不截断数学结果。
|
||||
|
||||
## 2. 接口组成
|
||||
|
||||
模块同时提供完整 AXI4 从接口、本地 DMA endpoint 和矩阵序列器直连控制接口。AXI
|
||||
接口支持 INCR burst，可由 CPU 或普通 DMA 访问控制寄存器及双 Bank 数据窗口。本地
|
||||
endpoint 直接接收 A/B 字或输出 C 字，不经过 Crossbar 的矩阵从端。序列器通过
|
||||
`mat_start_valid`、`mat_start_bank`、`mat_done_clear` 和 `mat_crc_clear` 完成批处理控制。
|
||||
|
||||
矩阵 AXI 从端、endpoint、乘法流水线和 CRC 均使用 `sys_clk/sys_resetn`。DMA 和序列器也
|
||||
位于 SYS 域，三者之间没有 CDC。CPU 发起的矩阵访问在 Crossbar 之前已经跨入 SYS 域。
|
||||
`matmul_intr` 产生于 SYS 域，接入 CPU 前的时钟边界见独立时钟域说明。
|
||||
|
||||
两个 endpoint ready 在当前实现中恒为 1，表示矩阵本地缓冲不施加反压。上游仍必须只在
|
||||
目标 Bank 空闲时写入，Bank 所有权由批处理序列器保证，而不是由加速器内部检查。
|
||||
|
||||
## 3. 寄存器与双 Bank 布局
|
||||
|
||||
| 偏移 | 内容 | 说明 |
|
||||
|---|---|---|
|
||||
| `0x000` | CTRL | bit 0 请求 Bank 0，bit 1 请求 Bank 1 |
|
||||
| `0x004` | STATUS | busy、done、error；done/error 支持 W1C |
|
||||
| `0x010` | CRC32 | 返回 `crc_reg XOR 0xffff_ffff`；写入用于清零 CRC |
|
||||
| `0x100` | Bank 0 A | 16 个 32 位元素 |
|
||||
| `0x140` | Bank 0 B | 16 个 32 位元素 |
|
||||
| `0x180` | Bank 0 C | 16 个 66 位元素，共 48 个 32 位字 |
|
||||
| `0x300` | Bank 1 A | 16 个 32 位元素 |
|
||||
| `0x340` | Bank 1 B | 16 个 32 位元素 |
|
||||
| `0x380` | Bank 1 C | 16 个 66 位元素，共 48 个 32 位字 |
|
||||
|
||||
A 和 B 均按行优先方式存储。endpoint 写地址 0--15 对应 A，16--31 对应 B；endpoint
|
||||
读地址 0--47 对应 C 的三字布局。双 Bank 允许一组数据计算时准备另一组，但计算核心
|
||||
本身一次只处理一个 Bank。
|
||||
|
||||
## 4. 乘法数据通路
|
||||
|
||||
核心包含四个 `pipelined_mult_32x32` 实例，并使用 `use_dsp="no"` 属性约束综合器将乘法
|
||||
映射到 LUT 逻辑。每个乘法器包含输入寄存、乘积寄存和输出寄存三个流水级，吞吐率为
|
||||
每周期一个乘积。
|
||||
|
||||
计算核心每周期选择一个输出元素 `(i,j)`，同时向四个乘法器发出
|
||||
`A[i][0..3]` 与 `B[0..3][j]`。流水线对齐后，四个 64 位乘积采用成对加法生成一个
|
||||
66 位结果。16 个输出元素连续发射，索引和 Bank 标识经过四级有效流水线与乘积对齐。
|
||||
因此稳态吞吐为每周期一个 C 元素，而不是逐项乘加的四周期结构。
|
||||
|
||||
当 Bank 0 完成且 Bank 1 已有待处理请求时，状态机可直接调用 `start_calc_bank` 切换
|
||||
Bank，不必先返回空闲态。最后一个有效结果写回时产生 `calc_done_pulse`，置位 done 并
|
||||
驱动电平型中断。
|
||||
|
||||
## 5. CRC32 数据通路
|
||||
|
||||
CRC 使用 IEEE 802.3 反射多项式 `0xedb8_8320`，初值为 `0xffff_ffff`，软件读取时执行
|
||||
末尾异或。每个 66 位 C 元素按低 32 位、高 32 位、最高 2 位补零三个字依次进入
|
||||
`crc32_word_next`。CRC 在计算结果有效时更新，与 CPU 或 DMA 是否读取 C 无关。
|
||||
|
||||
这一选择使快速评测可以关闭结果写回，只保留硬件计算与 CRC。CRC 顺序严格跟随输出
|
||||
元素发射顺序；整批任务开始时由序列器清零，Bank 切换和单组完成不会清零。
|
||||
|
||||
## 6. AXI 协议处理
|
||||
|
||||
写通道分别处理 AW、W 和 B 阶段，锁存 ID、burst 类型和起始地址；INCR burst 每次有效
|
||||
W 握手后地址增加 4。读通道锁存 AR 参数并连续产生 R beat，最后一拍置位 RLAST。
|
||||
无效写地址置位 error，响应码当前始终为 OKAY。输出 C 的组合读选择在当前地址上解析
|
||||
元素号和三字片段。
|
||||
|
||||
## 7. 验证要求
|
||||
|
||||
功能验证需要逐元素与 128 bit 或更宽的软件参考模型比较，覆盖全零、全 `0xffff_ffff`、
|
||||
单位矩阵和随机矩阵。协议验证需覆盖 AW/W 分离、R/B 反压、单 beat 与 burst、两个 Bank
|
||||
连续请求和非法地址。CRC 应独立比较完整 192 字节输出序列。当前官方板测只读取最终
|
||||
CRC，证明了长批处理的端到端一致性，但不能替代逐元素和 AXI 边界测试。
|
||||
73
doc/reports/system/modules/05_fft_accelerator.md
Normal file
73
doc/reports/system/modules/05_fft_accelerator.md
Normal file
@@ -0,0 +1,73 @@
|
||||
# 1024 点 FFT 加速器技术说明
|
||||
|
||||
## 1. 模块组成与数值格式
|
||||
|
||||
FFT 加速器由 `fft_controller`、五级 `SdfUnit` 流水、蝶形、延迟反馈存储、旋转因子 ROM
|
||||
和复数乘法器构成。当前配置处理 1024 点复数序列，实部和虚部均为 16 位有符号定点数。
|
||||
AXI 窗口按 32 位字编址，每个字的低 16 位承载一个输入或输出分量，读取时对 16 位结果
|
||||
进行符号扩展。
|
||||
|
||||
FFT 的 AXI 控制器、输入输出 BRAM、SDF 数据通路和完成状态全部工作在
|
||||
`sys_clk/sys_resetn`。DMA 访问 FFT 窗口时不跨域；CPU 请求在到达共享从端前已经通过
|
||||
CPU--SYS AXI CDC。FFT 不使用 `mlkem_clk`，即使两者共享同一外部地址从端。
|
||||
|
||||
顶层 `FFT` 使用 Radix-2^2 单路径延迟反馈架构。五个 `SdfUnit` 的参数 M 依次为 1024、
|
||||
256、64、16 和 4，每级完成两层 radix-2 蝶形并处理相应旋转因子。输入要求按自然顺序
|
||||
连续提供，核心输出为位反转顺序；AXI 控制器在读输出 BRAM 时反转地址位，使软件观察到
|
||||
自然顺序结果。
|
||||
|
||||
## 2. 地址窗口
|
||||
|
||||
FFT 位于共享物理基址 `0x1f40_0000` 的高半区。
|
||||
|
||||
| 偏移 | 内容 | 容量 |
|
||||
|---|---|---|
|
||||
| `0x8000` | 输入实部 | 1024 个 32 位字，低 16 位有效 |
|
||||
| `0x9000` | 输入虚部 | 1024 个 32 位字，低 16 位有效 |
|
||||
| `0xa000` | 输出实部 | 1024 个符号扩展的 32 位字 |
|
||||
| `0xb000` | 输出虚部 | 1024 个符号扩展的 32 位字 |
|
||||
| `0xc000` | CSR | bits 3:0 状态，bits 7:4 控制 |
|
||||
|
||||
CSR 控制 bit 4 为 start，状态 bit 0 为 busy，bit 1 为 done。写 start 同时清除旧 done；
|
||||
计算完成后 done 保持，`fft_finish` 直接反映该状态。输入和输出窗口均支持 AXI INCR
|
||||
burst，因此既可由 CPU 逐字访问，也可由 DMA 批量搬运。
|
||||
|
||||
## 3. 控制状态机
|
||||
|
||||
控制器包含 IDLE、LOAD、WAIT_OUT 和 DONE 四个状态。IDLE 检测 start；LOAD 在 1024 个
|
||||
周期内顺序读取输入实部和虚部 BRAM，并根据 BRAM 读延迟产生对齐的 `di_en`；WAIT_OUT
|
||||
接收 FFT 流水线输出并写入输出 BRAM；收到第 1024 个有效输出后进入 DONE，再返回 IDLE。
|
||||
|
||||
busy 在 LOAD 和 WAIT_OUT 期间有效。输入 BRAM 与输出 BRAM均采用独立读写端口，CPU 或
|
||||
DMA 的窗口访问与计算侧顺序访问通过双端口结构隔离。软件不得在 busy 期间覆盖输入，
|
||||
也不应在 done 前读取尚未完成的输出。
|
||||
|
||||
## 4. SDF 数据通路
|
||||
|
||||
每个 `SdfUnit` 含两级蝶形和两组延迟反馈缓存。计数器决定当前样本进入反馈存储还是参与
|
||||
加减运算。第二级蝶形输出根据当前阶段选择 `1`、`-j` 或 ROM 旋转因子，并通过复数乘法
|
||||
进入下一级。单路径结构每周期只传递一个复数样本，减少并行蝶形和存储端口数量。
|
||||
|
||||
`Butterfly` 对和、差各执行一次算术右移，相邻级使用不同的半舍入偏置以减小累计偏差。
|
||||
五个 SDF 单元合计执行十次除 2，因此总缩放因子为 `1/1024`。软件参考结果同样除以
|
||||
1024 后再与硬件比较。
|
||||
|
||||
复数乘法器计算四个有符号乘积并按 `WIDTH-1` 位右移恢复定点尺度。模块带有
|
||||
`use_dsp="no"` 属性，所有乘法映射到 LUT/CARRY 资源。该约束满足竞赛资源要求，但会
|
||||
增加 LUT 占用和组合路径压力。
|
||||
|
||||
## 5. 软件访问模式
|
||||
|
||||
CPU 路径逐字写入两个输入窗口、启动 FFT、轮询 done，再逐字读回两个输出窗口。DMA
|
||||
路径使用两个 DMA 通道分别搬入实部和虚部，计算完成后再分别搬回输出。CPU 路径测量
|
||||
包含大量寄存器访问，DMA 路径测量包含四次批量搬运和一次计算，二者均属于端到端时间，
|
||||
不能直接解释为纯 FFT 核延迟。
|
||||
|
||||
## 6. 验证与数值误差
|
||||
|
||||
板级程序使用相同的 1024 点多音输入和浮点 radix-2 DIT 软件参考。全部 1024 个点逐点
|
||||
比较，当前三次 CPU 路径和三次 DMA 路径的最大绝对误差均为实部 1、虚部 2，低于阈值
|
||||
8。CPU 路径端到端时间为 1,724,940 ns，DMA 路径为 296,730 ns；三次运行结果一致。
|
||||
|
||||
这些结果证明当前测试向量上的定点误差和数据搬运正确性。进一步验证应增加冲激、单频、
|
||||
满幅随机、接近溢出和复数输入，并检查连续 start、busy 期间非法写入以及 AXI 反压。
|
||||
78
doc/reports/system/modules/06_mlkem_core.md
Normal file
78
doc/reports/system/modules/06_mlkem_core.md
Normal file
@@ -0,0 +1,78 @@
|
||||
# ML-KEM 总控与算法数据通路技术说明
|
||||
|
||||
## 1. 功能范围
|
||||
|
||||
`mlkem_top` 实现 FIPS 203 ML-KEM 的 KeyGen、Encaps 和 Decaps 主数据通路。安全等级由
|
||||
运行时参数 `k_i` 选择：2、3、4 分别对应 ML-KEM-512、768、1024。模数固定为 3329，
|
||||
多项式次数固定为 256，共享密钥长度为 32 字节。模块在 `start_i` 有效时锁存安全等级和
|
||||
操作码，运行期间不再读取外部配置。
|
||||
|
||||
三个等级共享同一比特流。片上存储按最大等级静态分配，循环边界、槽位基址、密钥长度和
|
||||
压缩参数由锁存的 K 动态计算。对应公钥长度为 800、1184、1568 字节，私钥长度为 1632、
|
||||
2400、3168 字节，密文长度为 768、1088、1568 字节。
|
||||
|
||||
## 2. 顶层接口
|
||||
|
||||
配置端口包括 3 位安全等级、2 位操作码和单拍 start。KeyGen 输入 256 位随机种子 d 和 z；
|
||||
Encaps 输入消息 m，并在启动前通过字节端口装载公钥；Decaps 在启动前通过字节端口装载
|
||||
私钥和密文。`busy_o` 在非 IDLE 状态有效，`done_o` 在 ST_DONE 产生完成脉冲，`ss_o`
|
||||
输出 256 位共享密钥。
|
||||
|
||||
公钥、私钥和密文不使用超宽并行端口，而是通过 8 位写接口和调试读回接口访问内部 BRAM。
|
||||
系统集成层在该字节接口外提供 AXI 寄存器路径和 32 位批量窗口。
|
||||
|
||||
`mlkem_top` 及 Keccak、采样、NTT、多项式运算和局部 BRAM 全部工作在
|
||||
`mlkem_clk/mlkem_resetn`。模块内部算子之间没有 CDC。来自 SYS 域的寄存器和批量窗口
|
||||
事务在进入 `mlkem_axi_slave` 前已通过完整 AXI CDC；完成中断先同步回 SYS 域。
|
||||
|
||||
## 3. 集中式控制状态机
|
||||
|
||||
模块使用 5 位集中式状态机调度算子和存储端口。KeyGen 路径依次执行 G 哈希、SampleNTT
|
||||
生成矩阵、CBD 生成 s/e、前向 NTT、矩阵向量点乘、密钥编码和公钥哈希。各阶段通过
|
||||
系数 BRAM 和字节 BRAM 传递数据，不在阶段之间复制完整多项式总线。
|
||||
|
||||
Encaps 路径首先计算公钥哈希与 `G(m || H(ek))`，随后重新生成转置矩阵，解码公钥 t，
|
||||
采样 y/e1/e2，对 y 执行 NTT，计算 u 和 v，最后按等级参数 `du/dv` 压缩并编码密文。
|
||||
共享密钥为 G 输出的 K 部分。
|
||||
|
||||
Decaps 路径解码并解压密文，解码私钥 s，对 u 执行 NTT，恢复消息 m'，再计算
|
||||
`G(m' || H(ek))` 和 `J(z || c)`。D6 重加密不复制第二套加密硬件，而是把 m' 和 r'
|
||||
送回 Encaps 状态序列生成参考密文 c'。最后状态逐字节比较 c' 与输入 c，并选择正常密钥
|
||||
或隐式拒绝备用密钥。
|
||||
|
||||
比较循环不因首个不匹配字节提前退出，控制路径按完整密文长度运行。该行为是 RTL 的设计
|
||||
属性；当前 regional 板级日志没有专门注入篡改密文，因此现有系统报告不把负向隐式拒绝
|
||||
测试列为已验证结果。
|
||||
|
||||
## 4. 算子复用
|
||||
|
||||
Keccak-f[1600] 是面积最大的算子。SHA3/SHAKE 协议层、SampleNTT 和 CBD 在互斥状态中
|
||||
共享一个 `keccak_core`，输入由状态选择器复用，输出广播给当前活动消费者。NTT、逆 NTT、
|
||||
多项式基乘以及压缩/解压同样按状态复用，而不是为 KeyGen、Encaps 和 Decaps 分别复制。
|
||||
|
||||
该架构降低面积，但限制了状态间并行度。SampleNTT、CBD、NTT 和多项式乘法不能跨主状态
|
||||
重叠，整体延迟由各阶段串行累加。技术报告应将其描述为面积与吞吐之间的明确权衡。
|
||||
|
||||
## 5. 存储组织
|
||||
|
||||
系数数据使用三个主要存储库。`bank_a` 为 12 bit x 4096，存放 A 矩阵及部分临时多项式；
|
||||
`bank_se` 为 12 bit x 2048，存放 s/e、y、u 等向量；`bank_t` 为 12 bit x 1024，存放 t、
|
||||
点乘累加、v 和 w。槽位以 256 个系数为单位，基址由 K、K^2 和当前算法阶段计算。
|
||||
|
||||
字节数据使用独立的 `ek_bram`、`dkp_bram`、`ct_bram` 和 `c_in_bram`。输入密文与重加密
|
||||
产生的参考密文分开存储，使最终比较可以同周期读取两者。Decaps 私钥装载地址还会把
|
||||
`dk_pke`、嵌入的公钥、H(ek) 和 z 分派到不同存储或寄存器。
|
||||
|
||||
## 6. 数值与资源约束
|
||||
|
||||
多项式系数采用 12 位模 q 表示。模乘通过流水化 Barrett 约简实现，相关乘法强制不使用
|
||||
DSP。NTT 使用四路 Banked BRAM 和双蝶形流水，点乘使用独立偶/奇 Bank。当前实现中
|
||||
ML-KEM 计算域目标频率为 76.923 MHz，最终时序结论以布局布线报告为准。
|
||||
|
||||
## 7. 验证边界
|
||||
|
||||
叶子算子应分别与软件或 Python 参考模型比较；顶层应按 FIPS 203 KAT 对公钥、私钥、
|
||||
密文和共享密钥逐字节比较；系统级还需验证 CPU 寄存器路径和 DMA 窗口路径。当前板级
|
||||
证据由 ML-KEM-512、768、1024 三个独立编译程序组成，每个程序对软件、CPU 和 DMA
|
||||
路径各执行 100 次，现有日志的 FAILS 均为 0。该重复次数证明固定向量上的稳定性，不能
|
||||
表述为 900 个不同随机 KAT。
|
||||
74
doc/reports/system/modules/07_mlkem_axi_frontend.md
Normal file
74
doc/reports/system/modules/07_mlkem_axi_frontend.md
Normal file
@@ -0,0 +1,74 @@
|
||||
# ML-KEM AXI 前端与跨时钟域技术说明
|
||||
|
||||
## 1. 共享从端结构
|
||||
|
||||
`fft_mlkem_axi_slave` 将 Crossbar Slave 6 分成 FFT 和 ML-KEM 两个内部目标。写地址或读
|
||||
地址的 bits 15:12 小于等于 3 时选择 ML-KEM；FFT 使用 0x8000--0xc000 窗口。ML-KEM
|
||||
以外且未被 FFT 定义的地址仍会路由到 FFT 前端，但返回零或忽略写入，因此软件只应使用
|
||||
文档化区间。
|
||||
|
||||
AXI 写地址和写数据通道彼此独立。共享前端在 AW 握手时锁存 `write_sel`，直到对应 B
|
||||
响应完成才释放；读路径在 AR 握手时锁存 `read_sel`，直到带 RLAST 的最后一个 R beat
|
||||
完成才释放。响应选择不使用实时地址，避免 burst 期间地址变化导致响应串到另一个内部
|
||||
从端。
|
||||
|
||||
FFT 控制器直接工作在 `sys_clk`。ML-KEM 的完整 AXI 五通道通过 `Axi_CDC` 跨入
|
||||
`mlkem_clk`，之后由 `mlkem_axi_slave` 和 `mlkem_top` 在同一计算时钟域处理。ML-KEM
|
||||
中断从计算域返回系统域时经过两级同步寄存器。
|
||||
|
||||
XDC 将 SYS 与 ML-KEM 声明为异步时钟组，因此跨域有效性由 `Axi_CDC` 的双时钟 FIFO
|
||||
保证，而不是由 PLL 同源关系或普通时序路径保证。具体约束和复位关系见
|
||||
[时钟域、复位与跨时钟域设计说明](00_clock_domains.md)。
|
||||
|
||||
## 2. ML-KEM 寄存器接口
|
||||
|
||||
ML-KEM 物理基址为 `0x1f40_0000`，CPU 未缓存映射为 `0xbf40_0000`。
|
||||
|
||||
| 偏移 | 名称 | 说明 |
|
||||
|---|---|---|
|
||||
| `0x000` | CTRL | bit 0 启动，bit 1 软复位 |
|
||||
| `0x004` | STATUS | bit 0 busy，bit 1 done，bit 2 preload busy；done 为 W1C |
|
||||
| `0x008` | CONFIG | bits 2:0 为 K，bits 5:4 为操作码 |
|
||||
| `0x010--0x02c` | D | 32 字节 KeyGen 随机种子 |
|
||||
| `0x030--0x04c` | Z | 32 字节隐式拒绝种子 |
|
||||
| `0x050--0x06c` | MSG | 32 字节 Encaps 消息 |
|
||||
| `0x070--0x08c` | SS | 32 字节共享密钥，只读 |
|
||||
| `0x100/104/108` | PRE_SEL/ADR/DAT | 逐字节预装载接口 |
|
||||
| `0x10c/110/114` | RDB_SEL/ADR/DAT | 逐字节读回接口 |
|
||||
| `0x1000` | EK window | 公钥批量输入或输出窗口 |
|
||||
| `0x2000` | DK window | 私钥批量输入或输出窗口 |
|
||||
| `0x3000` | CT window | 密文批量输入或输出窗口 |
|
||||
|
||||
CONFIG 的操作码 0、1、2 分别表示 KeyGen、Encaps、Decaps。软件必须在启动前完成参数与
|
||||
输入装载，并在 busy 期间保持配置不变。done 保持到软件 W1C，便于轮询程序不丢失短脉冲。
|
||||
|
||||
## 3. 字节端口与批量窗口
|
||||
|
||||
传统 PRE 接口通过 PRE_SEL 选择 ek、dk 或 c，通过 PRE_ADR 设置字节地址，向 PRE_DAT
|
||||
写入低 8 位并自动递增地址。读回接口以同样方式选择 ek、完整 dk 或 ct。该路径便于调试，
|
||||
但每个字节至少需要一次 AXI 寄存器事务，传输大密钥时开销较高。
|
||||
|
||||
三个批量窗口把 AXI 32 位 beat 分解为最多四个有效字节。写状态机依据 WSTRB 跳过无效
|
||||
lane，将字节地址、选择和数据送入核心 BRAM 写口，并等待内部确认后继续下一个 lane。
|
||||
读状态机按字节地址读取内部 BRAM，补偿同步读延迟后组装 32 位 RDATA。窗口支持 INCR
|
||||
burst，使通用 DMA 能以少量控制事务搬运完整公钥、私钥和密文。
|
||||
|
||||
批量窗口不改变密码核心的算法执行时间，但显著减少 CPU 逐字节访问开销。性能报告应把
|
||||
CPU 寄存器路径和 DMA 窗口路径分别列出，不能把两者差值解释为核心计算加速。
|
||||
|
||||
## 4. 事件控制与复位
|
||||
|
||||
CTRL start、软复位和 done clear 在 `mlkem_axi_slave` 中均转换为 toggle 事件，再通过
|
||||
边沿检测产生单拍控制。软复位事件经计数器展宽，形成核心局部复位。预装载写入使用
|
||||
request/ack toggle，使 AXI 写 beat 只有在目标字节被核心侧接收后才完成。
|
||||
|
||||
外层 `Axi_CDC` 已承担 SYS--ML-KEM 的 AXI 通道跨域；前端内部的 toggle 机制主要用于
|
||||
把寄存器写动作转换为不会重复触发的单拍事件，并串行化字节预装载。系统复位有效期间，
|
||||
所有 AXI valid、start 和预装载事件必须保持无效。
|
||||
|
||||
## 5. 协议验证重点
|
||||
|
||||
共享前端需要覆盖 AW 与 W 不同拍到达、B/R 反压、ML-KEM 与 FFT 交替访问、长 burst
|
||||
末拍、WSTRB 空洞以及读写并发。ML-KEM 窗口还需验证 800--3168 字节的非统一长度、最后
|
||||
一个不满字、BRAM 读延迟和软复位中止。当前板级 CPU 与 DMA 双路径证明了常用顺序访问，
|
||||
但不等价于覆盖所有并发和异常协议组合。
|
||||
62
doc/reports/system/modules/08_mlkem_hash_sampling.md
Normal file
62
doc/reports/system/modules/08_mlkem_hash_sampling.md
Normal file
@@ -0,0 +1,62 @@
|
||||
# ML-KEM Keccak、SHA3 与采样模块技术说明
|
||||
|
||||
## 1. Keccak-f[1600] 置换核
|
||||
|
||||
`keccak_core` 保存 1600 位状态，并调用组合 `keccak_round` 每周期执行一轮
|
||||
Keccak-f[1600]。轮函数包含 theta、rho、pi、chi 和 iota 五个步骤，轮常数由 5 位轮计数
|
||||
选择。默认执行 24 轮，输入在 `valid_i && ready_o` 时装载，最后一轮结果通过
|
||||
`valid_o/ready_i` 交付；接收端反压时保持最终状态。
|
||||
|
||||
该结构只实例化一份 1600 位轮函数，单次置换约需 24 个计算周期，面积主要来自宽 XOR、
|
||||
移位布线和 chi 非线性逻辑。它不是 24 轮完全展开的单周期实现，也不是每周期接收一个
|
||||
新状态的深流水实现。
|
||||
|
||||
本文件中的 Keccak、SHA3/SHAKE、SampleNTT 和 CBD 均位于 `mlkem_clk` 域。共享接口是
|
||||
同一时钟域内的 valid/ready 复用，不是 CDC。SYS--ML-KEM 跨域终止于外层 AXI 前端。
|
||||
|
||||
## 2. SHA3/SHAKE 协议层
|
||||
|
||||
`sha3_top_shared` 在置换核外实现吸收、填充、多块状态累积和输出提取。单块模式支持
|
||||
KeyGen 使用的 G、SHA3-256 H、SHAKE-256 J，以及对完整 64 字节消息执行的 SHA3-512 G。
|
||||
模块依据模式选择 576 位或 1088 位 rate，并加入 SHA3 或 SHAKE 域分隔后执行 pad10*1。
|
||||
|
||||
多块模式面向长度随安全等级变化的公钥哈希。调用方预先构造 1088 位 rate block，并用
|
||||
`mb_last_i` 标记最终块。模块将新块异或到累计 sponge 状态，调用共享 Keccak，最后从
|
||||
低 256 位提取摘要。多块状态在一次消息结束前保持，不会在块间重新初始化。
|
||||
|
||||
ML-KEM 顶层以状态机选择当前 Keccak 消费者。SHA3、SampleNTT 和 CBD 在算法调度上互斥，
|
||||
因此可以共享一个置换核；若未来引入跨状态并行，必须增加显式仲裁和每个消费者独立的
|
||||
sponge 上下文，不能继续依赖状态互斥假设。
|
||||
|
||||
## 3. SampleNTT 拒绝采样
|
||||
|
||||
`sample_ntt_sync_shared` 实现 FIPS 203 SampleNTT。模块吸收 32 字节 rho 以及行列索引
|
||||
`j,i`，形成 34 字节 SHAKE-128 输入。挤出字节流按每 3 字节拆成两个 12 位候选值，只有
|
||||
候选值小于 q=3329 时才输出。模块持续采样直到产生 256 个有效系数。
|
||||
|
||||
输出使用 `coeff_valid_o/coeff_ready_i` 握手，反压时保持当前系数和索引。拒绝采样的运行
|
||||
周期依赖候选值分布，因此系统 FSM 依据有效系数计数结束，而不是使用固定延迟。对固定
|
||||
rho 和索引，输出必须与软件 SampleNTT 逐系数一致。
|
||||
|
||||
## 4. 中心二项分布采样
|
||||
|
||||
`sample_cbd_sync_shared` 使用 SHAKE-256 PRF 生成伪随机字节，再实现 CBD_eta。eta=2 时，
|
||||
每个系数消耗 4 bit，计算两组 2 bit 的汉明重量差；eta=3 时，每个系数消耗 6 bit，计算
|
||||
两组 3 bit 的汉明重量差。ML-KEM-512 的 eta1 为 3，其余等级的 eta1 为 2，eta2 始终为 2。
|
||||
|
||||
CBD 输出转换到模 q 表示后，以 valid/ready 逐系数写入系数 Bank。当前优化版本对 CBD
|
||||
输出到 Bank 写入路径增加寄存，以缩短组合路径；地址和有效信号必须与该流水级同步延迟。
|
||||
|
||||
## 5. 共享接口约束
|
||||
|
||||
三个消费者向共享 Keccak 提供状态、valid 和 ready。选择信号由 ML-KEM 主状态直接推导，
|
||||
未选中的消费者不能认为广播输出属于自己。消费者内部必须只在活动上下文采样
|
||||
`kc_valid_o`。复位需要同时清除 Keccak busy、各 sponge 状态、候选字节缓存和输出计数，
|
||||
否则下一次请求可能继承前一消息状态。
|
||||
|
||||
## 6. 验证方法
|
||||
|
||||
Keccak 应使用标准空消息和多块测试向量逐 bit 比较。SHA3/SHAKE 层应覆盖 rate 边界前后
|
||||
的消息长度、域分隔和多块最后一块填充。SampleNTT 应比较全部 256 个系数并统计拒绝
|
||||
候选数；CBD 应覆盖 eta=2/3、输出反压和连续请求。顶层 KAT 通过能够发现大部分功能错误，
|
||||
但叶子级握手、边界填充和共享仲裁仍需要独立测试平台验证。
|
||||
72
doc/reports/system/modules/09_mlkem_polynomial_arithmetic.md
Normal file
72
doc/reports/system/modules/09_mlkem_polynomial_arithmetic.md
Normal file
@@ -0,0 +1,72 @@
|
||||
# ML-KEM 多项式运算模块技术说明
|
||||
|
||||
## 1. 运算域与数据表示
|
||||
|
||||
多项式运算位于环 `Z_q[x]/(x^256+1)`，其中 q=3329。系数在硬件中使用 12 位无符号模 q
|
||||
表示。该组模块包括前向/逆向 NTT、Barrett 模乘、NTT 域 basecase 乘法、多项式加减以及
|
||||
Compress/Decompress。算子使用 valid/ready 或 start/done 接口，由 `mlkem_top` 分时复用。
|
||||
|
||||
本文件中的 NTT、模乘、basecase、多项式加减、压缩模块及其局部 BRAM 均工作在
|
||||
`mlkem_clk/mlkem_resetn`。算子与 `mlkem_top` 之间是单时钟域同步接口，不包含独立 CDC。
|
||||
地址、valid 和数据的延迟对齐属于流水线时序问题，而不是跨时钟域问题。
|
||||
|
||||
## 2. NTT 核
|
||||
|
||||
`ntt_core` 实现 256 点前向和逆向 NTT。系数存储由 `coeff_bram_4way` 划分为四个 Bank，
|
||||
每个 Bank 具有同步读和写端口。地址生成器把同周期的两个蝶形对映射到互不冲突的 Bank，
|
||||
从而同时处理四个系数。
|
||||
|
||||
数据通路包含两个 `butterfly_unit_pipe`。第 t 周期发出 BRAM 地址，下一周期取得系数，
|
||||
随后进入流水化蝶形和 Barrett 模乘；写地址通过同长度延迟链与结果对齐。每层发射结束后
|
||||
等待流水排空，再更新层号和旋转因子索引。逆 NTT 在七层变换后复用模乘流水线执行末尾
|
||||
缩放。
|
||||
|
||||
`zeta_rom` 保存 128 个 12 位旋转因子。前向和逆向变换使用不同的索引方向及蝶形公式。
|
||||
验证不能只比较 NTT 后的频域值，还应执行 INTT(NTT(a)) 并检查恢复系数，覆盖 Bank 地址
|
||||
冲突和最后一层流水排空。
|
||||
|
||||
## 3. Barrett 模约简与蝶形
|
||||
|
||||
`barrett_mul_pipe` 先计算 12x12 位乘积，再用常数 5039 估计除以 q 的商，计算
|
||||
`r = p - q_est*q`，最后通过条件减 q 把结果限制到 `[0,q)`。各乘法级之间加入寄存器，
|
||||
并以 `use_dsp="no"` 约束映射到 LUT。蝶形单元在模乘前后执行模加或模减，并将 valid
|
||||
沿流水线传递。
|
||||
|
||||
商估计只在限定输入范围内成立，因此上游必须保证输入系数已经规范化。叶子测试应覆盖
|
||||
0、q-1、乘积最大值和所有修正分支，不能仅使用随机中间值。
|
||||
|
||||
## 4. NTT 域多项式乘法
|
||||
|
||||
`poly_mul_sync` 对 256 个频域系数按相邻偶/奇系数组成 128 个 basecase。每个 basecase
|
||||
结合对应 zeta 计算两个输出系数。输入多项式写入独立 Bank，控制器按 LOAD、RUN 和
|
||||
OUTPUT 阶段管理装载、流水计算和结果输出。
|
||||
|
||||
`basecase_mul_pipe` 并行计算多个模乘项，再完成模加。当前版本将系数存储改为偶/奇
|
||||
Banked BRAM，减少离散寄存器和 LUTRAM。受同步 BRAM 读延迟和发射控制影响，RUN 阶段
|
||||
每两周期发射一个 basecase。输出采用 valid/ready，接收端反压时不得覆盖尚未消费的系数。
|
||||
|
||||
`poly_arith_sync` 提供系数级模加和模减，用于点乘累加、噪声相加以及解封装中的差值。
|
||||
运算结果在每一步规范化到模 q 范围，避免后续模乘输入超界。
|
||||
|
||||
## 5. 压缩与解压缩
|
||||
|
||||
`comp_decomp_sync` 实现 FIPS 203 的 Compress_d 和 Decompress_d。压缩近似计算
|
||||
`round(2^d*x/q) mod 2^d`，解压计算 `round(q*y/2^d)`。当前流水线使用常数乘法和移位
|
||||
近似除法，避免综合组合除法器；模式、d 和 valid 随数据经过各级寄存。
|
||||
|
||||
输出端具有保持寄存器。当下游未 ready 时，结果和 valid 保持；输入 ready 由流水线及
|
||||
输出可用性共同决定，因此文档和测试不应假设任意反压下始终每周期接收一个系数。需要
|
||||
分别覆盖 d=1、4、5、10、11 等算法实际参数，并与精确整数公式逐值比较。
|
||||
|
||||
## 6. 存储和调度约束
|
||||
|
||||
NTT 核和多项式乘法器各自包含局部 BRAM，ML-KEM 顶层还包含全局系数 Bank。进入算子前
|
||||
需要将目标多项式装入局部存储，完成后再流式写回全局 Bank。这种结构简化端口仲裁，但
|
||||
增加装载和回写周期。主 FSM 保证同一全局 Bank 端口在一个状态内只有一个所有者。
|
||||
|
||||
## 7. 验证边界
|
||||
|
||||
叶子级验证应覆盖 NTT、INTT、basecase、完整多项式乘法、模加减和压缩解压，并对所有
|
||||
256 个系数比较。顶层 KAT 能验证算子组合后的算法结果，但当多个误差互相抵消时不能定位
|
||||
根因。实现后还需检查 BRAM 推断、DSP=0 和 valid/地址延迟对齐；这些属于结构验证，不能
|
||||
仅由软件结果正确推出。
|
||||
74
doc/reports/system/modules/10_software_runtime.md
Normal file
74
doc/reports/system/modules/10_software_runtime.md
Normal file
@@ -0,0 +1,74 @@
|
||||
# 软件运行时与测试程序技术说明
|
||||
|
||||
## 1. 软件职责
|
||||
|
||||
软件位于 `sdk/software/examples/`，负责构造输入、配置物理地址和寄存器、启动硬件、等待
|
||||
完成、读取结果并与参考值比较。算法的高开销数据通路由硬件完成；软件保留参考实现和
|
||||
诊断输出，用于区分计算错误、数据搬运错误和接口错误。
|
||||
|
||||
CPU 访问外设时使用 `0xbfxx_xxxx` 未缓存映射，DMA 描述符使用 `0x1xxx_xxxx` 物理地址。
|
||||
软件缓冲区通过未缓存别名读写，避免数据缓存中的旧副本与 DMA 结果不一致。该地址转换是
|
||||
驱动正确性的一部分，而不是性能优化细节。
|
||||
|
||||
软件指令在 `cpu_clk` 域执行，外设寄存器和 DMA 数据面主要位于 `sys_clk` 域，ML-KEM
|
||||
核心位于 `mlkem_clk` 域。软件不直接处理相位关系，而是通过 AXI valid/ready、状态保持
|
||||
和 W1C 完成语义与异步硬件交互。CPU 周期计数包含跨域 FIFO 和外设响应延迟。
|
||||
|
||||
## 2. DMA 驱动
|
||||
|
||||
`dma.c/dma.h` 将通道寄存器映射为 C 结构体。驱动先检查 busy，再写源地址、目的地址、
|
||||
字节数和 tag，配置 32 位 beat 与 burst 长度后置位 start。`dma_wait_polling` 轮询 done，
|
||||
完成后通过 W1C 清除状态。
|
||||
|
||||
FFT 驱动使用 AxLEN=15，即 16 beat burst；矩阵快速路径使用 AxLEN=63，即 64 beat 配置。
|
||||
实际末 burst 长度由硬件按剩余字节裁剪。当前驱动遇到通道 busy 时直接返回，没有错误码；
|
||||
轮询也没有软件超时。因此调用方必须保证通道所有权，正式运行时应增加返回值和超时处理。
|
||||
|
||||
## 3. 矩阵乘法评测程序
|
||||
|
||||
`asm/user-sample.c` 面向官方 5000 组评测。程序配置矩阵批处理序列器的源地址、目的地址、
|
||||
组数和 stride，发送 `MATMUL_START`，启动硬件并轮询序列器 done。完成后读取矩阵加速器
|
||||
CRC32，并以紧凑 UART 写入输出 CRC 和 `MATMUL_DONE`。
|
||||
|
||||
快速启动配置使用 `start_matmul_fast.S` 缩短通用 C 运行时初始化。UART 输出避免 `printf`
|
||||
格式化开销，并按 FIFO 可用状态分段写入。设置 `MATMUL_WRITEBACK_RESULTS=0` 时，序列器
|
||||
跳过 5000 组结果写回，但矩阵核心仍对全部 66 位结果更新 CRC。
|
||||
|
||||
官方计时从接收到 START 到接收到 DONE，因此软件启动顺序、串口发送和完成尾部均会进入
|
||||
端到端时间。当前 regional 证据包含三次运行，中位数为 6.944404 ms，CRC 均匹配。该数据
|
||||
不包含 `test_1` 中的后续优化。
|
||||
|
||||
## 4. FFT 测试程序
|
||||
|
||||
`fft/main.c` 通过 CPU 逐字写入 1024 个实部和虚部，启动 FFT，读回全部输出，再执行浮点
|
||||
radix-2 DIT 软件参考。`fft_dma/main.c` 使用两个 DMA 通道搬入输入，计算完成后搬回输出。
|
||||
两者都对 1024 个 bin 计算最大实部和虚部绝对误差，并以阈值 8 判定。
|
||||
|
||||
软件参考结果除以 1024，与硬件每级缩放后的输出尺度一致。当前 CPU 和 DMA 路径各有三份
|
||||
板级日志，结果完全一致。硬件时间为端到端测量，CPU 路径包含 4096 次窗口读写，DMA
|
||||
路径包含四次搬运，因此两者反映接口方案而非单独的 FFT 流水线周期。
|
||||
|
||||
## 5. ML-KEM 测试程序
|
||||
|
||||
`mlkem_test/main.c` 为每个安全等级分别构建和运行。当前源码通过 `LEVELS` 数组选择本次
|
||||
编译的 K，区域赛证据中的 512、768、1024 来自三个独立程序，不是一个程序内并行执行。
|
||||
每个程序使用固定 KAT count 0 输入，分别运行软件参考、CPU 寄存器路径和 DMA 窗口路径。
|
||||
|
||||
CPU 路径通过 PRE/RDB 接口逐字节装载和读取密钥、密文；DMA 路径通过 EK、DK、CT
|
||||
窗口批量搬运。两条硬件路径均执行 KeyGen、Encaps 和 Decaps，并检查封装/解封共享密钥
|
||||
一致性以及固定黄金值。每条路径重复 100 次，记录失败次数和平均 CPU 周期。
|
||||
|
||||
现有测试的重复输入用于稳定性和性能统计，不代表不同随机 KAT。程序未篡改密文触发负向
|
||||
隐式拒绝，因此报告只能说明正常输入路径通过，不能把 RTL 中存在的拒绝逻辑表述为已完成
|
||||
板级负向测试。
|
||||
|
||||
## 6. 构建与证据输出
|
||||
|
||||
报告工作流只编译 `asm`、`fft`、`fft_dma`、`mlkem_test` 和 `mlkem_hello`。FFT 与
|
||||
ML-KEM 的通用 SoC 软件仿真耗时较长，当前功能数据采用板级 UART 日志。日志使用固定
|
||||
机器可读字段，例如 `FFT_RESULT`、`MLKEM*_FAILS`、平均周期和完成标志，指标脚本从这些
|
||||
字段聚合报告数据。
|
||||
|
||||
软件测试的通过条件包括算法结果、DMA 完成和输出标记，不能只依据程序返回。后续改动
|
||||
寄存器布局、缓存属性、时钟频率或 UART 输出顺序时，必须同步更新驱动、测试判定和指标
|
||||
解析脚本。
|
||||
48
doc/reports/system/modules/README.md
Normal file
48
doc/reports/system/modules/README.md
Normal file
@@ -0,0 +1,48 @@
|
||||
# 自研模块技术说明索引
|
||||
|
||||
本目录记录区域赛仓库中由项目组设计、修改或完成系统级集成的模块。技术说明以当前
|
||||
`main` 分支 RTL 和软件源码为依据，服务于系统设计报告的后续重写。文档中的“已实现”
|
||||
表示源码中存在相应数据通路或控制逻辑；“已验证”仅指当前 `evidence/` 中能够直接支持
|
||||
的结论，两者不混用。
|
||||
|
||||
OpenLA500 处理器、UART、DVI、基础 SRAM 控制器以及赛事提供的 SoC 框架不作为自研 IP
|
||||
列入。项目组对这些模块的地址连接、时钟连接和中断集成记录在 SoC 集成说明中，但不把
|
||||
其内部实现归入项目贡献。
|
||||
|
||||
| 文档 | 主要 RTL 或软件 | 技术边界 |
|
||||
|---|---|---|
|
||||
| [时钟域、复位与 CDC](00_clock_domains.md) | `clk_pll`、`rst_sync`、`Axi_CDC`、`soc.xdc` | 三时钟域归属、复位链、跨域协议和约束模型 |
|
||||
| [SoC 集成与时钟复位](01_soc_integration.md) | `rtl/soc_top.v`、`rst_sync.v` | 地址空间、主从互连、时钟域、复位和中断集成 |
|
||||
| [通用 DMA 子系统](02_dma_subsystem.md) | `rtl/ip/cdma/snix_*.sv` | 四通道 DMA、AXI 搬运、本地 endpoint 和仲裁 |
|
||||
| [矩阵批处理序列器](03_matmul_batch_sequencer.md) | `cdma_matmul_bridge.sv` | 5000 组任务调度、双 Bank 流水和可选结果写回 |
|
||||
| [矩阵乘法加速器](04_matmul_accelerator.md) | `matmul_axi_slave.v` | 4x4 无符号矩阵乘法、AXI/endpoint、CRC32 |
|
||||
| [FFT 加速器](05_fft_accelerator.md) | `rtl/ip/fft/*.v` | 1024 点定点 FFT、SDF 数据通路和 AXI 存储窗口 |
|
||||
| [ML-KEM 总控与算法数据通路](06_mlkem_core.md) | `mlkem_top.v` | 三等级、三操作、集中式 FSM 和片上存储组织 |
|
||||
| [ML-KEM AXI 前端与 CDC](07_mlkem_axi_frontend.md) | `fft_mlkem_axi_slave.v`、`mlkem_axi_slave.v` | 共享地址窗口、批量数据窗口和跨时钟域握手 |
|
||||
| [Keccak 与采样模块](08_mlkem_hash_sampling.md) | `sha3/`、`sample_ntt/`、`sample_cbd/` | SHA3/SHAKE、拒绝采样和 CBD 采样 |
|
||||
| [多项式运算模块](09_mlkem_polynomial_arithmetic.md) | `ntt/`、`poly_mul/`、`comp_decomp/` | NTT、基乘、模约简、压缩与解压缩 |
|
||||
| [软件运行时与测试程序](10_software_runtime.md) | `sdk/software/examples/{asm,fft,fft_dma,mlkem_test}` | 寄存器驱动、DMA 调度、参考模型和结果判定 |
|
||||
|
||||
文档中的地址均为物理地址，除非明确写为 CPU 未缓存虚拟地址。AXI 信号名沿用 RTL，
|
||||
寄存器偏移以字节为单位。频率和资源数据属于当前 regional 仓库，不包含 `test_1` 中的
|
||||
后续矩阵乘法优化。
|
||||
|
||||
## RTL 模块覆盖说明
|
||||
|
||||
当前 SoC 有效层次中的计算和搬运模块均已纳入上述文档。DMA 说明覆盖
|
||||
`snix_axil_cdma_mux`、`snix_axi_mm2mm`、`snix_axis_fifo` 和 `snix_sync_fifo`；矩阵说明
|
||||
覆盖 `matmul_axi_slave`、`pipelined_mult_32x32` 和 `cdma_matmul_bridge`；FFT 说明覆盖
|
||||
`fft_controller`、`FFT`、`SdfUnit`、`Butterfly`、`Multiply`、`DelayBuffer` 和 `Twiddle`。
|
||||
|
||||
ML-KEM 说明覆盖当前集成层次中的 `fft_mlkem_axi_slave`、`mlkem_axi_slave`、
|
||||
`mlkem_top`、`keccak_core`、`keccak_round`、`sha3_top_shared`、
|
||||
`sample_ntt_sync_shared`、`sample_cbd_sync_shared`、`ntt_core`、`coeff_bram_4way`、
|
||||
`butterfly_unit_pipe`、`barrett_mul_pipe`、`poly_mul_sync`、`basecase_mul_pipe`、
|
||||
`poly_arith_sync`、`comp_decomp_sync`、`zeta_rom`、`poly_mul_zeta_rom`、`pipeline_reg`、
|
||||
`skid_buffer`、`sd_bram` 和 `s_bram`。
|
||||
|
||||
仓库还保留 `snix_axi_cdma`、`snix_axi_cdma_csr`、`snix_async_fifo`、
|
||||
`snix_register_slice`，以及非共享版 `sha3_top`、`sample_ntt_sync`、`sample_cbd_sync`、
|
||||
旧版 `ntt_sync`、`butterfly_unit`、`barrett_mul` 和 `basecase_mul`。这些文件用于早期方案、
|
||||
叶子测试或兼容参考，当前 `soc_top`/`mlkem_top` 未实例化，因而不作为独立系统模块另写
|
||||
性能结论。若后续重新接入，应先更新本索引及对应技术说明。
|
||||
54
doc/reports/system/report_metrics.tex
Normal file
54
doc/reports/system/report_metrics.tex
Normal file
@@ -0,0 +1,54 @@
|
||||
% Generated values may be refreshed with: make metrics
|
||||
% Evidence status is intentionally explicit so stale data is not presented as current.
|
||||
\newcommand{\EvidenceRevision}{d456463（当前 evidence）}
|
||||
\newcommand{\EvidenceDate}{2026-07-15}
|
||||
|
||||
\newcommand{\CpuFreqMHz}{33.333}
|
||||
\newcommand{\SysFreqMHz}{50.000}
|
||||
\newcommand{\MlkemFreqMHz}{76.923}
|
||||
\newcommand{\OverallWNS}{0.070}
|
||||
\newcommand{\CpuWNS}{0.737}
|
||||
\newcommand{\SysWNS}{0.125}
|
||||
\newcommand{\MlkemWNS}{0.070}
|
||||
|
||||
\newcommand{\SliceLUTs}{55,066}
|
||||
\newcommand{\SliceLUTPct}{41.16\%}
|
||||
\newcommand{\SliceFFs}{31,000}
|
||||
\newcommand{\SliceFFPct}{11.58\%}
|
||||
\newcommand{\BramTiles}{29.5}
|
||||
\newcommand{\BramPct}{8.08\%}
|
||||
\newcommand{\DspCount}{0}
|
||||
|
||||
\newcommand{\TotalPower}{0.779}
|
||||
\newcommand{\DynamicPower}{0.637}
|
||||
\newcommand{\StaticPower}{0.142}
|
||||
\newcommand{\PowerConfidence}{Low（未回标活动率）}
|
||||
|
||||
\newcommand{\MlkemFiveTwelveSW}{2,592,854}
|
||||
\newcommand{\MlkemFiveTwelveCPU}{198,778}
|
||||
\newcommand{\MlkemFiveTwelveDMA}{52,995}
|
||||
\newcommand{\MlkemSevenSixtyEightSW}{4,064,254}
|
||||
\newcommand{\MlkemSevenSixtyEightCPU}{293,717}
|
||||
\newcommand{\MlkemSevenSixtyEightDMA}{80,643}
|
||||
\newcommand{\MlkemTenTwentyFourSW}{6,036,553}
|
||||
\newcommand{\MlkemTenTwentyFourCPU}{401,177}
|
||||
\newcommand{\MlkemTenTwentyFourDMA}{113,261}
|
||||
|
||||
\newcommand{\FftCpuNs}{1,724,940}
|
||||
\newcommand{\FftDmaNs}{296,730}
|
||||
\newcommand{\FftSoftwareNs}{245,632,500}
|
||||
\newcommand{\FftCpuSpeedup}{142.53}
|
||||
\newcommand{\FftDmaSpeedup}{827.80}
|
||||
\newcommand{\FftMaxError}{Re=1，Im=2}
|
||||
|
||||
\newcommand{\MatmulGroups}{5,000}
|
||||
\newcommand{\MatmulRuns}{3}
|
||||
\newcommand{\MatmulBoardMinMs}{6.936468}
|
||||
\newcommand{\MatmulBoardMs}{6.944404}
|
||||
\newcommand{\MatmulBoardMaxMs}{6.950307}
|
||||
\newcommand{\MatmulScore}{96.54}
|
||||
\newcommand{\MatmulCrcStatus}{PASS}
|
||||
\newcommand{\MatmulFinalMs}{4.911765}
|
||||
\newcommand{\MatmulFinalScore}{100.00}
|
||||
\newcommand{\MatmulFinalSeed}{\texttt{0xa3772ec8}}
|
||||
\newcommand{\MatmulFinalCRC}{\texttt{0x0417d761}}
|
||||
BIN
doc/reports/system/score.png
Normal file
BIN
doc/reports/system/score.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 30 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 1.5 MiB After Width: | Height: | Size: 1.7 MiB |
Binary file not shown.
File diff suppressed because it is too large
Load Diff
7
doc/比赛总结.md
Normal file
7
doc/比赛总结.md
Normal file
@@ -0,0 +1,7 @@
|
||||
这次比赛的结果并不理想——拿了省/分区奖，却没能在国赛的名单里看到自己的队伍，还是觉得非常遗憾。而这也可能是我最后一次作为本科生参加这种级别的大赛了，最后没能画上一个圆满的句号。
|
||||
|
||||
这一路，陪伴我最多的大概是深夜的屏幕。FFT、DMA、4x4矩阵、MLKEM……一行行 RTL 从指间敲出来，仿真跑到凌晨，上板调试翻车了再从头排查，Vivado 的编译进度条不知道看过多少遍。PPT 之外，文档、代码、报告，几乎全是我一个人在撑。本次比赛仍然没能体现团队协作，说不心酸是假的。但那些一个人 debug 到凌晨三点、代码跑通的瞬间，也只有我一个人懂得那份开心。
|
||||
|
||||
还有一件事一直梗在心里：后端报告我给很多人看过，同学、队友，却没有一个人发现里面的时序违例。也许大家都只是匆匆扫一眼，也许根本没人真正在乎细节。如果我早一点自己盯住那条时序路径，结果会不会不一样？可惜没有如果，这条路上真正把它看进眼里的人，始终只有我自己。
|
||||
|
||||
如果还有下次，我想挑战单人参赛，solo一场——输赢都自己扛，赢得坦荡，也输得明白。
|
||||
@@ -68,6 +68,13 @@ def parse_project(xpr: Path) -> Tuple[str, Set[str], Set[str], Set[str]]:
|
||||
if not vlog.is_file():
|
||||
print("Source file", vlog, "does not exist")
|
||||
continue
|
||||
# An expanded XCI may add DCP/VHDL/netlist artifacts to the
|
||||
# project. They are not Verilog lint inputs; use the Verilog
|
||||
# stub and regular RTL sources only.
|
||||
if vlog.suffix.lower() not in (".v", ".sv", ".vh", ".svh", ".h"):
|
||||
continue
|
||||
if vlog.name.lower().endswith(("_sim_netlist.v", "_sim_netlist.sv")):
|
||||
continue
|
||||
vlog_target = target / vlog.relative_to(repo_root)
|
||||
vlog_target.parent.mkdir(exist_ok=True, parents=True)
|
||||
# shutil.copy(vlog, vlog_target)
|
||||
@@ -234,7 +241,7 @@ def run_linter(prjdir: Path, topname: str, headerlist: Set[str], srclist: Set[st
|
||||
incargs = [ '-I' + i for i in inclist]
|
||||
args += incargs
|
||||
args += sorted(headerlist)
|
||||
args += srclist
|
||||
args += sorted(srclist)
|
||||
|
||||
if os.name == "nt":
|
||||
response_args = [str(arg).replace("\\", "/") for arg in args[1:]]
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,39 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
<<<<<<< Updated upstream
|
||||
| Date : Fri Jul 10 04:14:55 2026
|
||||
=======
|
||||
| Date : Sat Jul 11 09:20:56 2026
|
||||
>>>>>>> Stashed changes
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_clock_interaction -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/clock_interaction.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200t-fbg676
|
||||
| Speed File : -1 PRODUCTION 1.23 2018-06-13
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Clock Interaction Report
|
||||
|
||||
Clock Interaction Table
|
||||
-----------------------
|
||||
|
||||
WNS TNS Failing TNS Total WNS Path Clock-Pair Inter-Clock
|
||||
From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints
|
||||
---------------- ---------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- -------------------
|
||||
<<<<<<< Updated upstream
|
||||
cpu_clk cpu_clk rise - rise 1.51 0.00 0 17264 30.32 Clean Timed
|
||||
cpu_clk sys_clk 0 154 Ignored Asynchronous Groups
|
||||
sys_clk cpu_clk 0 59 Ignored Asynchronous Groups
|
||||
sys_clk sys_clk rise - rise 0.15 0.00 0 96069 20.00 Clean Timed
|
||||
=======
|
||||
cpu_clk cpu_clk rise - rise 0.74 0.00 0 17264 30.00 Clean Timed
|
||||
cpu_clk sys_clk 0 162 Ignored Asynchronous Groups
|
||||
mlkem_clk mlkem_clk rise - rise 0.07 0.00 0 48386 13.00 Clean Timed
|
||||
mlkem_clk sys_clk 0 61 Ignored Asynchronous Groups
|
||||
sys_clk cpu_clk 0 59 Ignored Asynchronous Groups
|
||||
sys_clk mlkem_clk 0 112 Ignored Asynchronous Groups
|
||||
sys_clk sys_clk rise - rise 0.12 0.00 0 23193 20.00 Clean Timed
|
||||
>>>>>>> Stashed changes
|
||||
|
||||
|
||||
@@ -1,54 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
<<<<<<< Updated upstream
|
||||
| Date : Fri Jul 10 04:15:40 2026
|
||||
=======
|
||||
| Date : Sat Jul 11 09:21:26 2026
|
||||
>>>>>>> Stashed changes
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_design_analysis -complexity -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/design_analysis_complexity.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200t
|
||||
| Design State : Routed
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report Design Analysis
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Complexity Characteristics (Cells)
|
||||
|
||||
1. Complexity Characteristics (Cells)
|
||||
-------------------------------------
|
||||
|
||||
<<<<<<< Updated upstream
|
||||
+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+--------------+--------------+--------------+------------+-----+------+------+------+
|
||||
| Instance | Module | Rent | Average Fanout | Total Instances | LUT1 | LUT2 | LUT3 | LUT4 | LUT5 | LUT6 | Memory LUT | DSP | RAMB | MUXF | URAM |
|
||||
+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+--------------+--------------+--------------+------------+-----+------+------+------+
|
||||
| (top) | soc_top | 0.31 | 3.78 | 131904 | 802(1.0%) | 9228(11.4%) | 10135(12.5%) | 10316(12.7%) | 12781(15.7%) | 37981(46.7%) | 1175 | 0 | 41 | 6069 | 0 |
|
||||
| u_axi_axil_adapter | axi_axil_adapter | 0.37 | 4.65 | 1624 | 0(0.0%) | 25(1.8%) | 36(2.6%) | 860(61.8%) | 202(14.5%) | 269(19.3%) | 0 | 0 | 0 | 62 | 0 |
|
||||
| u_axi_uart_controller | axi_uart_controller | 0.55 | 3.54 | 1296 | 10(1.2%) | 84(10.4%) | 80(9.9%) | 144(17.9%) | 194(24.1%) | 293(36.4%) | 0 | 0 | 0 | 9 | 0 |
|
||||
| u_cpu | core_top | 0.59 | 3.96 | 15822 | 168(1.8%) | 579(6.3%) | 1029(11.1%) | 871(9.4%) | 1744(18.9%) | 4860(52.5%) | 0 | 0 | 20 | 276 | 0 |
|
||||
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 0.41 | 3.78 | 87846 | 374(0.7%) | 6103(11.5%) | 7425(14.0%) | 6353(12.0%) | 8174(15.5%) | 24445(46.2%) | 1169 | 0 | 20 | 5269 | 0 |
|
||||
| u_matmul_axi_slave | matmul_axi_slave | 0.60 | 3.76 | 15711 | 18(0.2%) | 1632(14.3%) | 345(3.0%) | 805(7.1%) | 1733(15.2%) | 6875(60.3%) | 6 | 0 | 0 | 417 | 0 |
|
||||
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 0.46 | 3.31 | 3435 | 136(7.4%) | 239(12.9%) | 432(23.4%) | 301(16.3%) | 234(12.6%) | 508(27.5%) | 0 | 0 | 1 | 4 | 0 |
|
||||
+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+--------------+--------------+--------------+------------+-----+------+------+------+
|
||||
=======
|
||||
+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+-------------+-------------+--------------+------------+-----+------+------+------+
|
||||
| Instance | Module | Rent | Average Fanout | Total Instances | LUT1 | LUT2 | LUT3 | LUT4 | LUT5 | LUT6 | Memory LUT | DSP | RAMB | MUXF | URAM |
|
||||
+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+-------------+-------------+--------------+------------+-----+------+------+------+
|
||||
| (top) | soc_top | 0.37 | 3.61 | 102050 | 871(1.4%) | 8543(13.4%) | 10370(16.3%) | 8684(13.7%) | 8274(13.0%) | 26800(42.2%) | 1216 | 0 | 49 | 2433 | 0 |
|
||||
| u_axi_axil_adapter | axi_axil_adapter | 0.43 | 4.86 | 1534 | 0(0.0%) | 28(2.2%) | 37(2.8%) | 763(58.6%) | 216(16.6%) | 258(19.8%) | 0 | 0 | 0 | 62 | 0 |
|
||||
| u_axi_uart_controller | axi_uart_controller | 0.55 | 3.54 | 1296 | 10(1.2%) | 84(10.4%) | 80(9.9%) | 144(17.9%) | 194(24.1%) | 293(36.4%) | 0 | 0 | 0 | 9 | 0 |
|
||||
| u_cpu | core_top | 0.62 | 3.96 | 15822 | 168(1.8%) | 579(6.3%) | 1029(11.1%) | 871(9.4%) | 1744(18.9%) | 4860(52.5%) | 0 | 0 | 20 | 276 | 0 |
|
||||
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 0.35 | 3.49 | 58249 | 424(1.2%) | 5455(15.4%) | 7551(21.3%) | 4691(13.2%) | 4348(12.2%) | 13041(36.7%) | 1210 | 0 | 28 | 1632 | 0 |
|
||||
| u_matmul_axi_slave | matmul_axi_slave | 0.58 | 3.76 | 15281 | 18(0.2%) | 1640(14.9%) | 369(3.4%) | 792(7.2%) | 1009(9.2%) | 7145(65.1%) | 6 | 0 | 0 | 418 | 0 |
|
||||
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 0.41 | 3.25 | 3423 | 136(7.4%) | 183(10.0%) | 430(23.4%) | 401(21.8%) | 243(13.2%) | 445(24.2%) | 0 | 0 | 1 | 4 | 0 |
|
||||
+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+-------------+-------------+--------------+------------+-----+------+------+------+
|
||||
>>>>>>> Stashed changes
|
||||
* Complexity Ranges
|
||||
** 0.0 - 0.3 -> Very Low, 0.3 - 0.5 -> low, 0.5 - 0.65 -> normal, 0.65 - 0.85 -> high, 0.85 - 1.0 -> very high
|
||||
*** -* -> Not computable as cell size is very small
|
||||
|
||||
|
||||
@@ -1,88 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
<<<<<<< Updated upstream
|
||||
| Date : Fri Jul 10 04:15:09 2026
|
||||
=======
|
||||
| Date : Sat Jul 11 09:21:05 2026
|
||||
>>>>>>> Stashed changes
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_design_analysis -timing -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/design_analysis_timing.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200t
|
||||
| Design State : Routed
|
||||
-------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report Design Analysis
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Setup Path Characteristics 1-1
|
||||
|
||||
1. Setup Path Characteristics 1-1
|
||||
---------------------------------
|
||||
|
||||
<<<<<<< Updated upstream
|
||||
+---------------------------+----------------------------------------------------------------------------------------+
|
||||
| Characteristics | Path #1 |
|
||||
+---------------------------+----------------------------------------------------------------------------------------+
|
||||
| Requirement | 20.000 |
|
||||
| Path Delay | 15.529 |
|
||||
| Logic Delay | 6.868(45%) |
|
||||
| Net Delay | 8.661(55%) |
|
||||
| Clock Skew | -3.955 |
|
||||
| Slack | 0.146 |
|
||||
| Clock Relationship | Safely Timed |
|
||||
| Logic Levels | 14 |
|
||||
| Routes | 12 |
|
||||
| Logical Path | FDCE LUT4 LUT5 LUT6 CARRY4 CARRY4 CARRY4 CARRY4 LUT4 CARRY4 CARRY4 LUT6 LUT6 LUT6 OBUF |
|
||||
| Start Point Clock | sys_clk |
|
||||
| End Point Clock | sys_clk |
|
||||
| DSP Block | None |
|
||||
| BRAM | None |
|
||||
| IO Crossings | 3 |
|
||||
| Config Crossings | 0 |
|
||||
| SLR Crossings | 0 |
|
||||
| PBlocks | 0 |
|
||||
| High Fanout | 80 |
|
||||
| Dont Touch | 0 |
|
||||
| Mark Debug | 0 |
|
||||
| Start Point Pin Primitive | FDCE/C |
|
||||
| End Point Pin Primitive | base_ram_be_n[3] |
|
||||
| Start Point Pin | ax_req_q_len_reg[3]/C |
|
||||
| End Point Pin | base_ram_be_n[3] |
|
||||
+---------------------------+----------------------------------------------------------------------------------------+
|
||||
=======
|
||||
+---------------------------+-----------------------+
|
||||
| Characteristics | Path #1 |
|
||||
+---------------------------+-----------------------+
|
||||
| Requirement | 13.000 |
|
||||
| Path Delay | 13.035 |
|
||||
| Logic Delay | 0.752(6%) |
|
||||
| Net Delay | 12.283(94%) |
|
||||
| Clock Skew | 0.135 |
|
||||
| Slack | 0.070 |
|
||||
| Clock Relationship | Safely Timed |
|
||||
| Logic Levels | 1 |
|
||||
| Routes | 1 |
|
||||
| Logical Path | FDRE MUXF7 FDCE |
|
||||
| Start Point Clock | mlkem_clk |
|
||||
| End Point Clock | mlkem_clk |
|
||||
| DSP Block | None |
|
||||
| BRAM | None |
|
||||
| IO Crossings | 0 |
|
||||
| Config Crossings | 0 |
|
||||
| SLR Crossings | 0 |
|
||||
| PBlocks | 0 |
|
||||
| High Fanout | 1088 |
|
||||
| Dont Touch | 0 |
|
||||
| Mark Debug | 0 |
|
||||
| Start Point Pin Primitive | FDRE/C |
|
||||
| End Point Pin Primitive | FDCE/D |
|
||||
| Start Point Pin | dj_wb_inz_reg/C |
|
||||
| End Point Pin | dj_block_r_reg[732]/D |
|
||||
+---------------------------+-----------------------+
|
||||
>>>>>>> Stashed changes
|
||||
* Bounding box calculated as % of dimensions for the target device (436, 500)
|
||||
|
||||
|
||||
@@ -1,406 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
<<<<<<< Updated upstream
|
||||
| Date : Fri Jul 10 04:14:55 2026
|
||||
=======
|
||||
| Date : Sat Jul 11 09:20:57 2026
|
||||
>>>>>>> Stashed changes
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/high_fanout.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200t
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
High Fan-out Nets Information
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+---------------------------------------------------------------------------------------+--------+-------------+
|
||||
| Net Name | Fanout | Driver Type |
|
||||
+---------------------------------------------------------------------------------------+--------+-------------+
|
||||
<<<<<<< Updated upstream
|
||||
| pll_clk.u_clk_pll/inst/sys_clk | 35652 | BUFG |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/delay_reg[1] | 24670 | LUT5 |
|
||||
| pll_clk.u_rst_sys/p_0_in | 5108 | LUT1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[0] | 3758 | FDCE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_0 | 2151 | FDRE |
|
||||
=======
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/delay_reg[1] | 15647 | LUT5 |
|
||||
| pll_clk.u_clk_pll/inst/sys_clk | 9971 | BUFG |
|
||||
| pll_clk.u_rst_sys/p_0_in | 4121 | LUT1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mb_en | 2121 | LUT6 |
|
||||
>>>>>>> Stashed changes
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/E[0] | 2048 | LUT2 |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[0]_0 | 2018 | FDSE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_n_0 | 1619 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 | 1613 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_0[0] | 1608 | LUT2 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sel_cbd | 1603 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 | 1601 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_6_n_0 | 1601 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_7_n_0 | 1601 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 | 1600 | LUT4 |
|
||||
<<<<<<< Updated upstream
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[1] | 1543 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[2] | 1542 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active | 1130 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1 | 1109 | LUT2 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0 | 1088 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0 | 1088 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_mb_en0 | 938 | LUT5 |
|
||||
| u_matmul_axi_slave/w_addr[2] | 873 | FDRE |
|
||||
| u_cpu/reset | 799 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[0] | 769 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[1] | 769 | CARRY4 |
|
||||
| u_cpu/u_mul/E[0] | 716 | LUT1 |
|
||||
| u_matmul_axi_slave/w_addr[4] | 655 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r1 | 525 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[1] | 518 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[0] | 515 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 | 512 | LUT2 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[3]_0[0] | 512 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[2] | 385 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_vld_reg_n_0 | 370 | FDCE |
|
||||
=======
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in | 1344 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1 | 1109 | LUT2 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0 | 1088 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0 | 1088 | FDRE |
|
||||
| pll_clk.u_rst_mlkem/delay_reg[1]_1 | 1066 | LUT1 |
|
||||
| u_cpu/reset | 799 | FDRE |
|
||||
| u_cpu/u_mul/E[0] | 716 | LUT1 |
|
||||
| u_matmul_axi_slave/w_addr[2] | 644 | FDRE |
|
||||
| u_matmul_axi_slave/current_r_offset[2] | 524 | LUT5 |
|
||||
| u_matmul_axi_slave/current_r_offset[3] | 522 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[2]_rep__3[0] | 513 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 | 512 | LUT2 |
|
||||
>>>>>>> Stashed changes
|
||||
| u_cpu/wb_stage/w_index[0] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[1] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[2] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[3] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[4] | 358 | LUT6 |
|
||||
| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 | 357 | LUT3 |
|
||||
| u_matmul_axi_slave/pipe_cnt[3]_i_3_n_0 | 356 | LUT3 |
|
||||
| u_matmul_axi_slave/acc_idx_d4[0] | 354 | FDRE |
|
||||
| u_matmul_axi_slave/acc_idx_d4[1] | 354 | FDRE |
|
||||
| u_matmul_axi_slave/acc_idx_d4[2] | 354 | FDRE |
|
||||
| u_matmul_axi_slave/acc_idx_d4[3] | 354 | FDRE |
|
||||
| u_cpu/wb_stage/we_0 | 324 | LUT4 |
|
||||
<<<<<<< Updated upstream
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1 | 293 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r2[4] | 288 | CARRY4 |
|
||||
| u_matmul_axi_slave/cur_bank_reg_n_0 | 274 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc | 261 | LUT5 |
|
||||
| u_matmul_axi_slave/sel0[1] | 259 | FDRE |
|
||||
| u_matmul_axi_slave/b1_b_reg[0][31]_i_8_n_7 | 258 | CARRY4 |
|
||||
| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0 | 258 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/dj_phase_reg[1]_0[0] | 256 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r | 256 | LUT3 |
|
||||
| u_matmul_axi_slave/m_in_a[3][31]_i_1_n_0 | 256 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode | 250 | LUT4 |
|
||||
| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge | 245 | LUT2 |
|
||||
| u_matmul_axi_slave/b0_a[6][25]_i_2_n_0 | 242 | LUT2 |
|
||||
| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 | 239 | LUT3 |
|
||||
| u_matmul_axi_slave/m_in_a[3][30]_i_6_n_0 | 238 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6] | 237 | FDCE |
|
||||
| u_cpu/exe_stage/ds_to_es_bus_r0 | 234 | LUT5 |
|
||||
| u_cpu/mem_stage/E[0] | 234 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[3] | 231 | FDCE |
|
||||
=======
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1 | 289 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r_reg[255]_i_5_n_4 | 288 | CARRY4 |
|
||||
| u_matmul_axi_slave/w_addr[4] | 286 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc | 260 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/E[0] | 256 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r | 256 | LUT3 |
|
||||
| u_matmul_axi_slave/m_in_a[3][31]_i_1_n_0 | 256 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode | 250 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN_7 | 248 | FDCE |
|
||||
| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge | 245 | LUT3 |
|
||||
| u_cpu/exe_stage/ds_to_es_bus_r0 | 234 | LUT5 |
|
||||
| u_cpu/mem_stage/E[0] | 234 | LUT6 |
|
||||
>>>>>>> Stashed changes
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1022]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[126]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[254]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[382]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[510]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[638]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[766]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[894]_i_2_n_0 | 224 | LUT4 |
|
||||
<<<<<<< Updated upstream
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[5] | 219 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10] | 216 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11] | 216 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8] | 215 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[2] | 215 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7] | 214 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9] | 214 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4] | 214 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0] | 212 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1] | 212 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2] | 212 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3] | 212 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4] | 212 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5] | 212 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6] | 212 | RAMB36E1 |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0 | 211 | LUT2 |
|
||||
| u_cpu/mem_stage/es_to_ms_bus_r0 | 210 | LUT2 |
|
||||
| u_cpu/u_csr/tlbw_r_tlbidx[2] | 210 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[7] | 207 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1] | 206 | FDCE |
|
||||
=======
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN_2 | 222 | FDCE |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0 | 211 | LUT2 |
|
||||
| u_cpu/mem_stage/es_to_ms_bus_r0 | 210 | LUT2 |
|
||||
| u_cpu/u_csr/tlbw_r_tlbidx[2] | 210 | FDRE |
|
||||
>>>>>>> Stashed changes
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/grp_ptr_r_reg_n_0_[2] | 196 | FDCE |
|
||||
| u_cpu/wb_stage/Q[33] | 194 | FDRE |
|
||||
| u_cpu/wb_stage/Q[34] | 194 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[5] | 194 | FDCE |
|
||||
<<<<<<< Updated upstream
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[3] | 193 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg_n_0_[3] | 187 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[2] | 186 | FDCE |
|
||||
| u_cpu/wb_stage/ws_valid_reg_0 | 180 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2] | 180 | FDCE |
|
||||
| u_matmul_axi_slave/b0_b_reg[1][30]_i_4_n_7 | 178 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] | 176 | FDCE |
|
||||
=======
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[2]_rep_n_0 | 191 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_6 | 186 | FDCE |
|
||||
| u_matmul_axi_slave/w_addr[5] | 184 | FDRE |
|
||||
| u_cpu/wb_stage/ws_valid_reg_0 | 180 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_1 | 179 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2] | 178 | FDCE |
|
||||
| u_matmul_axi_slave/b1_b[0][31]_i_7_n_0 | 177 | LUT3 |
|
||||
>>>>>>> Stashed changes
|
||||
| u_matmul_axi_slave/p_0_in__0 | 176 | LUT4 |
|
||||
| u_matmul_axi_slave/p_0_in__0__0 | 176 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt114_out | 175 | LUT2 |
|
||||
| u_cpu/wb_stage/Q[37] | 173 | FDRE |
|
||||
<<<<<<< Updated upstream
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]_rep__0_n_0 | 172 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[131][11]_i_4_n_0 | 171 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[127]_i_2_n_0 | 169 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[383]_i_2_n_0 | 169 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[639]_i_2_n_0 | 169 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[895]_i_2_n_0 | 169 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r2[3] | 169 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[74][11]_i_4_n_0 | 168 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[6]_0[0] | 168 | CARRY4 |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[6]_0 | 167 | LUT2 |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[6]_1 | 167 | LUT2 |
|
||||
| u_snix_axil_cdma_mux_8ch/ADDRA[0] | 167 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[129][11]_i_3_n_0 | 166 | LUT3 |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__0_n_0 | 165 | FDRE |
|
||||
=======
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_2 | 172 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r_reg[255]_i_5_n_5 | 171 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/z_word_reg[1][31]_i_6_n_7 | 170 | CARRY4 |
|
||||
| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0 | 170 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_4 | 168 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/z_word_reg[1][31]_i_6_n_6 | 168 | CARRY4 |
|
||||
>>>>>>> Stashed changes
|
||||
| u_cpu/wb_stage/Q[32] | 164 | FDRE |
|
||||
| u_cpu/wb_stage/Q[35] | 163 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg[0]_rep__0_n_0 | 163 | FDCE |
|
||||
| u_cpu/wb_stage/Q[36] | 162 | FDRE |
|
||||
<<<<<<< Updated upstream
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1023]_i_2_n_0 | 160 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[255]_i_2_n_0 | 160 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[511]_i_2_n_0 | 160 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[767]_i_2_n_0 | 160 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__12_n_0 | 158 | FDCE |
|
||||
| u_matmul_axi_slave/w_addr_reg[3]_rep__2_0 | 158 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[181][5]_i_3_n_0 | 157 | LUT2 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[6] | 156 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3] | 155 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[7] | 155 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[3] | 154 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[4] | 154 | FDCE |
|
||||
| u_matmul_axi_slave/w_addr[3] | 153 | FDRE |
|
||||
=======
|
||||
| u_matmul_axi_slave/pipe_cnt_reg_n_0_[3] | 162 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_0_5_i_34_n_0 | 161 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg_n_0_[3] | 158 | FDRE |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_rd_inst/m_axil_araddr_reg_reg[2]_0 | 157 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3] | 156 | FDCE |
|
||||
| u_matmul_axi_slave/w_addr_reg[3]_rep_n_0 | 153 | FDRE |
|
||||
>>>>>>> Stashed changes
|
||||
| u_cpu/axi_bridge/FSM_sequential_write_requst_state_reg[1]_0 | 151 | FDRE |
|
||||
| u_snix_axil_cdma_mux_8ch/u_core_engine/num_bytes_comb1 | 150 | CARRY4 |
|
||||
| u_cpu/dcache/awaddr[31]_i_3_n_0 | 148 | LUT2 |
|
||||
| u_cpu/dcache/awaddr[31]_i_4_n_0 | 148 | LUT2 |
|
||||
<<<<<<< Updated upstream
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1] | 148 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[202][11]_i_3_n_0 | 148 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0] | 147 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__1_n_0 | 146 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep_n_0 | 146 | FDCE |
|
||||
| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0 | 146 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[0] | 145 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__10_n_0 | 145 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[2] | 144 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/hek_r[247]_i_3_n_0 | 144 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/hek_r[255]_i_3_n_0 | 144 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__17_n_0 | 143 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[106][11]_i_3_n_0 | 143 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6] | 142 | FDCE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[0] | 142 | FDSE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[5] | 141 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[5] | 141 | FDCE |
|
||||
| u_cpu/dcache/write_buffer_state | 140 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4] | 140 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[5] | 140 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[7] | 140 | FDCE |
|
||||
=======
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN | 148 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_10 | 146 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_9 | 143 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] | 142 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_0_5_i_43_n_0 | 141 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_12_17_i_57_n_0 | 141 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[4] | 141 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[5] | 141 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[6] | 141 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[7] | 141 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6] | 141 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[7] | 141 | FDCE |
|
||||
| u_cpu/dcache/write_buffer_state | 140 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4] | 140 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep__3_n_0 | 140 | FDCE |
|
||||
| u_cpu/u_csr/tlbw_r_tlbidx[0] | 139 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[5] | 139 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN_3 | 138 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[3] | 138 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx_reg[6]_rep_n_0 | 138 | FDCE |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[7]_1 | 137 | LUT2 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx_reg[4]_rep_n_0 | 137 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx_reg[5]_rep_n_0 | 137 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg_n_0_[2] | 137 | FDRE |
|
||||
| u_matmul_axi_slave/pipe_cnt_reg[1]_rep_n_0 | 137 | FDRE |
|
||||
| u_cpu/u_csr/tlbw_r_tlbidx[1] | 136 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1080]_i_5_n_0 | 136 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1081]_i_5_n_0 | 136 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1082]_i_5_n_0 | 136 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1083]_i_5_n_0 | 136 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1084]_i_6_n_0 | 136 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1087]_i_3_n_0 | 136 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1087]_i_9_n_0 | 136 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1087]_i_3_n_0 | 136 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx_reg[7]_rep_n_0 | 136 | FDCE |
|
||||
| u_matmul_axi_slave/b1_b[0][31]_i_8_n_0 | 136 | LUT2 |
|
||||
| u_snix_axil_cdma_mux_8ch/ep_rd_elem[0] | 136 | LUT6 |
|
||||
| u_snix_axil_cdma_mux_8ch/ep_rd_elem[1] | 136 | LUT5 |
|
||||
| u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] | 135 | LUT6 |
|
||||
| u_snix_axil_cdma_mux_8ch/ep_rd_elem[3] | 135 | LUT5 |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[6]_0 | 134 | LUT2 |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[7]_0 | 134 | LUT2 |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[7]_2 | 134 | LUT2 |
|
||||
| u_matmul_axi_slave/w_addr[3] | 134 | FDRE |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_rd_inst/s_axil_rdata[29]_i_7_n_0 | 133 | LUT2 |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_rd_inst/s_axil_rdata[29]_i_9_n_0 | 133 | LUT2 |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_rd_inst/s_axil_rdata[31]_i_12_n_0 | 133 | LUT2 |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_rd_inst/s_axil_rdata[31]_i_13_n_0 | 133 | LUT2 |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[3]_0 | 133 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/dbg_dk_idx[4] | 133 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/dbg_dk_idx[3] | 132 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN_4 | 132 | FDCE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[2] | 132 | FDRE |
|
||||
| u_matmul_axi_slave/c1_elem[0] | 132 | LUT6 |
|
||||
| u_matmul_axi_slave/c1_elem[1] | 132 | LUT5 |
|
||||
| u_matmul_axi_slave/c1_elem[2] | 132 | LUT4 |
|
||||
| u_matmul_axi_slave/c1_elem[3] | 132 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep_n_0 | 131 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_reject | 130 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_8 | 130 | FDCE |
|
||||
| u_matmul_axi_slave/pipe_cnt_reg_n_0_[1] | 130 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[1] | 129 | FDRE |
|
||||
| u_confreg/s_rdata[31]_i_8_n_0 | 128 | LUT3 |
|
||||
| u_confreg/s_rdata[31]_i_9_n_0 | 128 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_reject_reg_rep_n_0 | 128 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[0] | 128 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[1] | 128 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[2] | 128 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[4] | 128 | FDCE |
|
||||
| u_matmul_axi_slave/current_r_offset[5] | 128 | LUT3 |
|
||||
| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0 | 128 | FDRE |
|
||||
| u_matmul_axi_slave/pipe_cnt_reg_n_0_[0] | 128 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__0_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__10_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__1_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__2_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__3_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__4_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__5_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__6_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__7_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__8_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__9_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__10_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__11_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__12_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__13_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__2_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__3_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__4_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__5_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__6_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__7_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__8_n_0 | 127 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__9_n_0 | 127 | FDRE |
|
||||
| u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] | 127 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep__0_n_0 | 126 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep__1_n_0 | 126 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep__2_n_0 | 126 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_3 | 126 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/state[1] | 126 | FDCE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__11_0 | 126 | FDRE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__1_n_0 | 126 | FDRE |
|
||||
| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[0] | 126 | FDRE |
|
||||
>>>>>>> Stashed changes
|
||||
+---------------------------------------------------------------------------------------+--------+-------------+
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,28 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 02:57:58 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_clock_interaction -file /home/fallensigh/vivado_reports_withdsp/clock_interaction.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200t-fbg676
|
||||
| Speed File : -1 PRODUCTION 1.23 2018-06-13
|
||||
--------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Clock Interaction Report
|
||||
|
||||
Clock Interaction Table
|
||||
-----------------------
|
||||
|
||||
WNS TNS Failing TNS Total WNS Path Clock-Pair Inter-Clock
|
||||
From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints
|
||||
----------------- ----------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- -------------------
|
||||
cpu_clk cpu_clk rise - rise 1.14 0.00 0 17264 30.32 Clean Timed
|
||||
cpu_clk sys_clk 0 162 Ignored Asynchronous Groups
|
||||
mlkem_clk_clk_pll mlkem_clk_clk_pll rise - rise 12.91 0.00 0 74882 40.00 Clean Timed
|
||||
mlkem_clk_clk_pll sys_clk rise - rise 16.72 0.00 0 61 20.00 Clean Timed
|
||||
sys_clk cpu_clk 0 59 Ignored Asynchronous Groups
|
||||
sys_clk mlkem_clk_clk_pll rise - rise 8.52 0.00 0 112 20.00 Clean Timed
|
||||
sys_clk sys_clk rise - rise 0.42 0.00 0 23732 20.00 Clean Timed
|
||||
|
||||
|
||||
@@ -1,76 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 02:57:58 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_clocks -file /home/fallensigh/vivado_reports_withdsp/clocks.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200t-fbg676
|
||||
| Speed File : -1 PRODUCTION 1.23 2018-06-13
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
Clock Report
|
||||
|
||||
|
||||
Attributes
|
||||
P: Propagated
|
||||
G: Generated
|
||||
A: Auto-derived
|
||||
R: Renamed
|
||||
V: Virtual
|
||||
I: Inverted
|
||||
S: Pin phase-shifted with Latency mode
|
||||
|
||||
Clock Period(ns) Waveform(ns) Attributes Sources
|
||||
clk 20.000 {0.000 10.000} P {clk}
|
||||
clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
|
||||
cpu_clk 30.323 {0.000 15.161} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
|
||||
mlkem_clk_clk_pll 40.000 {0.000 20.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
|
||||
sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
|
||||
|
||||
|
||||
====================================================
|
||||
Generated Clocks
|
||||
====================================================
|
||||
|
||||
Generated Clock : clkfbout_clk_pll
|
||||
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Master Clock : clk
|
||||
Multiply By : 1
|
||||
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
|
||||
|
||||
Generated Clock : cpu_clk
|
||||
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Master Clock : clk
|
||||
Edges : {1 2 3}
|
||||
Edge Shifts(ns) : {0.000 5.161 10.323}
|
||||
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
|
||||
|
||||
Generated Clock : mlkem_clk_clk_pll
|
||||
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Master Clock : clk
|
||||
Edges : {1 2 3}
|
||||
Edge Shifts(ns) : {0.000 10.000 20.000}
|
||||
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
|
||||
|
||||
Generated Clock : sys_clk
|
||||
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Master Clock : clk
|
||||
Multiply By : 1
|
||||
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
|
||||
|
||||
|
||||
|
||||
====================================================
|
||||
User Uncertainty
|
||||
====================================================
|
||||
|
||||
|
||||
|
||||
====================================================
|
||||
User Jitter
|
||||
====================================================
|
||||
|
||||
Clock Jitter(ns)
|
||||
clk 0.200
|
||||
|
||||
@@ -1,37 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 02:58:45 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_design_analysis -complexity -file /home/fallensigh/vivado_reports_withdsp/design_analysis_complexity.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200t
|
||||
| Design State : Routed
|
||||
---------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report Design Analysis
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Complexity Characteristics (Cells)
|
||||
|
||||
1. Complexity Characteristics (Cells)
|
||||
-------------------------------------
|
||||
|
||||
+---------------------------+---------------------+------+----------------+-----------------+-----------+------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
|
||||
| Instance | Module | Rent | Average Fanout | Total Instances | LUT1 | LUT2 | LUT3 | LUT4 | LUT5 | LUT6 | Memory LUT | DSP | RAMB | MUXF | URAM |
|
||||
+---------------------------+---------------------+------+----------------+-----------------+-----------+------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
|
||||
| (top) | soc_top | 0.49 | 3.76 | 108219 | 710(1.2%) | 5229(8.7%) | 8166(13.7%) | 8097(13.5%) | 8459(14.1%) | 29130(48.7%) | 1175 | 56 | 39 | 6074 | 0 |
|
||||
| u_axi_axil_adapter | axi_axil_adapter | 0.50 | 5.92 | 1309 | 0(0.0%) | 8(0.7%) | 43(3.8%) | 100(8.9%) | 200(17.7%) | 776(68.9%) | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_axi_uart_controller | axi_uart_controller | 0.55 | 3.54 | 1296 | 10(1.2%) | 84(10.4%) | 80(9.9%) | 144(17.9%) | 194(24.1%) | 293(36.4%) | 0 | 0 | 0 | 9 | 0 |
|
||||
| u_cdma_matmul_bridge | cdma_matmul_bridge | 0.56 | 2.22 | 1003 | 1(0.3%) | 66(17.3%) | 39(10.2%) | 174(45.7%) | 13(3.4%) | 88(23.1%) | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_cpu | core_top | 0.56 | 3.96 | 15822 | 168(1.8%) | 579(6.3%) | 1029(11.1%) | 871(9.4%) | 1744(18.9%) | 4860(52.5%) | 0 | 0 | 20 | 276 | 0 |
|
||||
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 0.53 | 3.70 | 70959 | 286(0.8%) | 3478(9.4%) | 4960(13.4%) | 5940(16.0%) | 4261(11.5%) | 18098(48.9%) | 1169 | 40 | 18 | 5241 | 0 |
|
||||
| u_matmul_axi_slave | matmul_axi_slave | 0.69 | 3.39 | 10715 | 18(0.2%) | 465(6.4%) | 1463(20.2%) | 312(4.3%) | 1333(18.4%) | 3646(50.4%) | 6 | 16 | 0 | 512 | 0 |
|
||||
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 0.45 | 3.68 | 3535 | 136(7.0%) | 181(9.3%) | 328(16.8%) | 258(13.2%) | 297(15.2%) | 750(38.5%) | 0 | 0 | 1 | 4 | 0 |
|
||||
+---------------------------+---------------------+------+----------------+-----------------+-----------+------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
|
||||
* Complexity Ranges
|
||||
** 0.0 - 0.3 -> Very Low, 0.3 - 0.5 -> low, 0.5 - 0.65 -> normal, 0.65 - 0.85 -> high, 0.85 - 1.0 -> very high
|
||||
*** -* -> Not computable as cell size is very small
|
||||
|
||||
|
||||
@@ -1,52 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 02:58:13 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_design_analysis -timing -file /home/fallensigh/vivado_reports_withdsp/design_analysis_timing.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200t
|
||||
| Design State : Routed
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report Design Analysis
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Setup Path Characteristics 1-1
|
||||
|
||||
1. Setup Path Characteristics 1-1
|
||||
---------------------------------
|
||||
|
||||
+---------------------------+----------------------------------------------------------------------------------------+
|
||||
| Characteristics | Path #1 |
|
||||
+---------------------------+----------------------------------------------------------------------------------------+
|
||||
| Requirement | 20.000 |
|
||||
| Path Delay | 15.252 |
|
||||
| Logic Delay | 7.003(46%) |
|
||||
| Net Delay | 8.249(54%) |
|
||||
| Clock Skew | -3.954 |
|
||||
| Slack | 0.424 |
|
||||
| Clock Relationship | Safely Timed |
|
||||
| Logic Levels | 14 |
|
||||
| Routes | 12 |
|
||||
| Logical Path | FDCE LUT4 LUT5 LUT6 CARRY4 CARRY4 CARRY4 CARRY4 CARRY4 LUT6 CARRY4 LUT6 LUT6 LUT6 OBUF |
|
||||
| Start Point Clock | sys_clk |
|
||||
| End Point Clock | sys_clk |
|
||||
| DSP Block | None |
|
||||
| BRAM | None |
|
||||
| IO Crossings | 3 |
|
||||
| Config Crossings | 0 |
|
||||
| SLR Crossings | 0 |
|
||||
| PBlocks | 0 |
|
||||
| High Fanout | 80 |
|
||||
| Dont Touch | 0 |
|
||||
| Mark Debug | 0 |
|
||||
| Start Point Pin Primitive | FDCE/C |
|
||||
| End Point Pin Primitive | base_ram_be_n[3] |
|
||||
| Start Point Pin | ax_req_q_len_reg[1]/C |
|
||||
| End Point Pin | base_ram_be_n[3] |
|
||||
+---------------------------+----------------------------------------------------------------------------------------+
|
||||
* Bounding box calculated as % of dimensions for the target device (436, 500)
|
||||
|
||||
|
||||
@@ -1,911 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 02:57:43 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_drc -file /home/fallensigh/vivado_reports_withdsp/drc.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200tfbg676-1
|
||||
| Speed File : -1
|
||||
| Design State : Fully Routed
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
Report DRC
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: impl_1
|
||||
Design limits: <entire design considered>
|
||||
Ruledeck: default
|
||||
Max violations: <unlimited>
|
||||
Violations found: 174
|
||||
+-----------+----------+----------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+-----------+----------+----------------------------+------------+
|
||||
| CHECK-3 | Warning | Report rule limit reached | 2 |
|
||||
| DPIP-1 | Warning | Input pipelining | 47 |
|
||||
| DPOP-1 | Warning | PREG Output pipelining | 29 |
|
||||
| DPOP-2 | Warning | MREG Output pipelining | 56 |
|
||||
| REQP-1839 | Warning | RAMB36 async control check | 20 |
|
||||
| REQP-1840 | Warning | RAMB18 async control check | 20 |
|
||||
+-----------+----------+----------------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
CHECK-3#1 Warning
|
||||
Report rule limit reached
|
||||
REQP-1839 rule limit reached: 20 violations have been found.
|
||||
Related violations: <none>
|
||||
|
||||
CHECK-3#2 Warning
|
||||
Report rule limit reached
|
||||
REQP-1840 rule limit reached: 20 violations have been found.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#1 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#2 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#3 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#4 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#5 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#6 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#7 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#8 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#9 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#10 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#11 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#12 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#13 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#14 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#15 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#16 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#17 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#18 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#19 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#20 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#21 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#22 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#23 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#24 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/tk_s20 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/tk_s20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#25 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#26 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#27 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/tk_s20 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/tk_s20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#28 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q0_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q0_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#29 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q1_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q1_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#30 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q2_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q2_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#31 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q3_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q3_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#32 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#33 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#34 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#35 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#36 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#37 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#38 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#39 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#40 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#41 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#42 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#43 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#44 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#45 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#46 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#47 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#1 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#2 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#3 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#4 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#5 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#6 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#7 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#8 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#9 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#10 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#11 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#12 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#13 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#14 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#15 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#16 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#17 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#18 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#19 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#20 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#21 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#22 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod0__16 output u_matmul_axi_slave/mult_inst[0].u_mult/prod0__16/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#23 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17 output u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#24 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod0 output u_matmul_axi_slave/mult_inst[1].u_mult/prod0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#25 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17 output u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#26 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod0 output u_matmul_axi_slave/mult_inst[2].u_mult/prod0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#27 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod0__17 output u_matmul_axi_slave/mult_inst[2].u_mult/prod0__17/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#28 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod0 output u_matmul_axi_slave/mult_inst[3].u_mult/prod0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#29 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod0__17 output u_matmul_axi_slave/mult_inst[3].u_mult/prod0__17/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#1 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#2 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#3 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#4 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#5 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#6 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#7 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#8 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#9 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#10 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#11 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#12 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#13 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#14 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#15 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#16 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#17 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#18 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#19 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#20 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#21 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#22 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/tk_s20 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/tk_s20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#23 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#24 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#25 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/tk_s20 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/tk_s20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#26 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q0_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q0_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#27 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q1_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q1_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#28 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q2_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q2_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#29 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q3_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q3_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#30 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#31 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#32 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#33 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#34 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#35 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#36 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#37 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#38 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#39 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#40 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#41 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod0__16 multiplier stage u_matmul_axi_slave/mult_inst[0].u_mult/prod0__16/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#42 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17 multiplier stage u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#43 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg multiplier stage u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#44 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0 multiplier stage u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#45 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod0 multiplier stage u_matmul_axi_slave/mult_inst[1].u_mult/prod0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#46 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17 multiplier stage u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#47 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg multiplier stage u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#48 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0 multiplier stage u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#49 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod0 multiplier stage u_matmul_axi_slave/mult_inst[2].u_mult/prod0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#50 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod0__17 multiplier stage u_matmul_axi_slave/mult_inst[2].u_mult/prod0__17/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#51 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg multiplier stage u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#52 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg__0 multiplier stage u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#53 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod0 multiplier stage u_matmul_axi_slave/mult_inst[3].u_mult/prod0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#54 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod0__17 multiplier stage u_matmul_axi_slave/mult_inst[3].u_mult/prod0__17/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#55 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg multiplier stage u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#56 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg__0 multiplier stage u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#1 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#2 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#3 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#4 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#5 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#6 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#7 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#8 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#9 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#10 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#11 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#12 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#13 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#14 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#15 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#16 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#17 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#18 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#19 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#20 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#1 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#2 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#3 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#4 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#5 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#6 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#7 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#8 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#9 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#10 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#11 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#12 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#13 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#14 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#15 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#16 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#17 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENARDEN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_1__15_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#18 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENBWREN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_2__13_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#19 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[2] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#20 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[3] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
@@ -1,221 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 02:57:58 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/vivado_reports_withdsp/high_fanout.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200t
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
High Fan-out Nets Information
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+---------------------------------------------------------------------------------------+--------+-------------+
|
||||
| Net Name | Fanout | Driver Type |
|
||||
+---------------------------------------------------------------------------------------+--------+-------------+
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/delay_reg[1] | 24229 | LUT5 |
|
||||
| pll_clk.u_clk_pll/inst/sys_clk | 9603 | BUFG |
|
||||
| pll_clk.u_rst_sys/prst | 3749 | LUT1 |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_0 | 2140 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mb_en | 2121 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/E[0] | 2048 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 | 1611 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_0[0] | 1608 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state[2]_i_3_n_0 | 1604 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 | 1601 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] | 1601 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[1] | 1601 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[2] | 1601 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 | 1600 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1 | 1122 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0 | 1088 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0 | 1088 | FDRE |
|
||||
| pll_clk.u_rst_mlkem/delay_reg[1]_0 | 1066 | LUT1 |
|
||||
| u_cpu/reset | 799 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sel0[3] | 773 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[0] | 769 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[1] | 769 | CARRY4 |
|
||||
| u_cpu/u_mul/E[0] | 716 | LUT1 |
|
||||
| u_matmul_axi_slave/w_addr[2] | 667 | FDRE |
|
||||
| u_matmul_axi_slave/w_addr[3] | 604 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 | 512 | LUT2 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[0]_0[0] | 512 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sel0[4] | 388 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[2] | 385 | CARRY4 |
|
||||
| u_cpu/wb_stage/w_index[0] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[1] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[2] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[3] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[4] | 358 | LUT6 |
|
||||
| u_matmul_axi_slave/Q[0] | 354 | FDRE |
|
||||
| u_matmul_axi_slave/acc_idx_d4[0] | 354 | FDRE |
|
||||
| u_matmul_axi_slave/acc_idx_d4[1] | 354 | FDRE |
|
||||
| u_matmul_axi_slave/acc_idx_d4[2] | 354 | FDRE |
|
||||
| u_matmul_axi_slave/acc_idx_d4[3] | 354 | FDRE |
|
||||
| u_cpu/wb_stage/we_0 | 324 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1 | 290 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r_reg[255]_i_5_n_4 | 288 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[4] | 272 | FDCE |
|
||||
| u_matmul_axi_slave/sel0[1] | 264 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10] | 263 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11] | 263 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8] | 262 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc | 262 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9] | 261 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[0] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[10] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[11] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[1] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[2] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[3] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[4] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[5] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[6] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[7] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[8] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[9] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/E[0] | 256 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r | 256 | LUT3 |
|
||||
| u_matmul_axi_slave/mult_inst[0].u_mult/E[0] | 256 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode | 250 | LUT4 |
|
||||
| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge | 245 | LUT3 |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[0] | 244 | FDSE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[7] | 239 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[2] | 238 | FDCE |
|
||||
| u_cpu/exe_stage/ds_to_es_bus_r0 | 234 | LUT5 |
|
||||
| u_cpu/mem_stage/E[0] | 234 | LUT6 |
|
||||
| u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/axiOut_7_wstrb[0] | 232 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1022]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[126]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[254]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[382]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[510]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[638]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[766]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[894]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[5] | 223 | FDCE |
|
||||
| u_matmul_axi_slave/w_addr[5] | 223 | FDRE |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0 | 211 | LUT2 |
|
||||
| u_cpu/mem_stage/es_to_ms_bus_r0 | 210 | LUT2 |
|
||||
| u_cpu/u_csr/tlbw_r_tlbidx[2] | 210 | FDRE |
|
||||
| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[0] | 203 | FDRE |
|
||||
| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[1] | 203 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/grp_ptr_r_reg_n_0_[2] | 196 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[6] | 195 | FDCE |
|
||||
| u_cpu/wb_stage/Q[33] | 194 | FDRE |
|
||||
| u_cpu/wb_stage/Q[34] | 194 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[5] | 194 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[3] | 193 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4] | 188 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r_reg[3]_rep_n_0 | 187 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1] | 184 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6] | 184 | FDCE |
|
||||
| u_snix_axil_cdma_mux_8ch/u_core_engine/_zz_ram_port1_reg[32] | 182 | LUT4 |
|
||||
| u_cpu/wb_stage/ws_valid_reg_0 | 180 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r_reg[5]_rep_n_0 | 180 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1] | 179 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[0] | 177 | FDCE |
|
||||
| u_matmul_axi_slave/p_0_in__0 | 176 | LUT4 |
|
||||
| u_matmul_axi_slave/p_0_in__0__0 | 176 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2] | 174 | FDCE |
|
||||
| u_cpu/wb_stage/Q[37] | 173 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_out[0] | 169 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[2]_rep__0_n_0 | 168 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[4] | 165 | FDCE |
|
||||
| u_cpu/wb_stage/Q[32] | 164 | FDRE |
|
||||
| u_cpu/wb_stage/Q[35] | 163 | FDRE |
|
||||
| u_cpu/wb_stage/Q[36] | 162 | FDRE |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_rd_inst/m_axil_araddr_reg_reg[2]_0 | 161 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[6] | 161 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0] | 160 | FDCE |
|
||||
| u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]_0 | 160 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[3] | 158 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3] | 156 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r_reg[255]_i_5_n_5 | 153 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[0] | 153 | FDCE |
|
||||
| u_cpu/axi_bridge/FSM_sequential_write_requst_state_reg[1]_0 | 151 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep_n_0 | 151 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[7] | 151 | FDCE |
|
||||
| u_snix_axil_cdma_mux_8ch/u_core_engine/num_bytes_comb1 | 150 | CARRY4 |
|
||||
| u_cpu/dcache/awaddr[31]_i_3_n_0 | 148 | LUT2 |
|
||||
| u_cpu/dcache/awaddr[31]_i_4_n_0 | 148 | LUT2 |
|
||||
| u_matmul_axi_slave/mult_inst[3].u_mult/FSM_sequential_state_reg | 148 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] | 146 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_12_17_i_57_n_0 | 144 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[1] | 142 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[4] | 141 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[5] | 141 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[6] | 141 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[7] | 141 | FDCE |
|
||||
| u_cpu/dcache/write_buffer_state | 140 | FDRE |
|
||||
| u_matmul_axi_slave/mult_inst[3].u_mult/cur_bank_reg_rep | 140 | LUT3 |
|
||||
| u_matmul_axi_slave/mult_inst[3].u_mult/req_0_reg | 140 | LUT3 |
|
||||
| u_snix_axil_cdma_mux_8ch/ADDRA[0] | 140 | LUT6 |
|
||||
| u_cpu/u_csr/tlbw_r_tlbidx[0] | 139 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[3] | 139 | FDCE |
|
||||
| u_matmul_axi_slave/sel0[0] | 139 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[3] | 138 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[2] | 138 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]_i_5_n_7 | 137 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_6_11_i_34_n_0 | 137 | LUT4 |
|
||||
| u_cpu/u_csr/tlbw_r_tlbidx[1] | 136 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1080]_i_5_n_0 | 136 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1081]_i_5_n_0 | 136 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1082]_i_5_n_0 | 136 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1083]_i_5_n_0 | 136 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1084]_i_6_n_0 | 136 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1087]_i_3_n_0 | 136 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1087]_i_9_n_0 | 136 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1087]_i_3_n_0 | 136 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/rl_idx[3] | 136 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 | 136 | FDCE |
|
||||
+---------------------------------------------------------------------------------------+--------+-------------+
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,179 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 02:58:09 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_power -file /home/fallensigh/vivado_reports_withdsp/power.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200tfbg676-1
|
||||
| Design State : routed
|
||||
| Grade : commercial
|
||||
| Process : typical
|
||||
| Characterization : Production
|
||||
--------------------------------------------------------------------------------------------------
|
||||
|
||||
Power Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
1.1 On-Chip Components
|
||||
1.2 Power Supply Summary
|
||||
1.3 Confidence Level
|
||||
2. Settings
|
||||
2.1 Environment
|
||||
2.2 Clock Constraints
|
||||
3. Detailed Reports
|
||||
3.1 By Hierarchy
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+--------------------------+--------------+
|
||||
| Total On-Chip Power (W) | 0.512 |
|
||||
| Design Power Budget (W) | Unspecified* |
|
||||
| Power Budget Margin (W) | NA |
|
||||
| Dynamic (W) | 0.371 |
|
||||
| Device Static (W) | 0.141 |
|
||||
| Effective TJA (C/W) | 1.9 |
|
||||
| Max Ambient (C) | 84.0 |
|
||||
| Junction Temperature (C) | 26.0 |
|
||||
| Confidence Level | Low |
|
||||
| Setting File | --- |
|
||||
| Simulation Activity File | --- |
|
||||
| Design Nets Matched | NA |
|
||||
+--------------------------+--------------+
|
||||
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
|
||||
|
||||
|
||||
1.1 On-Chip Components
|
||||
----------------------
|
||||
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
| On-Chip | Power (W) | Used | Available | Utilization (%) |
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
| Clocks | 0.037 | 7 | --- | --- |
|
||||
| Slice Logic | 0.056 | 109753 | --- | --- |
|
||||
| LUT as Logic | 0.052 | 56469 | 133800 | 42.20 |
|
||||
| CARRY4 | 0.001 | 1802 | 33450 | 5.39 |
|
||||
| Register | <0.001 | 39141 | 267600 | 14.63 |
|
||||
| LUT as Shift Register | <0.001 | 1175 | 46200 | 2.54 |
|
||||
| LUT as Distributed RAM | <0.001 | 740 | 46200 | 1.60 |
|
||||
| F7/F8 Muxes | <0.001 | 6090 | 133800 | 4.55 |
|
||||
| Others | 0.000 | 334 | --- | --- |
|
||||
| Signals | 0.095 | 78236 | --- | --- |
|
||||
| Block RAM | 0.018 | 23.5 | 365 | 6.44 |
|
||||
| PLL | 0.132 | 1 | 10 | 10.00 |
|
||||
| DSPs | 0.010 | 56 | 740 | 7.57 |
|
||||
| I/O | 0.023 | 202 | 400 | 50.50 |
|
||||
| Static Power | 0.141 | | | |
|
||||
| Total | 0.512 | | | |
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
|
||||
|
||||
1.2 Power Supply Summary
|
||||
------------------------
|
||||
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Vccint | 1.000 | 0.257 | 0.225 | 0.032 |
|
||||
| Vccaux | 1.800 | 0.099 | 0.069 | 0.031 |
|
||||
| Vcco33 | 3.300 | 0.011 | 0.006 | 0.005 |
|
||||
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccbram | 1.000 | 0.003 | 0.001 | 0.001 |
|
||||
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
|
||||
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
|
||||
|
||||
1.3 Confidence Level
|
||||
--------------------
|
||||
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| User Input Data | Confidence | Details | Action |
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| Design implementation state | High | Design is routed | |
|
||||
| Clock nodes activity | High | User specified more than 95% of clocks | |
|
||||
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
|
||||
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
|
||||
| Device models | High | Device models are Production | |
|
||||
| | | | |
|
||||
| Overall confidence level | Low | | |
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
2. Settings
|
||||
-----------
|
||||
|
||||
2.1 Environment
|
||||
---------------
|
||||
|
||||
+-----------------------+--------------------------+
|
||||
| Ambient Temp (C) | 25.0 |
|
||||
| ThetaJA (C/W) | 1.9 |
|
||||
| Airflow (LFM) | 250 |
|
||||
| Heat Sink | medium (Medium Profile) |
|
||||
| ThetaSA (C/W) | 3.4 |
|
||||
| Board Selection | medium (10"x10") |
|
||||
| # of Board Layers | 12to15 (12 to 15 Layers) |
|
||||
| Board Temperature (C) | 25.0 |
|
||||
+-----------------------+--------------------------+
|
||||
|
||||
|
||||
2.2 Clock Constraints
|
||||
---------------------
|
||||
|
||||
+-------------------+------------------------------------------+-----------------+
|
||||
| Clock | Domain | Constraint (ns) |
|
||||
+-------------------+------------------------------------------+-----------------+
|
||||
| clk | clk | 20.0 |
|
||||
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
|
||||
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 |
|
||||
| mlkem_clk_clk_pll | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 40.0 |
|
||||
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
|
||||
+-------------------+------------------------------------------+-----------------+
|
||||
|
||||
|
||||
3. Detailed Reports
|
||||
-------------------
|
||||
|
||||
3.1 By Hierarchy
|
||||
----------------
|
||||
|
||||
+----------------------------+-----------+
|
||||
| Name | Power (W) |
|
||||
+----------------------------+-----------+
|
||||
| soc_top | 0.371 |
|
||||
| pll_clk.u_clk_pll | 0.133 |
|
||||
| inst | 0.133 |
|
||||
| u_Axi_CDC | 0.002 |
|
||||
| wFifo | 0.001 |
|
||||
| u_axi_uart_controller | 0.001 |
|
||||
| u_cdma_matmul_bridge | 0.001 |
|
||||
| u_cpu | 0.017 |
|
||||
| addr_trans | 0.002 |
|
||||
| tlb_entry | 0.002 |
|
||||
| btb | 0.003 |
|
||||
| dcache | 0.004 |
|
||||
| icache | 0.005 |
|
||||
| u_csr | 0.001 |
|
||||
| u_fft_mlkem_axi_slave | 0.134 |
|
||||
| u_fft_controller | 0.032 |
|
||||
| u_FFT | 0.030 |
|
||||
| u_mlkem_axi_cdc | 0.001 |
|
||||
| u_mlkem_axi_slave | 0.101 |
|
||||
| u_mlkem | 0.098 |
|
||||
| u_matmul_axi_slave | 0.047 |
|
||||
| u_snix_axil_cdma_mux_8ch | 0.008 |
|
||||
| u_core_engine | 0.004 |
|
||||
| axis_fifo_u0 | 0.002 |
|
||||
+----------------------------+-----------+
|
||||
|
||||
|
||||
Binary file not shown.
|
Before Width: | Height: | Size: 45 KiB |
@@ -1,12 +0,0 @@
|
||||
Design Route Status
|
||||
: # nets :
|
||||
------------------------------------------- : ----------- :
|
||||
# of logical nets.......................... : 116330 :
|
||||
# of nets not needing routing.......... : 38083 :
|
||||
# of internally routed nets........ : 37618 :
|
||||
# of nets with no loads............ : 465 :
|
||||
# of routable nets..................... : 78247 :
|
||||
# of fully routed nets............. : 78247 :
|
||||
# of nets with routing errors.......... : 0 :
|
||||
------------------------------------------- : ----------- :
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,237 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 02:57:49 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_utilization -file /home/fallensigh/vivado_reports_withdsp/utilization.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200tfbg676-1
|
||||
| Design State : Routed
|
||||
--------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Slice Logic Distribution
|
||||
3. Memory
|
||||
4. DSP
|
||||
5. IO and GT Specific
|
||||
6. Clocking
|
||||
7. Specific Feature
|
||||
8. Primitives
|
||||
9. Black Boxes
|
||||
10. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
| Slice LUTs | 53691 | 0 | 133800 | 40.13 |
|
||||
| LUT as Logic | 51836 | 0 | 133800 | 38.74 |
|
||||
| LUT as Memory | 1855 | 0 | 46200 | 4.02 |
|
||||
| LUT as Distributed RAM | 740 | 0 | | |
|
||||
| LUT as Shift Register | 1115 | 0 | | |
|
||||
| Slice Registers | 39141 | 0 | 267600 | 14.63 |
|
||||
| Register as Flip Flop | 39141 | 0 | 267600 | 14.63 |
|
||||
| Register as Latch | 0 | 0 | 267600 | 0.00 |
|
||||
| F7 Muxes | 4519 | 0 | 66900 | 6.75 |
|
||||
| F8 Muxes | 1571 | 0 | 33450 | 4.70 |
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 24 | Yes | - | Set |
|
||||
| 26265 | Yes | - | Reset |
|
||||
| 126 | Yes | Set | - |
|
||||
| 12726 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Slice Logic Distribution
|
||||
---------------------------
|
||||
|
||||
+--------------------------------------------+-------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+--------------------------------------------+-------+-------+-----------+-------+
|
||||
| Slice | 18732 | 0 | 33450 | 56.00 |
|
||||
| SLICEL | 12122 | 0 | | |
|
||||
| SLICEM | 6610 | 0 | | |
|
||||
| LUT as Logic | 51836 | 0 | 133800 | 38.74 |
|
||||
| using O5 output only | 4 | | | |
|
||||
| using O6 output only | 43877 | | | |
|
||||
| using O5 and O6 | 7955 | | | |
|
||||
| LUT as Memory | 1855 | 0 | 46200 | 4.02 |
|
||||
| LUT as Distributed RAM | 740 | 0 | | |
|
||||
| using O5 output only | 0 | | | |
|
||||
| using O6 output only | 60 | | | |
|
||||
| using O5 and O6 | 680 | | | |
|
||||
| LUT as Shift Register | 1115 | 0 | | |
|
||||
| using O5 output only | 47 | | | |
|
||||
| using O6 output only | 1008 | | | |
|
||||
| using O5 and O6 | 60 | | | |
|
||||
| Slice Registers | 39141 | 0 | 267600 | 14.63 |
|
||||
| Register driven from within the Slice | 19059 | | | |
|
||||
| Register driven from outside the Slice | 20082 | | | |
|
||||
| LUT in front of the register is unused | 11401 | | | |
|
||||
| LUT in front of the register is used | 8681 | | | |
|
||||
| Unique Control Sets | 1440 | | 33450 | 4.30 |
|
||||
+--------------------------------------------+-------+-------+-----------+-------+
|
||||
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
|
||||
|
||||
|
||||
3. Memory
|
||||
---------
|
||||
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 23.5 | 0 | 365 | 6.44 |
|
||||
| RAMB36/FIFO* | 8 | 0 | 365 | 2.19 |
|
||||
| RAMB36E1 only | 8 | | | |
|
||||
| RAMB18 | 31 | 0 | 730 | 4.25 |
|
||||
| RAMB18E1 only | 31 | | | |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
4. DSP
|
||||
------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| DSPs | 56 | 0 | 740 | 7.57 |
|
||||
| DSP48E1 only | 56 | | | |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 202 | 202 | 400 | 50.50 |
|
||||
| IOB Master Pads | 97 | | | |
|
||||
| IOB Slave Pads | 102 | | | |
|
||||
| Bonded IPADs | 0 | 0 | 26 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 16 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 10 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 384 | 0.00 |
|
||||
| GTPE2_CHANNEL | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 400 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 400 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 4 | 0 | 32 | 12.50 |
|
||||
| BUFIO | 0 | 0 | 40 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| PLLE2_ADV | 1 | 0 | 10 | 10.00 |
|
||||
| BUFMRCE | 0 | 0 | 20 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 120 | 0.00 |
|
||||
| BUFR | 0 | 0 | 40 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
8. Primitives
|
||||
-------------
|
||||
|
||||
+-----------+-------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+-----------+-------+---------------------+
|
||||
| LUT6 | 29130 | LUT |
|
||||
| FDCE | 26265 | Flop & Latch |
|
||||
| FDRE | 12726 | Flop & Latch |
|
||||
| LUT5 | 8459 | LUT |
|
||||
| LUT3 | 8166 | LUT |
|
||||
| LUT4 | 8097 | LUT |
|
||||
| LUT2 | 5229 | LUT |
|
||||
| MUXF7 | 4519 | MuxFx |
|
||||
| CARRY4 | 1802 | CarryLogic |
|
||||
| MUXF8 | 1571 | MuxFx |
|
||||
| RAMD32 | 1060 | Distributed Memory |
|
||||
| SRLC32E | 992 | Distributed Memory |
|
||||
| LUT1 | 710 | LUT |
|
||||
| RAMS32 | 328 | Distributed Memory |
|
||||
| SRL16E | 183 | Distributed Memory |
|
||||
| FDSE | 126 | Flop & Latch |
|
||||
| IBUF | 104 | IO |
|
||||
| OBUF | 98 | IO |
|
||||
| OBUFT | 66 | IO |
|
||||
| DSP48E1 | 56 | Block Arithmetic |
|
||||
| RAMD64E | 32 | Distributed Memory |
|
||||
| RAMB18E1 | 31 | Block Memory |
|
||||
| FDPE | 24 | Flop & Latch |
|
||||
| RAMB36E1 | 8 | Block Memory |
|
||||
| BUFG | 4 | Clock |
|
||||
| PLLE2_ADV | 1 | Clock |
|
||||
+-----------+-------+---------------------+
|
||||
|
||||
|
||||
9. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
10. Instantiated Netlists
|
||||
-------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
| clk_pll | 1 |
|
||||
+----------+------+
|
||||
|
||||
|
||||
@@ -1,276 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 02:57:50 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_utilization -hierarchical -file /home/fallensigh/vivado_reports_withdsp/utilization_hier.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200tfbg676-1
|
||||
| Design State : Routed
|
||||
---------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Utilization by Hierarchy
|
||||
|
||||
1. Utilization by Hierarchy
|
||||
---------------------------
|
||||
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks |
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
| soc_top | (top) | 53691 | 51836 | 740 | 1115 | 39141 | 8 | 31 | 56 |
|
||||
| (soc_top) | (top) | 102 | 46 | 56 | 0 | 9 | 0 | 0 | 0 |
|
||||
| pll_clk.u_clk_pll | clk_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| inst | clk_pll__clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_mlkem | rst_sync_0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_sys | rst_sync_1 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 381 | 381 | 0 | 0 | 151 | 0 | 0 | 0 |
|
||||
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 6 | 6 | 0 | 0 | 24 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_82 | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_65 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_81 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_66 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_80 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_67 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_79 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 33 | 33 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_76 | 27 | 27 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_77 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_78 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_73 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_74 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_75 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_70 | 20 | 20 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_71 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_72 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 23 | 23 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 96 | 96 | 0 | 0 | 25 | 0 | 0 | 0 |
|
||||
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 75 | 75 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4ReadOnlyErrorSlave_1_69 | 21 | 21 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 40 | 40 | 0 | 0 | 18 | 0 | 0 | 0 |
|
||||
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 20 | 20 | 0 | 0 | 16 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4WriteOnlyErrorSlave_1_68 | 21 | 21 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 53 | 53 | 0 | 0 | 17 | 0 | 0 | 0 |
|
||||
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 38 | 38 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4ReadOnlyErrorSlave_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
|
||||
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 32 | 32 | 0 | 0 | 14 | 0 | 0 | 0 |
|
||||
| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 20 | 20 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 12 | 12 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| u_Axi_CDC | Axi_CDC | 412 | 284 | 128 | 0 | 317 | 0 | 0 | 0 |
|
||||
| arFifo | StreamFifoCC_3_48 | 185 | 149 | 36 | 0 | 77 | 0 | 0 | 0 |
|
||||
| (arFifo) | StreamFifoCC_3_48 | 180 | 144 | 36 | 0 | 65 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9_63 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11_64 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| awFifo | StreamFifoCC_49 | 102 | 66 | 36 | 0 | 79 | 0 | 0 | 0 |
|
||||
| (awFifo) | StreamFifoCC_49 | 98 | 62 | 36 | 0 | 65 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_10_60 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9_61 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11_62 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| bFifo | StreamFifoCC_2_50 | 14 | 14 | 0 | 0 | 26 | 0 | 0 | 0 |
|
||||
| (bFifo) | StreamFifoCC_2_50 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_5_57 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_4_58 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_6_59 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| rFifo | StreamFifoCC_4_51 | 45 | 17 | 28 | 0 | 66 | 0 | 0 | 0 |
|
||||
| (rFifo) | StreamFifoCC_4_51 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_55 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_1_56 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| wFifo | StreamFifoCC_1_52 | 66 | 38 | 28 | 0 | 69 | 0 | 0 | 0 |
|
||||
| (wFifo) | StreamFifoCC_1_52 | 62 | 34 | 28 | 0 | 53 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_7_53 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_8_54 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_axi_axil_adapter | axi_axil_adapter | 1072 | 1072 | 0 | 0 | 173 | 0 | 0 | 0 |
|
||||
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 497 | 497 | 0 | 0 | 85 | 0 | 0 | 0 |
|
||||
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 575 | 575 | 0 | 0 | 88 | 0 | 0 | 0 |
|
||||
| u_axi_dvi | axi_dvi | 284 | 284 | 0 | 0 | 211 | 0 | 0 | 0 |
|
||||
| u_axi_ram | axi_wrap_ram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
|
||||
| u_axi_sram_sp | axi2sram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
|
||||
| u_axi_uart_controller | axi_uart_controller | 683 | 667 | 16 | 0 | 457 | 0 | 0 | 0 |
|
||||
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 251 | 251 | 0 | 0 | 120 | 0 | 0 | 0 |
|
||||
| uart0 | UART_TOP | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 |
|
||||
| regs | uart_regs | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 |
|
||||
| (regs) | uart_regs | 119 | 119 | 0 | 0 | 155 | 0 | 0 | 0 |
|
||||
| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| receiver | uart_receiver | 229 | 221 | 8 | 0 | 124 | 0 | 0 | 0 |
|
||||
| (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 |
|
||||
| fifo_rx | uart_rfifo | 161 | 153 | 8 | 0 | 70 | 0 | 0 | 0 |
|
||||
| (fifo_rx) | uart_rfifo | 143 | 143 | 0 | 0 | 62 | 0 | 0 | 0 |
|
||||
| rfifo | raminfr_47 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
||||
| transmitter | uart_transmitter | 83 | 75 | 8 | 0 | 56 | 0 | 0 | 0 |
|
||||
| (transmitter) | uart_transmitter | 41 | 41 | 0 | 0 | 35 | 0 | 0 | 0 |
|
||||
| fifo_tx | uart_tfifo | 43 | 35 | 8 | 0 | 21 | 0 | 0 | 0 |
|
||||
| (fifo_tx) | uart_tfifo | 24 | 24 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_cdma_matmul_bridge | cdma_matmul_bridge | 250 | 250 | 0 | 0 | 578 | 0 | 0 | 0 |
|
||||
| u_confreg | confreg | 390 | 390 | 0 | 0 | 476 | 0 | 0 | 0 |
|
||||
| (u_confreg) | confreg | 230 | 230 | 0 | 0 | 399 | 0 | 0 | 0 |
|
||||
| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 |
|
||||
| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 |
|
||||
| u_cpu | core_top | 8556 | 8304 | 252 | 0 | 5591 | 0 | 20 | 0 |
|
||||
| (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 |
|
||||
| addr_trans | addr_trans | 2247 | 2107 | 140 | 0 | 1244 | 0 | 0 | 0 |
|
||||
| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 |
|
||||
| tlb_entry | tlb_entry | 2247 | 2107 | 140 | 0 | 1204 | 0 | 0 | 0 |
|
||||
| axi_bridge | axi_bridge | 39 | 39 | 0 | 0 | 214 | 0 | 0 | 0 |
|
||||
| btb | btb | 1048 | 968 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
||||
| (btb) | btb | 1045 | 965 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
||||
| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| dcache | dcache | 552 | 520 | 32 | 0 | 146 | 0 | 10 | 0 |
|
||||
| (dcache) | dcache | 87 | 55 | 32 | 0 | 138 | 0 | 0 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_36 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_39 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_40 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_41 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_42 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_43 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| lfsr | lfsr_44 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| tagv_ram_way[0].u | tagv_sram_45 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| tagv_ram_way[1].u | tagv_sram_46 | 43 | 43 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| exe_stage | exe_stage | 665 | 665 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| (exe_stage) | exe_stage | 634 | 634 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| icache | icache | 234 | 234 | 0 | 0 | 55 | 0 | 10 | 0 |
|
||||
| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_29 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_30 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_31 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_32 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_33 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_34 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| tagv_ram_way[1].u | tagv_sram_35 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| id_stage | id_stage | 1052 | 1052 | 0 | 0 | 108 | 0 | 0 | 0 |
|
||||
| if_stage | if_stage | 134 | 134 | 0 | 0 | 173 | 0 | 0 | 0 |
|
||||
| mem_stage | mem_stage | 115 | 115 | 0 | 0 | 211 | 0 | 0 | 0 |
|
||||
| u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 |
|
||||
| u_div | div | 142 | 142 | 0 | 0 | 107 | 0 | 0 | 0 |
|
||||
| u_mul | mul | 933 | 933 | 0 | 0 | 592 | 0 | 0 | 0 |
|
||||
| wb_stage | wb_stage | 689 | 689 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 32945 | 31724 | 112 | 1109 | 26787 | 8 | 10 | 40 |
|
||||
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| u_fft_controller | fft_controller | 2647 | 1607 | 0 | 1040 | 1083 | 6 | 4 | 16 |
|
||||
| (u_fft_controller) | fft_controller | 123 | 123 | 0 | 0 | 100 | 0 | 0 | 0 |
|
||||
| u_FFT | FFT | 2495 | 1455 | 0 | 1040 | 983 | 6 | 0 | 16 |
|
||||
| SU1 | SdfUnit | 1070 | 302 | 0 | 768 | 197 | 2 | 0 | 4 |
|
||||
| (SU1) | SdfUnit | 205 | 205 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_25 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer | 562 | 50 | 0 | 512 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized0 | 256 | 0 | 0 | 256 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 |
|
||||
| TW | Twiddle_27 | 1 | 1 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU2 | SdfUnit__parameterized0 | 492 | 300 | 0 | 192 | 197 | 2 | 0 | 4 |
|
||||
| (SU2) | SdfUnit__parameterized0 | 73 | 73 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_20 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_22 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
|
||||
| TW | Twiddle_23 | 3 | 3 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU3 | SdfUnit__parameterized1 | 347 | 299 | 0 | 48 | 197 | 0 | 0 | 4 |
|
||||
| (SU3) | SdfUnit__parameterized1 | 75 | 75 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_17 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized4 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_19 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
|
||||
| SU4 | SdfUnit__parameterized2 | 327 | 295 | 0 | 32 | 197 | 2 | 0 | 4 |
|
||||
| (SU4) | SdfUnit__parameterized2 | 69 | 69 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_15 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized5 | 128 | 112 | 0 | 16 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized6 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
|
||||
| TW | Twiddle | 2 | 2 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU5 | SdfUnit__parameterized3 | 260 | 260 | 0 | 0 | 195 | 0 | 0 | 0 |
|
||||
| (SU5) | SdfUnit__parameterized3 | 68 | 68 | 0 | 0 | 99 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 |
|
||||
| u_in0 | my_bram0 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_in1 | my_bram0_12 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_out0 | my_bram0_13 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_out1 | my_bram0_14 | 25 | 25 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_mlkem_axi_cdc | Axi_CDC_5 | 256 | 144 | 112 | 0 | 272 | 0 | 0 | 0 |
|
||||
| arFifo | StreamFifoCC_3 | 51 | 23 | 28 | 0 | 55 | 0 | 0 | 0 |
|
||||
| (arFifo) | StreamFifoCC_3 | 42 | 14 | 28 | 0 | 43 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9_10 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| awFifo | StreamFifoCC | 40 | 16 | 24 | 0 | 49 | 0 | 0 | 0 |
|
||||
| (awFifo) | StreamFifoCC | 31 | 7 | 24 | 0 | 35 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| bFifo | StreamFifoCC_2 | 18 | 14 | 4 | 0 | 27 | 0 | 0 | 0 |
|
||||
| (bFifo) | StreamFifoCC_2 | 11 | 7 | 4 | 0 | 13 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_4 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_6 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| rFifo | StreamFifoCC_4 | 56 | 28 | 28 | 0 | 72 | 0 | 0 | 0 |
|
||||
| (rFifo) | StreamFifoCC_4 | 49 | 21 | 28 | 0 | 56 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_1 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| wFifo | StreamFifoCC_1 | 91 | 63 | 28 | 0 | 69 | 0 | 0 | 0 |
|
||||
| (wFifo) | StreamFifoCC_1 | 86 | 58 | 28 | 0 | 53 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_8 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_mlkem_axi_slave | mlkem_axi_slave | 30043 | 29974 | 0 | 69 | 25426 | 2 | 6 | 24 |
|
||||
| (u_mlkem_axi_slave) | mlkem_axi_slave | 1278 | 1278 | 0 | 0 | 1064 | 0 | 0 | 0 |
|
||||
| u_mlkem | mlkem_top | 28768 | 28699 | 0 | 69 | 24362 | 2 | 6 | 24 |
|
||||
| (u_mlkem) | mlkem_top | 2326 | 2326 | 0 | 0 | 4911 | 0 | 0 | 0 |
|
||||
| u_bank_a | sd_bram__parameterized0 | 49 | 49 | 0 | 0 | 0 | 1 | 1 | 0 |
|
||||
| u_bank_se | sd_bram__parameterized1 | 61 | 61 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| u_bank_t | sd_bram__parameterized2 | 488 | 488 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_c_in_bram | sd_bram | 1291 | 1291 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_cbd | sample_cbd_sync_shared | 2512 | 2512 | 0 | 0 | 3199 | 0 | 0 | 0 |
|
||||
| u_comp | comp_decomp_sync | 322 | 321 | 0 | 1 | 269 | 0 | 0 | 3 |
|
||||
| u_ct_bram | sd_bram_6 | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_dkp_bram | sd_bram_7 | 73 | 73 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_ek_bram | sd_bram_8 | 388 | 388 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_keccak | keccak_core | 5622 | 5622 | 0 | 0 | 1606 | 0 | 0 | 0 |
|
||||
| u_ntt | ntt_core | 8192 | 8149 | 0 | 43 | 3743 | 0 | 0 | 6 |
|
||||
| (u_ntt) | ntt_core | 6140 | 6124 | 0 | 16 | 3364 | 0 | 0 | 0 |
|
||||
| u_bf | butterfly_unit_pipe | 1922 | 1896 | 0 | 26 | 224 | 0 | 0 | 3 |
|
||||
| (u_bf) | butterfly_unit_pipe | 69 | 44 | 0 | 25 | 75 | 0 | 0 | 0 |
|
||||
| u_barrett | barrett_mul_pipe_9 | 1854 | 1853 | 0 | 1 | 149 | 0 | 0 | 3 |
|
||||
| u_scl | barrett_mul_pipe | 131 | 130 | 0 | 1 | 155 | 0 | 0 | 3 |
|
||||
| u_pmul | poly_mul_sync | 2830 | 2805 | 0 | 25 | 6577 | 0 | 0 | 15 |
|
||||
| (u_pmul) | poly_mul_sync | 2474 | 2474 | 0 | 0 | 6299 | 0 | 0 | 0 |
|
||||
| u_bc | basecase_mul_pipe | 421 | 396 | 0 | 25 | 278 | 0 | 0 | 15 |
|
||||
| u_sha3 | sha3_top_shared | 3175 | 3175 | 0 | 0 | 2388 | 0 | 0 | 0 |
|
||||
| u_snt | sample_ntt_sync_shared | 1439 | 1439 | 0 | 0 | 1669 | 0 | 0 | 0 |
|
||||
| u_matmul_axi_slave | matmul_axi_slave | 6600 | 6418 | 176 | 6 | 2831 | 0 | 0 | 16 |
|
||||
| (u_matmul_axi_slave) | matmul_axi_slave | 5796 | 5614 | 176 | 6 | 2303 | 0 | 0 | 0 |
|
||||
| mult_inst[0].u_mult | pipelined_mult_32x32 | 203 | 203 | 0 | 0 | 132 | 0 | 0 | 4 |
|
||||
| mult_inst[1].u_mult | pipelined_mult_32x32_2 | 202 | 202 | 0 | 0 | 132 | 0 | 0 | 4 |
|
||||
| mult_inst[2].u_mult | pipelined_mult_32x32_3 | 202 | 202 | 0 | 0 | 132 | 0 | 0 | 4 |
|
||||
| mult_inst[3].u_mult | pipelined_mult_32x32_4 | 200 | 200 | 0 | 0 | 132 | 0 | 0 | 4 |
|
||||
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1673 | 1673 | 0 | 0 | 1476 | 0 | 1 | 0 |
|
||||
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 687 | 687 | 0 | 0 | 1180 | 0 | 0 | 0 |
|
||||
| u_core_engine | snix_axi_mm2mm | 988 | 988 | 0 | 0 | 296 | 0 | 1 | 0 |
|
||||
| (u_core_engine) | snix_axi_mm2mm | 763 | 763 | 0 | 0 | 243 | 0 | 0 | 0 |
|
||||
| axis_fifo_u0 | snix_axis_fifo | 225 | 225 | 0 | 0 | 53 | 0 | 1 | 0 |
|
||||
| u_fifo | snix_sync_fifo | 225 | 225 | 0 | 0 | 53 | 0 | 1 | 0 |
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining
|
||||
|
||||
|
||||
@@ -65,6 +65,7 @@ module axi2sram_sp_external #(
|
||||
output reg req_o,
|
||||
output reg we_o,
|
||||
output reg [AXI_ADDR_WIDTH-1:0] addr_o,
|
||||
output reg bank_o,
|
||||
output reg [AXI_DATA_WIDTH/8-1:0] be_o,
|
||||
output reg [AXI_DATA_WIDTH-1:0] data_o,
|
||||
input [AXI_DATA_WIDTH-1:0] data_i
|
||||
@@ -101,40 +102,34 @@ module axi2sram_sp_external #(
|
||||
localparam FIXED = 2'b00;
|
||||
localparam INCR = 2'b01;
|
||||
localparam WRAP = 2'b10;
|
||||
localparam [AXI_ADDR_WIDTH-1:0] ADDR_INCR =
|
||||
{{(AXI_ADDR_WIDTH-1){1'b0}}, 1'b1} << LOG_NR_BYTES;
|
||||
|
||||
reg [AXI_ADDR_WIDTH-1:0] req_addr_d, req_addr_q;
|
||||
reg [7:0] cnt_d, cnt_q;
|
||||
reg [8:0] cnt_d, cnt_q;
|
||||
reg [AXI_ADDR_WIDTH-1:0] wrap_mask_d, wrap_mask_q;
|
||||
reg req_bank_d, req_bank_q;
|
||||
reg [AXI_DATA_WIDTH-1:0] read_data_q;
|
||||
reg read_capture;
|
||||
|
||||
function automatic [AXI_ADDR_WIDTH-1:0] get_wrap_boundary;
|
||||
input [AXI_ADDR_WIDTH-1:0] unaligned_address;
|
||||
input [7:0] len;
|
||||
begin
|
||||
get_wrap_boundary = 'h0;
|
||||
// for wrapping transfers ax_len can only be of size 1, 3, 7 or 15
|
||||
if (len == 4'b1)
|
||||
get_wrap_boundary[AXI_ADDR_WIDTH-1:1+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:1+LOG_NR_BYTES];
|
||||
else if (len == 4'b11)
|
||||
get_wrap_boundary[AXI_ADDR_WIDTH-1:2+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:2+LOG_NR_BYTES];
|
||||
else if (len == 4'b111)
|
||||
get_wrap_boundary[AXI_ADDR_WIDTH-1:3+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:2+LOG_NR_BYTES];
|
||||
else if (len == 4'b1111)
|
||||
get_wrap_boundary[AXI_ADDR_WIDTH-1:4+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:4+LOG_NR_BYTES];
|
||||
end
|
||||
endfunction
|
||||
wire [AXI_ADDR_WIDTH-1:0] ar_burst_bytes =
|
||||
({{(AXI_ADDR_WIDTH-8){1'b0}}, s_arlen} + {{(AXI_ADDR_WIDTH-1){1'b0}}, 1'b1}) << LOG_NR_BYTES;
|
||||
wire [AXI_ADDR_WIDTH-1:0] aw_burst_bytes =
|
||||
({{(AXI_ADDR_WIDTH-8){1'b0}}, s_awlen} + {{(AXI_ADDR_WIDTH-1){1'b0}}, 1'b1}) << LOG_NR_BYTES;
|
||||
wire [AXI_ADDR_WIDTH-1:0] ar_wrap_mask = ar_burst_bytes - {{(AXI_ADDR_WIDTH-1){1'b0}}, 1'b1};
|
||||
wire [AXI_ADDR_WIDTH-1:0] aw_wrap_mask = aw_burst_bytes - {{(AXI_ADDR_WIDTH-1){1'b0}}, 1'b1};
|
||||
|
||||
reg [AXI_ADDR_WIDTH-1:0] aligned_address;
|
||||
reg [AXI_ADDR_WIDTH-1:0] wrap_boundary;
|
||||
reg [AXI_ADDR_WIDTH-1:0] upper_wrap_boundary;
|
||||
reg [AXI_ADDR_WIDTH-1:0] cons_addr;
|
||||
reg [AXI_ADDR_WIDTH-1:0] next_addr;
|
||||
reg [AXI_ADDR_WIDTH-1:0] seq_addr;
|
||||
|
||||
always @ (*) begin
|
||||
// address generation
|
||||
aligned_address = {ax_req_q_addr[AXI_ADDR_WIDTH-1:LOG_NR_BYTES], {{LOG_NR_BYTES}{1'b0}}};
|
||||
wrap_boundary = get_wrap_boundary(ax_req_q_addr, ax_req_q_len);
|
||||
// this will overflow
|
||||
upper_wrap_boundary = wrap_boundary + ((ax_req_q_len + 1) << LOG_NR_BYTES);
|
||||
// calculate consecutive address
|
||||
cons_addr = aligned_address + (cnt_q << LOG_NR_BYTES);
|
||||
seq_addr = req_addr_q + ADDR_INCR;
|
||||
case (ax_req_q_burst)
|
||||
FIXED: next_addr = req_addr_q;
|
||||
INCR: next_addr = seq_addr;
|
||||
WRAP: next_addr = (req_addr_q & ~wrap_mask_q) | (seq_addr & wrap_mask_q);
|
||||
default: next_addr = seq_addr;
|
||||
endcase
|
||||
|
||||
// Transaction attributes
|
||||
// default assignments
|
||||
@@ -146,12 +141,16 @@ module axi2sram_sp_external #(
|
||||
ax_req_d_burst = ax_req_q_burst;
|
||||
req_addr_d = req_addr_q;
|
||||
cnt_d = cnt_q;
|
||||
wrap_mask_d = wrap_mask_q;
|
||||
req_bank_d = req_bank_q;
|
||||
read_capture = 1'b0;
|
||||
// Memory default assignments
|
||||
data_o = s_wdata;
|
||||
be_o = s_wstrb;
|
||||
we_o = 1'b0;
|
||||
req_o = 1'b0;
|
||||
addr_o = 'h0;
|
||||
bank_o = req_bank_q;
|
||||
// AXI assignments
|
||||
// request
|
||||
s_awready = 1'b0;
|
||||
@@ -184,14 +183,17 @@ module axi2sram_sp_external #(
|
||||
ax_req_d_len = s_arlen;
|
||||
ax_req_d_size = s_arsize;
|
||||
ax_req_d_burst = s_arburst;
|
||||
state_d = READ;
|
||||
wrap_mask_d = ar_wrap_mask;
|
||||
req_bank_d = s_araddr[22];
|
||||
state_d = READ_ADDR;
|
||||
// we can request the first address, this saves us time
|
||||
req_o = 1'b1;
|
||||
addr_o = s_araddr;
|
||||
bank_o = s_araddr[22];
|
||||
// save the address
|
||||
req_addr_d = s_araddr;
|
||||
// save the ar_len
|
||||
cnt_d = 1;
|
||||
cnt_d = 0;
|
||||
// ------------
|
||||
// Write
|
||||
// ------------
|
||||
@@ -205,6 +207,9 @@ module axi2sram_sp_external #(
|
||||
ax_req_d_len = s_awlen;
|
||||
ax_req_d_size = s_awsize;
|
||||
ax_req_d_burst = s_awburst;
|
||||
wrap_mask_d = aw_wrap_mask;
|
||||
req_bank_d = s_awaddr[22];
|
||||
bank_o = s_awaddr[22];
|
||||
// we've got our first w_valid so start the write process
|
||||
if (s_wvalid) begin
|
||||
req_o = 1'b1;
|
||||
@@ -231,40 +236,52 @@ module axi2sram_sp_external #(
|
||||
end
|
||||
|
||||
READ: begin
|
||||
// keep request to memory high
|
||||
req_o = 1'b1;
|
||||
addr_o = req_addr_q;
|
||||
// send the response
|
||||
s_rvalid = 1'b1;
|
||||
s_rdata = data_i;
|
||||
s_rdata = read_data_q;
|
||||
s_rid = ax_req_q_id;
|
||||
s_rlast = (cnt_q == ax_req_q_len + 1);
|
||||
s_rlast = (cnt_q == ({1'b0, ax_req_q_len} + 9'd1));
|
||||
if (FAST_READ_BURST && !s_rlast) begin
|
||||
req_o = 1'b1;
|
||||
addr_o = next_addr;
|
||||
end
|
||||
// check that the master is ready, the slave must not wait on this
|
||||
if (s_rready) begin
|
||||
// we sent the last byte -> go back to idle
|
||||
if (s_rlast) begin
|
||||
state_d = IDLE;
|
||||
// we already got everything
|
||||
if (s_arvalid) begin
|
||||
// Accept the next burst without an intervening
|
||||
// IDLE cycle and start its SRAM address phase.
|
||||
s_arready = 1'b1;
|
||||
ax_req_d_id = s_arid;
|
||||
ax_req_d_addr = s_araddr;
|
||||
ax_req_d_len = s_arlen;
|
||||
ax_req_d_size = s_arsize;
|
||||
ax_req_d_burst = s_arburst;
|
||||
wrap_mask_d = ar_wrap_mask;
|
||||
req_bank_d = s_araddr[22];
|
||||
req_o = 1'b1;
|
||||
addr_o = s_araddr;
|
||||
bank_o = s_araddr[22];
|
||||
req_addr_d = s_araddr;
|
||||
// ARVALID was presented during the preceding
|
||||
// beat, so the async-SRAM address has a full
|
||||
// cycle to settle before this capture edge.
|
||||
read_capture = 1'b1;
|
||||
cnt_d = 1;
|
||||
state_d = READ;
|
||||
end else begin
|
||||
state_d = IDLE;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
if (FAST_READ_BURST) begin
|
||||
// Queue the next async-SRAM address for the clock
|
||||
// edge after the current read data is sampled.
|
||||
case (ax_req_q_burst)
|
||||
FIXED, INCR: req_addr_d = cons_addr;
|
||||
WRAP: begin
|
||||
if (cons_addr == upper_wrap_boundary) begin
|
||||
req_addr_d = wrap_boundary;
|
||||
end else if (cons_addr > upper_wrap_boundary) begin
|
||||
req_addr_d = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES);
|
||||
end else begin
|
||||
req_addr_d = cons_addr;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
read_capture = 1'b1;
|
||||
req_addr_d = next_addr;
|
||||
cnt_d = cnt_q + 1;
|
||||
state_d = READ;
|
||||
end else begin
|
||||
req_addr_d = next_addr;
|
||||
state_d = READ_ADDR;
|
||||
end
|
||||
end
|
||||
@@ -272,34 +289,12 @@ module axi2sram_sp_external #(
|
||||
end
|
||||
|
||||
READ_ADDR: begin
|
||||
// keep request to memory high
|
||||
// Fill the read data register after the async-SRAM address has
|
||||
// been stable for one full sys_clk cycle.
|
||||
req_o = 1'b1;
|
||||
// send the response
|
||||
s_rvalid = 1'b0;
|
||||
// ----------------------------
|
||||
// Next address generation
|
||||
// ----------------------------
|
||||
// handle the correct burst type
|
||||
case (ax_req_q_burst)
|
||||
FIXED, INCR: addr_o = cons_addr;
|
||||
WRAP: begin
|
||||
// check if the address reached warp boundary
|
||||
if (cons_addr == upper_wrap_boundary) begin
|
||||
addr_o = wrap_boundary;
|
||||
// address warped beyond boundary
|
||||
end else if (cons_addr > upper_wrap_boundary) begin
|
||||
addr_o = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES);
|
||||
// we are still in the incremental regime
|
||||
end else begin
|
||||
addr_o = cons_addr;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
// we need to change the address here for the upcoming request
|
||||
// we can decrease the counter as the master has consumed the read data
|
||||
addr_o = req_addr_q;
|
||||
read_capture = 1'b1;
|
||||
cnt_d = cnt_q + 1;
|
||||
// save the request address for the next cycle
|
||||
req_addr_d = addr_o;
|
||||
state_d = READ;
|
||||
end
|
||||
|
||||
@@ -317,24 +312,9 @@ module axi2sram_sp_external #(
|
||||
// Next address generation
|
||||
// ----------------------------
|
||||
// handle the correct burst type
|
||||
case (ax_req_q_burst)
|
||||
|
||||
FIXED, INCR: addr_o = cons_addr;
|
||||
WRAP: begin
|
||||
// check if the address reached warp boundary
|
||||
if (cons_addr == upper_wrap_boundary) begin
|
||||
addr_o = wrap_boundary;
|
||||
// address warped beyond boundary
|
||||
end else if (cons_addr > upper_wrap_boundary) begin
|
||||
addr_o = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES);
|
||||
// we are still in the incremental regime
|
||||
end else begin
|
||||
addr_o = cons_addr;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
addr_o = next_addr;
|
||||
// save the request address for the next cycle
|
||||
req_addr_d = addr_o;
|
||||
req_addr_d = next_addr;
|
||||
// we can decrease the counter as the master has consumed the read data
|
||||
cnt_d = cnt_q + 1;
|
||||
|
||||
@@ -365,7 +345,10 @@ module axi2sram_sp_external #(
|
||||
ax_req_q_len <= 8'h0;
|
||||
ax_req_q_size <= 3'h0;
|
||||
req_addr_q <= 'h0;
|
||||
cnt_q <= 8'h0;
|
||||
cnt_q <= 9'h0;
|
||||
wrap_mask_q <= 'h0;
|
||||
req_bank_q <= 1'b0;
|
||||
read_data_q <= 'h0;
|
||||
end else begin
|
||||
state_q <= state_d;
|
||||
ax_req_q_addr <= ax_req_d_addr;
|
||||
@@ -375,6 +358,10 @@ module axi2sram_sp_external #(
|
||||
ax_req_q_size <= ax_req_d_size;
|
||||
req_addr_q <= req_addr_d;
|
||||
cnt_q <= cnt_d;
|
||||
wrap_mask_q <= wrap_mask_d;
|
||||
req_bank_q <= req_bank_d;
|
||||
if (read_capture)
|
||||
read_data_q <= data_i;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
@@ -35,6 +35,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.PortWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.SENSITIVITY">LEVEL_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_BUSIF"/>
|
||||
@@ -136,7 +142,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
@@ -249,7 +255,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">20.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">20.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">20.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">30.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
@@ -259,11 +265,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<<<<<<< Updated upstream
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
=======
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">13</spirit:configurableElementValue>
|
||||
>>>>>>> Stashed changes
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
@@ -293,18 +295,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MAX">64.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MIN">2.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
|
||||
<<<<<<< Updated upstream
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">_cpu_clk__32.97872______0.000______50.0______130.093____123.600</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">_sys_clk__50.00000______0.000______50.0______122.035____123.600</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
|
||||
=======
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">_cpu_clk__33.33333______0.000______50.0______215.691____164.985</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">_sys_clk__50.00000______0.000______50.0______192.113____164.985</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">mlkem_clk__76.92308______0.000______50.0______172.249____164.985</spirit:configurableElementValue>
|
||||
>>>>>>> Stashed changes
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
|
||||
@@ -424,32 +420,32 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">130.093</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">243.156</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">123.600</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">144.334</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">33.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">122.035</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">222.587</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">123.600</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">144.334</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">110.420</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">186.330</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">123.600</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">144.334</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
@@ -538,7 +534,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">20</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">20.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">20.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">30</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
@@ -548,11 +544,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<<<<<<< Updated upstream
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
=======
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">13</spirit:configurableElementValue>
|
||||
>>>>>>> Stashed changes
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
@@ -580,13 +572,8 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
|
||||
<<<<<<< Updated upstream
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
|
||||
=======
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">true</spirit:configurableElementValue>
|
||||
>>>>>>> Stashed changes
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
|
||||
@@ -726,7 +713,6 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_JITTER" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_USED" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT5_DRIVES" xilinx:valueSource="user"/>
|
||||
@@ -735,7 +721,6 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT1_PORT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT2_PORT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT3_PORT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FEEDBACK_SOURCE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_BANDWIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
|
||||
|
||||
@@ -1,235 +0,0 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
// Date : Tue Jul 7 23:25:51 2026
|
||||
// Host : fedora running 64-bit unknown
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v
|
||||
// Design : clk_pll
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7a200tfbg676-1
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* NotValidForBitStream *)
|
||||
module clk_pll
|
||||
(cpu_clk,
|
||||
sys_clk,
|
||||
mlkem_clk,
|
||||
resetn,
|
||||
locked,
|
||||
clk_in1);
|
||||
output cpu_clk;
|
||||
output sys_clk;
|
||||
output mlkem_clk;
|
||||
input resetn;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
|
||||
(* IBUF_LOW_PWR *) wire clk_in1;
|
||||
wire cpu_clk;
|
||||
wire locked;
|
||||
wire mlkem_clk;
|
||||
wire resetn;
|
||||
wire sys_clk;
|
||||
|
||||
clk_pll_clk_pll_clk_wiz inst
|
||||
(.clk_in1(clk_in1),
|
||||
.cpu_clk(cpu_clk),
|
||||
.locked(locked),
|
||||
.mlkem_clk(mlkem_clk),
|
||||
.resetn(resetn),
|
||||
.sys_clk(sys_clk));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "clk_pll_clk_wiz" *)
|
||||
module clk_pll_clk_pll_clk_wiz
|
||||
(cpu_clk,
|
||||
sys_clk,
|
||||
mlkem_clk,
|
||||
resetn,
|
||||
locked,
|
||||
clk_in1);
|
||||
output cpu_clk;
|
||||
output sys_clk;
|
||||
output mlkem_clk;
|
||||
input resetn;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
|
||||
wire clk_in1;
|
||||
wire clk_in1_clk_pll;
|
||||
wire clkfbout_buf_clk_pll;
|
||||
wire clkfbout_clk_pll;
|
||||
wire cpu_clk;
|
||||
wire cpu_clk_clk_pll;
|
||||
wire locked;
|
||||
wire mlkem_clk;
|
||||
wire mlkem_clk_clk_pll;
|
||||
wire reset_high;
|
||||
wire resetn;
|
||||
wire sys_clk;
|
||||
wire sys_clk_clk_pll;
|
||||
wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
|
||||
wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
|
||||
wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
|
||||
wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
|
||||
wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
|
||||
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkf_buf
|
||||
(.I(clkfbout_clk_pll),
|
||||
.O(clkfbout_buf_clk_pll));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
IBUF #(
|
||||
.IOSTANDARD("DEFAULT"))
|
||||
clkin1_ibufg
|
||||
(.I(clk_in1),
|
||||
.O(clk_in1_clk_pll));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkout1_buf
|
||||
(.I(cpu_clk_clk_pll),
|
||||
.O(cpu_clk));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkout2_buf
|
||||
(.I(sys_clk_clk_pll),
|
||||
.O(sys_clk));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkout3_buf
|
||||
(.I(mlkem_clk_clk_pll),
|
||||
.O(mlkem_clk));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
PLLE2_ADV #(
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
.CLKFBOUT_MULT(31),
|
||||
.CLKFBOUT_PHASE(0.000000),
|
||||
.CLKIN1_PERIOD(20.000000),
|
||||
.CLKIN2_PERIOD(0.000000),
|
||||
.CLKOUT0_DIVIDE(47),
|
||||
.CLKOUT0_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT0_PHASE(0.000000),
|
||||
.CLKOUT1_DIVIDE(31),
|
||||
.CLKOUT1_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT1_PHASE(0.000000),
|
||||
.CLKOUT2_DIVIDE(78),
|
||||
.CLKOUT2_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT2_PHASE(0.000000),
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT3_PHASE(0.000000),
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT4_PHASE(0.000000),
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT5_PHASE(0.000000),
|
||||
.COMPENSATION("ZHOLD"),
|
||||
.DIVCLK_DIVIDE(1),
|
||||
.IS_CLKINSEL_INVERTED(1'b0),
|
||||
.IS_PWRDWN_INVERTED(1'b0),
|
||||
.IS_RST_INVERTED(1'b0),
|
||||
.REF_JITTER1(0.010000),
|
||||
.REF_JITTER2(0.010000),
|
||||
.STARTUP_WAIT("FALSE"))
|
||||
plle2_adv_inst
|
||||
(.CLKFBIN(clkfbout_buf_clk_pll),
|
||||
.CLKFBOUT(clkfbout_clk_pll),
|
||||
.CLKIN1(clk_in1_clk_pll),
|
||||
.CLKIN2(1'b0),
|
||||
.CLKINSEL(1'b1),
|
||||
.CLKOUT0(cpu_clk_clk_pll),
|
||||
.CLKOUT1(sys_clk_clk_pll),
|
||||
.CLKOUT2(mlkem_clk_clk_pll),
|
||||
.CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
|
||||
.CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
|
||||
.CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
|
||||
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DCLK(1'b0),
|
||||
.DEN(1'b0),
|
||||
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
|
||||
.DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
|
||||
.DWE(1'b0),
|
||||
.LOCKED(locked),
|
||||
.PWRDWN(1'b0),
|
||||
.RST(reset_high));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
plle2_adv_inst_i_1
|
||||
(.I0(resetn),
|
||||
.O(reset_high));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
@@ -1,179 +0,0 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
-- Date : Tue Jul 7 23:25:51 2026
|
||||
-- Host : fedora running 64-bit unknown
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl
|
||||
-- Design : clk_pll
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7a200tfbg676-1
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity clk_pll_clk_pll_clk_wiz is
|
||||
port (
|
||||
cpu_clk : out STD_LOGIC;
|
||||
sys_clk : out STD_LOGIC;
|
||||
mlkem_clk : out STD_LOGIC;
|
||||
resetn : in STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of clk_pll_clk_pll_clk_wiz : entity is "clk_pll_clk_wiz";
|
||||
end clk_pll_clk_pll_clk_wiz;
|
||||
|
||||
architecture STRUCTURE of clk_pll_clk_pll_clk_wiz is
|
||||
signal clk_in1_clk_pll : STD_LOGIC;
|
||||
signal clkfbout_buf_clk_pll : STD_LOGIC;
|
||||
signal clkfbout_clk_pll : STD_LOGIC;
|
||||
signal cpu_clk_clk_pll : STD_LOGIC;
|
||||
signal mlkem_clk_clk_pll : STD_LOGIC;
|
||||
signal reset_high : STD_LOGIC;
|
||||
signal sys_clk_clk_pll : STD_LOGIC;
|
||||
signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute BOX_TYPE : string;
|
||||
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE : string;
|
||||
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE : string;
|
||||
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
|
||||
attribute IFD_DELAY_VALUE : string;
|
||||
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
|
||||
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of clkout3_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE";
|
||||
begin
|
||||
clkf_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clkfbout_clk_pll,
|
||||
O => clkfbout_buf_clk_pll
|
||||
);
|
||||
clkin1_ibufg: unisim.vcomponents.IBUF
|
||||
generic map(
|
||||
IOSTANDARD => "DEFAULT"
|
||||
)
|
||||
port map (
|
||||
I => clk_in1,
|
||||
O => clk_in1_clk_pll
|
||||
);
|
||||
clkout1_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => cpu_clk_clk_pll,
|
||||
O => cpu_clk
|
||||
);
|
||||
clkout2_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => sys_clk_clk_pll,
|
||||
O => sys_clk
|
||||
);
|
||||
clkout3_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => mlkem_clk_clk_pll,
|
||||
O => mlkem_clk
|
||||
);
|
||||
plle2_adv_inst: unisim.vcomponents.PLLE2_ADV
|
||||
generic map(
|
||||
BANDWIDTH => "OPTIMIZED",
|
||||
CLKFBOUT_MULT => 31,
|
||||
CLKFBOUT_PHASE => 0.000000,
|
||||
CLKIN1_PERIOD => 20.000000,
|
||||
CLKIN2_PERIOD => 0.000000,
|
||||
CLKOUT0_DIVIDE => 47,
|
||||
CLKOUT0_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT0_PHASE => 0.000000,
|
||||
CLKOUT1_DIVIDE => 31,
|
||||
CLKOUT1_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT1_PHASE => 0.000000,
|
||||
CLKOUT2_DIVIDE => 78,
|
||||
CLKOUT2_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT2_PHASE => 0.000000,
|
||||
CLKOUT3_DIVIDE => 1,
|
||||
CLKOUT3_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT3_PHASE => 0.000000,
|
||||
CLKOUT4_DIVIDE => 1,
|
||||
CLKOUT4_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT4_PHASE => 0.000000,
|
||||
CLKOUT5_DIVIDE => 1,
|
||||
CLKOUT5_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT5_PHASE => 0.000000,
|
||||
COMPENSATION => "ZHOLD",
|
||||
DIVCLK_DIVIDE => 1,
|
||||
IS_CLKINSEL_INVERTED => '0',
|
||||
IS_PWRDWN_INVERTED => '0',
|
||||
IS_RST_INVERTED => '0',
|
||||
REF_JITTER1 => 0.010000,
|
||||
REF_JITTER2 => 0.010000,
|
||||
STARTUP_WAIT => "FALSE"
|
||||
)
|
||||
port map (
|
||||
CLKFBIN => clkfbout_buf_clk_pll,
|
||||
CLKFBOUT => clkfbout_clk_pll,
|
||||
CLKIN1 => clk_in1_clk_pll,
|
||||
CLKIN2 => '0',
|
||||
CLKINSEL => '1',
|
||||
CLKOUT0 => cpu_clk_clk_pll,
|
||||
CLKOUT1 => sys_clk_clk_pll,
|
||||
CLKOUT2 => mlkem_clk_clk_pll,
|
||||
CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED,
|
||||
CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED,
|
||||
CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED,
|
||||
DADDR(6 downto 0) => B"0000000",
|
||||
DCLK => '0',
|
||||
DEN => '0',
|
||||
DI(15 downto 0) => B"0000000000000000",
|
||||
DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0),
|
||||
DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED,
|
||||
DWE => '0',
|
||||
LOCKED => locked,
|
||||
PWRDWN => '0',
|
||||
RST => reset_high
|
||||
);
|
||||
plle2_adv_inst_i_1: unisim.vcomponents.LUT1
|
||||
generic map(
|
||||
INIT => X"1"
|
||||
)
|
||||
port map (
|
||||
I0 => resetn,
|
||||
O => reset_high
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity clk_pll is
|
||||
port (
|
||||
cpu_clk : out STD_LOGIC;
|
||||
sys_clk : out STD_LOGIC;
|
||||
mlkem_clk : out STD_LOGIC;
|
||||
resetn : in STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of clk_pll : entity is true;
|
||||
end clk_pll;
|
||||
|
||||
architecture STRUCTURE of clk_pll is
|
||||
begin
|
||||
inst: entity work.clk_pll_clk_pll_clk_wiz
|
||||
port map (
|
||||
clk_in1 => clk_in1,
|
||||
cpu_clk => cpu_clk,
|
||||
locked => locked,
|
||||
mlkem_clk => mlkem_clk,
|
||||
resetn => resetn,
|
||||
sys_clk => sys_clk
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -1,25 +0,0 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
// Date : Tue Jul 7 23:25:51 2026
|
||||
// Host : fedora running 64-bit unknown
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_stub.v
|
||||
// Design : clk_pll
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7a200tfbg676-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
module clk_pll(cpu_clk, sys_clk, mlkem_clk, resetn, locked,
|
||||
clk_in1)
|
||||
/* synthesis syn_black_box black_box_pad_pin="cpu_clk,sys_clk,mlkem_clk,resetn,locked,clk_in1" */;
|
||||
output cpu_clk;
|
||||
output sys_clk;
|
||||
output mlkem_clk;
|
||||
input resetn;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
endmodule
|
||||
@@ -1,33 +0,0 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
-- Date : Tue Jul 7 23:25:51 2026
|
||||
-- Host : fedora running 64-bit unknown
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_stub.vhdl
|
||||
-- Design : clk_pll
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7a200tfbg676-1
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity clk_pll is
|
||||
Port (
|
||||
cpu_clk : out STD_LOGIC;
|
||||
sys_clk : out STD_LOGIC;
|
||||
mlkem_clk : out STD_LOGIC;
|
||||
resetn : in STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
|
||||
end clk_pll;
|
||||
|
||||
architecture stub of clk_pll is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "cpu_clk,sys_clk,mlkem_clk,resetn,locked,clk_in1";
|
||||
begin
|
||||
end;
|
||||
@@ -64,6 +64,7 @@ module cdma_matmul_bridge #(
|
||||
output logic mat_done_clear,
|
||||
output logic mat_crc_clear,
|
||||
input logic mat_done,
|
||||
input logic mat_crc_idle,
|
||||
|
||||
output logic seq_done_irq
|
||||
);
|
||||
@@ -102,10 +103,10 @@ module cdma_matmul_bridge #(
|
||||
logic [31:0] load_next_dst_addr;
|
||||
logic [31:0] bank_dst_addr [2];
|
||||
|
||||
logic rd_busy;
|
||||
logic wr_busy;
|
||||
logic rd_active_bank;
|
||||
logic wr_active_bank;
|
||||
logic [1:0] rd_outstanding_count;
|
||||
logic [1:0] rd_bank_fifo;
|
||||
logic [1:0] compute_q;
|
||||
logic [1:0] compute_q_count;
|
||||
logic mat_done_seen;
|
||||
@@ -136,6 +137,7 @@ module cdma_matmul_bridge #(
|
||||
wire retire_from_store = seq_busy && cdma_wr_req_done;
|
||||
wire retire_from_compute = seq_busy && seq_skip_writeback && mat_done_event && (compute_q_count != 2'd0);
|
||||
wire [31:0] retire_inc = {31'd0, retire_from_store} + {31'd0, retire_from_compute};
|
||||
wire rd_req_fire = cdma_rd_req_valid && cdma_rd_req_ready;
|
||||
|
||||
function automatic logic [31:0] apply_wstrb(
|
||||
input logic [31:0] old_val,
|
||||
@@ -257,10 +259,10 @@ module cdma_matmul_bridge #(
|
||||
load_next_dst_addr <= 32'd0;
|
||||
bank_dst_addr[0] <= 32'd0;
|
||||
bank_dst_addr[1] <= 32'd0;
|
||||
rd_busy <= 1'b0;
|
||||
wr_busy <= 1'b0;
|
||||
rd_active_bank <= 1'b0;
|
||||
wr_active_bank <= 1'b0;
|
||||
rd_outstanding_count <= 2'd0;
|
||||
rd_bank_fifo <= 2'b00;
|
||||
compute_q <= 2'b00;
|
||||
compute_q_count <= 2'd0;
|
||||
mat_done_seen <= 1'b0;
|
||||
@@ -290,7 +292,7 @@ module cdma_matmul_bridge #(
|
||||
if (done_clear_req)
|
||||
seq_done_flag <= 1'b0;
|
||||
|
||||
if (cdma_rd_req_valid && cdma_rd_req_ready)
|
||||
if (rd_req_fire)
|
||||
cdma_rd_req_valid <= 1'b0;
|
||||
|
||||
if (cdma_wr_req_valid && cdma_wr_req_ready)
|
||||
@@ -313,8 +315,9 @@ module cdma_matmul_bridge #(
|
||||
load_next_dst_addr <= seq_dst_base;
|
||||
bank_dst_addr[0] <= 32'd0;
|
||||
bank_dst_addr[1] <= 32'd0;
|
||||
rd_busy <= 1'b0;
|
||||
wr_busy <= 1'b0;
|
||||
rd_outstanding_count <= 2'd0;
|
||||
rd_bank_fifo <= 2'b00;
|
||||
compute_q <= 2'b00;
|
||||
compute_q_count <= 2'd0;
|
||||
mat_done_seen <= 1'b1;
|
||||
@@ -325,18 +328,50 @@ module cdma_matmul_bridge #(
|
||||
end else if (seq_busy) begin
|
||||
if (retire_inc != 32'd0) begin
|
||||
groups_retired <= groups_retired + retire_inc;
|
||||
if ((groups_retired + retire_inc) >= seq_groups) begin
|
||||
seq_busy <= 1'b0;
|
||||
seq_done_flag <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
if (cdma_rd_req_done) begin
|
||||
rd_busy <= 1'b0;
|
||||
bank_load_active[rd_active_bank] <= 1'b0;
|
||||
bank_ab_valid[rd_active_bank] <= 1'b1;
|
||||
// The final compute completion can precede the recursive CRC
|
||||
// consumer. Do not expose sequence completion until it drains.
|
||||
if ((groups_retired >= seq_groups) && mat_crc_idle) begin
|
||||
seq_busy <= 1'b0;
|
||||
seq_done_flag <= 1'b1;
|
||||
end
|
||||
|
||||
if (cdma_rd_req_done && (rd_outstanding_count != 2'd0)) begin
|
||||
bank_load_active[rd_bank_fifo[0]] <= 1'b0;
|
||||
bank_ab_valid[rd_bank_fifo[0]] <= 1'b1;
|
||||
end
|
||||
|
||||
|
||||
// Track the active read and one prefetched read. Completion
|
||||
// pulses are in request order, so a two-entry bank FIFO is
|
||||
// sufficient to associate each RLAST with its destination.
|
||||
case ({rd_req_fire, cdma_rd_req_done})
|
||||
2'b10: begin
|
||||
if (rd_outstanding_count == 2'd0)
|
||||
rd_bank_fifo[0] <= cdma_rd_req_ep_bank[0];
|
||||
else
|
||||
rd_bank_fifo[1] <= cdma_rd_req_ep_bank[0];
|
||||
rd_outstanding_count <= rd_outstanding_count + 2'd1;
|
||||
end
|
||||
2'b01: begin
|
||||
if (rd_outstanding_count == 2'd2)
|
||||
rd_bank_fifo[0] <= rd_bank_fifo[1];
|
||||
if (rd_outstanding_count != 2'd0)
|
||||
rd_outstanding_count <= rd_outstanding_count - 2'd1;
|
||||
end
|
||||
2'b11: begin
|
||||
if (rd_outstanding_count == 2'd1) begin
|
||||
rd_bank_fifo[0] <= cdma_rd_req_ep_bank[0];
|
||||
end else begin
|
||||
rd_bank_fifo[0] <= rd_bank_fifo[1];
|
||||
rd_bank_fifo[1] <= cdma_rd_req_ep_bank[0];
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
end
|
||||
endcase
|
||||
|
||||
if (cdma_wr_req_done) begin
|
||||
wr_busy <= 1'b0;
|
||||
bank_store_active[wr_active_bank] <= 1'b0;
|
||||
@@ -354,15 +389,14 @@ module cdma_matmul_bridge #(
|
||||
compute_q_count <= compute_q_count - 2'd1;
|
||||
end
|
||||
|
||||
if (!rd_busy && !cdma_rd_req_valid && (load_next_idx < seq_groups) && load_target_free) begin
|
||||
if ((rd_outstanding_count < 2'd2) && !cdma_rd_req_valid &&
|
||||
(load_next_idx < seq_groups) && load_target_free) begin
|
||||
cdma_rd_req_src <= load_next_src_addr;
|
||||
cdma_rd_req_bytes <= MAT_AB_BYTES;
|
||||
cdma_rd_req_ep_id <= 4'd0;
|
||||
cdma_rd_req_ep_bank <= {3'b000, load_target_bank};
|
||||
cdma_rd_req_ep_word_off <= 8'd0;
|
||||
cdma_rd_req_valid <= 1'b1;
|
||||
rd_busy <= 1'b1;
|
||||
rd_active_bank <= load_target_bank;
|
||||
bank_load_active[load_target_bank] <= 1'b1;
|
||||
bank_group_idx[load_target_bank] <= load_next_idx;
|
||||
bank_dst_addr[load_target_bank] <= load_next_dst_addr;
|
||||
|
||||
@@ -423,6 +423,13 @@ module snix_axil_cdma_mux #(
|
||||
logic [7:0] ext_rd_word_addr_r;
|
||||
logic [3:0] ext_rd_ep_id_r;
|
||||
logic [3:0] ext_rd_ep_bank_r;
|
||||
logic ext_rd_queue_valid;
|
||||
logic ext_rd_queue_ar_sent;
|
||||
logic [ADDR_WIDTH-1:0] ext_rd_queue_addr;
|
||||
logic [31:0] ext_rd_queue_bytes;
|
||||
logic [7:0] ext_rd_queue_word_addr;
|
||||
logic [3:0] ext_rd_queue_ep_id;
|
||||
logic [3:0] ext_rd_queue_ep_bank;
|
||||
|
||||
logic [ADDR_WIDTH-1:0] ext_wr_addr_r;
|
||||
logic [31:0] ext_wr_bytes_left;
|
||||
@@ -434,7 +441,10 @@ module snix_axil_cdma_mux #(
|
||||
wire ext_wr_active = (ext_wr_state != EXT_WR_IDLE);
|
||||
wire ext_rd_accept = ext_rd_req_valid && ext_rd_req_ready;
|
||||
wire ext_wr_accept = ext_wr_req_valid && ext_wr_req_ready;
|
||||
wire ext_any_busy_or_req = ext_rd_active || ext_wr_active || ext_rd_req_valid || ext_wr_req_valid;
|
||||
wire ext_rd_prefetch_ar = (ext_rd_state == EXT_RD_READ) &&
|
||||
ext_rd_queue_valid && !ext_rd_queue_ar_sent;
|
||||
wire ext_any_busy_or_req = ext_rd_active || ext_rd_queue_valid || ext_wr_active ||
|
||||
ext_rd_req_valid || ext_wr_req_valid;
|
||||
wire use_ep_engine = ((state == RUN) && (engine_mode != MODE_MEM2MEM));
|
||||
|
||||
// Dynamic routing to the engine based on current active channel
|
||||
@@ -478,8 +488,12 @@ module snix_axil_cdma_mux #(
|
||||
assign mm2mm_bready = ext_wr_active ? (ext_wr_state == EXT_WR_BRESP) : (use_ep_engine ? ep_bready : core_bready);
|
||||
|
||||
assign mm2mm_arid = ext_rd_active ? '0 : (use_ep_engine ? ep_arid : core_arid);
|
||||
assign mm2mm_araddr = ext_rd_active ? ext_rd_addr_r : (use_ep_engine ? ep_araddr : core_araddr);
|
||||
assign mm2mm_arlen = ext_rd_active ? (((ext_rd_bytes_left[31:2] == 30'd0) ? 8'd1 : ext_rd_bytes_left[9:2]) - 8'd1) : (use_ep_engine ? ep_arlen : core_arlen);
|
||||
assign mm2mm_araddr = ext_rd_prefetch_ar ? ext_rd_queue_addr :
|
||||
(ext_rd_active ? ext_rd_addr_r : (use_ep_engine ? ep_araddr : core_araddr));
|
||||
assign mm2mm_arlen = ext_rd_prefetch_ar ?
|
||||
(((ext_rd_queue_bytes[31:2] == 30'd0) ? 8'd1 : ext_rd_queue_bytes[9:2]) - 8'd1) :
|
||||
(ext_rd_active ? (((ext_rd_bytes_left[31:2] == 30'd0) ? 8'd1 : ext_rd_bytes_left[9:2]) - 8'd1) :
|
||||
(use_ep_engine ? ep_arlen : core_arlen));
|
||||
assign mm2mm_arsize = ext_rd_active ? 3'd2 : (use_ep_engine ? ep_arsize : core_arsize);
|
||||
assign mm2mm_arburst = ext_rd_active ? 2'b01 : (use_ep_engine ? ep_arburst : core_arburst);
|
||||
assign mm2mm_arlock = ext_rd_active ? 1'b0 : (use_ep_engine ? ep_arlock : core_arlock);
|
||||
@@ -487,7 +501,8 @@ module snix_axil_cdma_mux #(
|
||||
assign mm2mm_arprot = ext_rd_active ? 3'b0 : (use_ep_engine ? ep_arprot : core_arprot);
|
||||
assign mm2mm_arqos = ext_rd_active ? 4'b0 : (use_ep_engine ? ep_arqos : core_arqos);
|
||||
assign mm2mm_aruser = ext_rd_active ? '0 : (use_ep_engine ? ep_aruser : core_aruser);
|
||||
assign mm2mm_arvalid = ext_rd_active ? (ext_rd_state == EXT_RD_AR) : (use_ep_engine ? ep_arvalid : core_arvalid);
|
||||
assign mm2mm_arvalid = ext_rd_active ? ((ext_rd_state == EXT_RD_AR) || ext_rd_prefetch_ar) :
|
||||
(use_ep_engine ? ep_arvalid : core_arvalid);
|
||||
assign mm2mm_rready = ext_rd_active ? ((ext_rd_state == EXT_RD_READ) && ep_wr_ready) : (use_ep_engine ? ep_rready : core_rready);
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
@@ -597,7 +612,10 @@ module snix_axil_cdma_mux #(
|
||||
// ==========================================
|
||||
// Generic external endpoint requester
|
||||
// ==========================================
|
||||
assign ext_rd_req_ready = (state == IDLE) && (ep_state == EP_IDLE) && !ext_rd_active;
|
||||
assign ext_rd_req_ready = (state == IDLE) && (ep_state == EP_IDLE) && !ext_wr_active &&
|
||||
((ext_rd_state == EXT_RD_IDLE) ||
|
||||
((ext_rd_state == EXT_RD_READ) && !ext_rd_queue_valid &&
|
||||
!ext_rd_done_fire));
|
||||
assign ext_wr_req_ready = (state == IDLE) && (ep_state == EP_IDLE) && !ext_wr_active;
|
||||
assign ext_rd_req_done = ext_rd_done_fire;
|
||||
assign ext_wr_req_done = ext_wr_done_fire;
|
||||
@@ -610,7 +628,17 @@ module snix_axil_cdma_mux #(
|
||||
ext_rd_word_addr_r <= '0;
|
||||
ext_rd_ep_id_r <= '0;
|
||||
ext_rd_ep_bank_r <= '0;
|
||||
ext_rd_queue_valid <= 1'b0;
|
||||
ext_rd_queue_ar_sent <= 1'b0;
|
||||
ext_rd_queue_addr <= '0;
|
||||
ext_rd_queue_bytes <= '0;
|
||||
ext_rd_queue_word_addr <= '0;
|
||||
ext_rd_queue_ep_id <= '0;
|
||||
ext_rd_queue_ep_bank <= '0;
|
||||
end else begin
|
||||
if (ext_rd_prefetch_ar && mm2mm_arvalid && mm2mm_arready)
|
||||
ext_rd_queue_ar_sent <= 1'b1;
|
||||
|
||||
case (ext_rd_state)
|
||||
EXT_RD_IDLE: begin
|
||||
if (ext_rd_accept) begin
|
||||
@@ -629,11 +657,37 @@ module snix_axil_cdma_mux #(
|
||||
end
|
||||
|
||||
EXT_RD_READ: begin
|
||||
if (ext_rd_accept) begin
|
||||
ext_rd_queue_valid <= 1'b1;
|
||||
ext_rd_queue_ar_sent <= 1'b0;
|
||||
ext_rd_queue_addr <= ext_rd_req_src;
|
||||
ext_rd_queue_bytes <= ext_rd_req_bytes;
|
||||
ext_rd_queue_word_addr <= ext_rd_req_ep_word_off;
|
||||
ext_rd_queue_ep_id <= ext_rd_req_ep_id;
|
||||
ext_rd_queue_ep_bank <= ext_rd_req_ep_bank;
|
||||
end
|
||||
|
||||
if (mm2mm_rvalid && mm2mm_rready) begin
|
||||
ext_rd_word_addr_r <= ext_rd_word_addr_r + 8'd1;
|
||||
ext_rd_bytes_left <= (ext_rd_bytes_left > 32'd4) ? (ext_rd_bytes_left - 32'd4) : 32'd0;
|
||||
if (mm2mm_rlast)
|
||||
ext_rd_state <= EXT_RD_IDLE;
|
||||
if (mm2mm_rlast) begin
|
||||
if (ext_rd_queue_valid) begin
|
||||
ext_rd_addr_r <= ext_rd_queue_addr;
|
||||
ext_rd_bytes_left <= ext_rd_queue_bytes;
|
||||
ext_rd_word_addr_r <= ext_rd_queue_word_addr;
|
||||
ext_rd_ep_id_r <= ext_rd_queue_ep_id;
|
||||
ext_rd_ep_bank_r <= ext_rd_queue_ep_bank;
|
||||
ext_rd_queue_valid <= 1'b0;
|
||||
ext_rd_queue_ar_sent <= 1'b0;
|
||||
if (ext_rd_queue_ar_sent ||
|
||||
(ext_rd_prefetch_ar && mm2mm_arvalid && mm2mm_arready))
|
||||
ext_rd_state <= EXT_RD_READ;
|
||||
else
|
||||
ext_rd_state <= EXT_RD_AR;
|
||||
end else begin
|
||||
ext_rd_state <= EXT_RD_IDLE;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
@@ -102,6 +102,7 @@ module matmul_axi_slave (
|
||||
input mat_done_clear,
|
||||
input mat_crc_clear,
|
||||
output mat_done,
|
||||
output mat_crc_idle,
|
||||
|
||||
// Interrupt output (active high level, pulsed by calc_done)
|
||||
output intr
|
||||
@@ -184,22 +185,44 @@ module matmul_axi_slave (
|
||||
reg [31:0] crc32_table [0:255];
|
||||
reg [31:0] crc_reg;
|
||||
|
||||
function [31:0] crc32_word_next;
|
||||
function [31:0] crc32_update_word;
|
||||
input [31:0] crc_in;
|
||||
input [31:0] data_in;
|
||||
reg [31:0] t0, c0, t1, c1, t2, c2, t3;
|
||||
reg [31:0] c0;
|
||||
reg [31:0] c1;
|
||||
reg [31:0] c2;
|
||||
begin
|
||||
t0 = crc32_table[(crc_in[7:0] ^ data_in[7:0])];
|
||||
c0 = t0 ^ {8'h00, crc_in[31:8]};
|
||||
t1 = crc32_table[(c0[7:0] ^ data_in[15:8])];
|
||||
c1 = t1 ^ {8'h00, c0[31:8]};
|
||||
t2 = crc32_table[(c1[7:0] ^ data_in[23:16])];
|
||||
c2 = t2 ^ {8'h00, c1[31:8]};
|
||||
t3 = crc32_table[(c2[7:0] ^ data_in[31:24])];
|
||||
crc32_word_next = t3 ^ {8'h00, c2[31:8]};
|
||||
c0 = crc32_table[(crc_in[7:0] ^ data_in[7:0])] ^ {8'h00, crc_in[31:8]};
|
||||
c1 = crc32_table[(c0[7:0] ^ data_in[15:8])] ^ {8'h00, c0[31:8]};
|
||||
c2 = crc32_table[(c1[7:0] ^ data_in[23:16])] ^ {8'h00, c1[31:8]};
|
||||
crc32_update_word = crc32_table[(c2[7:0] ^ data_in[31:24])] ^
|
||||
{8'h00, c2[31:8]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [31:0] crc32_update_6bytes;
|
||||
input [31:0] crc_in;
|
||||
input [47:0] data_in;
|
||||
reg [31:0] c;
|
||||
integer byte_idx;
|
||||
begin
|
||||
c = crc_in;
|
||||
for (byte_idx = 0; byte_idx < 6; byte_idx = byte_idx + 1)
|
||||
c = crc32_table[(c[7:0] ^ data_in[byte_idx*8 +: 8])] ^
|
||||
{8'h00, c[31:8]};
|
||||
crc32_update_6bytes = c;
|
||||
end
|
||||
endfunction
|
||||
|
||||
localparam CRC_FIFO_DEPTH = 32;
|
||||
reg [65:0] crc_fifo [0:CRC_FIFO_DEPTH-1];
|
||||
reg [4:0] crc_fifo_wr_ptr;
|
||||
reg [4:0] crc_fifo_rd_ptr;
|
||||
reg [5:0] crc_fifo_count;
|
||||
reg crc_c66_busy;
|
||||
reg [65:0] crc_c66_data;
|
||||
reg [31:0] crc_c66_half;
|
||||
|
||||
initial begin
|
||||
crc32_table[0 ] = 32'h00000000; crc32_table[1 ] = 32'h77073096;
|
||||
crc32_table[2 ] = 32'hEE0E612C; crc32_table[3 ] = 32'h990951BA;
|
||||
@@ -587,10 +610,21 @@ module matmul_axi_slave (
|
||||
reg [4:0] pipe_cnt;
|
||||
wire [65:0] calc_c_result = ({2'b0, mult_p[0]} + {2'b0, mult_p[1]}) +
|
||||
({2'b0, mult_p[2]} + {2'b0, mult_p[3]});
|
||||
wire calc_crc_valid = acc_valid_d4;
|
||||
wire [31:0] crc_calc_0 = crc32_word_next(crc_reg, calc_c_result[31:0]);
|
||||
wire [31:0] crc_calc_1 = crc32_word_next(crc_calc_0, calc_c_result[63:32]);
|
||||
wire [31:0] crc_calc_2 = crc32_word_next(crc_calc_1, {30'b0, calc_c_result[65:64]});
|
||||
|
||||
wire crc_fifo_empty = (crc_fifo_count == 6'd0);
|
||||
wire crc_fifo_push = acc_valid_d4;
|
||||
wire crc_fifo_pop = !crc_c66_busy && !crc_fifo_empty;
|
||||
wire [31:0] crc_c66_first_next =
|
||||
crc32_update_6bytes(crc_reg, crc_fifo[crc_fifo_rd_ptr][47:0]);
|
||||
wire [47:0] crc_c66_second_data = {30'b0, crc_c66_data[65:48]};
|
||||
wire [31:0] crc_c66_final_next =
|
||||
crc32_update_6bytes(crc_c66_half, crc_c66_second_data);
|
||||
|
||||
// Reserve space for results already in the four-stage multiplier pipeline.
|
||||
wire crc_issue_ready = (crc_fifo_count < 6'd24);
|
||||
assign mat_crc_idle = crc_fifo_empty && !crc_c66_busy &&
|
||||
!acc_valid_d1 && !acc_valid_d2 &&
|
||||
!acc_valid_d3 && !acc_valid_d4;
|
||||
|
||||
task start_calc_bank;
|
||||
input bank;
|
||||
@@ -616,14 +650,46 @@ module matmul_axi_slave (
|
||||
end
|
||||
endtask
|
||||
|
||||
// CRC tracks completed C elements directly, independent of result writeback.
|
||||
// Buffer completed C elements so the recursive CRC path is split across
|
||||
// two cycles without reducing the multiplier's burst throughput.
|
||||
always @(posedge clk) begin
|
||||
if (!resetn) begin
|
||||
crc_reg <= 32'hFFFFFFFF;
|
||||
crc_reg <= 32'hFFFFFFFF;
|
||||
crc_fifo_wr_ptr <= 5'd0;
|
||||
crc_fifo_rd_ptr <= 5'd0;
|
||||
crc_fifo_count <= 6'd0;
|
||||
crc_c66_busy <= 1'b0;
|
||||
crc_c66_data <= 66'd0;
|
||||
crc_c66_half <= 32'd0;
|
||||
end else if (crc_clear_pulse) begin
|
||||
crc_reg <= 32'hFFFFFFFF;
|
||||
end else if (calc_crc_valid) begin
|
||||
crc_reg <= crc_calc_2;
|
||||
crc_reg <= 32'hFFFFFFFF;
|
||||
crc_fifo_wr_ptr <= 5'd0;
|
||||
crc_fifo_rd_ptr <= 5'd0;
|
||||
crc_fifo_count <= 6'd0;
|
||||
crc_c66_busy <= 1'b0;
|
||||
crc_c66_data <= 66'd0;
|
||||
crc_c66_half <= 32'd0;
|
||||
end else begin
|
||||
if (crc_fifo_push) begin
|
||||
crc_fifo[crc_fifo_wr_ptr] <= calc_c_result;
|
||||
crc_fifo_wr_ptr <= crc_fifo_wr_ptr + 5'd1;
|
||||
end
|
||||
|
||||
case ({crc_fifo_push, crc_fifo_pop})
|
||||
2'b10: crc_fifo_count <= crc_fifo_count + 6'd1;
|
||||
2'b01: crc_fifo_count <= crc_fifo_count - 6'd1;
|
||||
default: crc_fifo_count <= crc_fifo_count;
|
||||
endcase
|
||||
|
||||
if (crc_c66_busy) begin
|
||||
crc_reg <= crc_c66_final_next;
|
||||
crc_c66_busy <= 1'b0;
|
||||
end else if (crc_fifo_pop) begin
|
||||
crc_c66_data <= crc_fifo[crc_fifo_rd_ptr];
|
||||
crc_c66_half <= crc_c66_first_next;
|
||||
crc_c66_busy <= 1'b1;
|
||||
crc_fifo_rd_ptr <= crc_fifo_rd_ptr + 5'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
@@ -676,21 +742,25 @@ module matmul_axi_slave (
|
||||
end
|
||||
|
||||
C_RUN: begin
|
||||
// Issue 4 new operands every cycle (pipe_cnt 0-15, 16 rounds)
|
||||
// Issue one C element per cycle while the CRC result FIFO
|
||||
// has room for this result and the in-flight pipeline.
|
||||
if (pipe_cnt < 5'd16) begin
|
||||
acc_idx_d1 <= pipe_cnt[3:0];
|
||||
acc_bank_d1 <= cur_bank;
|
||||
acc_valid_d1 <= 1'b1;
|
||||
if (cur_bank == 1'b0) begin
|
||||
m_in_a[0] <= b0_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b0_b[{2'd0, pipe_cnt[1:0]}];
|
||||
m_in_a[1] <= b0_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b0_b[{2'd1, pipe_cnt[1:0]}];
|
||||
m_in_a[2] <= b0_a[{pipe_cnt[3:2], 2'd2}]; m_in_b[2] <= b0_b[{2'd2, pipe_cnt[1:0]}];
|
||||
m_in_a[3] <= b0_a[{pipe_cnt[3:2], 2'd3}]; m_in_b[3] <= b0_b[{2'd3, pipe_cnt[1:0]}];
|
||||
end else begin
|
||||
m_in_a[0] <= b1_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b1_b[{2'd0, pipe_cnt[1:0]}];
|
||||
m_in_a[1] <= b1_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b1_b[{2'd1, pipe_cnt[1:0]}];
|
||||
m_in_a[2] <= b1_a[{pipe_cnt[3:2], 2'd2}]; m_in_b[2] <= b1_b[{2'd2, pipe_cnt[1:0]}];
|
||||
m_in_a[3] <= b1_a[{pipe_cnt[3:2], 2'd3}]; m_in_b[3] <= b1_b[{2'd3, pipe_cnt[1:0]}];
|
||||
if (crc_issue_ready) begin
|
||||
acc_idx_d1 <= pipe_cnt[3:0];
|
||||
acc_bank_d1 <= cur_bank;
|
||||
acc_valid_d1 <= 1'b1;
|
||||
if (cur_bank == 1'b0) begin
|
||||
m_in_a[0] <= b0_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b0_b[{2'd0, pipe_cnt[1:0]}];
|
||||
m_in_a[1] <= b0_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b0_b[{2'd1, pipe_cnt[1:0]}];
|
||||
m_in_a[2] <= b0_a[{pipe_cnt[3:2], 2'd2}]; m_in_b[2] <= b0_b[{2'd2, pipe_cnt[1:0]}];
|
||||
m_in_a[3] <= b0_a[{pipe_cnt[3:2], 2'd3}]; m_in_b[3] <= b0_b[{2'd3, pipe_cnt[1:0]}];
|
||||
end else begin
|
||||
m_in_a[0] <= b1_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b1_b[{2'd0, pipe_cnt[1:0]}];
|
||||
m_in_a[1] <= b1_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b1_b[{2'd1, pipe_cnt[1:0]}];
|
||||
m_in_a[2] <= b1_a[{pipe_cnt[3:2], 2'd2}]; m_in_b[2] <= b1_b[{2'd2, pipe_cnt[1:0]}];
|
||||
m_in_a[3] <= b1_a[{pipe_cnt[3:2], 2'd3}]; m_in_b[3] <= b1_b[{2'd3, pipe_cnt[1:0]}];
|
||||
end
|
||||
pipe_cnt <= pipe_cnt + 5'd1;
|
||||
end
|
||||
end
|
||||
|
||||
@@ -706,16 +776,14 @@ module matmul_axi_slave (
|
||||
calc_done_pulse <= 1'b1;
|
||||
end
|
||||
|
||||
if (pipe_cnt < 5'd16) begin
|
||||
pipe_cnt <= pipe_cnt + 5'd1;
|
||||
end else if (cur_bank == 1'b0 && req_1) begin
|
||||
if (pipe_cnt >= 5'd16 && cur_bank == 1'b0 && req_1) begin
|
||||
start_calc_bank(1'b1);
|
||||
end else if (cur_bank == 1'b1 && req_0) begin
|
||||
end else if (pipe_cnt >= 5'd16 && cur_bank == 1'b1 && req_0) begin
|
||||
start_calc_bank(1'b0);
|
||||
end else if (acc_valid_d4 && acc_idx_d4 == 4'd15) begin
|
||||
end else if (pipe_cnt >= 5'd16 && acc_valid_d4 && acc_idx_d4 == 4'd15) begin
|
||||
busy <= 1'b0;
|
||||
state <= C_IDLE;
|
||||
end else begin
|
||||
end else if (pipe_cnt >= 5'd16) begin
|
||||
pipe_cnt <= pipe_cnt + 5'd1;
|
||||
end
|
||||
end
|
||||
|
||||
@@ -30,15 +30,16 @@
|
||||
|
||||
`include "defines.vh"
|
||||
|
||||
/* verilator lint_off UNUSED */
|
||||
/* verilator lint_off UNUSEDPARAM */
|
||||
(* use_dsp = "no" *)
|
||||
module sample_ntt_sync #(parameter K = 4) (
|
||||
/* verilator lint_on UNUSED */
|
||||
/* verilator lint_on UNUSEDPARAM */
|
||||
input clk,
|
||||
input rst_n,
|
||||
input [255:0] rho_i,
|
||||
/* verilator lint_off UNUSED */
|
||||
/* verilator lint_off UNUSEDSIGNAL */
|
||||
input [2:0] k_i,
|
||||
/* verilator lint_on UNUSED */
|
||||
/* verilator lint_on UNUSEDSIGNAL */
|
||||
input [1:0] i_idx,
|
||||
input [1:0] j_idx,
|
||||
input valid_i,
|
||||
@@ -72,12 +73,12 @@ module sample_ntt_sync #(parameter K = 4) (
|
||||
// ================================================================
|
||||
// Registered inputs (captured on valid_i)
|
||||
// ================================================================
|
||||
/* verilator lint_off UNUSED */
|
||||
/* verilator lint_off UNUSEDSIGNAL */
|
||||
reg [255:0] rho_r;
|
||||
reg [2:0] k_r;
|
||||
reg [1:0] i_r;
|
||||
reg [1:0] j_r;
|
||||
/* verilator lint_on UNUSED */
|
||||
/* verilator lint_on UNUSEDSIGNAL */
|
||||
|
||||
// ================================================================
|
||||
// Coefficient counter (0..256). 9 bits to avoid overflow when
|
||||
@@ -163,9 +164,9 @@ module sample_ntt_sync #(parameter K = 4) (
|
||||
// ================================================================
|
||||
wire kc_valid_i;
|
||||
wire [1599:0] kc_state_i;
|
||||
/* verilator lint_off UNUSED */
|
||||
/* verilator lint_off UNUSEDSIGNAL */
|
||||
wire kc_ready_o;
|
||||
/* verilator lint_on UNUSED */
|
||||
/* verilator lint_on UNUSEDSIGNAL */
|
||||
wire [1599:0] kc_state_o;
|
||||
wire kc_valid_o;
|
||||
|
||||
@@ -209,6 +210,10 @@ module sample_ntt_sync #(parameter K = 4) (
|
||||
// d2 rejected, no longer need coefficients, or d2 was just accepted out.
|
||||
wire grp_done = (state_r == ST_SQUEEZE) && (sq_phase_r == 2'd2) &&
|
||||
(!d2_acc_r || !need_more || (valid_o_r && ready_i));
|
||||
// `need_more` observes the registered counter before the final d2
|
||||
// handshake increments it. Detect that boundary explicitly so a full
|
||||
// rate block does not launch an unnecessary final re-permutation.
|
||||
wire completes_output = valid_o_r && ready_i && (coeff_cnt_r == 9'd255);
|
||||
|
||||
// ================================================================
|
||||
// FSM: state_next (combinational)
|
||||
@@ -234,7 +239,7 @@ module sample_ntt_sync #(parameter K = 4) (
|
||||
// next group in this block, re-permute (block exhausted), or
|
||||
// finish.
|
||||
if (grp_done) begin
|
||||
if (!need_more)
|
||||
if (!need_more || completes_output)
|
||||
state_next = ST_DONE;
|
||||
else if (grp_ptr_r < GRP_MAX)
|
||||
state_next = ST_SQUEEZE; // next group, no re-permute
|
||||
|
||||
@@ -43,15 +43,16 @@
|
||||
|
||||
`include "defines.vh"
|
||||
|
||||
/* verilator lint_off UNUSED */
|
||||
/* verilator lint_off UNUSEDPARAM */
|
||||
(* use_dsp = "no" *)
|
||||
module sample_ntt_sync_shared #(parameter K = 4) (
|
||||
/* verilator lint_on UNUSED */
|
||||
/* verilator lint_on UNUSEDPARAM */
|
||||
input clk,
|
||||
input rst_n,
|
||||
input [255:0] rho_i,
|
||||
/* verilator lint_off UNUSED */
|
||||
/* verilator lint_off UNUSEDSIGNAL */
|
||||
input [2:0] k_i,
|
||||
/* verilator lint_on UNUSED */
|
||||
/* verilator lint_on UNUSEDSIGNAL */
|
||||
input [1:0] i_idx,
|
||||
input [1:0] j_idx,
|
||||
input valid_i,
|
||||
@@ -67,9 +68,9 @@ module sample_ntt_sync_shared #(parameter K = 4) (
|
||||
output kc_ready_i,
|
||||
output [1599:0] kc_state_i,
|
||||
output kc_valid_i,
|
||||
/* verilator lint_off UNUSED */
|
||||
/* verilator lint_off UNUSEDSIGNAL */
|
||||
input kc_ready_o
|
||||
/* verilator lint_on UNUSED */
|
||||
/* verilator lint_on UNUSEDSIGNAL */
|
||||
);
|
||||
|
||||
// ================================================================
|
||||
@@ -95,12 +96,12 @@ module sample_ntt_sync_shared #(parameter K = 4) (
|
||||
// ================================================================
|
||||
// Registered inputs (captured on valid_i)
|
||||
// ================================================================
|
||||
/* verilator lint_off UNUSED */
|
||||
/* verilator lint_off UNUSEDSIGNAL */
|
||||
reg [255:0] rho_r;
|
||||
reg [2:0] k_r;
|
||||
reg [1:0] i_r;
|
||||
reg [1:0] j_r;
|
||||
/* verilator lint_on UNUSED */
|
||||
/* verilator lint_on UNUSEDSIGNAL */
|
||||
|
||||
// ================================================================
|
||||
// Coefficient counter (0..256). 9 bits to avoid overflow when
|
||||
@@ -223,6 +224,10 @@ module sample_ntt_sync_shared #(parameter K = 4) (
|
||||
// d2 rejected, no longer need coefficients, or d2 was just accepted out.
|
||||
wire grp_done = (state_r == ST_SQUEEZE) && (sq_phase_r == 2'd2) &&
|
||||
(!d2_acc_r || !need_more || (valid_o_r && ready_i));
|
||||
// `need_more` observes the registered counter before the final d2
|
||||
// handshake increments it. Detect that boundary explicitly so a full
|
||||
// rate block does not launch an unnecessary final re-permutation.
|
||||
wire completes_output = valid_o_r && ready_i && (coeff_cnt_r == 9'd255);
|
||||
|
||||
// ================================================================
|
||||
// FSM: state_next (combinational)
|
||||
@@ -248,7 +253,7 @@ module sample_ntt_sync_shared #(parameter K = 4) (
|
||||
// next group in this block, re-permute (block exhausted), or
|
||||
// finish.
|
||||
if (grp_done) begin
|
||||
if (!need_more)
|
||||
if (!need_more || completes_output)
|
||||
state_next = ST_DONE;
|
||||
else if (grp_ptr_r < GRP_MAX)
|
||||
state_next = ST_SQUEEZE; // next group, no re-permute
|
||||
|
||||
@@ -75,21 +75,21 @@ module axi_wrap_ram_sp_external (
|
||||
output axi_bvalid ,
|
||||
input axi_bready ,
|
||||
|
||||
//BaseRAM信号
|
||||
inout [31:0] base_ram_data, //BaseRAM数据，低8位与CPLD串口控制器共享
|
||||
output [19:0] base_ram_addr, //BaseRAM地址
|
||||
output [ 3:0] base_ram_be_n, //BaseRAM字节使能，低有效。如果不使用字节使能，请保持为0
|
||||
output base_ram_ce_n, //BaseRAM片选，低有效
|
||||
output base_ram_oe_n, //BaseRAM读使能，低有效
|
||||
output base_ram_we_n, //BaseRAM写使能，低有效
|
||||
// BaseRAM
|
||||
inout [31:0] base_ram_data,
|
||||
output [19:0] base_ram_addr,
|
||||
output [ 3:0] base_ram_be_n,
|
||||
output base_ram_ce_n,
|
||||
output base_ram_oe_n,
|
||||
output base_ram_we_n,
|
||||
|
||||
//ExtRAM信号
|
||||
inout [31:0] ext_ram_data, //ExtRAM数据
|
||||
output [19:0] ext_ram_addr, //ExtRAM地址
|
||||
output [ 3:0] ext_ram_be_n, //ExtRAM字节使能，低有效。如果不使用字节使能，请保持为0
|
||||
output ext_ram_ce_n, //ExtRAM片选，低有效
|
||||
output ext_ram_oe_n, //ExtRAM读使能，低有效
|
||||
output ext_ram_we_n //ExtRAM写使能，低有效
|
||||
// ExtRAM
|
||||
inout [31:0] ext_ram_data,
|
||||
output [19:0] ext_ram_addr,
|
||||
output [ 3:0] ext_ram_be_n,
|
||||
output ext_ram_ce_n,
|
||||
output ext_ram_oe_n,
|
||||
output ext_ram_we_n
|
||||
);
|
||||
|
||||
|
||||
@@ -139,6 +139,7 @@ wire ram_bready ;
|
||||
wire [31:0] soc_sram_addr;
|
||||
wire soc_sram_cs;
|
||||
wire soc_sram_we;
|
||||
wire soc_sram_bank;
|
||||
wire [3:0] soc_sram_be;
|
||||
wire [31:0] soc_sram_wdata;
|
||||
wire [31:0] soc_sram_rdata;
|
||||
@@ -188,7 +189,8 @@ assign ram_bready = axi_bready ;
|
||||
axi2sram_sp_external #(
|
||||
.AXI_ID_WIDTH ( 5 ),
|
||||
.AXI_ADDR_WIDTH ( 32 ),
|
||||
.AXI_DATA_WIDTH ( 32 ))
|
||||
.AXI_DATA_WIDTH ( 32 ),
|
||||
.FAST_READ_BURST( 1 ))
|
||||
u_axi_sram_sp (
|
||||
.clk ( aclk ),
|
||||
.resetn ( aresetn ),
|
||||
@@ -232,12 +234,13 @@ axi2sram_sp_external #(
|
||||
.req_o ( soc_sram_cs ),
|
||||
.we_o ( soc_sram_we ),
|
||||
.addr_o ( soc_sram_addr ),
|
||||
.bank_o ( soc_sram_bank ),
|
||||
.be_o ( soc_sram_be ),
|
||||
.data_o ( soc_sram_wdata ),
|
||||
.data_i ( soc_sram_rdata )
|
||||
);
|
||||
|
||||
wire choose_sram = soc_sram_addr[22];//1:ExtRAM 0:BaseRAM
|
||||
wire choose_sram = soc_sram_bank;//1:ExtRAM 0:BaseRAM
|
||||
wire [3:0] be_out = soc_sram_we ? soc_sram_be : 4'b1111;
|
||||
|
||||
assign base_ram_addr = soc_sram_addr[21:2];
|
||||
|
||||
@@ -635,9 +635,10 @@ wire [31:0] matmul_ep_rd_data;
|
||||
wire matmul_ep_rd_ready;
|
||||
wire matmul_direct_start_valid;
|
||||
wire matmul_direct_start_bank;
|
||||
wire matmul_direct_done_clear;
|
||||
wire matmul_direct_crc_clear;
|
||||
wire matmul_direct_done;
|
||||
wire matmul_direct_done_clear;
|
||||
wire matmul_direct_crc_clear;
|
||||
wire matmul_direct_done;
|
||||
wire matmul_direct_crc_idle;
|
||||
wire mlkem_intr;
|
||||
|
||||
AxiCrossbar_2x8 u_AxiCrossbar_2x8 (
|
||||
@@ -1577,8 +1578,9 @@ matmul_axi_slave u_matmul_axi_slave (
|
||||
.mat_start_valid(matmul_direct_start_valid),
|
||||
.mat_start_bank (matmul_direct_start_bank),
|
||||
.mat_done_clear (matmul_direct_done_clear),
|
||||
.mat_crc_clear (matmul_direct_crc_clear),
|
||||
.mat_done (matmul_direct_done),
|
||||
.mat_crc_clear (matmul_direct_crc_clear),
|
||||
.mat_done (matmul_direct_done),
|
||||
.mat_crc_idle (matmul_direct_crc_idle),
|
||||
|
||||
.intr (matmul_intr)
|
||||
);
|
||||
@@ -1828,8 +1830,9 @@ cdma_matmul_bridge #(
|
||||
.mat_start_valid (matmul_direct_start_valid),
|
||||
.mat_start_bank (matmul_direct_start_bank),
|
||||
.mat_done_clear (matmul_direct_done_clear),
|
||||
.mat_crc_clear (matmul_direct_crc_clear),
|
||||
.mat_done (matmul_direct_done),
|
||||
.mat_crc_clear (matmul_direct_crc_clear),
|
||||
.mat_done (matmul_direct_done),
|
||||
.mat_crc_idle (matmul_direct_crc_idle),
|
||||
.seq_done_irq (cdma_matmul_seq_irq)
|
||||
);
|
||||
|
||||
|
||||
@@ -15,6 +15,8 @@ unsigned long CORE_CLOCKS_PER_SEC = 33000000L;
|
||||
|
||||
const float PI = 3.14159265358979323846;
|
||||
|
||||
#define FFT_MAX_ABS_ERROR_LIMIT 8
|
||||
|
||||
// 读取定时器的当前Tick
|
||||
unsigned int get_timer_ticks() {
|
||||
return RegRead(CONFREG_TIMER_BASE);
|
||||
@@ -139,14 +141,35 @@ int main(int argc, char** argv)
|
||||
}
|
||||
|
||||
printf("\n--- Verification (Only showing Bins with energy > 10) ---\n");
|
||||
int max_abs_err_re = 0;
|
||||
int max_abs_err_im = 0;
|
||||
for (int i = 0; i < FFT_POINT_NUM; i++) {
|
||||
int sw_re = (int)sw_in_re[i] / FFT_POINT_NUM;
|
||||
int sw_im = (int)sw_in_im[i] / FFT_POINT_NUM;
|
||||
int err_re = hw_out_re[i] - sw_re;
|
||||
int err_im = hw_out_im[i] - sw_im;
|
||||
|
||||
if (err_re < 0) err_re = -err_re;
|
||||
if (err_im < 0) err_im = -err_im;
|
||||
if (err_re > max_abs_err_re) max_abs_err_re = err_re;
|
||||
if (err_im > max_abs_err_im) max_abs_err_im = err_im;
|
||||
|
||||
if (fabs(hw_out_re[i]) > 10 || fabs(hw_out_im[i]) > 10) {
|
||||
printf("Bin [%4d] Hz: HW(Re:%6d, Im:%6d) | SW(Re:%6d, Im:%6d)\n",
|
||||
i,
|
||||
hw_out_re[i], hw_out_im[i],
|
||||
(int)sw_in_re[i] / FFT_POINT_NUM, (int)sw_in_im[i] / FFT_POINT_NUM);
|
||||
sw_re, sw_im);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
int passed = max_abs_err_re <= FFT_MAX_ABS_ERROR_LIMIT &&
|
||||
max_abs_err_im <= FFT_MAX_ABS_ERROR_LIMIT;
|
||||
printf("Max Abs Error : Re=%d, Im=%d\n", max_abs_err_re, max_abs_err_im);
|
||||
printf("FFT_MAX_ABS_ERROR_RE=%d\n", max_abs_err_re);
|
||||
printf("FFT_MAX_ABS_ERROR_IM=%d\n", max_abs_err_im);
|
||||
printf("FFT_ERROR_LIMIT=%d\n", FFT_MAX_ABS_ERROR_LIMIT);
|
||||
printf("FFT_RESULT=%s\n", passed ? "PASS" : "FAIL");
|
||||
printf("FFT_DONE\n");
|
||||
|
||||
return passed ? 0 : 1;
|
||||
}
|
||||
|
||||
@@ -18,6 +18,8 @@ unsigned long CORE_CLOCKS_PER_SEC = 33000000L;
|
||||
|
||||
const float PI = 3.14159265358979323846;
|
||||
|
||||
#define FFT_MAX_ABS_ERROR_LIMIT 8
|
||||
|
||||
// 软件FFT实现 (基2 DIT-FFT 算法)
|
||||
void sw_fft(float re[], float im[], int n) {
|
||||
int i, j, k, l;
|
||||
@@ -185,5 +187,13 @@ int main(int argc, char** argv)
|
||||
}
|
||||
printf("Max Abs Error : Re=%d, Im=%d\n", max_abs_err_re, max_abs_err_im);
|
||||
|
||||
return 0;
|
||||
int passed = max_abs_err_re <= FFT_MAX_ABS_ERROR_LIMIT &&
|
||||
max_abs_err_im <= FFT_MAX_ABS_ERROR_LIMIT;
|
||||
printf("FFT_DMA_MAX_ABS_ERROR_RE=%d\n", max_abs_err_re);
|
||||
printf("FFT_DMA_MAX_ABS_ERROR_IM=%d\n", max_abs_err_im);
|
||||
printf("FFT_DMA_ERROR_LIMIT=%d\n", FFT_MAX_ABS_ERROR_LIMIT);
|
||||
printf("FFT_DMA_RESULT=%s\n", passed ? "PASS" : "FAIL");
|
||||
printf("FFT_DMA_DONE\n");
|
||||
|
||||
return passed ? 0 : 1;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user