29 lines
3.1 KiB
Plaintext
29 lines
3.1 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
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| Date : Wed Jul 15 05:09:35 2026
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| Host : Roc_Wang running 64-bit major release (build 9200)
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| Command : report_clock_interaction -delay_type min_max -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/clock_interaction.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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Clock Interaction Report
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Clock Interaction Table
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-----------------------
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WNS TNS Failing TNS Total WNS Path WHS THS Failing THS Total WHS Path Clock-Pair Inter-Clock
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From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Clock Edges WHS(ns) THS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints
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---------------- ---------------- ----------- ------- ------- ----------- ----------- --------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- -------------------
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cpu_clk cpu_clk rise - rise 0.74 0.00 0 17264 30.00 rise - rise 0.04 0.00 0 17264 0.00 Clean Timed
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cpu_clk sys_clk 0 162 0 162 Ignored Asynchronous Groups
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mlkem_clk mlkem_clk rise - rise 0.07 0.00 0 48386 13.00 rise - rise 0.06 0.00 0 48386 0.00 Clean Timed
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mlkem_clk sys_clk 0 61 0 61 Ignored Asynchronous Groups
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sys_clk cpu_clk 0 59 0 59 Ignored Asynchronous Groups
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sys_clk mlkem_clk 0 112 0 112 Ignored Asynchronous Groups
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sys_clk sys_clk rise - rise 0.12 0.00 0 23193 20.00 rise - rise 0.02 0.00 0 23193 0.00 Clean Timed
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