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FallenSigh c4d36515cc fix samples ntt bugs & set PLL & optimize matmul

2026-07-15 10:36:38 +08:00

doc

test: add board FFT validation and VCD capture

2026-07-15 04:13:15 +08:00

fpga

docs: rebuild system report and test workflow

2026-07-15 03:48:19 +08:00

rtl

fix samples ntt bugs & set PLL & optimize matmul

2026-07-15 10:36:38 +08:00

sdk

test: add board FFT validation and VCD capture

2026-07-15 04:13:15 +08:00

sim

update test data and remove mif files

2026-07-05 20:16:13 +08:00

test_data

mlkem test diagnostics and allocator updates

2026-07-08 02:35:56 +08:00

tools

update test data and remove mif files

2026-07-05 20:16:13 +08:00

.gitignore

mlkem test diagnostics and allocator updates

2026-07-08 02:35:56 +08:00

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193 MiB

Languages

Verilog 46.5%

C 27.8%

Assembly 20.5%

SystemVerilog 3.3%

Python 0.7%

Other 1.2%