The open-la500 core has USE_CACHE enabled. Writes to 0x1c400000
go to the write-back data cache and never reach the SRAM model
before the testbench checks ExtRAM. Use the 0xA0000000 uncached
segment (same pattern as fft_dma/main.c).
The open-la500 CPU maps 0xbfxx_xxxx to the peripheral address space
(crossbar sees 0x1fxx_xxxx). FFT uses 0xbf400000, CONFREG uses
0xbf20f100, UART uses 0xbf000000. Matmul must follow the same
convention.
- Rewrite main.c to read from ExtRAM (0x1c400000), compute
via matmul IP, write results back. Matches testbench
expectation of 10 groups.
- Add in matmul_axi_slave to trace error writes
