fallensigh/ciciec2026
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This repository has been archived on 2026-08-21. You can view files and clone it. You cannot open issues or pull requests or push a commit.
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e35fa5884d9ba383f9469775cfcbdf5b44b44e09
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FallenSigh e35fa5884d Use uncached ExtRAM access (0xBC400000) to bypass CPU data cache 
The open-la500 core has USE_CACHE enabled. Writes to 0x1c400000
go to the write-back data cache and never reach the SRAM model
before the testbench checks ExtRAM. Use the 0xA0000000 uncached
segment (same pattern as fft_dma/main.c).
2026-06-24 02:04:40 +08:00
doc
Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
2026-06-23 01:22:45 +08:00
fpga
Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists
2026-06-23 01:33:56 +08:00
rtl
matmul_test: rewrite for ExtRAM flow, add IP error debug
2026-06-24 01:49:02 +08:00
sdk
Use uncached ExtRAM access (0xBC400000) to bypass CPU data cache
2026-06-24 02:04:40 +08:00
sim
Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
2026-06-23 01:22:45 +08:00
tools
Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
2026-06-23 01:22:45 +08:00
.gitignore
Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists
2026-06-23 01:33:56 +08:00
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