fallensigh/ciciec2026
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FallenSigh b8a4fcc30b Fix matmul_base address: 0x1f500000 -> 0xbf500000 
The open-la500 CPU maps 0xbfxx_xxxx to the peripheral address space
(crossbar sees 0x1fxx_xxxx). FFT uses 0xbf400000, CONFREG uses
0xbf20f100, UART uses 0xbf000000. Matmul must follow the same
convention.
2026-06-24 01:58:29 +08:00
doc
Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
2026-06-23 01:22:45 +08:00
fpga
Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists
2026-06-23 01:33:56 +08:00
rtl
matmul_test: rewrite for ExtRAM flow, add IP error debug
2026-06-24 01:49:02 +08:00
sdk
Fix matmul_base address: 0x1f500000 -> 0xbf500000
2026-06-24 01:58:29 +08:00
sim
Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
2026-06-23 01:22:45 +08:00
tools
Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
2026-06-23 01:22:45 +08:00
.gitignore
Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists
2026-06-23 01:33:56 +08:00
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