fallensigh/ciciec2026
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FallenSigh ff6e572996 matmul_test: rewrite for ExtRAM flow, add IP error debug 
- Rewrite main.c to read from ExtRAM (0x1c400000), compute
  via matmul IP, write results back. Matches testbench
  expectation of 10 groups.
- Add  in matmul_axi_slave to trace error writes
2026-06-24 01:49:02 +08:00
doc
Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
2026-06-23 01:22:45 +08:00
fpga
Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists
2026-06-23 01:33:56 +08:00
rtl
matmul_test: rewrite for ExtRAM flow, add IP error debug
2026-06-24 01:49:02 +08:00
sdk
matmul_test: rewrite for ExtRAM flow, add IP error debug
2026-06-24 01:49:02 +08:00
sim
Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
2026-06-23 01:22:45 +08:00
tools
Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
2026-06-23 01:22:45 +08:00
.gitignore
Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists
2026-06-23 01:33:56 +08:00
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