e8893a28dd
mlkem_test: add mlkem-native
2026-07-05 21:26:39 +08:00
cd039e2e2e
mlkem_test: add mlkem-native
2026-07-05 21:26:19 +08:00
b8ddb2ef08
c program: use prng
2026-07-05 21:04:42 +08:00
4eca83bd3d
Add MLKEM DMA comparison test
2026-07-05 20:23:58 +08:00
2b7c43edcb
Add DMA-friendly MLKEM windows
2026-07-05 20:07:14 +08:00
d13f7933d8
Optimize FFT test input generation
2026-07-05 19:48:16 +08:00
48072c5ecb
remove all the LF
2026-07-05 18:23:23 +08:00
264e65f8d9
optimize uart output
2026-07-05 17:59:31 +08:00
7281df356f
feat: optimize startup and linking
2026-07-05 17:27:26 +08:00
c37f493bcb
Compute matmul CRC before result store
2026-07-04 19:45:22 +08:00
b7553418fa
Add direct CDMA matmul path
2026-07-04 19:15:34 +08:00
c5072d7170
feat: add ML-KEM accelerator with AXI slave wrapper
...
Wrap mlkem_top in an AXI4 burst slave (mlkem_axi_slave) mapped to the
freed FFT slot 6 at 0x1f400000 (virtual 0xbf400000). The core runs on
sys_clk/2 (25 MHz); the wrapper handles the clock-domain crossing:
start toggle->pulse, wait-stated byte-preload handshake, busy/done
sync, and direct readback taps (ek/dk/ct/ss). CPU drives it via a
register map (CTRL/STATUS/CONFIG, d/z/msg, preload + readback windows).
Wire into soc_top on the existing axiOut_6 nets (no crossbar change),
add mlkem_intr on intrpt[3]. Add sdk mlkem_test example running a
KeyGen->Encaps->Decaps self-consistency round trip.
2026-06-30 01:39:35 +08:00
95fe94063c
fix: revert UART FIFO batching — caused FIFO overflow + syserr on board
...
uart_puts(13B) + uart_puthex(8B) = 21 bytes without polling → FIFO overflow.
Board UART IP asserts AXI error → CPU syserr exception.
Simulation UART model is lenient, so sim passed but board failed.
Back to per-byte polling (safe).
2026-06-26 23:53:15 +08:00
9202327dd0
perf: batch UART FIFO writes — poll once per 16 bytes instead of per byte
...
uart_puts: burst-write up to 16 chars before polling LSR
uart_puthex: write all 8 hex digits without polling (8 < 16 FIFO depth)
Reduces AXI register reads from ~50 to ~3 per CRC output.
Each saved poll: -1 uncached AXI read (~390ns)
2026-06-26 23:48:23 +08:00
52e85aa6fb
perf: drop stdint.h + picolibc — zero libc dependency
...
dma.h: typedef u32 instead of uint32_t, no stdint.h include
dma.c: use u32 instead of uint32_t
user-sample.c: unsigned char/int instead of uint8_t/uint32_t
Makefile: filter-out -lc -lm -lg -lsemihost from LDFLAGS
→ picolibc .data section (2.1KB, 532 words) eliminated
→ startup data-copy loop: ~30000 → ~200 cycles
→ total start.S latency: ~44000 → ~14000 cycles (~0.42ms at 33MHz)
2026-06-26 22:34:26 +08:00
ae89363227
perf(matmul): bypass printf — direct UART 16550 register writes
...
Replace all printf() calls with direct UART THR register access:
- uart_tx(): poll LSR bit5, write byte to THR
- uart_puts(): null-terminated string output
- uart_puthex(): 8-digit lowercase hex for CRC32
Eliminates picolibc printf overhead: no format parsing, no FILE* I/O,
no locale, no buffering. UART runs at 115200 baud (~8.7μs/byte),
THR nearly always empty at 33MHz core → single poll iteration.
Output: MATMUL_START, MATMUL_CRC32=XXXXXXXX, MATMUL_DONE
2026-06-26 17:51:13 +08:00
f55e15af32
perf(matmul): remove all DMA TAG writes (hardware ignores TAG register)
...
Each uncached TAG write costs ~810ns on the AXI bus. Removed:
- 2 TAG writes per main loop iteration (Ch1 store + Ch0 pre-fire)
- 2 TAG writes in prologue (group 0 load + pre-fire group 1)
- 1 TAG write in epilogue (final store)
Total: ~10,000 wasted AXI transactions eliminated for 5000 groups.
Estimated ~8% reduction in per-iteration time.
2026-06-26 17:49:39 +08:00
07b670b4c9
perf(matmul): strip ALL timing — zero get_ns() calls, zero TIME_* output
...
Removed:
- confreg_time.h and common_func.h includes
- All get_ns() calls (6 in prologue/loop/epilogue boundaries)
- All timing variables (t_prologue, t_mainloop, t_epilogue)
- All TIME_* printf markers
- Unused extram pointer and stdbool.h
Only essential output remains: MATMUL_START, MATMUL_CRC32, MATMUL_DONE
2026-06-26 17:46:07 +08:00
6aab84bf4b
perf(matmul): remove diagnostic get_ns() calls from hot loop (v2 clean)
...
Stripped all per-iteration timing instrumentation:
- Removed 16 get_ns() calls per iteration from main loop
- Removed pipeline diagnostic print section
- Removed timing accumulator variables
- Retained outer timing markers only (prologue/loop/epilogue)
Expected ~45% speedup from removing measurement overhead
(previous run: 179.6ms with diag → estimated ~100ms clean)
2026-06-26 17:44:13 +08:00
45731e05b7
perf(matmul): add pipeline timing diagnostics (v2.1)
...
Measure per-phase wait times and stall counts to identify bottleneck:
- PIPE_WAIT_IP / DMA0 / DMA1: aggregate wait time per resource
- PIPE_FIRE_DMA / IP: register write overhead
- PIPE_STALL_*: iterations where each resource actually blocked
Output after standard markers, before MATMUL_DONE.
Allows data-driven decision on next optimization target:
wait_ip dominant → optimize IP (HW multiplier pipeline)
wait_dma0 dominant → pre-fire insufficient (wider bus/faster RAM)
wait_dma1 dominant → bank reuse delay (deeper buffering)
2026-06-26 03:54:20 +08:00
81c636fb56
perf(matmul): pre-fire DMA Ch0 load + inline wait/DMA start + XOR bank toggle
...
user-sample.c v2 optimizations:
- Pre-fire DMA Ch0 load at loop tail to overlap fully with IP compute
- Inline wait_matmul_done/wait_dma_done to eliminate function call overhead
- Inline DMA register writes, skip redundant STATUS_BUSY_BIT check
- Replace g%2 with XOR bank toggle (bank ^= 1)
- Cache volatile pointers in locals (ch0, ch1, mat_status, mat_ctrl)
Makefile: bump -O2 to -O3
2026-06-26 03:39:32 +08:00
a2b496ca8d
Restore timing + switch to polling + disable CPU interrupts (IE=0)
2026-06-26 01:01:48 +08:00
115466353d
Remove timing instrumentation from user-sample.c
2026-06-26 00:34:44 +08:00
f8459f2478
Hardware CRC32 engine in matmul IP: 4-byte/cycle combinational, register at 0x010
2026-06-25 20:40:08 +08:00
76b5f30c6b
Move MATMUL_DONE to last line
2026-06-25 20:11:45 +08:00
d9483a9d39
Add timing instrumentation for profiling (prologue/loop/epilogue/crc32)
2026-06-25 20:10:31 +08:00
956cd67773
Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines
2026-06-25 20:03:53 +08:00
57ba5d271d
Remove all debug and printf
2026-06-25 15:44:18 +08:00
a9958ee4fa
BURST_LEN 47->63 (64 beats)
2026-06-25 04:08:18 +08:00
3cad98a811
Increase BURST_LEN to 47 (48 beats) to cover 192-byte C reads in one burst
2026-06-25 03:54:10 +08:00
54aa37adee
Add debug output for C[0][0]/C[1][1]/C[2][3] of groups 0,1
2026-06-25 03:03:10 +08:00
9ecda4aa7a
Fix CRC32 table, remove debug output
2026-06-25 02:51:36 +08:00
5e467175ea
Merge main (user mods) into no-fft
2026-06-25 00:44:01 +08:00
641d055f18
User mods: matmul RTL + shift_add_mult + C program
2026-06-25 00:43:16 +08:00
1660b283c4
Move DMA files to asm/, remove from common.mk
2026-06-24 23:52:30 +08:00
5dcee80b95
DMA-driven: A+B+C per group via DMA ch0/ch1, -O2 CRC32 from ExtRAM
2026-06-24 23:46:58 +08:00
a42568f635
Clean production code: -O2, read CRC32 from ExtRAM, remove all debug
2026-06-24 23:42:35 +08:00
c1fcb3c796
CRC32 on-the-fly from c_buf — bypass ExtRAM reads entirely
2026-06-24 23:38:06 +08:00
07f8422d75
Fix CRC32 table entry 187: 0x5CB30A04 -> 0x5CB36A04
2026-06-24 23:32:24 +08:00
93361733f6
Definitive write test: write 0xDEADBEEF then read back
2026-06-24 23:29:00 +08:00
16c0d7b639
Use __sync_synchronize() hardware barrier instead of asm compiler barrier
2026-06-24 23:22:38 +08:00
f0ebf1f5fa
Output A0/B0/C0 for groups 0-3 and N-2,N-1
2026-06-24 23:16:26 +08:00
2c8f5d37f3
Add asm memory barrier before CRC32 to flush write buffer
2026-06-24 23:09:06 +08:00
afef1f1433
Add group 1 A/B/C debug output
2026-06-24 23:03:46 +08:00
23bb112586
Print CRC32 loop counter to verify iteration count
2026-06-24 23:01:29 +08:00
8ea98874a5
Inline CRC32 computation into main (bypass function call)
2026-06-24 22:52:08 +08:00
d27e147652
Fix escaped quotes
2026-06-24 22:50:14 +08:00
f6146bd467
Minimal debug: CRC32 self-test + group 0 rdback in one line
2026-06-24 22:49:06 +08:00
e39a655861
Add CRC32 self-test debug output
2026-06-24 22:42:46 +08:00
bbd3e3358b
Fix extra brace in debug code
2026-06-24 22:38:18 +08:00
