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FallenSigh 48072c5ecb remove all the LF

2026-07-05 18:23:23 +08:00

..

asm

remove all the LF

2026-07-05 18:23:23 +08:00

c_prg

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

coremark

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

dhrystone

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

dma

Use uncached ExtRAM access (0xBC400000) to bypass CPU data cache

2026-06-24 02:04:40 +08:00

fft

Remove all debug and printf

2026-06-25 15:44:18 +08:00

fft_dma

Remove all debug and printf

2026-06-25 15:44:18 +08:00

fireye

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

hello_world

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

int_test

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

lenet

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

matmul_test

Add direct CDMA matmul path

2026-07-04 19:15:34 +08:00

mlkem_test

feat: optimize startup and linking

2026-07-05 17:27:26 +08:00

pinball_game

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

.gitignore

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00