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FallenSigh 45731e05b7 perf(matmul): add pipeline timing diagnostics (v2.1) ...

Measure per-phase wait times and stall counts to identify bottleneck:
- PIPE_WAIT_IP / DMA0 / DMA1: aggregate wait time per resource
- PIPE_FIRE_DMA / IP: register write overhead
- PIPE_STALL_*: iterations where each resource actually blocked

Output after standard markers, before MATMUL_DONE.
Allows data-driven decision on next optimization target:
  wait_ip dominant → optimize IP (HW multiplier pipeline)
  wait_dma0 dominant → pre-fire insufficient (wider bus/faster RAM)
  wait_dma1 dominant → bank reuse delay (deeper buffering)

2026-06-26 03:54:20 +08:00

..

asm

perf(matmul): add pipeline timing diagnostics (v2.1)

2026-06-26 03:54:20 +08:00

c_prg

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

coremark

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

dhrystone

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

dma

Use uncached ExtRAM access (0xBC400000) to bypass CPU data cache

2026-06-24 02:04:40 +08:00

fft

Remove all debug and printf

2026-06-25 15:44:18 +08:00

fft_dma

Remove all debug and printf

2026-06-25 15:44:18 +08:00

fireye

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

hello_world

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

int_test

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

lenet

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

matmul_test

Rewrite matmul_test for CIC-IEC Stage 3 evaluation

2026-06-24 16:42:08 +08:00

pinball_game

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

.gitignore

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00