Measure per-phase wait times and stall counts to identify bottleneck: - PIPE_WAIT_IP / DMA0 / DMA1: aggregate wait time per resource - PIPE_FIRE_DMA / IP: register write overhead - PIPE_STALL_*: iterations where each resource actually blocked Output after standard markers, before MATMUL_DONE. Allows data-driven decision on next optimization target: wait_ip dominant → optimize IP (HW multiplier pipeline) wait_dma0 dominant → pre-fire insufficient (wider bus/faster RAM) wait_dma1 dominant → bank reuse delay (deeper buffering)
12 KiB
12 KiB