/** * user-sample - CIC-IEC 2026 Stage 3 Evaluation Program * * (ULTIMATE PERFORMANCE DMA + PING-PONG BUFFER ARCHITECTURE v2) * * Optimizations over v1: * 1. Pre-fire DMA Ch0 load at loop tail → fully overlaps with IP compute * 2. Inlined wait loops → zero function-call overhead in hot path * 3. Inlined DMA start → skips redundant STATUS_BUSY_BIT check * 4. XOR bank toggle → avoids g%2 recomputation per iteration * * v2.1: Pipeline timing diagnostics — measures per-phase wait times * and stall counts to identify the real bottleneck (IP vs DMA vs store). */ #include #include #include #include #include #include /* ─── Configurable group count (default 5000 for diagnostics) ──────── */ #ifndef MATMUL_GROUP_NUM #define MATMUL_GROUP_NUM 5000 #endif /* ─── BSP globals ─────────────────────────────────────────────────── */ unsigned long UART_BASE = 0xbf000000; unsigned long CONFREG_TIMER_BASE = 0xbf20f100; unsigned long CONFREG_CLOCKS_PER_SEC = 50000000L; unsigned long CORE_CLOCKS_PER_SEC = 33000000L; /* ─── Memory layout ────────────────────────────────────────────────── */ #define EXTRAM_BASE_PHYS 0x1c400000 #define EXTRAM_BASE_UNCACHED (0xA0000000 | (EXTRAM_BASE_PHYS & 0x1FFFFFFF)) #define SRC_BASE_WORDS 0 #define DST_BASE_WORDS (SRC_BASE_WORDS + MATMUL_GROUP_NUM * 32) #define RESULT_WORDS (MATMUL_GROUP_NUM * 48) /* ExtRAM Physical Addresses for DMA */ #define EXTRAM_PHYS_AB(g) (EXTRAM_BASE_PHYS + (SRC_BASE_WORDS * 4) + (g) * 128) #define EXTRAM_PHYS_C(g) (EXTRAM_BASE_PHYS + (DST_BASE_WORDS * 4) + (g) * 192) /* ─── MATMUL IP registers (Ping-Pong Memory Map) ──────────────────── */ #define MATMUL_BASE_PHYS 0x1f500000 #define MATMUL_BASE_UNCACHED 0xbf500000 #define MATMUL_CTRL (MATMUL_BASE_UNCACHED + 0x000) #define MATMUL_STATUS (MATMUL_BASE_UNCACHED + 0x004) #define MATMUL_PHYS_B0_AB (MATMUL_BASE_PHYS + 0x100) #define MATMUL_PHYS_B0_C (MATMUL_BASE_PHYS + 0x180) #define MATMUL_PHYS_B1_AB (MATMUL_BASE_PHYS + 0x300) #define MATMUL_PHYS_B1_C (MATMUL_BASE_PHYS + 0x380) #define CTRL_START_B0 0x1 #define CTRL_START_B1 0x2 #define STATUS_DONE 0x2 #define STATUS_ERROR 0x4 #define MATMUL_CRC (MATMUL_BASE_UNCACHED + 0x010) /* ─── Pre-computed DMA burst control word ──────────────────────────── */ #define DMA_CTRL_VAL (CTRL_BURST_SIZE(2) | CTRL_BURST_LEN(63) | CTRL_START_BIT) /* ═══════════════════════════════════════════════════════════════════ */ int main(void) { if (MATMUL_GROUP_NUM <= 0) return 0; /* ── Hot-path local volatile pointers (one-time addr calc) ──────── */ volatile uint32_t *extram = (volatile uint32_t *)EXTRAM_BASE_UNCACHED; volatile uint32_t *mat_status = (volatile uint32_t *)MATMUL_STATUS; volatile uint32_t *mat_ctrl = (volatile uint32_t *)MATMUL_CTRL; volatile uint32_t *mat_crc = (volatile uint32_t *)MATMUL_CRC; volatile dma_ch_regs_t *ch0 = DMA_CH(0); volatile dma_ch_regs_t *ch1 = DMA_CH(1); uint32_t crc, t_prologue, t_mainloop, t_epilogue; int g, bank; // Ping-Pong Register Address Arrays (Physical for DMA) uint32_t phys_bank_AB[2] = {MATMUL_PHYS_B0_AB, MATMUL_PHYS_B1_AB}; uint32_t phys_bank_C[2] = {MATMUL_PHYS_B0_C, MATMUL_PHYS_B1_C}; uint32_t ctrl_start[2] = {CTRL_START_B0, CTRL_START_B1}; /* ── Pipeline timing diagnostics ──────────────────────────────── */ uint32_t t_now; uint32_t t_wait_ip = 0; // total ns waiting for IP done uint32_t t_wait_dma0 = 0; // total ns waiting for DMA Ch0 done uint32_t t_wait_dma1 = 0; // total ns waiting for DMA Ch1 done uint32_t t_fire_dma = 0; // total ns writing DMA registers uint32_t t_fire_ip = 0; // total ns writing IP ctrl register int n_loops = 0; // main loop iteration count int stall_ip = 0; // iterations where wait_ip actually blocked int stall_dma0 = 0; // iterations where wait_dma0 actually blocked int stall_dma1 = 0; // iterations where wait_dma1 actually blocked /* ── Start marker (must be first output) ──────────────────── */ printf("MATMUL_START\n"); // Reset IP state *mat_status = STATUS_DONE | STATUS_ERROR; *mat_crc = 0; /* ═══════════════════════════════════════════════════════════════ * PROLOGUE: Load group 0 → Bank 0, start IP, pre-fire group 1 * ═══════════════════════════════════════════════════════════════ */ t_prologue = get_ns(); // DMA Ch0: Load group 0 A+B (128 bytes) → IP Bank 0 ch0->SRC_ADDR = EXTRAM_PHYS_AB(0); ch0->DST_ADDR = phys_bank_AB[0]; ch0->LENGTH = 128; ch0->TAG = 10; ch0->CTRL = DMA_CTRL_VAL; while (!(ch0->STATUS & STATUS_DONE_BIT)) {} ch0->STATUS = STATUS_DONE_BIT; // Start IP Bank 0 (group 0) *mat_ctrl = ctrl_start[0]; // Pre-fire: DMA Ch0 load group 1 → Bank 1 (overlaps with IP compute) if (MATMUL_GROUP_NUM > 1) { ch0->SRC_ADDR = EXTRAM_PHYS_AB(1); ch0->DST_ADDR = phys_bank_AB[1]; ch0->LENGTH = 128; ch0->TAG = 10; ch0->CTRL = DMA_CTRL_VAL; } t_prologue = get_ns() - t_prologue; /* ═══════════════════════════════════════════════════════════════ * MAIN LOOP: Fully-pipelined — pre-fire DMA load at loop tail * + per-phase timing diagnostics * ═══════════════════════════════════════════════════════════════ */ t_mainloop = get_ns(); bank = 1; // Prologue IP start time (for measuring first IP compute duration) // We can't easily isolate pure IP time, but aggregate wait tells us. for (g = 1; g < MATMUL_GROUP_NUM; g++) { int cur_bank = bank; int prev_bank = bank ^ 1; /* ── 1. Wait for previous IP computation ─────────────────── */ t_now = get_ns(); while (!(*mat_status & STATUS_DONE)) {} *mat_status = STATUS_DONE; { uint32_t dt = get_ns() - t_now; t_wait_ip += dt; if (dt > 0) stall_ip++; } /* ── 2. Wait for previous DMA Ch1 store ──────────────────── */ if (g > 1) { t_now = get_ns(); while (!(ch1->STATUS & STATUS_DONE_BIT)) {} ch1->STATUS = STATUS_DONE_BIT; uint32_t dt = get_ns() - t_now; t_wait_dma1 += dt; if (dt > 0) stall_dma1++; } /* ── 3. Start DMA Ch1 store: group (g-1) result → ExtRAM ── */ t_now = get_ns(); ch1->SRC_ADDR = phys_bank_C[prev_bank]; ch1->DST_ADDR = EXTRAM_PHYS_C(g - 1); ch1->LENGTH = 192; ch1->TAG = 20; ch1->CTRL = DMA_CTRL_VAL; t_fire_dma += (get_ns() - t_now); /* ── 4. Wait for DMA Ch0 load (pre-fired in prev iteration) */ t_now = get_ns(); while (!(ch0->STATUS & STATUS_DONE_BIT)) {} ch0->STATUS = STATUS_DONE_BIT; { uint32_t dt = get_ns() - t_now; t_wait_dma0 += dt; if (dt > 0) stall_dma0++; } /* ── 5. Start IP computation ─────────────────────────────── */ t_now = get_ns(); *mat_ctrl = ctrl_start[cur_bank]; t_fire_ip += (get_ns() - t_now); /* ── 6. PRE-FIRE DMA Ch0 load for next group ─────────────── */ if (g < MATMUL_GROUP_NUM - 1) { int next_bank = bank ^ 1; t_now = get_ns(); ch0->SRC_ADDR = EXTRAM_PHYS_AB(g + 1); ch0->DST_ADDR = phys_bank_AB[next_bank]; ch0->LENGTH = 128; ch0->TAG = 10; ch0->CTRL = DMA_CTRL_VAL; t_fire_dma += (get_ns() - t_now); } bank ^= 1; n_loops++; } t_mainloop = get_ns() - t_mainloop; /* ═══════════════════════════════════════════════════════════════ * EPILOGUE: Flush the final group * ═══════════════════════════════════════════════════════════════ */ t_epilogue = get_ns(); // Wait for last IP computation while (!(*mat_status & STATUS_DONE)) {} *mat_status = STATUS_DONE; // Wait for previous DMA store and start/complete final store while (!(ch1->STATUS & STATUS_DONE_BIT)) {} ch1->STATUS = STATUS_DONE_BIT; ch1->SRC_ADDR = phys_bank_C[(MATMUL_GROUP_NUM - 1) % 2]; ch1->DST_ADDR = EXTRAM_PHYS_C(MATMUL_GROUP_NUM - 1); ch1->LENGTH = 192; ch1->TAG = 20; ch1->CTRL = DMA_CTRL_VAL; while (!(ch1->STATUS & STATUS_DONE_BIT)) {} ch1->STATUS = STATUS_DONE_BIT; t_epilogue = get_ns() - t_epilogue; /* ── Read hardware CRC32 ──────────────────────────────────── */ crc = *mat_crc; /* ── Standard markers (required by test harness) ────────────── */ printf("MATMUL_CRC32=%08lx\n", (unsigned long)crc); printf("TIME_PROLOGUE=%lu\n", (unsigned long)t_prologue); printf("TIME_LOOP=%lu\n", (unsigned long)t_mainloop); printf("TIME_LOOP_PER=%lu\n", (unsigned long)(t_mainloop / MATMUL_GROUP_NUM)); printf("TIME_EPILOGUE=%lu\n", (unsigned long)t_epilogue); printf("TIME_TOTAL=%lu\n", (unsigned long)(t_prologue + t_mainloop + t_epilogue)); /* ═══════════════════════════════════════════════════════════════ * Pipeline Timing Diagnostics * * Interpretation guide: * PIPE_WAIT_DMA0 ≈ 0 → pre-fire working, DMA load never blocks * PIPE_WAIT_DMA0 > 0 → DMA load is bottleneck (wider bus / faster RAM) * PIPE_WAIT_IP > 0 → IP compute is bottleneck (optimize multiplier HW) * PIPE_WAIT_DMA1 > 0 → DMA store is bottleneck (bank reuse delay) * PIPE_STALL_* = N → that resource blocked EVERY iteration * * All times in nanoseconds. Averages over N-1 loop iterations. * ═══════════════════════════════════════════════════════════════ */ printf("--- Pipeline Profile (%d loop iterations) ---\n", n_loops); printf("PIPE_WAIT_IP=%lu\n", (unsigned long)t_wait_ip); printf("PIPE_WAIT_IP_AVG=%lu\n", (unsigned long)(n_loops ? t_wait_ip / n_loops : 0)); printf("PIPE_WAIT_DMA0=%lu\n", (unsigned long)t_wait_dma0); printf("PIPE_WAIT_DMA0_AVG=%lu\n", (unsigned long)(n_loops ? t_wait_dma0 / n_loops : 0)); printf("PIPE_WAIT_DMA1=%lu\n", (unsigned long)t_wait_dma1); printf("PIPE_WAIT_DMA1_AVG=%lu\n", (unsigned long)(n_loops ? t_wait_dma1 / n_loops : 0)); printf("PIPE_FIRE_DMA=%lu\n", (unsigned long)t_fire_dma); printf("PIPE_FIRE_IP=%lu\n", (unsigned long)t_fire_ip); printf("PIPE_STALL_IP=%d\n", stall_ip); printf("PIPE_STALL_DMA0=%d\n", stall_dma0); printf("PIPE_STALL_DMA1=%d\n", stall_dma1); printf("PIPE_SUM_WAITS=%lu\n", (unsigned long)(t_wait_ip + t_wait_dma0 + t_wait_dma1 + t_fire_dma + t_fire_ip)); printf("MATMUL_DONE\n"); return 0; }