FallenSigh
45731e05b7
Measure per-phase wait times and stall counts to identify bottleneck: - PIPE_WAIT_IP / DMA0 / DMA1: aggregate wait time per resource - PIPE_FIRE_DMA / IP: register write overhead - PIPE_STALL_*: iterations where each resource actually blocked Output after standard markers, before MATMUL_DONE. Allows data-driven decision on next optimization target: wait_ip dominant → optimize IP (HW multiplier pipeline) wait_dma0 dominant → pre-fire insufficient (wider bus/faster RAM) wait_dma1 dominant → bank reuse delay (deeper buffering)
274 lines
12 KiB
C
274 lines
12 KiB
C
/**
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* user-sample - CIC-IEC 2026 Stage 3 Evaluation Program
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*
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* (ULTIMATE PERFORMANCE DMA + PING-PONG BUFFER ARCHITECTURE v2)
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*
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* Optimizations over v1:
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* 1. Pre-fire DMA Ch0 load at loop tail → fully overlaps with IP compute
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* 2. Inlined wait loops → zero function-call overhead in hot path
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* 3. Inlined DMA start → skips redundant STATUS_BUSY_BIT check
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* 4. XOR bank toggle → avoids g%2 recomputation per iteration
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*
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* v2.1: Pipeline timing diagnostics — measures per-phase wait times
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* and stall counts to identify the real bottleneck (IP vs DMA vs store).
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*/
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#include <stdio.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <common_func.h>
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#include <confreg_time.h>
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#include <dma.h>
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/* ─── Configurable group count (default 5000 for diagnostics) ──────── */
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#ifndef MATMUL_GROUP_NUM
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#define MATMUL_GROUP_NUM 5000
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#endif
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/* ─── BSP globals ─────────────────────────────────────────────────── */
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unsigned long UART_BASE = 0xbf000000;
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unsigned long CONFREG_TIMER_BASE = 0xbf20f100;
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unsigned long CONFREG_CLOCKS_PER_SEC = 50000000L;
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unsigned long CORE_CLOCKS_PER_SEC = 33000000L;
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/* ─── Memory layout ────────────────────────────────────────────────── */
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#define EXTRAM_BASE_PHYS 0x1c400000
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#define EXTRAM_BASE_UNCACHED (0xA0000000 | (EXTRAM_BASE_PHYS & 0x1FFFFFFF))
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#define SRC_BASE_WORDS 0
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#define DST_BASE_WORDS (SRC_BASE_WORDS + MATMUL_GROUP_NUM * 32)
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#define RESULT_WORDS (MATMUL_GROUP_NUM * 48)
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/* ExtRAM Physical Addresses for DMA */
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#define EXTRAM_PHYS_AB(g) (EXTRAM_BASE_PHYS + (SRC_BASE_WORDS * 4) + (g) * 128)
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#define EXTRAM_PHYS_C(g) (EXTRAM_BASE_PHYS + (DST_BASE_WORDS * 4) + (g) * 192)
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/* ─── MATMUL IP registers (Ping-Pong Memory Map) ──────────────────── */
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#define MATMUL_BASE_PHYS 0x1f500000
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#define MATMUL_BASE_UNCACHED 0xbf500000
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#define MATMUL_CTRL (MATMUL_BASE_UNCACHED + 0x000)
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#define MATMUL_STATUS (MATMUL_BASE_UNCACHED + 0x004)
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#define MATMUL_PHYS_B0_AB (MATMUL_BASE_PHYS + 0x100)
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#define MATMUL_PHYS_B0_C (MATMUL_BASE_PHYS + 0x180)
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#define MATMUL_PHYS_B1_AB (MATMUL_BASE_PHYS + 0x300)
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#define MATMUL_PHYS_B1_C (MATMUL_BASE_PHYS + 0x380)
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#define CTRL_START_B0 0x1
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#define CTRL_START_B1 0x2
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#define STATUS_DONE 0x2
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#define STATUS_ERROR 0x4
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#define MATMUL_CRC (MATMUL_BASE_UNCACHED + 0x010)
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/* ─── Pre-computed DMA burst control word ──────────────────────────── */
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#define DMA_CTRL_VAL (CTRL_BURST_SIZE(2) | CTRL_BURST_LEN(63) | CTRL_START_BIT)
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/* ═══════════════════════════════════════════════════════════════════ */
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int main(void)
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{
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if (MATMUL_GROUP_NUM <= 0) return 0;
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/* ── Hot-path local volatile pointers (one-time addr calc) ──────── */
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volatile uint32_t *extram = (volatile uint32_t *)EXTRAM_BASE_UNCACHED;
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volatile uint32_t *mat_status = (volatile uint32_t *)MATMUL_STATUS;
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volatile uint32_t *mat_ctrl = (volatile uint32_t *)MATMUL_CTRL;
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volatile uint32_t *mat_crc = (volatile uint32_t *)MATMUL_CRC;
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volatile dma_ch_regs_t *ch0 = DMA_CH(0);
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volatile dma_ch_regs_t *ch1 = DMA_CH(1);
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uint32_t crc, t_prologue, t_mainloop, t_epilogue;
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int g, bank;
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// Ping-Pong Register Address Arrays (Physical for DMA)
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uint32_t phys_bank_AB[2] = {MATMUL_PHYS_B0_AB, MATMUL_PHYS_B1_AB};
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uint32_t phys_bank_C[2] = {MATMUL_PHYS_B0_C, MATMUL_PHYS_B1_C};
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uint32_t ctrl_start[2] = {CTRL_START_B0, CTRL_START_B1};
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/* ── Pipeline timing diagnostics ──────────────────────────────── */
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uint32_t t_now;
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uint32_t t_wait_ip = 0; // total ns waiting for IP done
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uint32_t t_wait_dma0 = 0; // total ns waiting for DMA Ch0 done
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uint32_t t_wait_dma1 = 0; // total ns waiting for DMA Ch1 done
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uint32_t t_fire_dma = 0; // total ns writing DMA registers
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uint32_t t_fire_ip = 0; // total ns writing IP ctrl register
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int n_loops = 0; // main loop iteration count
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int stall_ip = 0; // iterations where wait_ip actually blocked
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int stall_dma0 = 0; // iterations where wait_dma0 actually blocked
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int stall_dma1 = 0; // iterations where wait_dma1 actually blocked
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/* ── Start marker (must be first output) ──────────────────── */
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printf("MATMUL_START\n");
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// Reset IP state
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*mat_status = STATUS_DONE | STATUS_ERROR;
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*mat_crc = 0;
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/* ═══════════════════════════════════════════════════════════════
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* PROLOGUE: Load group 0 → Bank 0, start IP, pre-fire group 1
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* ═══════════════════════════════════════════════════════════════ */
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t_prologue = get_ns();
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// DMA Ch0: Load group 0 A+B (128 bytes) → IP Bank 0
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ch0->SRC_ADDR = EXTRAM_PHYS_AB(0);
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ch0->DST_ADDR = phys_bank_AB[0];
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ch0->LENGTH = 128;
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ch0->TAG = 10;
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ch0->CTRL = DMA_CTRL_VAL;
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while (!(ch0->STATUS & STATUS_DONE_BIT)) {}
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ch0->STATUS = STATUS_DONE_BIT;
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// Start IP Bank 0 (group 0)
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*mat_ctrl = ctrl_start[0];
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// Pre-fire: DMA Ch0 load group 1 → Bank 1 (overlaps with IP compute)
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if (MATMUL_GROUP_NUM > 1) {
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ch0->SRC_ADDR = EXTRAM_PHYS_AB(1);
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ch0->DST_ADDR = phys_bank_AB[1];
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ch0->LENGTH = 128;
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ch0->TAG = 10;
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ch0->CTRL = DMA_CTRL_VAL;
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}
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t_prologue = get_ns() - t_prologue;
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/* ═══════════════════════════════════════════════════════════════
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* MAIN LOOP: Fully-pipelined — pre-fire DMA load at loop tail
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* + per-phase timing diagnostics
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* ═══════════════════════════════════════════════════════════════ */
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t_mainloop = get_ns();
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bank = 1;
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// Prologue IP start time (for measuring first IP compute duration)
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// We can't easily isolate pure IP time, but aggregate wait tells us.
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for (g = 1; g < MATMUL_GROUP_NUM; g++) {
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int cur_bank = bank;
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int prev_bank = bank ^ 1;
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/* ── 1. Wait for previous IP computation ─────────────────── */
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t_now = get_ns();
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while (!(*mat_status & STATUS_DONE)) {}
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*mat_status = STATUS_DONE;
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{
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uint32_t dt = get_ns() - t_now;
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t_wait_ip += dt;
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if (dt > 0) stall_ip++;
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}
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/* ── 2. Wait for previous DMA Ch1 store ──────────────────── */
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if (g > 1) {
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t_now = get_ns();
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while (!(ch1->STATUS & STATUS_DONE_BIT)) {}
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ch1->STATUS = STATUS_DONE_BIT;
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uint32_t dt = get_ns() - t_now;
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t_wait_dma1 += dt;
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if (dt > 0) stall_dma1++;
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}
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/* ── 3. Start DMA Ch1 store: group (g-1) result → ExtRAM ── */
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t_now = get_ns();
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ch1->SRC_ADDR = phys_bank_C[prev_bank];
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ch1->DST_ADDR = EXTRAM_PHYS_C(g - 1);
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ch1->LENGTH = 192;
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ch1->TAG = 20;
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ch1->CTRL = DMA_CTRL_VAL;
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t_fire_dma += (get_ns() - t_now);
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/* ── 4. Wait for DMA Ch0 load (pre-fired in prev iteration) */
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t_now = get_ns();
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while (!(ch0->STATUS & STATUS_DONE_BIT)) {}
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ch0->STATUS = STATUS_DONE_BIT;
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{
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uint32_t dt = get_ns() - t_now;
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t_wait_dma0 += dt;
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if (dt > 0) stall_dma0++;
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}
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/* ── 5. Start IP computation ─────────────────────────────── */
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t_now = get_ns();
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*mat_ctrl = ctrl_start[cur_bank];
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t_fire_ip += (get_ns() - t_now);
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/* ── 6. PRE-FIRE DMA Ch0 load for next group ─────────────── */
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if (g < MATMUL_GROUP_NUM - 1) {
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int next_bank = bank ^ 1;
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t_now = get_ns();
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ch0->SRC_ADDR = EXTRAM_PHYS_AB(g + 1);
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ch0->DST_ADDR = phys_bank_AB[next_bank];
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ch0->LENGTH = 128;
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ch0->TAG = 10;
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ch0->CTRL = DMA_CTRL_VAL;
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t_fire_dma += (get_ns() - t_now);
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}
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bank ^= 1;
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n_loops++;
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}
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t_mainloop = get_ns() - t_mainloop;
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/* ═══════════════════════════════════════════════════════════════
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* EPILOGUE: Flush the final group
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* ═══════════════════════════════════════════════════════════════ */
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t_epilogue = get_ns();
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// Wait for last IP computation
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while (!(*mat_status & STATUS_DONE)) {}
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*mat_status = STATUS_DONE;
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// Wait for previous DMA store and start/complete final store
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while (!(ch1->STATUS & STATUS_DONE_BIT)) {}
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ch1->STATUS = STATUS_DONE_BIT;
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ch1->SRC_ADDR = phys_bank_C[(MATMUL_GROUP_NUM - 1) % 2];
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ch1->DST_ADDR = EXTRAM_PHYS_C(MATMUL_GROUP_NUM - 1);
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ch1->LENGTH = 192;
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ch1->TAG = 20;
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ch1->CTRL = DMA_CTRL_VAL;
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while (!(ch1->STATUS & STATUS_DONE_BIT)) {}
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ch1->STATUS = STATUS_DONE_BIT;
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t_epilogue = get_ns() - t_epilogue;
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/* ── Read hardware CRC32 ──────────────────────────────────── */
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crc = *mat_crc;
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/* ── Standard markers (required by test harness) ────────────── */
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printf("MATMUL_CRC32=%08lx\n", (unsigned long)crc);
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printf("TIME_PROLOGUE=%lu\n", (unsigned long)t_prologue);
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printf("TIME_LOOP=%lu\n", (unsigned long)t_mainloop);
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printf("TIME_LOOP_PER=%lu\n", (unsigned long)(t_mainloop / MATMUL_GROUP_NUM));
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printf("TIME_EPILOGUE=%lu\n", (unsigned long)t_epilogue);
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printf("TIME_TOTAL=%lu\n", (unsigned long)(t_prologue + t_mainloop + t_epilogue));
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/* ═══════════════════════════════════════════════════════════════
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* Pipeline Timing Diagnostics
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*
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* Interpretation guide:
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* PIPE_WAIT_DMA0 ≈ 0 → pre-fire working, DMA load never blocks
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* PIPE_WAIT_DMA0 > 0 → DMA load is bottleneck (wider bus / faster RAM)
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* PIPE_WAIT_IP > 0 → IP compute is bottleneck (optimize multiplier HW)
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* PIPE_WAIT_DMA1 > 0 → DMA store is bottleneck (bank reuse delay)
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* PIPE_STALL_* = N → that resource blocked EVERY iteration
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*
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* All times in nanoseconds. Averages over N-1 loop iterations.
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* ═══════════════════════════════════════════════════════════════ */
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printf("--- Pipeline Profile (%d loop iterations) ---\n", n_loops);
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printf("PIPE_WAIT_IP=%lu\n", (unsigned long)t_wait_ip);
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printf("PIPE_WAIT_IP_AVG=%lu\n", (unsigned long)(n_loops ? t_wait_ip / n_loops : 0));
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printf("PIPE_WAIT_DMA0=%lu\n", (unsigned long)t_wait_dma0);
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printf("PIPE_WAIT_DMA0_AVG=%lu\n", (unsigned long)(n_loops ? t_wait_dma0 / n_loops : 0));
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printf("PIPE_WAIT_DMA1=%lu\n", (unsigned long)t_wait_dma1);
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printf("PIPE_WAIT_DMA1_AVG=%lu\n", (unsigned long)(n_loops ? t_wait_dma1 / n_loops : 0));
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printf("PIPE_FIRE_DMA=%lu\n", (unsigned long)t_fire_dma);
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printf("PIPE_FIRE_IP=%lu\n", (unsigned long)t_fire_ip);
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printf("PIPE_STALL_IP=%d\n", stall_ip);
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printf("PIPE_STALL_DMA0=%d\n", stall_dma0);
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printf("PIPE_STALL_DMA1=%d\n", stall_dma1);
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printf("PIPE_SUM_WAITS=%lu\n", (unsigned long)(t_wait_ip + t_wait_dma0 + t_wait_dma1 + t_fire_dma + t_fire_ip));
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printf("MATMUL_DONE\n");
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return 0;
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}
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