76b5f30c6b
Move MATMUL_DONE to last line
2026-06-25 20:11:45 +08:00
d9483a9d39
Add timing instrumentation for profiling (prologue/loop/epilogue/crc32)
2026-06-25 20:10:31 +08:00
956cd67773
Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines
2026-06-25 20:03:53 +08:00
57ba5d271d
Remove all debug and printf
2026-06-25 15:44:18 +08:00
a9958ee4fa
BURST_LEN 47->63 (64 beats)
2026-06-25 04:08:18 +08:00
3cad98a811
Increase BURST_LEN to 47 (48 beats) to cover 192-byte C reads in one burst
2026-06-25 03:54:10 +08:00
54aa37adee
Add debug output for C[0][0]/C[1][1]/C[2][3] of groups 0,1
2026-06-25 03:03:10 +08:00
9ecda4aa7a
Fix CRC32 table, remove debug output
2026-06-25 02:51:36 +08:00
5e467175ea
Merge main (user mods) into no-fft
2026-06-25 00:44:01 +08:00
641d055f18
User mods: matmul RTL + shift_add_mult + C program
2026-06-25 00:43:16 +08:00
1660b283c4
Move DMA files to asm/, remove from common.mk
2026-06-24 23:52:30 +08:00
5459538a04
Add dma.c to common.mk link list
2026-06-24 23:47:33 +08:00
5dcee80b95
DMA-driven: A+B+C per group via DMA ch0/ch1, -O2 CRC32 from ExtRAM
2026-06-24 23:46:58 +08:00
a42568f635
Clean production code: -O2, read CRC32 from ExtRAM, remove all debug
2026-06-24 23:42:35 +08:00
c1fcb3c796
CRC32 on-the-fly from c_buf — bypass ExtRAM reads entirely
2026-06-24 23:38:06 +08:00
07f8422d75
Fix CRC32 table entry 187: 0x5CB30A04 -> 0x5CB36A04
2026-06-24 23:32:24 +08:00
93361733f6
Definitive write test: write 0xDEADBEEF then read back
2026-06-24 23:29:00 +08:00
16c0d7b639
Use __sync_synchronize() hardware barrier instead of asm compiler barrier
2026-06-24 23:22:38 +08:00
f0ebf1f5fa
Output A0/B0/C0 for groups 0-3 and N-2,N-1
2026-06-24 23:16:26 +08:00
2c8f5d37f3
Add asm memory barrier before CRC32 to flush write buffer
2026-06-24 23:09:06 +08:00
afef1f1433
Add group 1 A/B/C debug output
2026-06-24 23:03:46 +08:00
23bb112586
Print CRC32 loop counter to verify iteration count
2026-06-24 23:01:29 +08:00
8ea98874a5
Inline CRC32 computation into main (bypass function call)
2026-06-24 22:52:08 +08:00
d27e147652
Fix escaped quotes
2026-06-24 22:50:14 +08:00
f6146bd467
Minimal debug: CRC32 self-test + group 0 rdback in one line
2026-06-24 22:49:06 +08:00
e39a655861
Add CRC32 self-test debug output
2026-06-24 22:42:46 +08:00
bbd3e3358b
Fix extra brace in debug code
2026-06-24 22:38:18 +08:00
3269e83d68
Debug: check ExtRAM write-back at start/mid/end of range
2026-06-24 22:36:29 +08:00
4a67ca5c83
Add debug output for group 0 write-back and group 1 compute
2026-06-24 22:09:06 +08:00
aaefb04737
Sync asm/ (user-sample.c + Makefile) from test branch
...
MATMUL_GROUP_NUM defaults to 5000, overridable for fast local testing.
2026-06-24 17:01:45 +08:00
f8edd878d4
Rewrite matmul_test for CIC-IEC Stage 3 evaluation
...
- 5000 groups (N_GROUPS=5000), group 0 all-zero as required
- MATMUL_START before computation, MATMUL_DONE after CRC
- IEEE CRC32 over 960000-byte result region (little-endian words)
- MATMUL_CRC32=XXXXXXXX format, 8 hex digits, no 0x prefix
- Uncached ExtRAM access (0xA0000000 segment)
- Removed all debug output for minimal UART traffic
2026-06-24 16:42:08 +08:00
4a5ecc8bdc
Add debug output: print A[0..3], B[0..3], C[0..5] for group 0
2026-06-24 16:35:43 +08:00
e35fa5884d
Use uncached ExtRAM access (0xBC400000) to bypass CPU data cache
...
The open-la500 core has USE_CACHE enabled. Writes to 0x1c400000
go to the write-back data cache and never reach the SRAM model
before the testbench checks ExtRAM. Use the 0xA0000000 uncached
segment (same pattern as fft_dma/main.c).
2026-06-24 02:04:40 +08:00
b8a4fcc30b
Fix matmul_base address: 0x1f500000 -> 0xbf500000
...
The open-la500 CPU maps 0xbfxx_xxxx to the peripheral address space
(crossbar sees 0x1fxx_xxxx). FFT uses 0xbf400000, CONFREG uses
0xbf20f100, UART uses 0xbf000000. Matmul must follow the same
convention.
2026-06-24 01:58:29 +08:00
ff6e572996
matmul_test: rewrite for ExtRAM flow, add IP error debug
...
- Rewrite main.c to read from ExtRAM (0x1c400000), compute
via matmul IP, write results back. Matches testbench
expectation of 10 groups.
- Add in matmul_axi_slave to trace error writes
2026-06-24 01:49:02 +08:00
fbc993b846
Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
2026-06-23 01:22:45 +08:00
