FallenSigh
717a9929b6
- Replace / and % operators in comp_decomp_sync with Barrett multiply-by-reciprocal (dividend * 5039 >> 24) + correction step. Eliminates ~100 CARRY4 divider chain. - Add include_dirs for sources_1 fileset so Windows Vivado synthesis finds defines.vh. - Change CLK_PERIOD from 10.0 (100MHz) to 40.0 (50MHz) to reflect actual target.
94 lines
4.2 KiB
Tcl
94 lines
4.2 KiB
Tcl
# create_project.tcl — 自动创建 Vivado 工程（仿真用），加载 ML-KEM 顶层模块
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# mlkem_top 及其全部叶子算子与 hello_world 端到端 testbench。
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#
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# 与已验证的 XSIM 流程保持一致：
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# - 加载 mlkem_top 实际依赖的全部 RTL 源文件（含 sd_bram 存储）
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# - 顶层仿真模块 = tb_mlkem_hello_world_xsim
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#
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# Usage:
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# cd ~/Dev/mlkem
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# vivado -mode batch -source create_project.tcl
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# 或在 Vivado Tcl Console 中：
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# source create_project.tcl
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set PROJECT_NAME mlkem
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set PROJECT_DIR [file normalize [file dirname [info script]]]
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# 仅仿真工程，无需指定 FPGA part（XSim 用默认 part 即可）
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create_project -force ${PROJECT_NAME} ${PROJECT_DIR}/vivado_prj
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set_property target_simulator XSim [current_project]
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# ===================================================================
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# RTL 源文件 —— hello_world 所需的全部模块
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# ===================================================================
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# ── SHA3 / Keccak ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/keccak_round.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/keccak_core.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/sha3_top_shared.v
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# ── 采样（共享 keccak_core 变体）──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/sample_ntt/sample_ntt_sync_shared.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/sample_cbd/sample_cbd_sync_shared.v
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# ── NTT ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/barrett_mul.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/zeta_rom.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/butterfly_unit.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/ntt_core.v
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# ── 多项式乘法 ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/basecase_mul.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/poly_mul_zeta_rom.v
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/poly_mul_sync.v
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# ── 存储（ek/dk 字节缓冲，registered-read BRAM）──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/storage/sd_bram.v
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# ── 公共原语 ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/common/pipeline_reg.v
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# ── 压缩 / 解压缩 ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/comp_decomp/comp_decomp_sync.v
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# ── 顶层 KeyGen 集成 ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/mlkem_top.v
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# ── hello_world 端到端 testbench ──
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read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/TB/tb_mlkem_hello_world_xsim.v
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# ===================================================================
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# 仿真设置
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# ===================================================================
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# 顶层仿真模块
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set_property top tb_mlkem_hello_world_xsim [get_filesets sim_1]
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set_property top_lib xil_defaultlib [get_filesets sim_1]
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# `include "sync_rtl/common/defines.vh" 的包含路径（同时用于仿真和综合）
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set_property include_dirs ${PROJECT_DIR} [get_filesets sim_1]
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set_property include_dirs ${PROJECT_DIR} [get_filesets sources_1]
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# hello_world TB 使用 localparam KP=2（硬编码），无 generic 传入
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# 切换 K 值需编辑 tb_mlkem_hello_world_xsim.v 中的 KP 参数后重跑
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# 跑到 $finish 为止；显式时标（XSim 默认已加 --relax，勿重复）
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set_property -name {xsim.simulate.runtime} -value {all} -objects [get_filesets sim_1]
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set_property -name {xsim.elaborate.xelab.more_options} \
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-value {--timescale 1ns/1ps} -objects [get_filesets sim_1]
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# ===================================================================
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puts "========================================"
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puts " Project created: ${PROJECT_DIR}/vivado_prj/${PROJECT_NAME}.xpr"
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puts " 仿真模块: tb_mlkem_hello_world_xsim (K=2 硬编码)"
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puts ""
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puts " 运行仿真（runtime=all，会自动跑到 TB 的 \$finish）："
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puts " - GUI: 打开工程后点 Run Simulation，或 Tcl Console: launch_simulation"
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puts " - batch: vivado -mode batch -source create_project.tcl 后，"
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puts " 另开: open_project vivado_prj/mlkem.xpr; launch_simulation"
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puts " （勿在 launch_simulation 后再手动 run all —— 仿真已到 \$finish，"
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puts " 再 run 会触发 TB 的 120ms 看门狗误报 timeout）"
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puts " 期望输出: hello_world 端到端: KeyGen→Encaps→XOR→Decaps→XOR 全 PASS"
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puts "========================================"
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