# create_project.tcl — 自动创建 Vivado 工程（仿真用），加载 ML-KEM 顶层模块
# mlkem_top 及其全部叶子算子与 hello_world 端到端 testbench。
#
# 与已验证的 XSIM 流程保持一致：
#   - 加载 mlkem_top 实际依赖的全部 RTL 源文件（含 sd_bram 存储）
#   - 顶层仿真模块 = tb_mlkem_hello_world_xsim
#
# Usage:
#   cd ~/Dev/mlkem
#   vivado -mode batch -source create_project.tcl
# 或在 Vivado Tcl Console 中：
#   source create_project.tcl

set PROJECT_NAME  mlkem
set PROJECT_DIR   [file normalize [file dirname [info script]]]

# 仅仿真工程，无需指定 FPGA part（XSim 用默认 part 即可）
create_project -force ${PROJECT_NAME} ${PROJECT_DIR}/vivado_prj

set_property target_simulator XSim [current_project]

# ===================================================================
# RTL 源文件 —— hello_world 所需的全部模块
# ===================================================================

# ── SHA3 / Keccak ──
read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/keccak_round.v
read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/keccak_core.v
read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/sha3_top_shared.v

# ── 采样（共享 keccak_core 变体）──
read_verilog -sv ${PROJECT_DIR}/sync_rtl/sample_ntt/sample_ntt_sync_shared.v
read_verilog -sv ${PROJECT_DIR}/sync_rtl/sample_cbd/sample_cbd_sync_shared.v

# ── NTT ──
read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/barrett_mul.v
read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/zeta_rom.v
read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/butterfly_unit.v
read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/ntt_core.v

# ── 多项式乘法 ──
read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/basecase_mul.v
read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/poly_mul_zeta_rom.v
read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/poly_mul_sync.v

# ── 存储（ek/dk 字节缓冲，registered-read BRAM）──
read_verilog -sv ${PROJECT_DIR}/sync_rtl/storage/sd_bram.v

# ── 公共原语 ──
read_verilog -sv ${PROJECT_DIR}/sync_rtl/common/pipeline_reg.v

# ── 压缩 / 解压缩 ──
read_verilog -sv ${PROJECT_DIR}/sync_rtl/comp_decomp/comp_decomp_sync.v

# ── 顶层 KeyGen 集成 ──
read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/mlkem_top.v

# ── hello_world 端到端 testbench ──
read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/TB/tb_mlkem_hello_world_xsim.v

# ===================================================================
# 仿真设置
# ===================================================================

# 顶层仿真模块
set_property top tb_mlkem_hello_world_xsim [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]

# `include "sync_rtl/common/defines.vh" 的包含路径（同时用于仿真和综合）
set_property include_dirs ${PROJECT_DIR} [get_filesets sim_1]
set_property include_dirs ${PROJECT_DIR} [get_filesets sources_1]

# hello_world TB 使用 localparam KP=2（硬编码），无 generic 传入
# 切换 K 值需编辑 tb_mlkem_hello_world_xsim.v 中的 KP 参数后重跑

# 跑到 $finish 为止；显式时标（XSim 默认已加 --relax，勿重复）
set_property -name {xsim.simulate.runtime} -value {all} -objects [get_filesets sim_1]
set_property -name {xsim.elaborate.xelab.more_options} \
  -value {--timescale 1ns/1ps} -objects [get_filesets sim_1]

# ===================================================================
puts "========================================"
puts " Project created: ${PROJECT_DIR}/vivado_prj/${PROJECT_NAME}.xpr"
puts " 仿真模块: tb_mlkem_hello_world_xsim (K=2 硬编码)"
puts ""
puts " 运行仿真（runtime=all，会自动跑到 TB 的 \$finish）："
puts "   - GUI:    打开工程后点 Run Simulation，或 Tcl Console: launch_simulation"
puts "   - batch:  vivado -mode batch -source create_project.tcl 后，"
puts "             另开: open_project vivado_prj/mlkem.xpr; launch_simulation"
puts "   （勿在 launch_simulation 后再手动 run all —— 仿真已到 \$finish，"
puts "     再 run 会触发 TB 的 120ms 看门狗误报 timeout）"
puts " 期望输出:  hello_world 端到端: KeyGen→Encaps→XOR→Decaps→XOR 全 PASS"
puts "========================================"