ciciec2026

fallensigh/ciciec2026

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FallenSigh be2e54c8ab revert(mlkem): drop poly_mul ping-pong (B2) to reclaim ~7k LUT

B2 (ping-pong poly_mul + decoupled MAC load) doubled the 256x12 coeff
register file (mem_A/B -> 4 arrays) costing ~7k LUT for only ~2.8% Encaps
latency (K=2) — the worst area/latency ratio of the optimization set.
Revert restores single-buffer poly_mul and serial MAC. B1 (compress
streaming) and R1 (dual-butterfly NTT) are kept.

Verified byte-exact vs NIST KAT: Encaps 9/9, Decaps 9/9, KeyGen, hello
end-to-end, poly_mul standalone TB 11/11 — all PASS.

ENC_U K=2 4177->4689, ENC_V 2089->2345 (B2's hidden load reappears).

2026-07-11 03:48:50 +08:00

APB_UART

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

axi_axil_adapter

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

bram0

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

Bus_interconnects

feat: optimize sram read channel