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FallenSigh 4857016b42 update reports & add mlkem cdc test result & update pll

2026-07-11 10:09:45 +08:00

..

APB_UART

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

axi_axil_adapter

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

bram0

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

Bus_interconnects

feat: optimize sram read channel

2026-07-05 17:12:38 +08:00

cdma

remove dsp usage

2026-07-04 21:20:32 +08:00

confreg

Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines

2026-06-25 20:03:53 +08:00

DVI

Fix linter: remove placeholder, fix DVI reg declarations

2026-06-24 21:41:05 +08:00

fft

fix: add use_dsp=no to FFT Multiply and fft_mlkem_axi_slave

2026-07-08 03:57:39 +08:00

matmul

add use_dsp=no for matmul

2026-07-08 03:20:34 +08:00

mlkem

perf(mlkem): pipeline CBD->bank write to cut 100 MHz critical path

2026-07-11 07:42:35 +08:00

open-la500

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

PLL_2018_3

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

PLL_2019_2

update reports & add mlkem cdc test result & update pll

2026-07-11 10:09:45 +08:00

PLL_2023_2

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

ram_wrap

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

rst_sync

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00