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v0.1
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matmul-crc
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24
.gitattributes
vendored
Normal file
24
.gitattributes
vendored
Normal file
@@ -0,0 +1,24 @@
|
||||
* text=auto eol=lf
|
||||
|
||||
# Binary artifacts
|
||||
*.bin -text
|
||||
*.elf -text
|
||||
*.o -text
|
||||
*.a -text
|
||||
*.so -text
|
||||
*.dll -text
|
||||
*.exe -text
|
||||
|
||||
# Documents and images
|
||||
*.pdf -text
|
||||
*.png -text
|
||||
*.jpg -text
|
||||
*.jpeg -text
|
||||
*.gif -text
|
||||
*.bmp -text
|
||||
*.ico -text
|
||||
|
||||
# FPGA packaged IP/checkpoints can be binary archives.
|
||||
*.xcix -text
|
||||
*.dcp -text
|
||||
*.bit -text
|
||||
6
.gitignore
vendored
6
.gitignore
vendored
@@ -18,12 +18,6 @@ webtalk*.jou
|
||||
vivado_pid*.txt
|
||||
*.bit
|
||||
|
||||
# ========================================
|
||||
# Generated binary / AXI images
|
||||
# ========================================
|
||||
*.bin
|
||||
*.mif
|
||||
|
||||
# ========================================
|
||||
# OS generated files
|
||||
# ========================================
|
||||
|
||||
@@ -1,18 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:35:52 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_cdc -file ./vivado_reports/impl_cdc.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200t-fbg676
|
||||
| Speed File : -1 PRODUCTION 1.23 2018-06-13
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
CDC Report
|
||||
|
||||
Severity Source Clock Destination Clock CDC Type Exceptions Endpoints Safe Unsafe Unknown No ASYNC_REG
|
||||
-------- ------------ ----------------- ------------ ------------------- --------- ---- ------ ------- ------------
|
||||
Critical sys_clk cpu_clk User Ignored Asynch Clock Groups 57 55 2 0 1
|
||||
Warning cpu_clk sys_clk User Ignored Asynch Clock Groups 153 153 0 0 0
|
||||
|
||||
@@ -1,27 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:35:51 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_clock_networks -file ./vivado_reports/impl_clock_networks.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200t-fbg676
|
||||
| Speed File : -1 PRODUCTION 1.23 2018-06-13
|
||||
--------------------------------------------------------------------------------------
|
||||
|
||||
Clock Networks Report
|
||||
|
||||
|
||||
Constrained Clocks
|
||||
-------------------
|
||||
|
||||
Clock clk (50MHz)(endpoints: 17477 clock, 2 nonclock)
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||||
Port clk
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||||
|
||||
|
||||
Unconstrained Clocks
|
||||
-------------------
|
||||
|
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Clock Q (endpoints: 23490 clock, 1 nonclock)
|
||||
FDCE/Q (u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg)
|
||||
|
||||
@@ -1,229 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:35:50 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_clock_utilization -file ./vivado_reports/impl_clock_utilization.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200t-fbg676
|
||||
| Speed File : -1 PRODUCTION 1.23 2018-06-13
|
||||
| Design State : Synthesized
|
||||
--------------------------------------------------------------------------------------------
|
||||
|
||||
Clock Utilization Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Clock Primitive Utilization
|
||||
2. Global Clock Resources
|
||||
3. Global Clock Source Details
|
||||
4. Clock Regions: Key Resource Utilization
|
||||
5. Clock Regions : Global Clock Summary
|
||||
6. Device Cell Placement Summary for Global Clock g0
|
||||
7. Device Cell Placement Summary for Global Clock g1
|
||||
8. Device Cell Placement Summary for Global Clock g2
|
||||
9. Device Cell Placement Summary for Global Clock g3
|
||||
10. Clock Region Cell Placement per Global Clock: Region X0Y3
|
||||
|
||||
1. Clock Primitive Utilization
|
||||
------------------------------
|
||||
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
| Type | Used | Available | LOC | Clock Region | Pblock |
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
| BUFGCTRL | 4 | 32 | 0 | 0 | 0 |
|
||||
| BUFH | 0 | 120 | 0 | 0 | 0 |
|
||||
| BUFIO | 0 | 40 | 0 | 0 | 0 |
|
||||
| BUFMR | 0 | 20 | 0 | 0 | 0 |
|
||||
| BUFR | 0 | 40 | 0 | 0 | 0 |
|
||||
| MMCM | 0 | 10 | 0 | 0 | 0 |
|
||||
| PLL | 1 | 10 | 0 | 0 | 0 |
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
|
||||
|
||||
2. Global Clock Resources
|
||||
-------------------------
|
||||
|
||||
+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
|
||||
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
|
||||
+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
|
||||
| g0 | src0 | BUFG/O | None | | n/a | 0 | 23490 | 0 | | | r_wb_reg[7]_i_3/O | u_mlkem_axi_slave/mlkem_clk |
|
||||
| g1 | src1 | BUFG/O | None | | n/a | 1 | 10604 | 1 | 20.000 | sys_clk | pll_clk.u_clk_pll/inst/clkout2_buf/O | pll_clk.u_clk_pll/inst/sys_clk |
|
||||
| g2 | src1 | BUFG/O | None | | n/a | 0 | 5859 | 0 | 30.323 | cpu_clk | pll_clk.u_clk_pll/inst/clkout1_buf/O | pll_clk.u_clk_pll/inst/cpu_clk |
|
||||
| g3 | src1 | BUFG/O | None | | n/a | 0 | 1 | 0 | 20.000 | clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkf_buf/O | pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll |
|
||||
+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
|
||||
|
||||
3. Global Clock Source Details
|
||||
------------------------------
|
||||
|
||||
+-----------+-----------+--------------------+------------+------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
|
||||
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
|
||||
+-----------+-----------+--------------------+------------+------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
|
||||
| src0 | g0 | FDCE/Q | None | | n/a | 1 | 1 | | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg/Q | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg_0 |
|
||||
| src1 | g3 | PLLE2_ADV/CLKFBOUT | None | | n/a | 1 | 0 | 20.000 | clkfbout_clk_pll | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT | pll_clk.u_clk_pll/inst/clkfbout_clk_pll |
|
||||
| src1 | g2 | PLLE2_ADV/CLKOUT0 | None | | n/a | 1 | 0 | 30.323 | cpu_clk | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll |
|
||||
| src1 | g1 | PLLE2_ADV/CLKOUT1 | None | | n/a | 1 | 0 | 20.000 | sys_clk | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 | pll_clk.u_clk_pll/inst/sys_clk_clk_pll |
|
||||
+-----------+-----------+--------------------+------------+------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
|
||||
|
||||
4. Clock Regions: Key Resource Utilization
|
||||
------------------------------------------
|
||||
|
||||
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
|
||||
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 800 | 0 | 60 | 0 | 30 | 0 | 60 |
|
||||
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
|
||||
| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4200 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
|
||||
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
|
||||
| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
|
||||
| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
|
||||
| X0Y3 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
|
||||
| X1Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
|
||||
| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 1 | 0 | 50 | 0 | 50 | 0 | 2550 | 0 | 750 | 0 | 50 | 0 | 25 | 0 | 60 |
|
||||
| X1Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
* Global Clock column represents track count; while other columns represents cell counts
|
||||
|
||||
|
||||
5. Clock Regions : Global Clock Summary
|
||||
---------------------------------------
|
||||
|
||||
All Modules
|
||||
+----+----+----+
|
||||
| | X0 | X1 |
|
||||
+----+----+----+
|
||||
| Y4 | 0 | 0 |
|
||||
| Y3 | 1 | 0 |
|
||||
| Y2 | 0 | 0 |
|
||||
| Y1 | 0 | 0 |
|
||||
| Y0 | 0 | 0 |
|
||||
+----+----+----+
|
||||
|
||||
|
||||
6. Device Cell Placement Summary for Global Clock g0
|
||||
----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
|
||||
| g0 | BUFG/O | n/a | | | | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
|
||||
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
|
||||
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
**** GT Loads column represents load cell count of GT types
|
||||
|
||||
|
||||
+----+----+----+
|
||||
| | X0 | X1 |
|
||||
+----+----+----+
|
||||
| Y4 | 0 | 0 |
|
||||
| Y3 | 0 | 0 |
|
||||
| Y2 | 0 | 0 |
|
||||
| Y1 | 0 | 0 |
|
||||
| Y0 | 0 | 0 |
|
||||
+----+----+----+
|
||||
|
||||
|
||||
7. Device Cell Placement Summary for Global Clock g1
|
||||
----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
|
||||
| g1 | BUFG/O | n/a | sys_clk | 20.000 | {0.000 10.000} | 0 | 1 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
|
||||
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
|
||||
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
**** GT Loads column represents load cell count of GT types
|
||||
|
||||
|
||||
+----+----+----+
|
||||
| | X0 | X1 |
|
||||
+----+----+----+
|
||||
| Y4 | 0 | 0 |
|
||||
| Y3 | 1 | 0 |
|
||||
| Y2 | 0 | 0 |
|
||||
| Y1 | 0 | 0 |
|
||||
| Y0 | 0 | 0 |
|
||||
+----+----+----+
|
||||
|
||||
|
||||
8. Device Cell Placement Summary for Global Clock g2
|
||||
----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
|
||||
| g2 | BUFG/O | n/a | cpu_clk | 30.323 | {0.000 15.161} | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
|
||||
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
|
||||
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
**** GT Loads column represents load cell count of GT types
|
||||
|
||||
|
||||
+----+----+----+
|
||||
| | X0 | X1 |
|
||||
+----+----+----+
|
||||
| Y4 | 0 | 0 |
|
||||
| Y3 | 0 | 0 |
|
||||
| Y2 | 0 | 0 |
|
||||
| Y1 | 0 | 0 |
|
||||
| Y0 | 0 | 0 |
|
||||
+----+----+----+
|
||||
|
||||
|
||||
9. Device Cell Placement Summary for Global Clock g3
|
||||
----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
|
||||
| g3 | BUFG/O | n/a | clkfbout_clk_pll | 20.000 | {0.000 10.000} | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll |
|
||||
+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
|
||||
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
**** GT Loads column represents load cell count of GT types
|
||||
|
||||
|
||||
+----+----+----+
|
||||
| | X0 | X1 |
|
||||
+----+----+----+
|
||||
| Y4 | 0 | 0 |
|
||||
| Y3 | 0 | 0 |
|
||||
| Y2 | 0 | 0 |
|
||||
| Y1 | 0 | 0 |
|
||||
| Y0 | 0 | 0 |
|
||||
+----+----+----+
|
||||
|
||||
|
||||
10. Clock Region Cell Placement per Global Clock: Region X0Y3
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
| g1 | n/a | BUFG/O | None | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
|
||||
# Location of IO Primitives which is load of clock spine
|
||||
set_property LOC IOB_X0Y173 [get_cells video_clk_OBUF_inst]
|
||||
|
||||
# Location of clock ports
|
||||
set_property LOC IOB_X0Y176 [get_ports clk]
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,66 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:38:45 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_design_analysis -timing -logic_level_distribution -file ./vivado_reports/impl_design_analysis.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200t
|
||||
| Design State : Synthesized
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report Design Analysis
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Setup Path Characteristics 1-1
|
||||
2. Logic Level Distribution
|
||||
|
||||
1. Setup Path Characteristics 1-1
|
||||
---------------------------------
|
||||
|
||||
+---------------------------+-----------------------------------------------------------------------------------------------------------+
|
||||
| Characteristics | Path #1 |
|
||||
+---------------------------+-----------------------------------------------------------------------------------------------------------+
|
||||
| Requirement | 20.000 |
|
||||
| Path Delay | 17.702 |
|
||||
| Logic Delay | 4.444(26%) |
|
||||
| Net Delay | 13.258(74%) |
|
||||
| Clock Skew | -0.145 |
|
||||
| Slack | 2.111 |
|
||||
| Clock Relationship | Safely Timed |
|
||||
| Logic Levels | 18 |
|
||||
| Routes | 0 |
|
||||
| Logical Path | FDRE LUT2 CARRY4 CARRY4 LUT2 CARRY4 LUT6 LUT6 LUT6 LUT6 LUT6 LUT5 LUT6 LUT5 LUT5 LUT5 LUT5 LUT6 LUT6 FDSE |
|
||||
| Start Point Clock | sys_clk |
|
||||
| End Point Clock | sys_clk |
|
||||
| DSP Block | None |
|
||||
| BRAM | None |
|
||||
| IO Crossings | 0 |
|
||||
| Config Crossings | 0 |
|
||||
| SLR Crossings | 0 |
|
||||
| PBlocks | 0 |
|
||||
| High Fanout | 16 |
|
||||
| Dont Touch | 0 |
|
||||
| Mark Debug | 0 |
|
||||
| Start Point Pin Primitive | FDRE/C |
|
||||
| End Point Pin Primitive | FDSE/D |
|
||||
| Start Point Pin | p_reg[1]/C |
|
||||
| End Point Pin | crc_reg_reg[18]/D |
|
||||
+---------------------------+-----------------------------------------------------------------------------------------------------------+
|
||||
* Bounding box calculated as % of dimensions for the target device (436, 500)
|
||||
|
||||
|
||||
2. Logic Level Distribution
|
||||
---------------------------
|
||||
|
||||
+-----------------+-------------+----+-----+----+-----+-----+----+----+----+----+----+----+----+----+----+
|
||||
| End Point Clock | Requirement | 10 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 29 | 30 | 31 | 32 |
|
||||
+-----------------+-------------+----+-----+----+-----+-----+----+----+----+----+----+----+----+----+----+
|
||||
| cpu_clk | 30.323ns | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 65 | 40 | 34 | 62 |
|
||||
| sys_clk | 20.000ns | 2 | 120 | 72 | 122 | 348 | 89 | 7 | 37 | 1 | 1 | 0 | 0 | 0 | 0 |
|
||||
+-----------------+-------------+----+-----+----+-----+-----+----+----+----+----+----+----+----+----+----+
|
||||
* Columns represent the logic levels per end point clock
|
||||
** Distribution is for top worst 1000 paths
|
||||
|
||||
|
||||
@@ -1,248 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:35:54 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_drc -file ./vivado_reports/impl_drc.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200tfbg676-1
|
||||
| Speed File : -1
|
||||
| Design State : Synthesized
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
Report DRC
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: design_1
|
||||
Design limits: <entire design considered>
|
||||
Ruledeck: default
|
||||
Max violations: <unlimited>
|
||||
Violations found: 42
|
||||
+-----------+----------+----------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+-----------+----------+----------------------------+------------+
|
||||
| CHECK-3 | Warning | Report rule limit reached | 2 |
|
||||
| REQP-1839 | Warning | RAMB36 async control check | 20 |
|
||||
| REQP-1840 | Warning | RAMB18 async control check | 20 |
|
||||
+-----------+----------+----------------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
CHECK-3#1 Warning
|
||||
Report rule limit reached
|
||||
REQP-1839 rule limit reached: 20 violations have been found.
|
||||
Related violations: <none>
|
||||
|
||||
CHECK-3#2 Warning
|
||||
Report rule limit reached
|
||||
REQP-1840 rule limit reached: 20 violations have been found.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#1 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#2 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#3 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#4 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#5 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#6 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#7 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#8 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#9 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#10 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#11 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#12 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#13 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#14 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#15 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#16 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#17 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#18 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#19 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#20 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#1 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#2 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#3 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#4 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#5 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#6 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#7 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#8 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#9 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#10 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#11 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#12 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#13 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#14 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#15 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#16 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#17 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENARDEN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_1__15_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#18 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENBWREN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_2__13_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#19 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[2] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#20 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[3] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
@@ -1,121 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:38:35 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_high_fanout_nets -max_nets 100 -file ./vivado_reports/impl_high_fanout_nets.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200t
|
||||
--------------------------------------------------------------------------------------------------------
|
||||
|
||||
High Fan-out Nets Information
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+---------------------------------------------------------------------------------------+--------+-------------+
|
||||
| Net Name | Fanout | Driver Type |
|
||||
+---------------------------------------------------------------------------------------+--------+-------------+
|
||||
| pll_clk.u_rst_sys/p_0_in | 28767 | LUT1 |
|
||||
| pll_clk.u_clk_pll/inst/sys_clk | 10994 | BUFG |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_0 | 2097 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/E[0] | 2048 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 | 1614 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1 | 1608 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/sha3_ack_reg | 1604 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sel_snt | 1602 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] | 1601 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_snt/state_next[1] | 1601 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_snt/state_next[2] | 1601 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mb_state_r[1599]_i_1_n_0 | 1600 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_2 | 1122 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0 | 1088 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0 | 1088 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[1]_rep__0_13 | 1088 | LUT5 |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[2] | 1080 | FDRE |
|
||||
| u_matmul_axi_slave/w_addr[2] | 879 | FDRE |
|
||||
| u_matmul_axi_slave/w_addr[3] | 874 | FDRE |
|
||||
| u_cpu/reset | 799 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg_n_0_[0] | 788 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg_n_0_[1] | 787 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr1[0] | 774 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr1[1] | 774 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[3] | 773 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[1] | 772 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[2] | 771 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/comp_k_reg[0]_rep_n_0 | 771 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/comp_k_reg[1]_rep_n_0 | 771 | FDCE |
|
||||
| u_cpu/u_mul/E[0] | 716 | LUT1 |
|
||||
| u_matmul_axi_slave/current_r_offset[2] | 525 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/r_r | 512 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 | 512 | LUT2 |
|
||||
| u_matmul_axi_slave/w_addr[4] | 438 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr1[2] | 390 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[4] | 388 | FDCE |
|
||||
| u_cpu/wb_stage/w_index[0] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[1] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[2] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[3] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[4] | 358 | LUT6 |
|
||||
| u_matmul_axi_slave/acc_idx_d4[0] | 354 | FDRE |
|
||||
| u_matmul_axi_slave/acc_idx_d4[1] | 354 | FDRE |
|
||||
| u_matmul_axi_slave/acc_idx_d4[2] | 354 | FDRE |
|
||||
| u_matmul_axi_slave/acc_idx_d4[3] | 354 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1022]_i_2_n_0 | 352 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[126]_i_2_n_0 | 352 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[254]_i_2_n_0 | 352 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[382]_i_2_n_0 | 352 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[510]_i_2_n_0 | 352 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[638]_i_2_n_0 | 352 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[766]_i_2_n_0 | 352 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[894]_i_2_n_0 | 352 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[4] | 329 | LUT3 |
|
||||
| u_cpu/wb_stage/we_0 | 324 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[3] | 321 | LUT3 |
|
||||
| u_matmul_axi_slave/w_addr[5] | 303 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rho_r1 | 294 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/pre_addr_l_reg[7]_0[0] | 288 | CARRY4 |
|
||||
| u_matmul_axi_slave/sel0[0] | 262 | FDRE |
|
||||
| u_matmul_axi_slave/sel0[1] | 261 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc | 260 | LUT5 |
|
||||
| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0 | 260 | LUT2 |
|
||||
| u_matmul_axi_slave/pipe_cnt_reg_n_0_[2] | 260 | FDRE |
|
||||
| u_matmul_axi_slave/pipe_cnt_reg_n_0_[3] | 259 | FDRE |
|
||||
| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 | 258 | LUT3 |
|
||||
| u_matmul_axi_slave/pipe_cnt[3]_i_3_n_0 | 257 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/dj_phase_reg[1]_1[0] | 256 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r | 256 | LUT3 |
|
||||
| u_matmul_axi_slave/m_in_b[0][31]_i_1_n_0 | 256 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode | 250 | LUT4 |
|
||||
| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge | 245 | LUT2 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10] | 239 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11] | 239 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8] | 238 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10] | 238 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11] | 238 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2] | 238 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5] | 238 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7] | 238 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8] | 238 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9] | 238 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7] | 237 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9] | 237 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0] | 237 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1] | 237 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6] | 237 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0] | 235 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1] | 235 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2] | 235 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3] | 235 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4] | 235 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5] | 235 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6] | 235 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3] | 235 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4] | 235 | RAMB36E1 |
|
||||
| u_cpu/exe_stage/ds_to_es_bus_r0 | 234 | LUT5 |
|
||||
| u_cpu/mem_stage/E[0] | 232 | LUT1 |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0 | 211 | LUT2 |
|
||||
| u_cpu/mem_stage/es_to_ms_bus_r0 | 210 | LUT2 |
|
||||
+---------------------------------------------------------------------------------------+--------+-------------+
|
||||
|
||||
|
||||
@@ -1,718 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:36:08 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_io -file ./vivado_reports/impl_io.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200t
|
||||
| Speed File : -1
|
||||
| Package : fbg676
|
||||
| Package Version : FINAL 2012-06-20
|
||||
| Package Pin Delay Version : FINAL VERS. 2.0 2012-06-20
|
||||
-------------------------------------------------------------------------------------------------
|
||||
|
||||
IO Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
2. IO Assignments by Package Pin
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+---------------+
|
||||
| Total User IO |
|
||||
+---------------+
|
||||
| 202 |
|
||||
+---------------+
|
||||
|
||||
|
||||
2. IO Assignments by Package Pin
|
||||
--------------------------------
|
||||
|
||||
+------------+-------------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
|
||||
+------------+-------------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
| A1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
|
||||
| A2 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A3 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A4 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A5 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A7 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| A8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A9 | | | MGTPTXN2_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| A10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A11 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A13 | | | MGTPRXN2_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| A14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A15 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| A16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A17 | dpy1[0] | High Range | IO_L9P_T1_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| A18 | leds[11] | High Range | IO_L9N_T1_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| A19 | dpy0[3] | High Range | IO_L10N_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| A20 | leds[14] | High Range | IO_L15N_T2_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| A21 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
|
||||
| A22 | leds[13] | High Range | IO_L17N_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| A23 | leds[9] | High Range | IO_L21P_T3_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| A24 | leds[2] | High Range | IO_L21N_T3_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| A25 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA1 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
|
||||
| AA2 | | High Range | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA3 | | High Range | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA4 | | High Range | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA5 | | High Range | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA7 | | High Range | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA8 | | High Range | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA10 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AA11 | | | MGTREFCLK1P_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AA12 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AA13 | | | MGTREFCLK0P_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AA14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA15 | ext_ram_data[23] | High Range | IO_L23N_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA17 | ext_ram_addr[8] | High Range | IO_L19P_T3_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA18 | ext_ram_addr[7] | High Range | IO_L17N_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA19 | ext_ram_data[30] | High Range | IO_L13P_T2_MRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA20 | | High Range | IO_L12P_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AA21 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
|
||||
| AA22 | base_ram_addr[14] | High Range | IO_L8P_T1_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA23 | base_ram_addr[11] | High Range | IO_L8N_T1_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA24 | base_ram_data[8] | High Range | IO_L7P_T1_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA25 | ext_ram_addr[10] | High Range | IO_L5N_T0_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB1 | | High Range | IO_L7P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AB2 | | High Range | IO_L11P_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AB3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB4 | | High Range | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AB5 | | High Range | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AB6 | | High Range | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AB7 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| AB8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB11 | | | MGTREFCLK1N_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AB12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB13 | | | MGTREFCLK0N_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AB14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB15 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | | | |
|
||||
| AB16 | ext_ram_data[16] | High Range | IO_L22P_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AB17 | ext_ram_data[18] | High Range | IO_L19N_T3_VREF_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AB18 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
|
||||
| AB19 | ext_ram_oe_n | High Range | IO_L13N_T2_MRCC_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AB20 | | High Range | IO_L12N_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AB21 | ext_ram_data[27] | High Range | IO_L11P_T1_SRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AB22 | ext_ram_be_n[3] | High Range | IO_0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AB23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB24 | base_ram_addr[10] | High Range | IO_L9P_T1_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AB25 | ext_ram_addr[12] | High Range | IO_L7N_T1_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AB26 | ext_ram_addr[11] | High Range | IO_L3P_T0_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC1 | | High Range | IO_L7N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AC2 | | High Range | IO_L11N_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AC3 | | High Range | IO_L14P_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AC4 | | High Range | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AC5 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
|
||||
| AC6 | | High Range | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AC7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AC8 | | | MGTPTXP2_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AC9 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AC10 | | | MGTPTXP0_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AC11 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AC12 | | | MGTPRXP0_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AC13 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AC14 | | | MGTPRXP2_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AC15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AC16 | ext_ram_data[21] | High Range | IO_L22N_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC17 | ext_ram_data[25] | High Range | IO_L20P_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC18 | ext_ram_data[19] | High Range | IO_L15P_T2_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC19 | ext_ram_data[17] | High Range | IO_L14P_T2_SRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AC21 | ext_ram_data[29] | High Range | IO_L11N_T1_SRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC22 | ext_ram_addr[5] | High Range | IO_L2P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC23 | ext_ram_data[31] | High Range | IO_L2N_T0_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC24 | ext_ram_addr[14] | High Range | IO_L9N_T1_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC25 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
|
||||
| AC26 | ext_ram_addr[13] | High Range | IO_L3N_T0_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD1 | | High Range | IO_L9P_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AD2 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
|
||||
| AD3 | | High Range | IO_L14N_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AD4 | | High Range | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AD5 | | High Range | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AD6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AD7 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AD8 | | | MGTPTXN2_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AD9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AD10 | | | MGTPTXN0_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AD11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AD12 | | | MGTPRXN0_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AD13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AD14 | | | MGTPRXN2_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AD15 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AD16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AD17 | ext_ram_data[24] | High Range | IO_L20N_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD18 | ext_ram_data[20] | High Range | IO_L15N_T2_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD19 | ext_ram_we_n | High Range | IO_L14N_T2_SRCC_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD20 | ext_ram_data[26] | High Range | IO_L10P_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD21 | ext_ram_data[28] | High Range | IO_L7P_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD22 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
|
||||
| AD23 | ext_ram_ce_n | High Range | IO_L6P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD24 | ext_ram_be_n[2] | High Range | IO_L6N_T0_VREF_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD25 | ext_ram_addr[3] | High Range | IO_L4P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD26 | ext_ram_addr[4] | High Range | IO_L4N_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE1 | | High Range | IO_L9N_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AE2 | | High Range | IO_L10P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AE3 | | High Range | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AE4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AE5 | | High Range | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AE6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AE7 | | | MGTPTXP3_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AE8 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AE9 | | | MGTPTXP1_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AE10 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AE11 | | | MGTPRXP3_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AE12 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AE13 | | | MGTPRXP1_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AE14 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AE15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AE16 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| AE17 | ext_ram_addr[16] | High Range | IO_L18P_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE18 | ext_ram_addr[18] | High Range | IO_L16P_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE19 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
|
||||
| AE20 | ext_ram_data[6] | High Range | IO_L10N_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE21 | ext_ram_data[5] | High Range | IO_L7N_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE22 | ext_ram_data[3] | High Range | IO_L9P_T1_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE23 | ext_ram_data[1] | High Range | IO_L5P_T0_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AE25 | ext_ram_addr[1] | High Range | IO_L1P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE26 | ext_ram_addr[2] | High Range | IO_L1N_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF2 | | High Range | IO_L10N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AF3 | | High Range | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AF4 | | High Range | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AF5 | | High Range | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AF6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF7 | | | MGTPTXN3_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AF8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF9 | | | MGTPTXN1_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AF10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF11 | | | MGTPRXN3_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AF12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF13 | | | MGTPRXN1_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AF14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF15 | | | MGTRREF_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AF16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF17 | ext_ram_addr[15] | High Range | IO_L18N_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF18 | ext_ram_addr[17] | High Range | IO_L16N_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF19 | ext_ram_addr[19] | High Range | IO_L8P_T1_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF20 | ext_ram_data[7] | High Range | IO_L8N_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF22 | ext_ram_data[4] | High Range | IO_L9N_T1_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF23 | ext_ram_data[2] | High Range | IO_L5N_T0_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF24 | ext_ram_data[0] | High Range | IO_L3P_T0_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF25 | ext_ram_addr[0] | High Range | IO_L3N_T0_DQS_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF26 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
|
||||
| B1 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B2 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B4 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B5 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B7 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| B8 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| B9 | | | MGTPTXP2_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| B10 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| B11 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| B12 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| B13 | | | MGTPRXP2_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| B14 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B17 | dpy0[6] | High Range | IO_L7N_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| B18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
|
||||
| B19 | dpy0[0] | High Range | IO_L10P_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| B20 | leds[15] | High Range | IO_L15P_T2_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| B21 | dpy0[2] | High Range | IO_L16N_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| B22 | leds[7] | High Range | IO_L17P_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| B23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B24 | leds[0] | High Range | IO_L23N_T3_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| B25 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| B26 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C1 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C2 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C3 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C4 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
|
||||
| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C7 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| C8 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| C9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C10 | | | MGTPTXN3_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| C11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C12 | | | MGTPRXN3_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| C13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C14 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| C15 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C17 | dpy0[7] | High Range | IO_L7P_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| C18 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C19 | dpy0[5] | High Range | IO_L13N_T2_MRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| C20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C21 | leds[5] | High Range | IO_L16P_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| C22 | leds[4] | High Range | IO_L19P_T3_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| C23 | leds[8] | High Range | IO_L19N_T3_VREF_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| C24 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C25 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
|
||||
| C26 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
|
||||
| D3 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D4 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D5 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D6 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D8 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| D9 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| D10 | | | MGTPTXP3_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| D11 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| D12 | | | MGTPRXP3_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| D13 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| D14 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| D15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D16 | dpy1[1] | High Range | IO_L8N_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| D17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D18 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D19 | dpy0[1] | High Range | IO_L13P_T2_MRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| D20 | leds[12] | High Range | IO_L14N_T2_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| D21 | leds[10] | High Range | IO_L18N_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| D22 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
|
||||
| D23 | leds[3] | High Range | IO_L24P_T3_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| D24 | | High Range | IO_L24N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D25 | video_blue[1] | High Range | IO_L20N_T3_A19_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| D26 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| E1 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E3 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E5 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E11 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| E12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E13 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E16 | dpy1[4] | High Range | IO_L8P_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| E17 | dpy1[2] | High Range | IO_L11P_T1_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| E18 | dpy0[4] | High Range | IO_L11N_T1_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| E19 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
|
||||
| E20 | leds[6] | High Range | IO_L14P_T2_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| E21 | leds[1] | High Range | IO_L18P_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| E22 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| E23 | video_green[1] | High Range | IO_L17N_T2_A25_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| E24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E25 | video_blue[0] | High Range | IO_L20P_T3_A20_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| E26 | video_red[2] | High Range | IO_L21P_T3_DQS_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| F1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F2 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F3 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F5 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
|
||||
| F7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F10 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| F11 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| F12 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| F13 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| F14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F15 | dpy1[6] | High Range | IO_L4N_T0_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| F16 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
|
||||
| F17 | dpy1[3] | High Range | IO_L2N_T0_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| F18 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F19 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F20 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F22 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| F23 | video_green[2] | High Range | IO_L17P_T2_A26_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| F24 | video_red[1] | High Range | IO_L19N_T3_A21_VREF_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| F25 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| F26 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
|
||||
| G1 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G2 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
|
||||
| G4 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G5 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G6 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G7 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G8 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G9 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G14 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| G15 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| G16 | dpy1[5] | High Range | IO_L6N_T0_VREF_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| G17 | dpy1[7] | High Range | IO_L2P_T0_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| G18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G19 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| G20 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G21 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G22 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G23 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
|
||||
| G24 | video_de | High Range | IO_L19P_T3_A22_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| G25 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G26 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H1 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| H2 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| H3 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H4 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H7 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H8 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H9 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H10 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| H11 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| H12 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| H13 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| H14 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| H15 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| H16 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| H17 | | High Range | IO_0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| H18 | UART_TX | High Range | IO_L10N_T1_AD11N_15 | BIDIR | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| H19 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
|
||||
| H21 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H22 | video_clk | High Range | IO_L13N_T2_MRCC_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| H23 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H24 | video_vsync | High Range | IO_L16N_T2_A27_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| H25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H26 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J1 | dip_sw[14] | High Range | IO_L7N_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J3 | dip_sw[1] | High Range | IO_L1N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| J4 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J5 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J6 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
|
||||
| J8 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| J10 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| J14 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J15 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J16 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
|
||||
| J18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J19 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J20 | UART_RX | High Range | IO_L9N_T1_DQS_AD3N_15 | BIDIR | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| J21 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J23 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J24 | video_hsync | High Range | IO_L16P_T2_A28_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| J25 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J26 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K1 | dip_sw[17] | High Range | IO_L7P_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| K2 | dip_sw[16] | High Range | IO_L8N_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| K3 | dip_sw[13] | High Range | IO_L1P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| K5 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| K6 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K7 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K8 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
|
||||
| K15 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K16 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K17 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K18 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K20 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K21 | clk | High Range | IO_L12P_T1_MRCC_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| K22 | video_green[0] | High Range | IO_L18P_T2_A24_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| K23 | video_red[0] | High Range | IO_L18N_T2_A23_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| K24 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
|
||||
| K25 | base_ram_be_n[3] | High Range | IO_L7P_T1_D09_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| K26 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| L1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| L2 | dip_sw[15] | High Range | IO_L11N_T1_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| L3 | dip_sw[6] | High Range | IO_L8P_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| L4 | dip_sw[19] | High Range | IO_L3N_T0_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| L5 | dip_sw[5] | High Range | IO_L4P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| L6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L7 | dip_sw[11] | High Range | IO_L2N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| L8 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| L9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| L14 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L15 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L17 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L18 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L19 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L20 | base_ram_be_n[0] | High Range | IO_L8N_T1_D12_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| L21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
|
||||
| L22 | base_ram_be_n[1] | High Range | IO_L11P_T1_SRCC_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| L23 | base_ram_be_n[2] | High Range | IO_L11N_T1_SRCC_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| L24 | base_ram_data[0] | High Range | IO_L9P_T1_DQS_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| L25 | base_ram_data[1] | High Range | IO_L9N_T1_DQS_D13_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| L26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M1 | touch_btn[1] | High Range | IO_L9N_T1_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| M2 | dip_sw[2] | High Range | IO_L11P_T1_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| M3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M4 | dip_sw[20] | High Range | IO_L3P_T0_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| M5 | dip_sw[12] | High Range | IO_L6N_T0_VREF_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| M6 | dip_sw[8] | High Range | IO_L6P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| M7 | dip_sw[10] | High Range | IO_L2P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| M8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| M11 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| M12 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M14 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| M15 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| M16 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| M17 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| M18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
|
||||
| M19 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| M20 | base_ram_data[21] | High Range | IO_L8P_T1_D11_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| M21 | base_ram_data[17] | High Range | IO_L12P_T1_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| M22 | base_ram_data[31] | High Range | IO_L12N_T1_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| M23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M24 | base_ram_data[30] | High Range | IO_L10P_T1_D14_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| M25 | base_ram_data[3] | High Range | IO_L10N_T1_D15_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| M26 | base_ram_data[2] | High Range | IO_L20N_T3_A07_D23_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| N1 | dip_sw[23] | High Range | IO_L9P_T1_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| N2 | dip_sw[21] | High Range | IO_L12N_T1_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| N3 | dip_sw[18] | High Range | IO_L12P_T1_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| N4 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| N5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| N6 | dip_sw[7] | High Range | IO_L5N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| N7 | dip_sw[9] | High Range | IO_L5P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| N8 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| N9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N11 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| N12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| N13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| N14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| N15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
|
||||
| N16 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| N17 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| N18 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| N19 | base_ram_data[20] | High Range | IO_L16N_T2_A15_D31_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| N20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N21 | base_ram_data[23] | High Range | IO_L13P_T2_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| N22 | base_ram_data[28] | High Range | IO_L13N_T2_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| N23 | base_ram_data[29] | High Range | IO_L15P_T2_DQS_RDWR_B_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| N24 | base_ram_data[22] | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| N25 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
|
||||
| N26 | base_ram_data[4] | High Range | IO_L20P_T3_A08_D24_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P1 | dip_sw[3] | High Range | IO_L15N_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| P2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| P3 | touch_btn[2] | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| P4 | dip_sw[4] | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| P5 | dip_sw[24] | High Range | IO_L19N_T3_VREF_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| P6 | dip_sw[22] | High Range | IO_L19P_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P8 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| P11 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| P12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| P15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| P16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P18 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| P19 | base_ram_data[19] | High Range | IO_L16P_T2_CSI_B_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P20 | base_ram_data[27] | High Range | IO_L14P_T2_SRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P21 | base_ram_data[16] | High Range | IO_L14N_T2_SRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
|
||||
| P23 | base_ram_data[18] | High Range | IO_L17P_T2_A14_D30_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P24 | base_ram_data[5] | High Range | IO_L17N_T2_A13_D29_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P25 | base_ram_data[7] | High Range | IO_L19N_T3_A09_D25_VREF_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P26 | base_ram_data[6] | High Range | IO_L22N_T3_A04_D20_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| R1 | dip_sw[27] | High Range | IO_L15P_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| R2 | dip_sw[31] | High Range | IO_L17N_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| R3 | dip_sw[25] | High Range | IO_L13P_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R5 | dip_sw[28] | High Range | IO_L20N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| R6 | dip_sw[30] | High Range | IO_L23N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R8 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
|
||||
| R12 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
|
||||
| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| R14 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R15 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R16 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R17 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R18 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
|
||||
| R20 | base_ram_addr[5] | High Range | IO_L18P_T2_A12_D28_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| R21 | base_ram_data[26] | High Range | IO_L18N_T2_A11_D27_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| R22 | base_ram_data[25] | High Range | IO_L23N_T3_A02_D18_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| R23 | base_ram_addr[6] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| R24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R25 | ext_ram_be_n[1] | High Range | IO_L19P_T3_A10_D26_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| R26 | ext_ram_be_n[0] | High Range | IO_L22P_T3_A05_D21_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| T1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T2 | touch_btn[0] | High Range | IO_L17P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| T3 | dip_sw[0] | High Range | IO_L16N_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| T4 | dip_sw[26] | High Range | IO_L16P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| T5 | dip_sw[29] | High Range | IO_L20P_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| T6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| T7 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| T13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T14 | | High Range | IO_L20P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| T15 | | High Range | IO_L20N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| T16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
|
||||
| T17 | | High Range | IO_L21P_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| T18 | base_ram_addr[2] | High Range | IO_L21N_T3_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| T19 | base_ram_addr[0] | High Range | IO_L17P_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| T20 | base_ram_oe_n | High Range | IO_L15P_T2_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| T21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T22 | base_ram_data[24] | High Range | IO_L23P_T3_A03_D19_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| T23 | base_ram_addr[7] | High Range | IO_L24P_T3_A01_D17_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| T24 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| T25 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| T26 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
|
||||
| U1 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U2 | touch_btn[3] | High Range | IO_L18P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| U3 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
|
||||
| U4 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U5 | reset | High Range | IO_L21N_T3_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| U6 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U7 | | High Range | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| U8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| U12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| U14 | | High Range | IO_L23P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| U15 | | High Range | IO_L22P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| U16 | | High Range | IO_L22N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| U17 | base_ram_addr[4] | High Range | IO_25_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| U18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U19 | base_ram_ce_n | High Range | IO_L17N_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| U20 | base_ram_we_n | High Range | IO_L15N_T2_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| U21 | base_ram_data[15] | High Range | IO_L13P_T2_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| U22 | base_ram_addr[8] | High Range | IO_L12P_T1_MRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| U23 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
|
||||
| U24 | ext_ram_data[15] | High Range | IO_0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| U25 | ext_ram_data[13] | High Range | IO_L1P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| U26 | ext_ram_data[14] | High Range | IO_L1N_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V1 | | High Range | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V2 | | High Range | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V3 | | High Range | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V4 | | High Range | IO_0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V6 | | High Range | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V7 | | High Range | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V8 | | High Range | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V9 | | High Range | IO_25_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| V11 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| V12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V14 | | High Range | IO_L23N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| V15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V16 | | High Range | IO_L24P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| V17 | base_ram_addr[3] | High Range | IO_L24N_T3_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V18 | base_ram_addr[1] | High Range | IO_L19P_T3_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V19 | base_ram_addr[19] | High Range | IO_L18P_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V20 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
|
||||
| V21 | base_ram_data[10] | High Range | IO_L13N_T2_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V22 | base_ram_data[13] | High Range | IO_L12N_T1_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V23 | base_ram_data[14] | High Range | IO_L10P_T1_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V24 | ext_ram_data[11] | High Range | IO_L6P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V26 | ext_ram_data[12] | High Range | IO_L2P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W1 | | High Range | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| W2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| W3 | | High Range | IO_L5P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| W4 | | High Range | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| W5 | | High Range | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| W6 | | High Range | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| W7 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
|
||||
| W8 | | High Range | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| W9 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| W10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| W11 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | |
|
||||
| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| W13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| W14 | | High Range | IO_L24P_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| W15 | | High Range | IO_L24N_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| W16 | | High Range | IO_25_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| W17 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
|
||||
| W18 | base_ram_addr[18] | High Range | IO_L19N_T3_VREF_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W19 | base_ram_addr[15] | High Range | IO_L18N_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W20 | base_ram_addr[17] | High Range | IO_L16P_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W21 | base_ram_addr[16] | High Range | IO_L14P_T2_SRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| W23 | base_ram_data[12] | High Range | IO_L10N_T1_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W24 | base_ram_data[11] | High Range | IO_L6N_T0_VREF_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W25 | ext_ram_data[9] | High Range | IO_L4P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W26 | ext_ram_data[10] | High Range | IO_L2N_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y1 | | High Range | IO_L8N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y2 | | High Range | IO_L8P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y3 | | High Range | IO_L5N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y4 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
|
||||
| Y5 | | High Range | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y6 | | High Range | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y7 | | High Range | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y8 | | High Range | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y9 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| Y10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y14 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | |
|
||||
| Y15 | ext_ram_data[22] | High Range | IO_L23P_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y16 | | High Range | IO_L21P_T3_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| Y17 | ext_ram_addr[6] | High Range | IO_L21N_T3_DQS_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y18 | | High Range | IO_L17P_T2_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| Y19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y20 | base_ram_addr[13] | High Range | IO_L16N_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y21 | base_ram_addr[12] | High Range | IO_L14N_T2_SRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y22 | base_ram_addr[9] | High Range | IO_L11P_T1_SRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y23 | base_ram_data[9] | High Range | IO_L11N_T1_SRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y24 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
|
||||
| Y25 | ext_ram_addr[9] | High Range | IO_L5P_T0_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y26 | ext_ram_data[8] | High Range | IO_L4N_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
+------------+-------------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
* Default value
|
||||
** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,188 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:35:41 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_power -file ./vivado_reports/impl_power.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200tfbg676-1
|
||||
| Design State : synthesized
|
||||
| Grade : commercial
|
||||
| Process : typical
|
||||
| Characterization : Production
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
Power Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
1.1 On-Chip Components
|
||||
1.2 Power Supply Summary
|
||||
1.3 Confidence Level
|
||||
2. Settings
|
||||
2.1 Environment
|
||||
2.2 Clock Constraints
|
||||
3. Detailed Reports
|
||||
3.1 By Hierarchy
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+--------------------------+--------------+
|
||||
| Total On-Chip Power (W) | 0.727 |
|
||||
| Design Power Budget (W) | Unspecified* |
|
||||
| Power Budget Margin (W) | NA |
|
||||
| Dynamic (W) | 0.586 |
|
||||
| Device Static (W) | 0.141 |
|
||||
| Effective TJA (C/W) | 1.9 |
|
||||
| Max Ambient (C) | 83.6 |
|
||||
| Junction Temperature (C) | 26.4 |
|
||||
| Confidence Level | Low |
|
||||
| Setting File | --- |
|
||||
| Simulation Activity File | --- |
|
||||
| Design Nets Matched | NA |
|
||||
+--------------------------+--------------+
|
||||
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
|
||||
|
||||
|
||||
1.1 On-Chip Components
|
||||
----------------------
|
||||
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
| On-Chip | Power (W) | Used | Available | Utilization (%) |
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
| Clocks | 0.030 | 6 | --- | --- |
|
||||
| Slice Logic | 0.180 | 137345 | --- | --- |
|
||||
| LUT as Logic | 0.172 | 73234 | 134600 | 54.41 |
|
||||
| CARRY4 | 0.005 | 3590 | 33650 | 10.67 |
|
||||
| LUT as Distributed RAM | 0.001 | 652 | 46200 | 1.41 |
|
||||
| Register | 0.001 | 38603 | 269200 | 14.34 |
|
||||
| LUT as Shift Register | <0.001 | 1094 | 46200 | 2.37 |
|
||||
| F7/F8 Muxes | <0.001 | 5666 | 134600 | 4.21 |
|
||||
| BUFG | <0.001 | 1 | 32 | 3.13 |
|
||||
| Others | 0.000 | 287 | --- | --- |
|
||||
| Signals | 0.190 | 113832 | --- | --- |
|
||||
| Block RAM | 0.020 | 25.5 | 365 | 6.99 |
|
||||
| PLL | 0.137 | 1 | 10 | 10.00 |
|
||||
| I/O | 0.029 | 202 | 400 | 50.50 |
|
||||
| Static Power | 0.141 | | | |
|
||||
| Total | 0.727 | | | |
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
|
||||
|
||||
1.2 Power Supply Summary
|
||||
------------------------
|
||||
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Vccint | 1.000 | 0.465 | 0.432 | 0.032 |
|
||||
| Vccaux | 1.800 | 0.101 | 0.070 | 0.031 |
|
||||
| Vcco33 | 3.300 | 0.013 | 0.008 | 0.005 |
|
||||
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccbram | 1.000 | 0.003 | 0.001 | 0.001 |
|
||||
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
|
||||
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
|
||||
|
||||
1.3 Confidence Level
|
||||
--------------------
|
||||
|
||||
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
|
||||
| User Input Data | Confidence | Details | Action |
|
||||
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
|
||||
| Design implementation state | Low | Design is synthesized | Accuracy of the tool is not optimal until design is fully placed and routed |
|
||||
| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
|
||||
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
|
||||
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
|
||||
| Device models | High | Device models are Production | |
|
||||
| | | | |
|
||||
| Overall confidence level | Low | | |
|
||||
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
2. Settings
|
||||
-----------
|
||||
|
||||
2.1 Environment
|
||||
---------------
|
||||
|
||||
+-----------------------+--------------------------+
|
||||
| Ambient Temp (C) | 25.0 |
|
||||
| ThetaJA (C/W) | 1.9 |
|
||||
| Airflow (LFM) | 250 |
|
||||
| Heat Sink | medium (Medium Profile) |
|
||||
| ThetaSA (C/W) | 3.4 |
|
||||
| Board Selection | medium (10"x10") |
|
||||
| # of Board Layers | 12to15 (12 to 15 Layers) |
|
||||
| Board Temperature (C) | 25.0 |
|
||||
+-----------------------+--------------------------+
|
||||
|
||||
|
||||
2.2 Clock Constraints
|
||||
---------------------
|
||||
|
||||
+------------------+-----------------------------------------+-----------------+
|
||||
| Clock | Domain | Constraint (ns) |
|
||||
+------------------+-----------------------------------------+-----------------+
|
||||
| clk | clk | 20.0 |
|
||||
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
|
||||
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 |
|
||||
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
|
||||
+------------------+-----------------------------------------+-----------------+
|
||||
|
||||
|
||||
3. Detailed Reports
|
||||
-------------------
|
||||
|
||||
3.1 By Hierarchy
|
||||
----------------
|
||||
|
||||
+----------------------------+-----------+
|
||||
| Name | Power (W) |
|
||||
+----------------------------+-----------+
|
||||
| soc_top | 0.586 |
|
||||
| pll_clk.u_clk_pll | 0.138 |
|
||||
| inst | 0.138 |
|
||||
| u_AxiCrossbar_2x8 | 0.001 |
|
||||
| u_Axi_CDC | 0.003 |
|
||||
| u_axi_uart_controller | 0.002 |
|
||||
| uart0 | 0.001 |
|
||||
| regs | 0.001 |
|
||||
| u_cdma_matmul_bridge | 0.001 |
|
||||
| u_confreg | 0.001 |
|
||||
| u_cpu | 0.026 |
|
||||
| addr_trans | 0.002 |
|
||||
| tlb_entry | 0.002 |
|
||||
| btb | 0.003 |
|
||||
| dcache | 0.004 |
|
||||
| icache | 0.005 |
|
||||
| u_csr | 0.001 |
|
||||
| u_mul | 0.006 |
|
||||
| u_fft_mlkem_axi_slave | 0.285 |
|
||||
| u_fft_controller | 0.032 |
|
||||
| u_FFT | 0.029 |
|
||||
| u_out0 | 0.001 |
|
||||
| u_out1 | 0.001 |
|
||||
| u_mlkem_axi_slave | 0.250 |
|
||||
| u_mlkem | 0.227 |
|
||||
| u_prng_axi_slave | 0.004 |
|
||||
| u_matmul_axi_slave | 0.072 |
|
||||
| mult_inst[0].u_mult | 0.002 |
|
||||
| mult_inst[1].u_mult | 0.002 |
|
||||
| mult_inst[2].u_mult | 0.002 |
|
||||
| mult_inst[3].u_mult | 0.002 |
|
||||
| u_snix_axil_cdma_mux_8ch | 0.010 |
|
||||
| u_core_engine | 0.005 |
|
||||
| axis_fifo_u0 | 0.004 |
|
||||
+----------------------------+-----------+
|
||||
|
||||
|
||||
@@ -1,50 +0,0 @@
|
||||
Design Route Status
|
||||
: # nets :
|
||||
------------------------------------------- : ----------- :
|
||||
# of logical nets.......................... : 158000 :
|
||||
# of nets with no placed pins.......... : 157584 :
|
||||
# of nets not needing routing.......... : 202 :
|
||||
# of internally routed nets........ : 202 :
|
||||
# of routable nets..................... : 0 :
|
||||
# of nets with routing errors.......... : 214 :
|
||||
# of nets with some unplaced pins.. : 214 :
|
||||
# of nets with some unrouted pins.. : 160 :
|
||||
------------------------------------------- : ----------- :
|
||||
|
||||
|
||||
Nets with Routing Errors: (only the first 10 nets are listed)
|
||||
GLOBAL_LOGIC0
|
||||
Unplaced Pins -- only the first 10 are listed, use -show_all to get the full list:
|
||||
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/RADR2
|
||||
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/RADR3
|
||||
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/RADR4
|
||||
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR2
|
||||
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR3
|
||||
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR4
|
||||
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/RADR2
|
||||
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/RADR3
|
||||
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/RADR4
|
||||
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR2
|
||||
UART_RX_IOBUF_inst/O
|
||||
Unplaced Pin: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/I3
|
||||
UART_TX_IOBUF_inst/O
|
||||
Unplaced Pins:
|
||||
u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/I2
|
||||
u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/I0
|
||||
u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/I1
|
||||
u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/I2
|
||||
base_ram_data_IOBUF[0]_inst/O
|
||||
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_251__0/I4
|
||||
base_ram_data_IOBUF[10]_inst/O
|
||||
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_182/I4
|
||||
base_ram_data_IOBUF[11]_inst/O
|
||||
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_177__0/I4
|
||||
base_ram_data_IOBUF[12]_inst/O
|
||||
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_169__0/I4
|
||||
base_ram_data_IOBUF[13]_inst/O
|
||||
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_159__0/I4
|
||||
base_ram_data_IOBUF[14]_inst/O
|
||||
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_152__0/I4
|
||||
base_ram_data_IOBUF[15]_inst/O
|
||||
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_355__0/I4
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,203 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:35:22 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_utilization -file ./vivado_reports/impl_utilization.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200tfbg676-1
|
||||
| Design State : Synthesized
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
| Slice LUTs* | 74980 | 0 | 134600 | 55.71 |
|
||||
| LUT as Logic | 73234 | 0 | 134600 | 54.41 |
|
||||
| LUT as Memory | 1746 | 0 | 46200 | 3.78 |
|
||||
| LUT as Distributed RAM | 652 | 0 | | |
|
||||
| LUT as Shift Register | 1094 | 0 | | |
|
||||
| Slice Registers | 38603 | 0 | 269200 | 14.34 |
|
||||
| Register as Flip Flop | 38603 | 0 | 269200 | 14.34 |
|
||||
| Register as Latch | 0 | 0 | 269200 | 0.00 |
|
||||
| F7 Muxes | 4263 | 0 | 67300 | 6.33 |
|
||||
| F8 Muxes | 1403 | 0 | 33650 | 4.17 |
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 101 | Yes | - | Set |
|
||||
| 25523 | Yes | - | Reset |
|
||||
| 134 | Yes | Set | - |
|
||||
| 12845 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 25.5 | 0 | 365 | 6.99 |
|
||||
| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 |
|
||||
| RAMB36E1 only | 10 | | | |
|
||||
| RAMB18 | 31 | 0 | 730 | 4.25 |
|
||||
| RAMB18E1 only | 31 | | | |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 740 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 202 | 202 | 400 | 50.50 |
|
||||
| IOB Master Pads | 97 | | | |
|
||||
| IOB Slave Pads | 102 | | | |
|
||||
| Bonded IPADs | 0 | 0 | 26 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 16 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 10 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 384 | 0.00 |
|
||||
| GTPE2_CHANNEL | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 400 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 400 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 4 | 0 | 32 | 12.50 |
|
||||
| BUFIO | 0 | 0 | 40 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| PLLE2_ADV | 1 | 0 | 10 | 10.00 |
|
||||
| BUFMRCE | 0 | 0 | 20 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 120 | 0.00 |
|
||||
| BUFR | 0 | 0 | 40 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+-----------+-------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+-----------+-------+---------------------+
|
||||
| LUT6 | 36042 | LUT |
|
||||
| FDCE | 25523 | Flop & Latch |
|
||||
| LUT5 | 16007 | LUT |
|
||||
| LUT3 | 13060 | LUT |
|
||||
| FDRE | 12845 | Flop & Latch |
|
||||
| LUT4 | 11977 | LUT |
|
||||
| LUT2 | 9006 | LUT |
|
||||
| MUXF7 | 4263 | MuxFx |
|
||||
| CARRY4 | 3590 | CarryLogic |
|
||||
| MUXF8 | 1403 | MuxFx |
|
||||
| SRLC32E | 992 | Distributed Memory |
|
||||
| RAMD32 | 892 | Distributed Memory |
|
||||
| LUT1 | 816 | LUT |
|
||||
| RAMS32 | 272 | Distributed Memory |
|
||||
| FDSE | 134 | Flop & Latch |
|
||||
| IBUF | 104 | IO |
|
||||
| SRL16E | 102 | Distributed Memory |
|
||||
| FDPE | 101 | Flop & Latch |
|
||||
| OBUF | 98 | IO |
|
||||
| OBUFT | 66 | IO |
|
||||
| RAMD64E | 32 | Distributed Memory |
|
||||
| RAMB18E1 | 31 | Block Memory |
|
||||
| RAMB36E1 | 10 | Block Memory |
|
||||
| BUFG | 4 | Clock |
|
||||
| PLLE2_ADV | 1 | Clock |
|
||||
+-----------+-------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
| clk_pll | 1 |
|
||||
+----------+------+
|
||||
|
||||
|
||||
@@ -1,255 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:35:23 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_utilization -hierarchical -hierarchical_depth 10 -file ./vivado_reports/impl_utilization_hier.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200tfbg676-1
|
||||
| Design State : Synthesized
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Utilization by Hierarchy
|
||||
|
||||
1. Utilization by Hierarchy
|
||||
---------------------------
|
||||
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks |
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
| soc_top | (top) | 74980 | 73234 | 652 | 1094 | 38603 | 10 | 31 | 0 |
|
||||
| (soc_top) | (top) | 2116 | 2060 | 56 | 0 | 4 | 0 | 0 | 0 |
|
||||
| pll_clk.u_clk_pll | clk_pll | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| inst | clk_pll_clk_pll_clk_wiz | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_sys | rst_sync_0 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 519 | 519 | 0 | 0 | 151 | 0 | 0 | 0 |
|
||||
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 8 | 8 | 0 | 0 | 24 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_67 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_50 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_66 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_51 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_65 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_52 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_64 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 32 | 32 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_61 | 25 | 25 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_62 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_63 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_58 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_59 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_60 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_55 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_56 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_57 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 61 | 61 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7 | 48 | 48 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 13 | 13 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3 | 13 | 13 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 89 | 89 | 0 | 0 | 25 | 0 | 0 | 0 |
|
||||
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 73 | 73 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4ReadOnlyErrorSlave_1_54 | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 |
|
||||
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4WriteOnlyErrorSlave_1_53 | 20 | 20 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 181 | 181 | 0 | 0 | 17 | 0 | 0 | 0 |
|
||||
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 165 | 165 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4ReadOnlyErrorSlave_1 | 16 | 16 | 0 | 0 | 9 | 0 | 0 | 0 |
|
||||
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 25 | 25 | 0 | 0 | 14 | 0 | 0 | 0 |
|
||||
| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 18 | 18 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 7 | 7 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| u_Axi_CDC | Axi_CDC | 505 | 377 | 128 | 0 | 309 | 0 | 0 | 0 |
|
||||
| arFifo | StreamFifoCC_3 | 262 | 226 | 36 | 0 | 73 | 0 | 0 | 0 |
|
||||
| (arFifo) | StreamFifoCC_3 | 256 | 220 | 36 | 0 | 61 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9_48 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11_49 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| awFifo | StreamFifoCC | 112 | 76 | 36 | 0 | 75 | 0 | 0 | 0 |
|
||||
| (awFifo) | StreamFifoCC | 105 | 69 | 36 | 0 | 61 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| bFifo | StreamFifoCC_2 | 16 | 16 | 0 | 0 | 26 | 0 | 0 | 0 |
|
||||
| (bFifo) | StreamFifoCC_2 | 9 | 9 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_4 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_6 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| rFifo | StreamFifoCC_4 | 46 | 18 | 28 | 0 | 66 | 0 | 0 | 0 |
|
||||
| (rFifo) | StreamFifoCC_4 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_1 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| wFifo | StreamFifoCC_1 | 69 | 41 | 28 | 0 | 69 | 0 | 0 | 0 |
|
||||
| (wFifo) | StreamFifoCC_1 | 64 | 36 | 28 | 0 | 53 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_8 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_axi_axil_adapter | axi_axil_adapter | 1355 | 1355 | 0 | 0 | 161 | 0 | 0 | 0 |
|
||||
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 648 | 648 | 0 | 0 | 81 | 0 | 0 | 0 |
|
||||
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 707 | 707 | 0 | 0 | 80 | 0 | 0 | 0 |
|
||||
| u_axi_dvi | axi_dvi | 285 | 285 | 0 | 0 | 211 | 0 | 0 | 0 |
|
||||
| u_axi_ram | axi_wrap_ram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
|
||||
| u_axi_sram_sp | axi2sram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
|
||||
| u_axi_uart_controller | axi_uart_controller | 693 | 677 | 16 | 0 | 457 | 0 | 0 | 0 |
|
||||
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 252 | 252 | 0 | 0 | 120 | 0 | 0 | 0 |
|
||||
| uart0 | UART_TOP | 441 | 425 | 16 | 0 | 337 | 0 | 0 | 0 |
|
||||
| regs | uart_regs | 441 | 425 | 16 | 0 | 337 | 0 | 0 | 0 |
|
||||
| (regs) | uart_regs | 121 | 121 | 0 | 0 | 155 | 0 | 0 | 0 |
|
||||
| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| receiver | uart_receiver | 231 | 223 | 8 | 0 | 124 | 0 | 0 | 0 |
|
||||
| (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 |
|
||||
| fifo_rx | uart_rfifo | 163 | 155 | 8 | 0 | 70 | 0 | 0 | 0 |
|
||||
| (fifo_rx) | uart_rfifo | 144 | 144 | 0 | 0 | 62 | 0 | 0 | 0 |
|
||||
| rfifo | raminfr_47 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
||||
| transmitter | uart_transmitter | 86 | 78 | 8 | 0 | 56 | 0 | 0 | 0 |
|
||||
| (transmitter) | uart_transmitter | 42 | 42 | 0 | 0 | 35 | 0 | 0 | 0 |
|
||||
| fifo_tx | uart_tfifo | 44 | 36 | 8 | 0 | 21 | 0 | 0 | 0 |
|
||||
| (fifo_tx) | uart_tfifo | 25 | 25 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_cdma_matmul_bridge | cdma_matmul_bridge | 250 | 250 | 0 | 0 | 578 | 0 | 0 | 0 |
|
||||
| u_confreg | confreg | 391 | 391 | 0 | 0 | 460 | 0 | 0 | 0 |
|
||||
| (u_confreg) | confreg | 231 | 231 | 0 | 0 | 383 | 0 | 0 | 0 |
|
||||
| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 |
|
||||
| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 |
|
||||
| u_cpu | core_top | 8656 | 8380 | 276 | 0 | 5591 | 0 | 20 | 0 |
|
||||
| (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 |
|
||||
| addr_trans | addr_trans | 2264 | 2100 | 164 | 0 | 1244 | 0 | 0 | 0 |
|
||||
| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 |
|
||||
| tlb_entry | tlb_entry | 2264 | 2100 | 164 | 0 | 1204 | 0 | 0 | 0 |
|
||||
| axi_bridge | axi_bridge | 40 | 40 | 0 | 0 | 214 | 0 | 0 | 0 |
|
||||
| btb | btb | 1064 | 984 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
||||
| (btb) | btb | 1061 | 981 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
||||
| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| dcache | dcache | 569 | 537 | 32 | 0 | 146 | 0 | 10 | 0 |
|
||||
| (dcache) | dcache | 92 | 60 | 32 | 0 | 138 | 0 | 0 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_36 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_39 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_40 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_41 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_42 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_43 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| lfsr | lfsr_44 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| tagv_ram_way[0].u | tagv_sram_45 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| tagv_ram_way[1].u | tagv_sram_46 | 46 | 46 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| exe_stage | exe_stage | 681 | 681 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| (exe_stage) | exe_stage | 650 | 650 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| icache | icache | 239 | 239 | 0 | 0 | 55 | 0 | 10 | 0 |
|
||||
| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_29 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_30 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_31 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_32 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_33 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_34 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| tagv_ram_way[1].u | tagv_sram_35 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| id_stage | id_stage | 1058 | 1058 | 0 | 0 | 108 | 0 | 0 | 0 |
|
||||
| if_stage | if_stage | 135 | 135 | 0 | 0 | 173 | 0 | 0 | 0 |
|
||||
| mem_stage | mem_stage | 116 | 116 | 0 | 0 | 211 | 0 | 0 | 0 |
|
||||
| u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 |
|
||||
| u_div | div | 143 | 143 | 0 | 0 | 107 | 0 | 0 | 0 |
|
||||
| u_mul | mul | 943 | 943 | 0 | 0 | 592 | 0 | 0 | 0 |
|
||||
| wb_stage | wb_stage | 685 | 685 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 48074 | 46986 | 0 | 1088 | 25915 | 10 | 10 | 0 |
|
||||
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 17 | 17 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| u_fft_controller | fft_controller | 6966 | 5878 | 0 | 1088 | 1087 | 8 | 4 | 0 |
|
||||
| (u_fft_controller) | fft_controller | 90 | 90 | 0 | 0 | 104 | 0 | 0 | 0 |
|
||||
| u_FFT | FFT | 6855 | 5767 | 0 | 1088 | 983 | 8 | 0 | 0 |
|
||||
| SU1 | SdfUnit | 2150 | 1382 | 0 | 768 | 197 | 2 | 0 | 0 |
|
||||
| (SU1) | SdfUnit | 39 | 39 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_25 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer | 624 | 112 | 0 | 512 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized0 | 320 | 64 | 0 | 256 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_26 | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle_27 | 543 | 543 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU2 | SdfUnit__parameterized0 | 1571 | 1379 | 0 | 192 | 197 | 2 | 0 | 0 |
|
||||
| (SU2) | SdfUnit__parameterized0 | 38 | 38 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_20 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_21 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_22 | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle_23 | 541 | 541 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU3 | SdfUnit__parameterized1 | 1439 | 1375 | 0 | 64 | 197 | 2 | 0 | 0 |
|
||||
| (SU3) | SdfUnit__parameterized1 | 35 | 35 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_16 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_17 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized4 | 96 | 64 | 0 | 32 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_18 | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle_19 | 540 | 540 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU4 | SdfUnit__parameterized2 | 1436 | 1372 | 0 | 64 | 197 | 2 | 0 | 0 |
|
||||
| (SU4) | SdfUnit__parameterized2 | 34 | 34 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_14 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_15 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized5 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized6 | 96 | 64 | 0 | 32 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle | 538 | 538 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU5 | SdfUnit__parameterized3 | 259 | 259 | 0 | 0 | 195 | 0 | 0 | 0 |
|
||||
| (SU5) | SdfUnit__parameterized3 | 35 | 35 | 0 | 0 | 99 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 |
|
||||
| u_in0 | my_bram0 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_in1 | my_bram0_11 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_out0 | my_bram0_12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_out1 | my_bram0_13 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_mlkem_axi_slave | mlkem_axi_slave | 40589 | 40589 | 0 | 0 | 24484 | 2 | 6 | 0 |
|
||||
| (u_mlkem_axi_slave) | mlkem_axi_slave | 3642 | 3642 | 0 | 0 | 1021 | 0 | 0 | 0 |
|
||||
| u_mlkem | mlkem_top | 36975 | 36975 | 0 | 0 | 23463 | 2 | 6 | 0 |
|
||||
| (u_mlkem) | mlkem_top | 2550 | 2550 | 0 | 0 | 4907 | 0 | 0 | 0 |
|
||||
| u_bank_a | sd_bram__parameterized0 | 39 | 39 | 0 | 0 | 0 | 1 | 1 | 0 |
|
||||
| u_bank_se | sd_bram__parameterized1 | 62 | 62 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| u_bank_t | sd_bram__parameterized2 | 484 | 484 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_c_in_bram | sd_bram | 1291 | 1291 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_cbd | sample_cbd_sync_shared | 2469 | 2469 | 0 | 0 | 3199 | 0 | 0 | 0 |
|
||||
| u_comp | comp_decomp_sync | 177 | 177 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| u_pipe | pipeline_reg | 177 | 177 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| u_ct_bram | sd_bram_4 | 20 | 20 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_dkp_bram | sd_bram_5 | 101 | 101 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_ek_bram | sd_bram_6 | 226 | 226 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_keccak | keccak_core | 5251 | 5251 | 0 | 0 | 1619 | 0 | 0 | 0 |
|
||||
| u_ntt | ntt_core | 13498 | 13498 | 0 | 0 | 3354 | 0 | 0 | 0 |
|
||||
| u_pmul | poly_mul_sync | 7392 | 7392 | 0 | 0 | 6314 | 0 | 0 | 0 |
|
||||
| (u_pmul) | poly_mul_sync | 5013 | 5013 | 0 | 0 | 6314 | 0 | 0 | 0 |
|
||||
| u_bc | basecase_mul | 2379 | 2379 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| (u_bc) | basecase_mul | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_mul1 | barrett_mul | 969 | 969 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_mul2 | barrett_mul_7 | 118 | 118 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_mul3 | barrett_mul_8 | 561 | 561 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_mul4 | barrett_mul_9 | 549 | 549 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_mul_zeta | barrett_mul_10 | 130 | 130 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_sha3 | sha3_top_shared | 1983 | 1983 | 0 | 0 | 2388 | 0 | 0 | 0 |
|
||||
| u_snt | sample_ntt_sync_shared | 1433 | 1433 | 0 | 0 | 1669 | 0 | 0 | 0 |
|
||||
| u_prng_axi_slave | prng_axi_slave | 502 | 502 | 0 | 0 | 338 | 0 | 0 | 0 |
|
||||
| u_matmul_axi_slave | matmul_axi_slave | 9974 | 9792 | 176 | 6 | 3208 | 0 | 0 | 0 |
|
||||
| (u_matmul_axi_slave) | matmul_axi_slave | 5758 | 5576 | 176 | 6 | 2440 | 0 | 0 | 0 |
|
||||
| mult_inst[0].u_mult | pipelined_mult_32x32 | 1086 | 1086 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| mult_inst[1].u_mult | pipelined_mult_32x32_1 | 1022 | 1022 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| mult_inst[2].u_mult | pipelined_mult_32x32_2 | 1086 | 1086 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| mult_inst[3].u_mult | pipelined_mult_32x32_3 | 1022 | 1022 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1823 | 1823 | 0 | 0 | 1476 | 0 | 1 | 0 |
|
||||
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 605 | 605 | 0 | 0 | 1180 | 0 | 0 | 0 |
|
||||
| u_core_engine | snix_axi_mm2mm | 1218 | 1218 | 0 | 0 | 296 | 0 | 1 | 0 |
|
||||
| (u_core_engine) | snix_axi_mm2mm | 776 | 776 | 0 | 0 | 243 | 0 | 0 | 0 |
|
||||
| axis_fifo_u0 | snix_axis_fifo | 442 | 442 | 0 | 0 | 53 | 0 | 1 | 0 |
|
||||
| u_fifo | snix_sync_fifo | 442 | 442 | 0 | 0 | 53 | 0 | 1 | 0 |
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,914 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:34:34 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_timing_summary -file ./vivado_reports/synth_timing_summary.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200t-fbg676
|
||||
| Speed File : -1 PRODUCTION 1.23 2018-06-13
|
||||
---------------------------------------------------------------------------------------
|
||||
|
||||
Timing Summary Report
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Timer Settings
|
||||
| --------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
Enable Multi Corner Analysis : Yes
|
||||
Enable Pessimism Removal : Yes
|
||||
Pessimism Removal Resolution : Nearest Common Node
|
||||
Enable Input Delay Default Clock : No
|
||||
Enable Preset / Clear Arcs : No
|
||||
Disable Flight Delays : No
|
||||
Ignore I/O Paths : No
|
||||
Timing Early Launch at Borrowing Latches : No
|
||||
Borrow Time for Max Delay Exceptions : Yes
|
||||
Merge Timing Exceptions : Yes
|
||||
|
||||
Corner Analyze Analyze
|
||||
Name Max Paths Min Paths
|
||||
------ --------- ---------
|
||||
Slow Yes Yes
|
||||
Fast Yes Yes
|
||||
|
||||
|
||||
|
||||
check_timing report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. checking no_clock
|
||||
2. checking constant_clock
|
||||
3. checking pulse_width_clock
|
||||
4. checking unconstrained_internal_endpoints
|
||||
5. checking no_input_delay
|
||||
6. checking no_output_delay
|
||||
7. checking multiple_clock
|
||||
8. checking generated_clocks
|
||||
9. checking loops
|
||||
10. checking partial_input_delay
|
||||
11. checking partial_output_delay
|
||||
12. checking latch_loops
|
||||
|
||||
1. checking no_clock
|
||||
--------------------
|
||||
There are 23490 register/latch pins with no clock driven by root clock pin: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg/Q (HIGH)
|
||||
|
||||
|
||||
2. checking constant_clock
|
||||
--------------------------
|
||||
There are 0 register/latch pins with constant_clock.
|
||||
|
||||
|
||||
3. checking pulse_width_clock
|
||||
-----------------------------
|
||||
There are 0 register/latch pins which need pulse_width check
|
||||
|
||||
|
||||
4. checking unconstrained_internal_endpoints
|
||||
--------------------------------------------
|
||||
There are 69061 pins that are not constrained for maximum delay. (HIGH)
|
||||
|
||||
There are 0 pins that are not constrained for maximum delay due to constant clock.
|
||||
|
||||
|
||||
5. checking no_input_delay
|
||||
--------------------------
|
||||
There are 38 input ports with no input delay specified. (HIGH)
|
||||
|
||||
There are 0 input ports with no input delay but user has a false path constraint.
|
||||
|
||||
|
||||
6. checking no_output_delay
|
||||
---------------------------
|
||||
There are 40 ports with no output delay specified. (HIGH)
|
||||
|
||||
There are 0 ports with no output delay but user has a false path constraint
|
||||
|
||||
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
|
||||
|
||||
|
||||
7. checking multiple_clock
|
||||
--------------------------
|
||||
There are 0 register/latch pins with multiple clocks.
|
||||
|
||||
|
||||
8. checking generated_clocks
|
||||
----------------------------
|
||||
There are 0 generated clocks that are not connected to a clock source.
|
||||
|
||||
|
||||
9. checking loops
|
||||
-----------------
|
||||
There are 0 combinational loops in the design.
|
||||
|
||||
|
||||
10. checking partial_input_delay
|
||||
--------------------------------
|
||||
There are 0 input ports with partial input delay specified.
|
||||
|
||||
|
||||
11. checking partial_output_delay
|
||||
---------------------------------
|
||||
There are 0 ports with partial output delay specified.
|
||||
|
||||
|
||||
12. checking latch_loops
|
||||
------------------------
|
||||
There are 0 combinational latch loops in the design through latch input
|
||||
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Design Timing Summary
|
||||
| ---------------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
|
||||
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
|
||||
2.111 0.000 0 43229 0.011 0.000 0 43229 7.000 0.000 0 17485
|
||||
|
||||
|
||||
All user specified timing constraints are met.
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Clock Summary
|
||||
| -------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
Clock Waveform(ns) Period(ns) Frequency(MHz)
|
||||
----- ------------ ---------- --------------
|
||||
clk {0.000 10.000} 20.000 50.000
|
||||
clkfbout_clk_pll {0.000 10.000} 20.000 50.000
|
||||
cpu_clk {0.000 15.161} 30.323 32.979
|
||||
sys_clk {0.000 10.000} 20.000 50.000
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Intra Clock Table
|
||||
| -----------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
|
||||
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
|
||||
clk 7.000 0.000 0 1
|
||||
clkfbout_clk_pll 17.845 0.000 0 3
|
||||
cpu_clk 6.897 0.000 0 17197 0.011 0.000 0 17197 13.911 0.000 0 6486
|
||||
sys_clk 2.111 0.000 0 23819 0.011 0.000 0 23819 8.750 0.000 0 10995
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Inter Clock Table
|
||||
| -----------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
|
||||
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Other Path Groups Table
|
||||
| -----------------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
|
||||
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
|
||||
**async_default** cpu_clk cpu_clk 27.780 0.000 0 67 0.676 0.000 0 67
|
||||
**async_default** sys_clk sys_clk 17.299 0.000 0 2146 0.679 0.000 0 2146
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Timing Details
|
||||
| --------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------------------------
|
||||
From Clock: clk
|
||||
To Clock: clk
|
||||
|
||||
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
||||
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
||||
PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns
|
||||
---------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Pulse Width Checks
|
||||
--------------------------------------------------------------------------------------
|
||||
Clock Name: clk
|
||||
Waveform(ns): { 0.000 10.000 }
|
||||
Period(ns): 20.000
|
||||
Sources: { clk }
|
||||
|
||||
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
||||
Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 20.000 18.751 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------------------------
|
||||
From Clock: clkfbout_clk_pll
|
||||
To Clock: clkfbout_clk_pll
|
||||
|
||||
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
||||
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
||||
PW : 0 Failing Endpoints, Worst Slack 17.845ns, Total Violation 0.000ns
|
||||
---------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Pulse Width Checks
|
||||
--------------------------------------------------------------------------------------
|
||||
Clock Name: clkfbout_clk_pll
|
||||
Waveform(ns): { 0.000 10.000 }
|
||||
Period(ns): 20.000
|
||||
Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT }
|
||||
|
||||
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
||||
Min Period n/a BUFG/I n/a 2.155 20.000 17.845 pll_clk.u_clk_pll/inst/clkf_buf/I
|
||||
Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN
|
||||
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------------------------
|
||||
From Clock: cpu_clk
|
||||
To Clock: cpu_clk
|
||||
|
||||
Setup : 0 Failing Endpoints, Worst Slack 6.897ns, Total Violation 0.000ns
|
||||
Hold : 0 Failing Endpoints, Worst Slack 0.011ns, Total Violation 0.000ns
|
||||
PW : 0 Failing Endpoints, Worst Slack 13.911ns, Total Violation 0.000ns
|
||||
---------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Max Delay Paths
|
||||
--------------------------------------------------------------------------------------
|
||||
Slack (MET) : 6.897ns (required time - arrival time)
|
||||
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[25]/C
|
||||
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
||||
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D
|
||||
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
||||
Path Group: cpu_clk
|
||||
Path Type: Setup (Max at Slow Process Corner)
|
||||
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
||||
Data Path Delay: 23.236ns (logic 6.978ns (30.031%) route 16.258ns (69.969%))
|
||||
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=7 LUT6=12 MUXF7=1 MUXF8=1)
|
||||
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
||||
Destination Clock Delay (DCD): -2.918ns = ( 27.404 - 30.323 )
|
||||
Source Clock Delay (SCD): -3.241ns
|
||||
Clock Pessimism Removal (CPR): -0.468ns
|
||||
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.071ns
|
||||
Discrete Jitter (DJ): 0.130ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
(clock cpu_clk rise edge) 0.000 0.000 r
|
||||
K21 0.000 0.000 r clk (IN)
|
||||
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
||||
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
||||
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
||||
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
||||
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
||||
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
||||
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
||||
net (fo=6484, unplaced) 0.584 -3.241 u_cpu/addr_trans/cpu_clk
|
||||
FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[25]/C
|
||||
------------------------------------------------------------------- -------------------
|
||||
FDRE (Prop_fdre_C_Q) 0.456 -2.785 r u_cpu/addr_trans/data_vaddr_buffer_reg[25]/Q
|
||||
net (fo=65, unplaced) 1.054 -1.731 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[13]
|
||||
LUT6 (Prop_lut6_I0_O) 0.295 -1.436 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_105/O
|
||||
net (fo=1, unplaced) 0.000 -1.436 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_105_n_0
|
||||
CARRY4 (Prop_carry4_S[1]_CO[3])
|
||||
0.550 -0.886 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_30/CO[3]
|
||||
net (fo=1, unplaced) 0.900 0.014 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_30_n_0
|
||||
LUT6 (Prop_lut6_I3_O) 0.124 0.138 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_8/O
|
||||
net (fo=4, unplaced) 0.926 1.064 u_cpu/addr_trans/tlb_entry/match1[31]
|
||||
LUT4 (Prop_lut4_I1_O) 0.150 1.214 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
||||
net (fo=2, unplaced) 0.460 1.674 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
||||
LUT5 (Prop_lut5_I0_O) 0.118 1.792 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
||||
net (fo=2, unplaced) 0.460 2.252 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
||||
LUT6 (Prop_lut6_I0_O) 0.124 2.376 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
||||
net (fo=89, unplaced) 0.571 2.947 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
||||
MUXF7 (Prop_muxf7_S_O) 0.296 3.243 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
||||
net (fo=1, unplaced) 0.000 3.243 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
||||
MUXF8 (Prop_muxf8_I0_O) 0.104 3.347 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
||||
net (fo=1, unplaced) 0.717 4.064 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
||||
LUT5 (Prop_lut5_I0_O) 0.319 4.383 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
||||
net (fo=1, unplaced) 0.449 4.832 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
||||
LUT6 (Prop_lut6_I5_O) 0.124 4.956 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
||||
net (fo=1, unplaced) 0.449 5.405 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
||||
LUT6 (Prop_lut6_I5_O) 0.124 5.529 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
||||
net (fo=10, unplaced) 0.492 6.021 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
||||
LUT6 (Prop_lut6_I3_O) 0.124 6.145 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[4]_i_1__0/O
|
||||
net (fo=6, unplaced) 0.934 7.079 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[16]
|
||||
LUT6 (Prop_lut6_I0_O) 0.124 7.203 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
|
||||
net (fo=1, unplaced) 0.000 7.203 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
|
||||
CARRY4 (Prop_carry4_S[1]_CO[3])
|
||||
0.550 7.753 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
|
||||
net (fo=1, unplaced) 0.009 7.762 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
|
||||
CARRY4 (Prop_carry4_CI_CO[2])
|
||||
0.250 8.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
|
||||
net (fo=5, unplaced) 0.480 8.492 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
|
||||
LUT3 (Prop_lut3_I0_O) 0.310 8.802 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
|
||||
net (fo=32, unplaced) 0.520 9.322 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
|
||||
LUT6 (Prop_lut6_I5_O) 0.124 9.446 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O
|
||||
net (fo=3, unplaced) 0.920 10.366 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22]
|
||||
LUT6 (Prop_lut6_I1_O) 0.124 10.490 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
||||
net (fo=3, unplaced) 0.467 10.957 u_cpu/mem_stage/p_5_in6_in[0]
|
||||
LUT4 (Prop_lut4_I0_O) 0.118 11.075 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O
|
||||
net (fo=8, unplaced) 0.487 11.562 u_cpu/u_div/ms_to_ws_bus_r_reg[40]
|
||||
LUT5 (Prop_lut5_I4_O) 0.124 11.686 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O
|
||||
net (fo=1, unplaced) 0.449 12.135 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40]
|
||||
LUT4 (Prop_lut4_I2_O) 0.124 12.259 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O
|
||||
net (fo=4, unplaced) 0.473 12.732 u_cpu/id_stage/ms_to_ds_forward_bus[8]
|
||||
LUT5 (Prop_lut5_I2_O) 0.124 12.856 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O
|
||||
net (fo=1, unplaced) 0.000 12.856 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0
|
||||
CARRY4 (Prop_carry4_S[1]_CO[3])
|
||||
0.550 13.406 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
||||
net (fo=1, unplaced) 0.000 13.406 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
||||
CARRY4 (Prop_carry4_CI_O[1])
|
||||
0.348 13.754 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
||||
net (fo=1, unplaced) 0.611 14.365 u_cpu/id_stage/rd_csr_addr0[12]
|
||||
LUT5 (Prop_lut5_I0_O) 0.332 14.697 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
||||
net (fo=1, unplaced) 0.449 15.146 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
||||
LUT5 (Prop_lut5_I1_O) 0.124 15.270 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
||||
net (fo=3, unplaced) 0.467 15.737 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
||||
LUT4 (Prop_lut4_I3_O) 0.124 15.861 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
||||
net (fo=7, unplaced) 0.484 16.345 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
||||
LUT6 (Prop_lut6_I5_O) 0.124 16.469 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
||||
net (fo=19, unplaced) 0.508 16.977 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
||||
LUT5 (Prop_lut5_I4_O) 0.124 17.101 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_24/O
|
||||
net (fo=20, unplaced) 0.509 17.610 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_10
|
||||
LUT4 (Prop_lut4_I2_O) 0.124 17.734 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_7/O
|
||||
net (fo=1, unplaced) 1.111 18.845 u_cpu/id_stage/ds_to_es_bus_r[180]_i_7_n_0
|
||||
LUT6 (Prop_lut6_I0_O) 0.124 18.969 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_2/O
|
||||
net (fo=1, unplaced) 0.902 19.871 u_cpu/id_stage/ds_to_es_bus_r[180]_i_2_n_0
|
||||
LUT6 (Prop_lut6_I1_O) 0.124 19.995 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_1/O
|
||||
net (fo=1, unplaced) 0.000 19.995 u_cpu/exe_stage/ds_to_es_bus[130]
|
||||
FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
(clock cpu_clk rise edge) 30.323 30.323 r
|
||||
K21 0.000 30.323 r clk (IN)
|
||||
net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1
|
||||
K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
||||
net (fo=1, unplaced) 0.439 32.154 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
||||
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
||||
-6.040 26.114 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
||||
net (fo=1, unplaced) 0.760 26.874 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
||||
BUFG (Prop_bufg_I_O) 0.091 26.965 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
||||
net (fo=6484, unplaced) 0.439 27.404 u_cpu/exe_stage/cpu_clk
|
||||
FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/C
|
||||
clock pessimism -0.468 26.936
|
||||
clock uncertainty -0.074 26.862
|
||||
FDRE (Setup_fdre_C_D) 0.029 26.891 u_cpu/exe_stage/ds_to_es_bus_r_reg[180]
|
||||
-------------------------------------------------------------------
|
||||
required time 26.891
|
||||
arrival time -19.995
|
||||
-------------------------------------------------------------------
|
||||
slack 6.897
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Min Delay Paths
|
||||
--------------------------------------------------------------------------------------
|
||||
Slack (MET) : 0.011ns (arrival time - required time)
|
||||
Source: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
||||
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
||||
Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
||||
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
||||
Path Group: cpu_clk
|
||||
Path Type: Hold (Min at Fast Process Corner)
|
||||
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
||||
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
||||
Logic Levels: 0
|
||||
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
||||
Destination Clock Delay (DCD): -0.650ns
|
||||
Source Clock Delay (SCD): -0.978ns
|
||||
Clock Pessimism Removal (CPR): 0.183ns
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
(clock cpu_clk rise edge) 0.000 0.000 r
|
||||
K21 0.000 0.000 r clk (IN)
|
||||
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
||||
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
||||
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
||||
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
||||
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
||||
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
||||
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
||||
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
|
||||
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
||||
------------------------------------------------------------------- -------------------
|
||||
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
||||
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0[0]
|
||||
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
(clock cpu_clk rise edge) 0.000 0.000 r
|
||||
K21 0.000 0.000 r clk (IN)
|
||||
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
||||
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
||||
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
||||
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
||||
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
||||
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
||||
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
||||
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
|
||||
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C
|
||||
clock pessimism -0.183 -0.833
|
||||
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
||||
-------------------------------------------------------------------
|
||||
required time 0.763
|
||||
arrival time -0.752
|
||||
-------------------------------------------------------------------
|
||||
slack 0.011
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Pulse Width Checks
|
||||
--------------------------------------------------------------------------------------
|
||||
Clock Name: cpu_clk
|
||||
Waveform(ns): { 0.000 15.161 }
|
||||
Period(ns): 30.323
|
||||
Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 }
|
||||
|
||||
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
||||
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK
|
||||
Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.323 129.677 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
||||
Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_12_17/RAMA/CLK
|
||||
High Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_12_17/RAMA/CLK
|
||||
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------------------------
|
||||
From Clock: sys_clk
|
||||
To Clock: sys_clk
|
||||
|
||||
Setup : 0 Failing Endpoints, Worst Slack 2.111ns, Total Violation 0.000ns
|
||||
Hold : 0 Failing Endpoints, Worst Slack 0.011ns, Total Violation 0.000ns
|
||||
PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns
|
||||
---------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Max Delay Paths
|
||||
--------------------------------------------------------------------------------------
|
||||
Slack (MET) : 2.111ns (required time - arrival time)
|
||||
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
||||
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
||||
Destination: u_matmul_axi_slave/crc_reg_reg[18]/D
|
||||
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
||||
Path Group: sys_clk
|
||||
Path Type: Setup (Max at Slow Process Corner)
|
||||
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
||||
Data Path Delay: 17.702ns (logic 4.444ns (25.105%) route 13.258ns (74.895%))
|
||||
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT5=5 LUT6=8)
|
||||
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
||||
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
||||
Source Clock Delay (SCD): -3.025ns
|
||||
Clock Pessimism Removal (CPR): -0.468ns
|
||||
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.071ns
|
||||
Discrete Jitter (DJ): 0.122ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
(clock sys_clk rise edge) 0.000 0.000 r
|
||||
K21 0.000 0.000 r clk (IN)
|
||||
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
||||
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
||||
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
||||
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
||||
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
||||
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
||||
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
||||
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
||||
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
||||
------------------------------------------------------------------- -------------------
|
||||
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
||||
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
||||
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
||||
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
||||
CARRY4 (Prop_carry4_S[1]_CO[3])
|
||||
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
||||
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
||||
CARRY4 (Prop_carry4_CI_O[1])
|
||||
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
||||
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
||||
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
||||
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
||||
CARRY4 (Prop_carry4_S[1]_O[3])
|
||||
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
||||
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
||||
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
||||
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
||||
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
||||
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
||||
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
||||
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
||||
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
||||
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
||||
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
||||
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
||||
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
||||
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
||||
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
|
||||
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
|
||||
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
|
||||
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
|
||||
LUT5 (Prop_lut5_I1_O) 0.150 9.989 r u_matmul_axi_slave/crc_reg[30]_i_10/O
|
||||
net (fo=1, unplaced) 1.111 11.100 u_matmul_axi_slave/crc32_word_next0_return0[22]
|
||||
LUT5 (Prop_lut5_I0_O) 0.152 11.252 r u_matmul_axi_slave/crc_reg[30]_i_4/O
|
||||
net (fo=1, unplaced) 0.902 12.154 u_matmul_axi_slave/p_0_in0_in[8]
|
||||
LUT5 (Prop_lut5_I2_O) 0.124 12.278 r u_matmul_axi_slave/crc_reg[30]_i_2/O
|
||||
net (fo=9, unplaced) 1.005 13.283 u_matmul_axi_slave/crc32_word_next1_return1[0]
|
||||
LUT6 (Prop_lut6_I0_O) 0.124 13.407 r u_matmul_axi_slave/crc_reg[28]_i_2/O
|
||||
net (fo=7, unplaced) 1.146 14.553 u_matmul_axi_slave/crc_reg[28]_i_2_n_0
|
||||
LUT6 (Prop_lut6_I1_O) 0.124 14.677 r u_matmul_axi_slave/crc_reg[18]_i_1/O
|
||||
net (fo=1, unplaced) 0.000 14.677 u_matmul_axi_slave/crc32_word_next1_return[18]
|
||||
FDSE r u_matmul_axi_slave/crc_reg_reg[18]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
(clock sys_clk rise edge) 20.000 20.000 r
|
||||
K21 0.000 20.000 r clk (IN)
|
||||
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
||||
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
||||
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
||||
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
||||
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
||||
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
||||
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
||||
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
||||
FDSE r u_matmul_axi_slave/crc_reg_reg[18]/C
|
||||
clock pessimism -0.468 16.830
|
||||
clock uncertainty -0.071 16.759
|
||||
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[18]
|
||||
-------------------------------------------------------------------
|
||||
required time 16.788
|
||||
arrival time -14.677
|
||||
-------------------------------------------------------------------
|
||||
slack 2.111
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Min Delay Paths
|
||||
--------------------------------------------------------------------------------------
|
||||
Slack (MET) : 0.011ns (arrival time - required time)
|
||||
Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
||||
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
||||
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
||||
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
||||
Path Group: sys_clk
|
||||
Path Type: Hold (Min at Fast Process Corner)
|
||||
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
||||
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
||||
Logic Levels: 0
|
||||
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
||||
Destination Clock Delay (DCD): -0.555ns
|
||||
Source Clock Delay (SCD): -0.882ns
|
||||
Clock Pessimism Removal (CPR): 0.183ns
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
(clock sys_clk rise edge) 0.000 0.000 r
|
||||
K21 0.000 0.000 r clk (IN)
|
||||
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
||||
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
||||
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
||||
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
||||
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
||||
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
||||
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
||||
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
|
||||
FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
||||
------------------------------------------------------------------- -------------------
|
||||
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
|
||||
net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0]
|
||||
FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
(clock sys_clk rise edge) 0.000 0.000 r
|
||||
K21 0.000 0.000 r clk (IN)
|
||||
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
||||
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
||||
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
||||
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
||||
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
||||
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
||||
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
||||
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
|
||||
FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
|
||||
clock pessimism -0.183 -0.737
|
||||
FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
||||
-------------------------------------------------------------------
|
||||
required time 0.667
|
||||
arrival time -0.657
|
||||
-------------------------------------------------------------------
|
||||
slack 0.011
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Pulse Width Checks
|
||||
--------------------------------------------------------------------------------------
|
||||
Clock Name: sys_clk
|
||||
Waveform(ns): { 0.000 10.000 }
|
||||
Period(ns): 20.000
|
||||
Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 }
|
||||
|
||||
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
||||
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK
|
||||
Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
||||
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK
|
||||
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK
|
||||
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------------------------
|
||||
Path Group: **async_default**
|
||||
From Clock: cpu_clk
|
||||
To Clock: cpu_clk
|
||||
|
||||
Setup : 0 Failing Endpoints, Worst Slack 27.780ns, Total Violation 0.000ns
|
||||
Hold : 0 Failing Endpoints, Worst Slack 0.676ns, Total Violation 0.000ns
|
||||
---------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Max Delay Paths
|
||||
--------------------------------------------------------------------------------------
|
||||
Slack (MET) : 27.780ns (required time - arrival time)
|
||||
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
||||
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
||||
Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR
|
||||
(recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
||||
Path Group: **async_default**
|
||||
Path Type: Recovery (Max at Slow Process Corner)
|
||||
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
||||
Data Path Delay: 1.915ns (logic 0.751ns (39.217%) route 1.164ns (60.783%))
|
||||
Logic Levels: 1 (LUT1=1)
|
||||
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
||||
Destination Clock Delay (DCD): -2.918ns = ( 27.404 - 30.323 )
|
||||
Source Clock Delay (SCD): -3.241ns
|
||||
Clock Pessimism Removal (CPR): -0.468ns
|
||||
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.071ns
|
||||
Discrete Jitter (DJ): 0.130ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
(clock cpu_clk rise edge) 0.000 0.000 r
|
||||
K21 0.000 0.000 r clk (IN)
|
||||
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
||||
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
||||
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
||||
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
||||
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
||||
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
||||
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
||||
net (fo=6484, unplaced) 0.584 -3.241 pll_clk.u_rst_cpu/cpu_clk
|
||||
FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
||||
------------------------------------------------------------------- -------------------
|
||||
FDCE (Prop_fdce_C_Q) 0.456 -2.785 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
||||
net (fo=1, unplaced) 0.311 -2.474 pll_clk.u_rst_cpu/cpu_resetn
|
||||
LUT1 (Prop_lut1_I0_O) 0.295 -2.179 f pll_clk.u_rst_cpu/reset_i_1/O
|
||||
net (fo=40, unplaced) 0.853 -1.326 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in
|
||||
FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
(clock cpu_clk rise edge) 30.323 30.323 r
|
||||
K21 0.000 30.323 r clk (IN)
|
||||
net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1
|
||||
K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
||||
net (fo=1, unplaced) 0.439 32.154 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
||||
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
||||
-6.040 26.114 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
||||
net (fo=1, unplaced) 0.760 26.874 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
||||
BUFG (Prop_bufg_I_O) 0.091 26.965 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
||||
net (fo=6484, unplaced) 0.439 27.404 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
|
||||
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
||||
clock pessimism -0.468 26.936
|
||||
clock uncertainty -0.074 26.862
|
||||
FDCE (Recov_fdce_C_CLR) -0.409 26.453 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]
|
||||
-------------------------------------------------------------------
|
||||
required time 26.453
|
||||
arrival time 1.326
|
||||
-------------------------------------------------------------------
|
||||
slack 27.780
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Min Delay Paths
|
||||
--------------------------------------------------------------------------------------
|
||||
Slack (MET) : 0.676ns (arrival time - required time)
|
||||
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
||||
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
||||
Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR
|
||||
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
||||
Path Group: **async_default**
|
||||
Path Type: Removal (Min at Fast Process Corner)
|
||||
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
||||
Data Path Delay: 0.727ns (logic 0.239ns (32.888%) route 0.488ns (67.112%))
|
||||
Logic Levels: 1 (LUT1=1)
|
||||
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
||||
Destination Clock Delay (DCD): -0.650ns
|
||||
Source Clock Delay (SCD): -0.978ns
|
||||
Clock Pessimism Removal (CPR): 0.183ns
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
(clock cpu_clk rise edge) 0.000 0.000 r
|
||||
K21 0.000 0.000 r clk (IN)
|
||||
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
||||
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
||||
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
||||
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
||||
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
||||
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
||||
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
||||
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
||||
FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
||||
------------------------------------------------------------------- -------------------
|
||||
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
||||
net (fo=1, unplaced) 0.131 -0.706 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
||||
LUT1 (Prop_lut1_I0_O) 0.098 -0.608 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
||||
net (fo=30, unplaced) 0.357 -0.251 u_Axi_CDC/bFifo/buffers_1_reg
|
||||
FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
(clock cpu_clk rise edge) 0.000 0.000 r
|
||||
K21 0.000 0.000 r clk (IN)
|
||||
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
||||
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
||||
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
||||
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
||||
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
||||
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
||||
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
||||
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/bFifo/cpu_clk
|
||||
FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C
|
||||
clock pessimism -0.183 -0.833
|
||||
FDCE (Remov_fdce_C_CLR) -0.094 -0.927 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg
|
||||
-------------------------------------------------------------------
|
||||
required time 0.927
|
||||
arrival time -0.251
|
||||
-------------------------------------------------------------------
|
||||
slack 0.676
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------------------------
|
||||
Path Group: **async_default**
|
||||
From Clock: sys_clk
|
||||
To Clock: sys_clk
|
||||
|
||||
Setup : 0 Failing Endpoints, Worst Slack 17.299ns, Total Violation 0.000ns
|
||||
Hold : 0 Failing Endpoints, Worst Slack 0.679ns, Total Violation 0.000ns
|
||||
---------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Max Delay Paths
|
||||
--------------------------------------------------------------------------------------
|
||||
Slack (MET) : 17.299ns (required time - arrival time)
|
||||
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
||||
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
||||
Destination: u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/locked_reg/CLR
|
||||
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
||||
Path Group: **async_default**
|
||||
Path Type: Recovery (Max at Slow Process Corner)
|
||||
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
||||
Data Path Delay: 2.076ns (logic 0.745ns (35.886%) route 1.331ns (64.114%))
|
||||
Logic Levels: 1 (LUT1=1)
|
||||
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
||||
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
||||
Source Clock Delay (SCD): -3.025ns
|
||||
Clock Pessimism Removal (CPR): -0.468ns
|
||||
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.071ns
|
||||
Discrete Jitter (DJ): 0.122ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
(clock sys_clk rise edge) 0.000 0.000 r
|
||||
K21 0.000 0.000 r clk (IN)
|
||||
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
||||
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
||||
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
||||
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
||||
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
||||
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
||||
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
||||
net (fo=10994, unplaced) 0.800 -3.025 pll_clk.u_rst_sys/sys_clk
|
||||
FDCE r pll_clk.u_rst_sys/delay_reg[1]/C
|
||||
------------------------------------------------------------------- -------------------
|
||||
FDCE (Prop_fdce_C_Q) 0.456 -2.569 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
||||
net (fo=119, unplaced) 0.415 -2.154 pll_clk.u_rst_sys/Q[0]
|
||||
LUT1 (Prop_lut1_I0_O) 0.289 -1.865 f pll_clk.u_rst_sys/r_wb[7]_i_4/O
|
||||
net (fo=28767, unplaced) 0.916 -0.949 u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/p_0_in
|
||||
FDCE f u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/locked_reg/CLR
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
(clock sys_clk rise edge) 20.000 20.000 r
|
||||
K21 0.000 20.000 r clk (IN)
|
||||
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
||||
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
||||
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
||||
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
||||
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
||||
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
||||
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
||||
net (fo=10994, unplaced) 0.655 17.297 u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/sys_clk
|
||||
FDCE r u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/locked_reg/C
|
||||
clock pessimism -0.468 16.830
|
||||
clock uncertainty -0.071 16.759
|
||||
FDCE (Recov_fdce_C_CLR) -0.409 16.350 u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/locked_reg
|
||||
-------------------------------------------------------------------
|
||||
required time 16.350
|
||||
arrival time 0.949
|
||||
-------------------------------------------------------------------
|
||||
slack 17.299
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Min Delay Paths
|
||||
--------------------------------------------------------------------------------------
|
||||
Slack (MET) : 0.679ns (arrival time - required time)
|
||||
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
||||
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
||||
Destination: u_Axi_CDC/arFifo/popCC_addressGen_rValid_reg/CLR
|
||||
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
||||
Path Group: **async_default**
|
||||
Path Type: Removal (Min at Fast Process Corner)
|
||||
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
||||
Data Path Delay: 0.730ns (logic 0.239ns (32.718%) route 0.491ns (67.282%))
|
||||
Logic Levels: 1 (LUT1=1)
|
||||
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
||||
Destination Clock Delay (DCD): -0.555ns
|
||||
Source Clock Delay (SCD): -0.882ns
|
||||
Clock Pessimism Removal (CPR): 0.183ns
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
(clock sys_clk rise edge) 0.000 0.000 r
|
||||
K21 0.000 0.000 r clk (IN)
|
||||
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
||||
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
||||
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
||||
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
||||
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
||||
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
||||
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
||||
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
||||
FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
||||
------------------------------------------------------------------- -------------------
|
||||
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
||||
net (fo=1, unplaced) 0.131 -0.610 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
||||
LUT1 (Prop_lut1_I0_O) 0.098 -0.512 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
||||
net (fo=43, unplaced) 0.360 -0.152 u_Axi_CDC/arFifo/buffers_0_reg[2]
|
||||
FDCE f u_Axi_CDC/arFifo/popCC_addressGen_rValid_reg/CLR
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
(clock sys_clk rise edge) 0.000 0.000 r
|
||||
K21 0.000 0.000 r clk (IN)
|
||||
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
||||
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
||||
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
||||
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
||||
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
||||
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
||||
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
||||
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/arFifo/sys_clk
|
||||
FDCE r u_Axi_CDC/arFifo/popCC_addressGen_rValid_reg/C
|
||||
clock pessimism -0.183 -0.737
|
||||
FDCE (Remov_fdce_C_CLR) -0.094 -0.831 u_Axi_CDC/arFifo/popCC_addressGen_rValid_reg
|
||||
-------------------------------------------------------------------
|
||||
required time 0.831
|
||||
arrival time -0.152
|
||||
-------------------------------------------------------------------
|
||||
slack 0.679
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -1,203 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:34:12 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_utilization -file ./vivado_reports/synth_utilization.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200tfbg676-1
|
||||
| Design State : Synthesized
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
| Slice LUTs* | 74980 | 0 | 134600 | 55.71 |
|
||||
| LUT as Logic | 73234 | 0 | 134600 | 54.41 |
|
||||
| LUT as Memory | 1746 | 0 | 46200 | 3.78 |
|
||||
| LUT as Distributed RAM | 652 | 0 | | |
|
||||
| LUT as Shift Register | 1094 | 0 | | |
|
||||
| Slice Registers | 38603 | 0 | 269200 | 14.34 |
|
||||
| Register as Flip Flop | 38603 | 0 | 269200 | 14.34 |
|
||||
| Register as Latch | 0 | 0 | 269200 | 0.00 |
|
||||
| F7 Muxes | 4263 | 0 | 67300 | 6.33 |
|
||||
| F8 Muxes | 1403 | 0 | 33650 | 4.17 |
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 101 | Yes | - | Set |
|
||||
| 25523 | Yes | - | Reset |
|
||||
| 134 | Yes | Set | - |
|
||||
| 12845 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 25.5 | 0 | 365 | 6.99 |
|
||||
| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 |
|
||||
| RAMB36E1 only | 10 | | | |
|
||||
| RAMB18 | 31 | 0 | 730 | 4.25 |
|
||||
| RAMB18E1 only | 31 | | | |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 740 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 202 | 202 | 400 | 50.50 |
|
||||
| IOB Master Pads | 97 | | | |
|
||||
| IOB Slave Pads | 102 | | | |
|
||||
| Bonded IPADs | 0 | 0 | 26 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 16 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 10 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 384 | 0.00 |
|
||||
| GTPE2_CHANNEL | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 400 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 400 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 4 | 0 | 32 | 12.50 |
|
||||
| BUFIO | 0 | 0 | 40 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| PLLE2_ADV | 1 | 0 | 10 | 10.00 |
|
||||
| BUFMRCE | 0 | 0 | 20 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 120 | 0.00 |
|
||||
| BUFR | 0 | 0 | 40 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+-----------+-------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+-----------+-------+---------------------+
|
||||
| LUT6 | 36042 | LUT |
|
||||
| FDCE | 25523 | Flop & Latch |
|
||||
| LUT5 | 16007 | LUT |
|
||||
| LUT3 | 13060 | LUT |
|
||||
| FDRE | 12845 | Flop & Latch |
|
||||
| LUT4 | 11977 | LUT |
|
||||
| LUT2 | 9006 | LUT |
|
||||
| MUXF7 | 4263 | MuxFx |
|
||||
| CARRY4 | 3590 | CarryLogic |
|
||||
| MUXF8 | 1403 | MuxFx |
|
||||
| SRLC32E | 992 | Distributed Memory |
|
||||
| RAMD32 | 892 | Distributed Memory |
|
||||
| LUT1 | 816 | LUT |
|
||||
| RAMS32 | 272 | Distributed Memory |
|
||||
| FDSE | 134 | Flop & Latch |
|
||||
| IBUF | 104 | IO |
|
||||
| SRL16E | 102 | Distributed Memory |
|
||||
| FDPE | 101 | Flop & Latch |
|
||||
| OBUF | 98 | IO |
|
||||
| OBUFT | 66 | IO |
|
||||
| RAMD64E | 32 | Distributed Memory |
|
||||
| RAMB18E1 | 31 | Block Memory |
|
||||
| RAMB36E1 | 10 | Block Memory |
|
||||
| BUFG | 4 | Clock |
|
||||
| PLLE2_ADV | 1 | Clock |
|
||||
+-----------+-------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
| clk_pll | 1 |
|
||||
+----------+------+
|
||||
|
||||
|
||||
@@ -1,255 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:34:18 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_utilization -hierarchical -hierarchical_depth 10 -file ./vivado_reports/synth_utilization_hier.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200tfbg676-1
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Utilization by Hierarchy
|
||||
|
||||
1. Utilization by Hierarchy
|
||||
---------------------------
|
||||
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks |
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
| soc_top | (top) | 74980 | 73234 | 652 | 1094 | 38603 | 10 | 31 | 0 |
|
||||
| (soc_top) | (top) | 2116 | 2060 | 56 | 0 | 4 | 0 | 0 | 0 |
|
||||
| pll_clk.u_clk_pll | clk_pll | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| inst | clk_pll_clk_pll_clk_wiz | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_sys | rst_sync_0 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 519 | 519 | 0 | 0 | 151 | 0 | 0 | 0 |
|
||||
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 8 | 8 | 0 | 0 | 24 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_67 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_50 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_66 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_51 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_65 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_52 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_64 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 32 | 32 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_61 | 25 | 25 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_62 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_63 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_58 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_59 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_60 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_55 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_56 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_57 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 61 | 61 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7 | 48 | 48 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 13 | 13 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3 | 13 | 13 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 89 | 89 | 0 | 0 | 25 | 0 | 0 | 0 |
|
||||
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 73 | 73 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4ReadOnlyErrorSlave_1_54 | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 |
|
||||
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4WriteOnlyErrorSlave_1_53 | 20 | 20 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 181 | 181 | 0 | 0 | 17 | 0 | 0 | 0 |
|
||||
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 165 | 165 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4ReadOnlyErrorSlave_1 | 16 | 16 | 0 | 0 | 9 | 0 | 0 | 0 |
|
||||
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 25 | 25 | 0 | 0 | 14 | 0 | 0 | 0 |
|
||||
| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 18 | 18 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 7 | 7 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| u_Axi_CDC | Axi_CDC | 505 | 377 | 128 | 0 | 309 | 0 | 0 | 0 |
|
||||
| arFifo | StreamFifoCC_3 | 262 | 226 | 36 | 0 | 73 | 0 | 0 | 0 |
|
||||
| (arFifo) | StreamFifoCC_3 | 256 | 220 | 36 | 0 | 61 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9_48 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11_49 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| awFifo | StreamFifoCC | 112 | 76 | 36 | 0 | 75 | 0 | 0 | 0 |
|
||||
| (awFifo) | StreamFifoCC | 105 | 69 | 36 | 0 | 61 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| bFifo | StreamFifoCC_2 | 16 | 16 | 0 | 0 | 26 | 0 | 0 | 0 |
|
||||
| (bFifo) | StreamFifoCC_2 | 9 | 9 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_4 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_6 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| rFifo | StreamFifoCC_4 | 46 | 18 | 28 | 0 | 66 | 0 | 0 | 0 |
|
||||
| (rFifo) | StreamFifoCC_4 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_1 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| wFifo | StreamFifoCC_1 | 69 | 41 | 28 | 0 | 69 | 0 | 0 | 0 |
|
||||
| (wFifo) | StreamFifoCC_1 | 64 | 36 | 28 | 0 | 53 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_8 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_axi_axil_adapter | axi_axil_adapter | 1355 | 1355 | 0 | 0 | 161 | 0 | 0 | 0 |
|
||||
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 648 | 648 | 0 | 0 | 81 | 0 | 0 | 0 |
|
||||
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 707 | 707 | 0 | 0 | 80 | 0 | 0 | 0 |
|
||||
| u_axi_dvi | axi_dvi | 285 | 285 | 0 | 0 | 211 | 0 | 0 | 0 |
|
||||
| u_axi_ram | axi_wrap_ram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
|
||||
| u_axi_sram_sp | axi2sram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
|
||||
| u_axi_uart_controller | axi_uart_controller | 693 | 677 | 16 | 0 | 457 | 0 | 0 | 0 |
|
||||
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 252 | 252 | 0 | 0 | 120 | 0 | 0 | 0 |
|
||||
| uart0 | UART_TOP | 441 | 425 | 16 | 0 | 337 | 0 | 0 | 0 |
|
||||
| regs | uart_regs | 441 | 425 | 16 | 0 | 337 | 0 | 0 | 0 |
|
||||
| (regs) | uart_regs | 121 | 121 | 0 | 0 | 155 | 0 | 0 | 0 |
|
||||
| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| receiver | uart_receiver | 231 | 223 | 8 | 0 | 124 | 0 | 0 | 0 |
|
||||
| (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 |
|
||||
| fifo_rx | uart_rfifo | 163 | 155 | 8 | 0 | 70 | 0 | 0 | 0 |
|
||||
| (fifo_rx) | uart_rfifo | 144 | 144 | 0 | 0 | 62 | 0 | 0 | 0 |
|
||||
| rfifo | raminfr_47 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
||||
| transmitter | uart_transmitter | 86 | 78 | 8 | 0 | 56 | 0 | 0 | 0 |
|
||||
| (transmitter) | uart_transmitter | 42 | 42 | 0 | 0 | 35 | 0 | 0 | 0 |
|
||||
| fifo_tx | uart_tfifo | 44 | 36 | 8 | 0 | 21 | 0 | 0 | 0 |
|
||||
| (fifo_tx) | uart_tfifo | 25 | 25 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_cdma_matmul_bridge | cdma_matmul_bridge | 250 | 250 | 0 | 0 | 578 | 0 | 0 | 0 |
|
||||
| u_confreg | confreg | 391 | 391 | 0 | 0 | 460 | 0 | 0 | 0 |
|
||||
| (u_confreg) | confreg | 231 | 231 | 0 | 0 | 383 | 0 | 0 | 0 |
|
||||
| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 |
|
||||
| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 |
|
||||
| u_cpu | core_top | 8656 | 8380 | 276 | 0 | 5591 | 0 | 20 | 0 |
|
||||
| (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 |
|
||||
| addr_trans | addr_trans | 2264 | 2100 | 164 | 0 | 1244 | 0 | 0 | 0 |
|
||||
| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 |
|
||||
| tlb_entry | tlb_entry | 2264 | 2100 | 164 | 0 | 1204 | 0 | 0 | 0 |
|
||||
| axi_bridge | axi_bridge | 40 | 40 | 0 | 0 | 214 | 0 | 0 | 0 |
|
||||
| btb | btb | 1064 | 984 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
||||
| (btb) | btb | 1061 | 981 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
||||
| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| dcache | dcache | 569 | 537 | 32 | 0 | 146 | 0 | 10 | 0 |
|
||||
| (dcache) | dcache | 92 | 60 | 32 | 0 | 138 | 0 | 0 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_36 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_39 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_40 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_41 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_42 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_43 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| lfsr | lfsr_44 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| tagv_ram_way[0].u | tagv_sram_45 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| tagv_ram_way[1].u | tagv_sram_46 | 46 | 46 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| exe_stage | exe_stage | 681 | 681 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| (exe_stage) | exe_stage | 650 | 650 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| icache | icache | 239 | 239 | 0 | 0 | 55 | 0 | 10 | 0 |
|
||||
| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_29 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_30 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_31 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_32 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_33 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_34 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| tagv_ram_way[1].u | tagv_sram_35 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| id_stage | id_stage | 1058 | 1058 | 0 | 0 | 108 | 0 | 0 | 0 |
|
||||
| if_stage | if_stage | 135 | 135 | 0 | 0 | 173 | 0 | 0 | 0 |
|
||||
| mem_stage | mem_stage | 116 | 116 | 0 | 0 | 211 | 0 | 0 | 0 |
|
||||
| u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 |
|
||||
| u_div | div | 143 | 143 | 0 | 0 | 107 | 0 | 0 | 0 |
|
||||
| u_mul | mul | 943 | 943 | 0 | 0 | 592 | 0 | 0 | 0 |
|
||||
| wb_stage | wb_stage | 685 | 685 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 48074 | 46986 | 0 | 1088 | 25915 | 10 | 10 | 0 |
|
||||
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 17 | 17 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| u_fft_controller | fft_controller | 6966 | 5878 | 0 | 1088 | 1087 | 8 | 4 | 0 |
|
||||
| (u_fft_controller) | fft_controller | 90 | 90 | 0 | 0 | 104 | 0 | 0 | 0 |
|
||||
| u_FFT | FFT | 6855 | 5767 | 0 | 1088 | 983 | 8 | 0 | 0 |
|
||||
| SU1 | SdfUnit | 2150 | 1382 | 0 | 768 | 197 | 2 | 0 | 0 |
|
||||
| (SU1) | SdfUnit | 39 | 39 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_25 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer | 624 | 112 | 0 | 512 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized0 | 320 | 64 | 0 | 256 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_26 | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle_27 | 543 | 543 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU2 | SdfUnit__parameterized0 | 1571 | 1379 | 0 | 192 | 197 | 2 | 0 | 0 |
|
||||
| (SU2) | SdfUnit__parameterized0 | 38 | 38 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_20 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_21 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_22 | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle_23 | 541 | 541 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU3 | SdfUnit__parameterized1 | 1439 | 1375 | 0 | 64 | 197 | 2 | 0 | 0 |
|
||||
| (SU3) | SdfUnit__parameterized1 | 35 | 35 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_16 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_17 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized4 | 96 | 64 | 0 | 32 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_18 | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle_19 | 540 | 540 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU4 | SdfUnit__parameterized2 | 1436 | 1372 | 0 | 64 | 197 | 2 | 0 | 0 |
|
||||
| (SU4) | SdfUnit__parameterized2 | 34 | 34 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_14 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_15 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized5 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized6 | 96 | 64 | 0 | 32 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle | 538 | 538 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU5 | SdfUnit__parameterized3 | 259 | 259 | 0 | 0 | 195 | 0 | 0 | 0 |
|
||||
| (SU5) | SdfUnit__parameterized3 | 35 | 35 | 0 | 0 | 99 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 |
|
||||
| u_in0 | my_bram0 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_in1 | my_bram0_11 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_out0 | my_bram0_12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_out1 | my_bram0_13 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_mlkem_axi_slave | mlkem_axi_slave | 40589 | 40589 | 0 | 0 | 24484 | 2 | 6 | 0 |
|
||||
| (u_mlkem_axi_slave) | mlkem_axi_slave | 3642 | 3642 | 0 | 0 | 1021 | 0 | 0 | 0 |
|
||||
| u_mlkem | mlkem_top | 36975 | 36975 | 0 | 0 | 23463 | 2 | 6 | 0 |
|
||||
| (u_mlkem) | mlkem_top | 2550 | 2550 | 0 | 0 | 4907 | 0 | 0 | 0 |
|
||||
| u_bank_a | sd_bram__parameterized0 | 39 | 39 | 0 | 0 | 0 | 1 | 1 | 0 |
|
||||
| u_bank_se | sd_bram__parameterized1 | 62 | 62 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| u_bank_t | sd_bram__parameterized2 | 484 | 484 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_c_in_bram | sd_bram | 1291 | 1291 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_cbd | sample_cbd_sync_shared | 2469 | 2469 | 0 | 0 | 3199 | 0 | 0 | 0 |
|
||||
| u_comp | comp_decomp_sync | 177 | 177 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| u_pipe | pipeline_reg | 177 | 177 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| u_ct_bram | sd_bram_4 | 20 | 20 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_dkp_bram | sd_bram_5 | 101 | 101 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_ek_bram | sd_bram_6 | 226 | 226 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_keccak | keccak_core | 5251 | 5251 | 0 | 0 | 1619 | 0 | 0 | 0 |
|
||||
| u_ntt | ntt_core | 13498 | 13498 | 0 | 0 | 3354 | 0 | 0 | 0 |
|
||||
| u_pmul | poly_mul_sync | 7392 | 7392 | 0 | 0 | 6314 | 0 | 0 | 0 |
|
||||
| (u_pmul) | poly_mul_sync | 5013 | 5013 | 0 | 0 | 6314 | 0 | 0 | 0 |
|
||||
| u_bc | basecase_mul | 2379 | 2379 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| (u_bc) | basecase_mul | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_mul1 | barrett_mul | 969 | 969 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_mul2 | barrett_mul_7 | 118 | 118 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_mul3 | barrett_mul_8 | 561 | 561 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_mul4 | barrett_mul_9 | 549 | 549 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_mul_zeta | barrett_mul_10 | 130 | 130 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_sha3 | sha3_top_shared | 1983 | 1983 | 0 | 0 | 2388 | 0 | 0 | 0 |
|
||||
| u_snt | sample_ntt_sync_shared | 1433 | 1433 | 0 | 0 | 1669 | 0 | 0 | 0 |
|
||||
| u_prng_axi_slave | prng_axi_slave | 502 | 502 | 0 | 0 | 338 | 0 | 0 | 0 |
|
||||
| u_matmul_axi_slave | matmul_axi_slave | 9974 | 9792 | 176 | 6 | 3208 | 0 | 0 | 0 |
|
||||
| (u_matmul_axi_slave) | matmul_axi_slave | 5758 | 5576 | 176 | 6 | 2440 | 0 | 0 | 0 |
|
||||
| mult_inst[0].u_mult | pipelined_mult_32x32 | 1086 | 1086 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| mult_inst[1].u_mult | pipelined_mult_32x32_1 | 1022 | 1022 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| mult_inst[2].u_mult | pipelined_mult_32x32_2 | 1086 | 1086 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| mult_inst[3].u_mult | pipelined_mult_32x32_3 | 1022 | 1022 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1823 | 1823 | 0 | 0 | 1476 | 0 | 1 | 0 |
|
||||
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 605 | 605 | 0 | 0 | 1180 | 0 | 0 | 0 |
|
||||
| u_core_engine | snix_axi_mm2mm | 1218 | 1218 | 0 | 0 | 296 | 0 | 1 | 0 |
|
||||
| (u_core_engine) | snix_axi_mm2mm | 776 | 776 | 0 | 0 | 243 | 0 | 0 | 0 |
|
||||
| axis_fifo_u0 | snix_axis_fifo | 442 | 442 | 0 | 0 | 53 | 0 | 1 | 0 |
|
||||
| u_fifo | snix_sync_fifo | 442 | 442 | 0 | 0 | 53 | 0 | 1 | 0 |
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
|
||||
|
||||
@@ -1,438 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:46:27 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_clock_utilization -file ./vivado_reports_impl/routed_clock_utilization.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200t-fbg676
|
||||
| Speed File : -1 PRODUCTION 1.23 2018-06-13
|
||||
| Design State : Routed
|
||||
---------------------------------------------------------------------------------------------------
|
||||
|
||||
Clock Utilization Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Clock Primitive Utilization
|
||||
2. Global Clock Resources
|
||||
3. Global Clock Source Details
|
||||
4. Clock Regions: Key Resource Utilization
|
||||
5. Clock Regions : Global Clock Summary
|
||||
6. Device Cell Placement Summary for Global Clock g0
|
||||
7. Device Cell Placement Summary for Global Clock g1
|
||||
8. Device Cell Placement Summary for Global Clock g2
|
||||
9. Device Cell Placement Summary for Global Clock g3
|
||||
10. Device Cell Placement Summary for Global Clock g4
|
||||
11. Clock Region Cell Placement per Global Clock: Region X0Y0
|
||||
12. Clock Region Cell Placement per Global Clock: Region X1Y0
|
||||
13. Clock Region Cell Placement per Global Clock: Region X0Y1
|
||||
14. Clock Region Cell Placement per Global Clock: Region X1Y1
|
||||
15. Clock Region Cell Placement per Global Clock: Region X0Y2
|
||||
16. Clock Region Cell Placement per Global Clock: Region X1Y2
|
||||
17. Clock Region Cell Placement per Global Clock: Region X0Y3
|
||||
18. Clock Region Cell Placement per Global Clock: Region X1Y3
|
||||
19. Clock Region Cell Placement per Global Clock: Region X0Y4
|
||||
20. Clock Region Cell Placement per Global Clock: Region X1Y4
|
||||
|
||||
1. Clock Primitive Utilization
|
||||
------------------------------
|
||||
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
| Type | Used | Available | LOC | Clock Region | Pblock |
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
| BUFGCTRL | 5 | 32 | 0 | 0 | 0 |
|
||||
| BUFH | 0 | 120 | 0 | 0 | 0 |
|
||||
| BUFIO | 0 | 40 | 0 | 0 | 0 |
|
||||
| BUFMR | 0 | 20 | 0 | 0 | 0 |
|
||||
| BUFR | 0 | 40 | 0 | 0 | 0 |
|
||||
| MMCM | 0 | 10 | 0 | 0 | 0 |
|
||||
| PLL | 1 | 10 | 0 | 0 | 0 |
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
|
||||
|
||||
2. Global Clock Resources
|
||||
-------------------------
|
||||
|
||||
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
|
||||
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
|
||||
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
|
||||
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 8 | 23490 | 0 | | | r_wb_reg[7]_i_3/O | u_mlkem_axi_slave/mlkem_clk |
|
||||
| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 7 | 10620 | 1 | 20.000 | sys_clk | pll_clk.u_clk_pll/inst/clkout2_buf/O | pll_clk.u_clk_pll/inst/sys_clk |
|
||||
| g2 | src1 | BUFG/O | None | BUFGCTRL_X0Y17 | n/a | 4 | 5859 | 0 | 30.323 | cpu_clk | pll_clk.u_clk_pll/inst/clkout1_buf/O | pll_clk.u_clk_pll/inst/cpu_clk |
|
||||
| g3 | src1 | BUFG/O | None | BUFGCTRL_X0Y18 | n/a | 1 | 1 | 0 | 20.000 | clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkf_buf/O | pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll |
|
||||
| g4 | src2 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 10 | 0 | 28783 | n/a | n/a | pll_clk.u_rst_sys/p_0_in_BUFG_inst/O | pll_clk.u_rst_sys/p_0_in_BUFG |
|
||||
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
|
||||
|
||||
3. Global Clock Source Details
|
||||
------------------------------
|
||||
|
||||
+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
|
||||
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
|
||||
+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
|
||||
| src0 | g0 | FDCE/Q | None | SLICE_X84Y146 | X1Y2 | 1 | 1 | | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg/Q | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg_0 |
|
||||
| src1 | g3 | PLLE2_ADV/CLKFBOUT | None | PLLE2_ADV_X0Y3 | X0Y3 | 1 | 0 | 20.000 | clkfbout_clk_pll | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT | pll_clk.u_clk_pll/inst/clkfbout_clk_pll |
|
||||
| src1 | g2 | PLLE2_ADV/CLKOUT0 | None | PLLE2_ADV_X0Y3 | X0Y3 | 1 | 0 | 30.323 | cpu_clk | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll |
|
||||
| src1 | g1 | PLLE2_ADV/CLKOUT1 | None | PLLE2_ADV_X0Y3 | X0Y3 | 1 | 0 | 20.000 | sys_clk | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 | pll_clk.u_clk_pll/inst/sys_clk_clk_pll |
|
||||
| src2 | g4 | LUT1/O | None | SLICE_X132Y68 | X1Y1 | 1 | 0 | | | pll_clk.u_rst_sys/r_wb[7]_i_4/O | pll_clk.u_rst_sys/p_0_in |
|
||||
+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
|
||||
|
||||
4. Clock Regions: Key Resource Utilization
|
||||
------------------------------------------
|
||||
|
||||
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
|
||||
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
| X0Y0 | 3 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 5680 | 2700 | 1523 | 800 | 8 | 60 | 0 | 30 | 0 | 60 |
|
||||
| X1Y0 | 3 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 922 | 2500 | 677 | 800 | 0 | 40 | 6 | 20 | 0 | 40 |
|
||||
| X0Y1 | 4 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 8433 | 4200 | 2794 | 1400 | 1 | 100 | 0 | 50 | 0 | 100 |
|
||||
| X1Y1 | 4 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 6621 | 4000 | 2851 | 1400 | 3 | 80 | 2 | 40 | 0 | 80 |
|
||||
| X0Y2 | 3 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3500 | 3600 | 1397 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
|
||||
| X1Y2 | 3 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4349 | 4000 | 1624 | 1400 | 1 | 80 | 2 | 40 | 0 | 80 |
|
||||
| X0Y3 | 4 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 5614 | 3600 | 2576 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
|
||||
| X1Y3 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2775 | 4000 | 1183 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
|
||||
| X0Y4 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 1 | 0 | 50 | 0 | 50 | 671 | 2550 | 155 | 750 | 0 | 50 | 0 | 25 | 0 | 60 |
|
||||
| X1Y4 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 54 | 2500 | 18 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
* Global Clock column represents track count; while other columns represents cell counts
|
||||
|
||||
|
||||
5. Clock Regions : Global Clock Summary
|
||||
---------------------------------------
|
||||
|
||||
All Modules
|
||||
+----+----+----+
|
||||
| | X0 | X1 |
|
||||
+----+----+----+
|
||||
| Y4 | 2 | 2 |
|
||||
| Y3 | 4 | 2 |
|
||||
| Y2 | 3 | 3 |
|
||||
| Y1 | 4 | 4 |
|
||||
| Y0 | 3 | 3 |
|
||||
+----+----+----+
|
||||
|
||||
|
||||
6. Device Cell Placement Summary for Global Clock g0
|
||||
----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
|
||||
| g0 | BUFG/O | n/a | | | | 23482 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
|
||||
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
|
||||
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
**** GT Loads column represents load cell count of GT types
|
||||
|
||||
|
||||
+----+-------+-------+
|
||||
| | X0 | X1 |
|
||||
+----+-------+-------+
|
||||
| Y4 | 671 | 54 |
|
||||
| Y3 | 5614 | 2775 |
|
||||
| Y2 | 2763 | 4352 |
|
||||
| Y1 | 1435 | 5818 |
|
||||
| Y0 | 0 | 0 |
|
||||
+----+-------+-------+
|
||||
|
||||
|
||||
7. Device Cell Placement Summary for Global Clock g1
|
||||
----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
|
||||
| g1 | BUFG/O | n/a | sys_clk | 20.000 | {0.000 10.000} | 10556 | 1 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
|
||||
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
|
||||
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
**** GT Loads column represents load cell count of GT types
|
||||
|
||||
|
||||
+----+-------+-------+
|
||||
| | X0 | X1 |
|
||||
+----+-------+-------+
|
||||
| Y4 | 0 | 0 |
|
||||
| Y3 | 1 | 0 |
|
||||
| Y2 | 737 | 1 |
|
||||
| Y1 | 6977 | 1518 |
|
||||
| Y0 | 174 | 1149 |
|
||||
+----+-------+-------+
|
||||
|
||||
|
||||
8. Device Cell Placement Summary for Global Clock g2
|
||||
----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
|
||||
| g2 | BUFG/O | n/a | cpu_clk | 30.323 | {0.000 15.161} | 5716 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
|
||||
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
|
||||
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
**** GT Loads column represents load cell count of GT types
|
||||
|
||||
|
||||
+----+-------+-----+
|
||||
| | X0 | X1 |
|
||||
+----+-------+-----+
|
||||
| Y4 | 0 | 0 |
|
||||
| Y3 | 0 | 0 |
|
||||
| Y2 | 0 | 0 |
|
||||
| Y1 | 86 | 9 |
|
||||
| Y0 | 5526 | 95 |
|
||||
+----+-------+-----+
|
||||
|
||||
|
||||
9. Device Cell Placement Summary for Global Clock g3
|
||||
----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
|
||||
| g3 | BUFG/O | n/a | clkfbout_clk_pll | 20.000 | {0.000 10.000} | 0 | 0 | 1 | 0 | pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll |
|
||||
+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
|
||||
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
**** GT Loads column represents load cell count of GT types
|
||||
|
||||
|
||||
+----+----+----+
|
||||
| | X0 | X1 |
|
||||
+----+----+----+
|
||||
| Y4 | 0 | 0 |
|
||||
| Y3 | 1 | 0 |
|
||||
| Y2 | 0 | 0 |
|
||||
| Y1 | 0 | 0 |
|
||||
| Y0 | 0 | 0 |
|
||||
+----+----+----+
|
||||
|
||||
|
||||
10. Device Cell Placement Summary for Global Clock g4
|
||||
-----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------+
|
||||
| g4 | BUFG/O | n/a | | | | 28783 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
|
||||
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------+
|
||||
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
**** GT Loads column represents load cell count of GT types
|
||||
|
||||
|
||||
+----+-------+-------+
|
||||
| | X0 | X1 |
|
||||
+----+-------+-------+
|
||||
| Y4 | 671 | 54 |
|
||||
| Y3 | 5614 | 2775 |
|
||||
| Y2 | 3295 | 4349 |
|
||||
| Y1 | 5550 | 6266 |
|
||||
| Y0 | 61 | 148 |
|
||||
+----+-------+-------+
|
||||
|
||||
|
||||
11. Clock Region Cell Placement per Global Clock: Region X0Y0
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
| g1 | n/a | BUFG/O | None | 174 | 0 | 174 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
|
||||
| g2 | n/a | BUFG/O | None | 5526 | 0 | 5506 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
|
||||
| g4 | n/a | BUFG/O | None | 0 | 61 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
12. Clock Region Cell Placement per Global Clock: Region X1Y0
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
| g1 | n/a | BUFG/O | None | 1149 | 0 | 827 | 316 | 6 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
|
||||
| g2 | n/a | BUFG/O | None | 95 | 0 | 95 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
|
||||
| g4 | n/a | BUFG/O | None | 0 | 148 | 148 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
13. Clock Region Cell Placement per Global Clock: Region X0Y1
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
| g0 | n/a | BUFG/O | None | 1435 | 0 | 1435 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
|
||||
| g1 | n/a | BUFG/O | None | 6977 | 0 | 6912 | 62 | 1 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
|
||||
| g2 | n/a | BUFG/O | None | 86 | 0 | 86 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
|
||||
| g4 | n/a | BUFG/O | None | 0 | 5550 | 5550 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
14. Clock Region Cell Placement per Global Clock: Region X1Y1
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
| g0 | n/a | BUFG/O | None | 5818 | 0 | 5814 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
|
||||
| g1 | n/a | BUFG/O | None | 1518 | 0 | 798 | 716 | 3 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
|
||||
| g2 | n/a | BUFG/O | None | 9 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
|
||||
| g4 | n/a | BUFG/O | None | 0 | 6266 | 6266 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
15. Clock Region Cell Placement per Global Clock: Region X0Y2
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
| g0 | n/a | BUFG/O | None | 2763 | 0 | 2763 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
|
||||
| g1 | n/a | BUFG/O | None | 737 | 0 | 737 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
|
||||
| g4 | n/a | BUFG/O | None | 0 | 3295 | 3295 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
16. Clock Region Cell Placement per Global Clock: Region X1Y2
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
| g0 | n/a | BUFG/O | None | 4352 | 0 | 4348 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
|
||||
| g1 | n/a | BUFG/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
|
||||
| g4 | n/a | BUFG/O | None | 0 | 4349 | 4349 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
17. Clock Region Cell Placement per Global Clock: Region X0Y3
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+---------------------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+---------------------------------------------+
|
||||
| g0 | n/a | BUFG/O | None | 5614 | 0 | 5614 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
|
||||
| g1 | n/a | BUFG/O | None | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
|
||||
| g3 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll |
|
||||
| g4 | n/a | BUFG/O | None | 0 | 5614 | 5614 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+---------------------------------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
18. Clock Region Cell Placement per Global Clock: Region X1Y3
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------------------+
|
||||
| g0 | n/a | BUFG/O | None | 2775 | 0 | 2775 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
|
||||
| g4 | n/a | BUFG/O | None | 0 | 2775 | 2775 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
19. Clock Region Cell Placement per Global Clock: Region X0Y4
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-------------------------------+
|
||||
| g0 | n/a | BUFG/O | None | 671 | 0 | 671 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
|
||||
| g4 | n/a | BUFG/O | None | 0 | 671 | 671 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-------------------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
20. Clock Region Cell Placement per Global Clock: Region X1Y4
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------------+
|
||||
| g0 | n/a | BUFG/O | None | 54 | 0 | 54 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
|
||||
| g4 | n/a | BUFG/O | None | 0 | 54 | 54 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
|
||||
# Location of BUFG Primitives
|
||||
set_property LOC BUFGCTRL_X0Y1 [get_cells r_wb_reg[7]_i_3]
|
||||
set_property LOC BUFGCTRL_X0Y0 [get_cells pll_clk.u_rst_sys/p_0_in_BUFG_inst]
|
||||
set_property LOC BUFGCTRL_X0Y16 [get_cells pll_clk.u_clk_pll/inst/clkout2_buf]
|
||||
set_property LOC BUFGCTRL_X0Y17 [get_cells pll_clk.u_clk_pll/inst/clkout1_buf]
|
||||
set_property LOC BUFGCTRL_X0Y18 [get_cells pll_clk.u_clk_pll/inst/clkf_buf]
|
||||
|
||||
# Location of IO Primitives which is load of clock spine
|
||||
set_property LOC IOB_X0Y173 [get_cells video_clk_OBUF_inst]
|
||||
|
||||
# Location of clock ports
|
||||
set_property LOC IOB_X0Y176 [get_ports clk]
|
||||
|
||||
# Clock net "u_mlkem_axi_slave/mlkem_clk" driven by instance "r_wb_reg[7]_i_3" located at site "BUFGCTRL_X0Y1"
|
||||
#startgroup
|
||||
create_pblock {CLKAG_u_mlkem_axi_slave/mlkem_clk}
|
||||
add_cells_to_pblock [get_pblocks {CLKAG_u_mlkem_axi_slave/mlkem_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="u_mlkem_axi_slave/mlkem_clk"}]]]
|
||||
resize_pblock [get_pblocks {CLKAG_u_mlkem_axi_slave/mlkem_clk}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}
|
||||
#endgroup
|
||||
|
||||
# Clock net "pll_clk.u_rst_sys/p_0_in_BUFG" driven by instance "pll_clk.u_rst_sys/p_0_in_BUFG_inst" located at site "BUFGCTRL_X0Y0"
|
||||
#startgroup
|
||||
create_pblock {CLKAG_pll_clk.u_rst_sys/p_0_in_BUFG}
|
||||
add_cells_to_pblock [get_pblocks {CLKAG_pll_clk.u_rst_sys/p_0_in_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="pll_clk.u_rst_sys/p_0_in_BUFG"}]]]
|
||||
resize_pblock [get_pblocks {CLKAG_pll_clk.u_rst_sys/p_0_in_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}
|
||||
#endgroup
|
||||
|
||||
# Clock net "pll_clk.u_clk_pll/inst/sys_clk" driven by instance "pll_clk.u_clk_pll/inst/clkout2_buf" located at site "BUFGCTRL_X0Y16"
|
||||
#startgroup
|
||||
create_pblock {CLKAG_pll_clk.u_clk_pll/inst/sys_clk}
|
||||
add_cells_to_pblock [get_pblocks {CLKAG_pll_clk.u_clk_pll/inst/sys_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=video_clk_OBUF_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="pll_clk.u_clk_pll/inst/sys_clk"}]]]
|
||||
resize_pblock [get_pblocks {CLKAG_pll_clk.u_clk_pll/inst/sys_clk}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
|
||||
#endgroup
|
||||
|
||||
# Clock net "pll_clk.u_clk_pll/inst/cpu_clk" driven by instance "pll_clk.u_clk_pll/inst/clkout1_buf" located at site "BUFGCTRL_X0Y17"
|
||||
#startgroup
|
||||
create_pblock {CLKAG_pll_clk.u_clk_pll/inst/cpu_clk}
|
||||
add_cells_to_pblock [get_pblocks {CLKAG_pll_clk.u_clk_pll/inst/cpu_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="pll_clk.u_clk_pll/inst/cpu_clk"}]]]
|
||||
resize_pblock [get_pblocks {CLKAG_pll_clk.u_clk_pll/inst/cpu_clk}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
|
||||
#endgroup
|
||||
@@ -1,248 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:46:12 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_drc -file ./vivado_reports_impl/routed_drc.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200tfbg676-1
|
||||
| Speed File : -1
|
||||
| Design State : Fully Routed
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
Report DRC
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: impl_1
|
||||
Design limits: <entire design considered>
|
||||
Ruledeck: default
|
||||
Max violations: <unlimited>
|
||||
Violations found: 42
|
||||
+-----------+----------+----------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+-----------+----------+----------------------------+------------+
|
||||
| CHECK-3 | Warning | Report rule limit reached | 2 |
|
||||
| REQP-1839 | Warning | RAMB36 async control check | 20 |
|
||||
| REQP-1840 | Warning | RAMB18 async control check | 20 |
|
||||
+-----------+----------+----------------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
CHECK-3#1 Warning
|
||||
Report rule limit reached
|
||||
REQP-1839 rule limit reached: 20 violations have been found.
|
||||
Related violations: <none>
|
||||
|
||||
CHECK-3#2 Warning
|
||||
Report rule limit reached
|
||||
REQP-1840 rule limit reached: 20 violations have been found.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#1 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#2 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#3 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#4 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#5 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#6 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#7 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#8 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#9 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#10 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#11 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#12 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#13 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#14 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#15 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#16 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#17 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#18 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#19 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#20 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#1 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#2 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#3 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#4 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#5 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#6 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#7 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#8 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#9 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#10 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#11 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#12 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#13 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#14 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#15 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#16 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#17 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENARDEN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_1__15_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#18 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENBWREN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_2__13_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#19 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[2] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#20 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[3] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
@@ -1,718 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:46:27 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_io -file ./vivado_reports_impl/routed_io.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200t
|
||||
| Speed File : -1
|
||||
| Package : fbg676
|
||||
| Package Version : FINAL 2012-06-20
|
||||
| Package Pin Delay Version : FINAL VERS. 2.0 2012-06-20
|
||||
-------------------------------------------------------------------------------------------------
|
||||
|
||||
IO Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
2. IO Assignments by Package Pin
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+---------------+
|
||||
| Total User IO |
|
||||
+---------------+
|
||||
| 202 |
|
||||
+---------------+
|
||||
|
||||
|
||||
2. IO Assignments by Package Pin
|
||||
--------------------------------
|
||||
|
||||
+------------+-------------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
|
||||
+------------+-------------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
| A1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
|
||||
| A2 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A3 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A4 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A5 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A7 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| A8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A9 | | | MGTPTXN2_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| A10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A11 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A13 | | | MGTPRXN2_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| A14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A15 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| A16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A17 | dpy1[0] | High Range | IO_L9P_T1_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| A18 | leds[11] | High Range | IO_L9N_T1_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| A19 | dpy0[3] | High Range | IO_L10N_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| A20 | leds[14] | High Range | IO_L15N_T2_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| A21 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
|
||||
| A22 | leds[13] | High Range | IO_L17N_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| A23 | leds[9] | High Range | IO_L21P_T3_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| A24 | leds[2] | High Range | IO_L21N_T3_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| A25 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA1 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
|
||||
| AA2 | | High Range | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA3 | | High Range | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA4 | | High Range | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA5 | | High Range | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA7 | | High Range | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA8 | | High Range | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA10 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AA11 | | | MGTREFCLK1P_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AA12 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AA13 | | | MGTREFCLK0P_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AA14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA15 | ext_ram_data[23] | High Range | IO_L23N_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA17 | ext_ram_addr[8] | High Range | IO_L19P_T3_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA18 | ext_ram_addr[7] | High Range | IO_L17N_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA19 | ext_ram_data[30] | High Range | IO_L13P_T2_MRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA20 | | High Range | IO_L12P_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AA21 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
|
||||
| AA22 | base_ram_addr[14] | High Range | IO_L8P_T1_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA23 | base_ram_addr[11] | High Range | IO_L8N_T1_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA24 | base_ram_data[8] | High Range | IO_L7P_T1_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA25 | ext_ram_addr[10] | High Range | IO_L5N_T0_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB1 | | High Range | IO_L7P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AB2 | | High Range | IO_L11P_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AB3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB4 | | High Range | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AB5 | | High Range | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AB6 | | High Range | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AB7 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| AB8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB11 | | | MGTREFCLK1N_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AB12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB13 | | | MGTREFCLK0N_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AB14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB15 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | | | |
|
||||
| AB16 | ext_ram_data[16] | High Range | IO_L22P_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AB17 | ext_ram_data[18] | High Range | IO_L19N_T3_VREF_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AB18 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
|
||||
| AB19 | ext_ram_oe_n | High Range | IO_L13N_T2_MRCC_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AB20 | | High Range | IO_L12N_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AB21 | ext_ram_data[27] | High Range | IO_L11P_T1_SRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AB22 | ext_ram_be_n[3] | High Range | IO_0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AB23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB24 | base_ram_addr[10] | High Range | IO_L9P_T1_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AB25 | ext_ram_addr[12] | High Range | IO_L7N_T1_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AB26 | ext_ram_addr[11] | High Range | IO_L3P_T0_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC1 | | High Range | IO_L7N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AC2 | | High Range | IO_L11N_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AC3 | | High Range | IO_L14P_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AC4 | | High Range | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AC5 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
|
||||
| AC6 | | High Range | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AC7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AC8 | | | MGTPTXP2_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AC9 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AC10 | | | MGTPTXP0_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AC11 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AC12 | | | MGTPRXP0_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AC13 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AC14 | | | MGTPRXP2_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AC15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AC16 | ext_ram_data[21] | High Range | IO_L22N_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC17 | ext_ram_data[25] | High Range | IO_L20P_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC18 | ext_ram_data[19] | High Range | IO_L15P_T2_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC19 | ext_ram_data[17] | High Range | IO_L14P_T2_SRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AC21 | ext_ram_data[29] | High Range | IO_L11N_T1_SRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC22 | ext_ram_addr[5] | High Range | IO_L2P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC23 | ext_ram_data[31] | High Range | IO_L2N_T0_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC24 | ext_ram_addr[14] | High Range | IO_L9N_T1_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC25 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
|
||||
| AC26 | ext_ram_addr[13] | High Range | IO_L3N_T0_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD1 | | High Range | IO_L9P_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AD2 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
|
||||
| AD3 | | High Range | IO_L14N_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AD4 | | High Range | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AD5 | | High Range | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AD6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AD7 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AD8 | | | MGTPTXN2_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AD9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AD10 | | | MGTPTXN0_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AD11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AD12 | | | MGTPRXN0_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AD13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AD14 | | | MGTPRXN2_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AD15 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AD16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AD17 | ext_ram_data[24] | High Range | IO_L20N_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD18 | ext_ram_data[20] | High Range | IO_L15N_T2_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD19 | ext_ram_we_n | High Range | IO_L14N_T2_SRCC_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD20 | ext_ram_data[26] | High Range | IO_L10P_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD21 | ext_ram_data[28] | High Range | IO_L7P_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD22 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
|
||||
| AD23 | ext_ram_ce_n | High Range | IO_L6P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD24 | ext_ram_be_n[2] | High Range | IO_L6N_T0_VREF_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD25 | ext_ram_addr[3] | High Range | IO_L4P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD26 | ext_ram_addr[4] | High Range | IO_L4N_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE1 | | High Range | IO_L9N_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AE2 | | High Range | IO_L10P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AE3 | | High Range | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AE4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AE5 | | High Range | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AE6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AE7 | | | MGTPTXP3_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AE8 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AE9 | | | MGTPTXP1_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AE10 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AE11 | | | MGTPRXP3_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AE12 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AE13 | | | MGTPRXP1_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AE14 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AE15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AE16 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| AE17 | ext_ram_addr[16] | High Range | IO_L18P_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE18 | ext_ram_addr[18] | High Range | IO_L16P_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE19 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
|
||||
| AE20 | ext_ram_data[6] | High Range | IO_L10N_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE21 | ext_ram_data[5] | High Range | IO_L7N_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE22 | ext_ram_data[3] | High Range | IO_L9P_T1_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE23 | ext_ram_data[1] | High Range | IO_L5P_T0_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AE25 | ext_ram_addr[1] | High Range | IO_L1P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE26 | ext_ram_addr[2] | High Range | IO_L1N_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF2 | | High Range | IO_L10N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AF3 | | High Range | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AF4 | | High Range | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AF5 | | High Range | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AF6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF7 | | | MGTPTXN3_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AF8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF9 | | | MGTPTXN1_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AF10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF11 | | | MGTPRXN3_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AF12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF13 | | | MGTPRXN1_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AF14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF15 | | | MGTRREF_213 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AF16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF17 | ext_ram_addr[15] | High Range | IO_L18N_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF18 | ext_ram_addr[17] | High Range | IO_L16N_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF19 | ext_ram_addr[19] | High Range | IO_L8P_T1_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF20 | ext_ram_data[7] | High Range | IO_L8N_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF22 | ext_ram_data[4] | High Range | IO_L9N_T1_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF23 | ext_ram_data[2] | High Range | IO_L5N_T0_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF24 | ext_ram_data[0] | High Range | IO_L3P_T0_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF25 | ext_ram_addr[0] | High Range | IO_L3N_T0_DQS_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF26 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
|
||||
| B1 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B2 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B4 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B5 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B7 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| B8 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| B9 | | | MGTPTXP2_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| B10 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| B11 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| B12 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| B13 | | | MGTPRXP2_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| B14 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B17 | dpy0[6] | High Range | IO_L7N_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| B18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
|
||||
| B19 | dpy0[0] | High Range | IO_L10P_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| B20 | leds[15] | High Range | IO_L15P_T2_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| B21 | dpy0[2] | High Range | IO_L16N_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| B22 | leds[7] | High Range | IO_L17P_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| B23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B24 | leds[0] | High Range | IO_L23N_T3_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| B25 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| B26 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C1 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C2 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C3 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C4 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
|
||||
| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C7 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| C8 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| C9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C10 | | | MGTPTXN3_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| C11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C12 | | | MGTPRXN3_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| C13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C14 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| C15 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C17 | dpy0[7] | High Range | IO_L7P_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| C18 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C19 | dpy0[5] | High Range | IO_L13N_T2_MRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| C20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C21 | leds[5] | High Range | IO_L16P_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| C22 | leds[4] | High Range | IO_L19P_T3_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| C23 | leds[8] | High Range | IO_L19N_T3_VREF_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| C24 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C25 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
|
||||
| C26 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
|
||||
| D3 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D4 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D5 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D6 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D8 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| D9 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| D10 | | | MGTPTXP3_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| D11 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| D12 | | | MGTPRXP3_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| D13 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| D14 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| D15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D16 | dpy1[1] | High Range | IO_L8N_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| D17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D18 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D19 | dpy0[1] | High Range | IO_L13P_T2_MRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| D20 | leds[12] | High Range | IO_L14N_T2_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| D21 | leds[10] | High Range | IO_L18N_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| D22 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
|
||||
| D23 | leds[3] | High Range | IO_L24P_T3_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| D24 | | High Range | IO_L24N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D25 | video_blue[1] | High Range | IO_L20N_T3_A19_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| D26 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| E1 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E3 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E5 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E11 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| E12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E13 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E16 | dpy1[4] | High Range | IO_L8P_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| E17 | dpy1[2] | High Range | IO_L11P_T1_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| E18 | dpy0[4] | High Range | IO_L11N_T1_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| E19 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
|
||||
| E20 | leds[6] | High Range | IO_L14P_T2_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| E21 | leds[1] | High Range | IO_L18P_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| E22 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| E23 | video_green[1] | High Range | IO_L17N_T2_A25_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| E24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E25 | video_blue[0] | High Range | IO_L20P_T3_A20_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| E26 | video_red[2] | High Range | IO_L21P_T3_DQS_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| F1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F2 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F3 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F5 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
|
||||
| F7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F10 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| F11 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| F12 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| F13 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| F14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F15 | dpy1[6] | High Range | IO_L4N_T0_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| F16 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
|
||||
| F17 | dpy1[3] | High Range | IO_L2N_T0_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| F18 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F19 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F20 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F22 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| F23 | video_green[2] | High Range | IO_L17P_T2_A26_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| F24 | video_red[1] | High Range | IO_L19N_T3_A21_VREF_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| F25 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| F26 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
|
||||
| G1 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G2 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
|
||||
| G4 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G5 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G6 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G7 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G8 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G9 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G14 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| G15 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| G16 | dpy1[5] | High Range | IO_L6N_T0_VREF_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| G17 | dpy1[7] | High Range | IO_L2P_T0_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| G18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G19 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| G20 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G21 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G22 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G23 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
|
||||
| G24 | video_de | High Range | IO_L19P_T3_A22_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| G25 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G26 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H1 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| H2 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| H3 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H4 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H7 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H8 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H9 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H10 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| H11 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| H12 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| H13 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| H14 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| H15 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| H16 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| H17 | | High Range | IO_0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| H18 | UART_TX | High Range | IO_L10N_T1_AD11N_15 | BIDIR | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| H19 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
|
||||
| H21 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H22 | video_clk | High Range | IO_L13N_T2_MRCC_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| H23 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H24 | video_vsync | High Range | IO_L16N_T2_A27_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| H25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H26 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J1 | dip_sw[14] | High Range | IO_L7N_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J3 | dip_sw[1] | High Range | IO_L1N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| J4 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J5 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J6 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
|
||||
| J8 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| J10 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| J14 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J15 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J16 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
|
||||
| J18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J19 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J20 | UART_RX | High Range | IO_L9N_T1_DQS_AD3N_15 | BIDIR | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| J21 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J23 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J24 | video_hsync | High Range | IO_L16P_T2_A28_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| J25 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J26 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K1 | dip_sw[17] | High Range | IO_L7P_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| K2 | dip_sw[16] | High Range | IO_L8N_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| K3 | dip_sw[13] | High Range | IO_L1P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| K5 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| K6 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K7 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K8 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
|
||||
| K15 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K16 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K17 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K18 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K20 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K21 | clk | High Range | IO_L12P_T1_MRCC_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| K22 | video_green[0] | High Range | IO_L18P_T2_A24_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| K23 | video_red[0] | High Range | IO_L18N_T2_A23_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| K24 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
|
||||
| K25 | base_ram_be_n[3] | High Range | IO_L7P_T1_D09_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| K26 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| L1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| L2 | dip_sw[15] | High Range | IO_L11N_T1_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| L3 | dip_sw[6] | High Range | IO_L8P_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| L4 | dip_sw[19] | High Range | IO_L3N_T0_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| L5 | dip_sw[5] | High Range | IO_L4P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| L6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L7 | dip_sw[11] | High Range | IO_L2N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| L8 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| L9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| L14 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L15 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L17 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L18 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L19 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L20 | base_ram_be_n[0] | High Range | IO_L8N_T1_D12_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| L21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
|
||||
| L22 | base_ram_be_n[1] | High Range | IO_L11P_T1_SRCC_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| L23 | base_ram_be_n[2] | High Range | IO_L11N_T1_SRCC_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| L24 | base_ram_data[0] | High Range | IO_L9P_T1_DQS_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| L25 | base_ram_data[1] | High Range | IO_L9N_T1_DQS_D13_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| L26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M1 | touch_btn[1] | High Range | IO_L9N_T1_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| M2 | dip_sw[2] | High Range | IO_L11P_T1_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| M3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M4 | dip_sw[20] | High Range | IO_L3P_T0_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| M5 | dip_sw[12] | High Range | IO_L6N_T0_VREF_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| M6 | dip_sw[8] | High Range | IO_L6P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| M7 | dip_sw[10] | High Range | IO_L2P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| M8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| M11 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| M12 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M14 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| M15 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| M16 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| M17 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| M18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
|
||||
| M19 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| M20 | base_ram_data[21] | High Range | IO_L8P_T1_D11_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| M21 | base_ram_data[17] | High Range | IO_L12P_T1_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| M22 | base_ram_data[31] | High Range | IO_L12N_T1_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| M23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M24 | base_ram_data[30] | High Range | IO_L10P_T1_D14_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| M25 | base_ram_data[3] | High Range | IO_L10N_T1_D15_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| M26 | base_ram_data[2] | High Range | IO_L20N_T3_A07_D23_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| N1 | dip_sw[23] | High Range | IO_L9P_T1_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| N2 | dip_sw[21] | High Range | IO_L12N_T1_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| N3 | dip_sw[18] | High Range | IO_L12P_T1_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| N4 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| N5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| N6 | dip_sw[7] | High Range | IO_L5N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| N7 | dip_sw[9] | High Range | IO_L5P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| N8 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| N9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N11 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| N12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| N13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| N14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| N15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
|
||||
| N16 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| N17 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| N18 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| N19 | base_ram_data[20] | High Range | IO_L16N_T2_A15_D31_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| N20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N21 | base_ram_data[23] | High Range | IO_L13P_T2_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| N22 | base_ram_data[28] | High Range | IO_L13N_T2_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| N23 | base_ram_data[29] | High Range | IO_L15P_T2_DQS_RDWR_B_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| N24 | base_ram_data[22] | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| N25 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
|
||||
| N26 | base_ram_data[4] | High Range | IO_L20P_T3_A08_D24_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P1 | dip_sw[3] | High Range | IO_L15N_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| P2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| P3 | touch_btn[2] | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| P4 | dip_sw[4] | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| P5 | dip_sw[24] | High Range | IO_L19N_T3_VREF_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| P6 | dip_sw[22] | High Range | IO_L19P_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P8 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| P11 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| P12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| P15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| P16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P18 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| P19 | base_ram_data[19] | High Range | IO_L16P_T2_CSI_B_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P20 | base_ram_data[27] | High Range | IO_L14P_T2_SRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P21 | base_ram_data[16] | High Range | IO_L14N_T2_SRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
|
||||
| P23 | base_ram_data[18] | High Range | IO_L17P_T2_A14_D30_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P24 | base_ram_data[5] | High Range | IO_L17N_T2_A13_D29_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P25 | base_ram_data[7] | High Range | IO_L19N_T3_A09_D25_VREF_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P26 | base_ram_data[6] | High Range | IO_L22N_T3_A04_D20_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| R1 | dip_sw[27] | High Range | IO_L15P_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| R2 | dip_sw[31] | High Range | IO_L17N_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| R3 | dip_sw[25] | High Range | IO_L13P_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R5 | dip_sw[28] | High Range | IO_L20N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| R6 | dip_sw[30] | High Range | IO_L23N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R8 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
|
||||
| R12 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
|
||||
| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| R14 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R15 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R16 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R17 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R18 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
|
||||
| R20 | base_ram_addr[5] | High Range | IO_L18P_T2_A12_D28_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| R21 | base_ram_data[26] | High Range | IO_L18N_T2_A11_D27_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| R22 | base_ram_data[25] | High Range | IO_L23N_T3_A02_D18_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| R23 | base_ram_addr[6] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| R24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R25 | ext_ram_be_n[1] | High Range | IO_L19P_T3_A10_D26_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| R26 | ext_ram_be_n[0] | High Range | IO_L22P_T3_A05_D21_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| T1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T2 | touch_btn[0] | High Range | IO_L17P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| T3 | dip_sw[0] | High Range | IO_L16N_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| T4 | dip_sw[26] | High Range | IO_L16P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| T5 | dip_sw[29] | High Range | IO_L20P_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| T6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| T7 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| T13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T14 | | High Range | IO_L20P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| T15 | | High Range | IO_L20N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| T16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
|
||||
| T17 | | High Range | IO_L21P_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| T18 | base_ram_addr[2] | High Range | IO_L21N_T3_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| T19 | base_ram_addr[0] | High Range | IO_L17P_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| T20 | base_ram_oe_n | High Range | IO_L15P_T2_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| T21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T22 | base_ram_data[24] | High Range | IO_L23P_T3_A03_D19_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| T23 | base_ram_addr[7] | High Range | IO_L24P_T3_A01_D17_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| T24 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| T25 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| T26 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
|
||||
| U1 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U2 | touch_btn[3] | High Range | IO_L18P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| U3 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
|
||||
| U4 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U5 | reset | High Range | IO_L21N_T3_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| U6 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U7 | | High Range | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| U8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| U12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| U14 | | High Range | IO_L23P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| U15 | | High Range | IO_L22P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| U16 | | High Range | IO_L22N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| U17 | base_ram_addr[4] | High Range | IO_25_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| U18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U19 | base_ram_ce_n | High Range | IO_L17N_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| U20 | base_ram_we_n | High Range | IO_L15N_T2_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| U21 | base_ram_data[15] | High Range | IO_L13P_T2_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| U22 | base_ram_addr[8] | High Range | IO_L12P_T1_MRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| U23 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
|
||||
| U24 | ext_ram_data[15] | High Range | IO_0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| U25 | ext_ram_data[13] | High Range | IO_L1P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| U26 | ext_ram_data[14] | High Range | IO_L1N_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V1 | | High Range | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V2 | | High Range | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V3 | | High Range | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V4 | | High Range | IO_0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V6 | | High Range | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V7 | | High Range | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V8 | | High Range | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V9 | | High Range | IO_25_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| V11 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| V12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V14 | | High Range | IO_L23N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| V15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V16 | | High Range | IO_L24P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| V17 | base_ram_addr[3] | High Range | IO_L24N_T3_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V18 | base_ram_addr[1] | High Range | IO_L19P_T3_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V19 | base_ram_addr[19] | High Range | IO_L18P_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V20 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
|
||||
| V21 | base_ram_data[10] | High Range | IO_L13N_T2_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V22 | base_ram_data[13] | High Range | IO_L12N_T1_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V23 | base_ram_data[14] | High Range | IO_L10P_T1_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V24 | ext_ram_data[11] | High Range | IO_L6P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V26 | ext_ram_data[12] | High Range | IO_L2P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W1 | | High Range | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| W2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| W3 | | High Range | IO_L5P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| W4 | | High Range | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| W5 | | High Range | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| W6 | | High Range | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| W7 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
|
||||
| W8 | | High Range | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| W9 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| W10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| W11 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | |
|
||||
| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| W13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| W14 | | High Range | IO_L24P_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| W15 | | High Range | IO_L24N_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| W16 | | High Range | IO_25_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| W17 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
|
||||
| W18 | base_ram_addr[18] | High Range | IO_L19N_T3_VREF_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W19 | base_ram_addr[15] | High Range | IO_L18N_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W20 | base_ram_addr[17] | High Range | IO_L16P_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W21 | base_ram_addr[16] | High Range | IO_L14P_T2_SRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| W23 | base_ram_data[12] | High Range | IO_L10N_T1_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W24 | base_ram_data[11] | High Range | IO_L6N_T0_VREF_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W25 | ext_ram_data[9] | High Range | IO_L4P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W26 | ext_ram_data[10] | High Range | IO_L2N_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y1 | | High Range | IO_L8N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y2 | | High Range | IO_L8P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y3 | | High Range | IO_L5N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y4 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
|
||||
| Y5 | | High Range | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y6 | | High Range | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y7 | | High Range | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y8 | | High Range | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y9 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| Y10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y14 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | |
|
||||
| Y15 | ext_ram_data[22] | High Range | IO_L23P_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y16 | | High Range | IO_L21P_T3_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| Y17 | ext_ram_addr[6] | High Range | IO_L21N_T3_DQS_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y18 | | High Range | IO_L17P_T2_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| Y19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y20 | base_ram_addr[13] | High Range | IO_L16N_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y21 | base_ram_addr[12] | High Range | IO_L14N_T2_SRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y22 | base_ram_addr[9] | High Range | IO_L11P_T1_SRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y23 | base_ram_data[9] | High Range | IO_L11N_T1_SRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y24 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
|
||||
| Y25 | ext_ram_addr[9] | High Range | IO_L5P_T0_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y26 | ext_ram_data[8] | High Range | IO_L4N_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
+------------+-------------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
* Default value
|
||||
** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,190 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:46:05 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_power -file ./vivado_reports_impl/routed_power.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200tfbg676-1
|
||||
| Design State : routed
|
||||
| Grade : commercial
|
||||
| Process : typical
|
||||
| Characterization : Production
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
Power Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
1.1 On-Chip Components
|
||||
1.2 Power Supply Summary
|
||||
1.3 Confidence Level
|
||||
2. Settings
|
||||
2.1 Environment
|
||||
2.2 Clock Constraints
|
||||
3. Detailed Reports
|
||||
3.1 By Hierarchy
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+--------------------------+--------------+
|
||||
| Total On-Chip Power (W) | 0.918 |
|
||||
| Design Power Budget (W) | Unspecified* |
|
||||
| Power Budget Margin (W) | NA |
|
||||
| Dynamic (W) | 0.777 |
|
||||
| Device Static (W) | 0.142 |
|
||||
| Effective TJA (C/W) | 1.9 |
|
||||
| Max Ambient (C) | 83.3 |
|
||||
| Junction Temperature (C) | 26.7 |
|
||||
| Confidence Level | Low |
|
||||
| Setting File | --- |
|
||||
| Simulation Activity File | --- |
|
||||
| Design Nets Matched | NA |
|
||||
+--------------------------+--------------+
|
||||
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
|
||||
|
||||
|
||||
1.1 On-Chip Components
|
||||
----------------------
|
||||
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
| On-Chip | Power (W) | Used | Available | Utilization (%) |
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
| Clocks | 0.028 | 6 | --- | --- |
|
||||
| Slice Logic | 0.200 | 137329 | --- | --- |
|
||||
| LUT as Logic | 0.193 | 79570 | 133800 | 59.47 |
|
||||
| CARRY4 | 0.003 | 3590 | 33450 | 10.73 |
|
||||
| Register | 0.002 | 38619 | 267600 | 14.43 |
|
||||
| LUT as Distributed RAM | 0.001 | 628 | 46200 | 1.36 |
|
||||
| LUT as Shift Register | <0.001 | 1094 | 46200 | 2.37 |
|
||||
| F7/F8 Muxes | <0.001 | 5664 | 133800 | 4.23 |
|
||||
| BUFG | <0.001 | 2 | 32 | 6.25 |
|
||||
| Others | 0.000 | 302 | --- | --- |
|
||||
| Signals | 0.368 | 99001 | --- | --- |
|
||||
| Block RAM | 0.016 | 25.5 | 365 | 6.99 |
|
||||
| PLL | 0.137 | 1 | 10 | 10.00 |
|
||||
| I/O | 0.028 | 202 | 400 | 50.50 |
|
||||
| Static Power | 0.142 | | | |
|
||||
| Total | 0.918 | | | |
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
|
||||
|
||||
1.2 Power Supply Summary
|
||||
------------------------
|
||||
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Vccint | 1.000 | 0.657 | 0.624 | 0.033 |
|
||||
| Vccaux | 1.800 | 0.101 | 0.070 | 0.031 |
|
||||
| Vcco33 | 3.300 | 0.013 | 0.008 | 0.005 |
|
||||
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccbram | 1.000 | 0.002 | 0.001 | 0.001 |
|
||||
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
|
||||
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
|
||||
|
||||
1.3 Confidence Level
|
||||
--------------------
|
||||
|
||||
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
|
||||
| User Input Data | Confidence | Details | Action |
|
||||
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
|
||||
| Design implementation state | High | Design is routed | |
|
||||
| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
|
||||
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
|
||||
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
|
||||
| Device models | High | Device models are Production | |
|
||||
| | | | |
|
||||
| Overall confidence level | Low | | |
|
||||
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
2. Settings
|
||||
-----------
|
||||
|
||||
2.1 Environment
|
||||
---------------
|
||||
|
||||
+-----------------------+--------------------------+
|
||||
| Ambient Temp (C) | 25.0 |
|
||||
| ThetaJA (C/W) | 1.9 |
|
||||
| Airflow (LFM) | 250 |
|
||||
| Heat Sink | medium (Medium Profile) |
|
||||
| ThetaSA (C/W) | 3.4 |
|
||||
| Board Selection | medium (10"x10") |
|
||||
| # of Board Layers | 12to15 (12 to 15 Layers) |
|
||||
| Board Temperature (C) | 25.0 |
|
||||
+-----------------------+--------------------------+
|
||||
|
||||
|
||||
2.2 Clock Constraints
|
||||
---------------------
|
||||
|
||||
+------------------+-----------------------------------------+-----------------+
|
||||
| Clock | Domain | Constraint (ns) |
|
||||
+------------------+-----------------------------------------+-----------------+
|
||||
| clk | clk | 20.0 |
|
||||
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
|
||||
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 |
|
||||
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
|
||||
+------------------+-----------------------------------------+-----------------+
|
||||
|
||||
|
||||
3. Detailed Reports
|
||||
-------------------
|
||||
|
||||
3.1 By Hierarchy
|
||||
----------------
|
||||
|
||||
+------------------------------+-----------+
|
||||
| Name | Power (W) |
|
||||
+------------------------------+-----------+
|
||||
| soc_top | 0.777 |
|
||||
| pll_clk.u_clk_pll | 0.138 |
|
||||
| inst | 0.138 |
|
||||
| u_Axi_CDC | 0.003 |
|
||||
| u_axi_axil_adapter | 0.002 |
|
||||
| axi_axil_adapter_wr_inst | 0.001 |
|
||||
| u_axi_uart_controller | 0.002 |
|
||||
| uart0 | 0.001 |
|
||||
| regs | 0.001 |
|
||||
| u_cdma_matmul_bridge | 0.001 |
|
||||
| u_confreg | 0.001 |
|
||||
| u_cpu | 0.027 |
|
||||
| addr_trans | 0.002 |
|
||||
| tlb_entry | 0.002 |
|
||||
| btb | 0.003 |
|
||||
| dcache | 0.004 |
|
||||
| icache | 0.005 |
|
||||
| u_csr | 0.001 |
|
||||
| u_mul | 0.007 |
|
||||
| wb_stage | 0.001 |
|
||||
| u_fft_mlkem_axi_slave | 0.467 |
|
||||
| u_fft_controller | 0.027 |
|
||||
| u_FFT | 0.024 |
|
||||
| u_out0 | 0.001 |
|
||||
| u_out1 | 0.001 |
|
||||
| u_mlkem_axi_slave | 0.436 |
|
||||
| u_mlkem | 0.411 |
|
||||
| u_prng_axi_slave | 0.004 |
|
||||
| u_matmul_axi_slave | 0.081 |
|
||||
| mult_inst[0].u_mult | 0.003 |
|
||||
| mult_inst[1].u_mult | 0.003 |
|
||||
| mult_inst[2].u_mult | 0.003 |
|
||||
| mult_inst[3].u_mult | 0.003 |
|
||||
| u_snix_axil_cdma_mux_8ch | 0.011 |
|
||||
| u_core_engine | 0.006 |
|
||||
| axis_fifo_u0 | 0.005 |
|
||||
+------------------------------+-----------+
|
||||
|
||||
|
||||
@@ -1,12 +0,0 @@
|
||||
Design Route Status
|
||||
: # nets :
|
||||
------------------------------------------- : ----------- :
|
||||
# of logical nets.......................... : 148231 :
|
||||
# of nets not needing routing.......... : 49221 :
|
||||
# of internally routed nets........ : 48840 :
|
||||
# of nets with no loads............ : 381 :
|
||||
# of routable nets..................... : 99010 :
|
||||
# of fully routed nets............. : 99010 :
|
||||
# of nets with routing errors.......... : 0 :
|
||||
------------------------------------------- : ----------- :
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,235 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:45:45 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_utilization -file ./vivado_reports_impl/routed_utilization.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200tfbg676-1
|
||||
| Design State : Routed
|
||||
---------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Slice Logic Distribution
|
||||
3. Memory
|
||||
4. DSP
|
||||
5. IO and GT Specific
|
||||
6. Clocking
|
||||
7. Specific Feature
|
||||
8. Primitives
|
||||
9. Black Boxes
|
||||
10. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
| Slice LUTs | 74191 | 0 | 133800 | 55.45 |
|
||||
| LUT as Logic | 72517 | 0 | 133800 | 54.20 |
|
||||
| LUT as Memory | 1674 | 0 | 46200 | 3.62 |
|
||||
| LUT as Distributed RAM | 628 | 0 | | |
|
||||
| LUT as Shift Register | 1046 | 0 | | |
|
||||
| Slice Registers | 38619 | 0 | 267600 | 14.43 |
|
||||
| Register as Flip Flop | 38619 | 0 | 267600 | 14.43 |
|
||||
| Register as Latch | 0 | 0 | 267600 | 0.00 |
|
||||
| F7 Muxes | 4261 | 0 | 66900 | 6.37 |
|
||||
| F8 Muxes | 1403 | 0 | 33450 | 4.19 |
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 101 | Yes | - | Set |
|
||||
| 25523 | Yes | - | Reset |
|
||||
| 134 | Yes | Set | - |
|
||||
| 12861 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Slice Logic Distribution
|
||||
---------------------------
|
||||
|
||||
+--------------------------------------------+-------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+--------------------------------------------+-------+-------+-----------+-------+
|
||||
| Slice | 21994 | 0 | 33450 | 65.75 |
|
||||
| SLICEL | 14311 | 0 | | |
|
||||
| SLICEM | 7683 | 0 | | |
|
||||
| LUT as Logic | 72517 | 0 | 133800 | 54.20 |
|
||||
| using O5 output only | 4 | | | |
|
||||
| using O6 output only | 58168 | | | |
|
||||
| using O5 and O6 | 14345 | | | |
|
||||
| LUT as Memory | 1674 | 0 | 46200 | 3.62 |
|
||||
| LUT as Distributed RAM | 628 | 0 | | |
|
||||
| using O5 output only | 0 | | | |
|
||||
| using O6 output only | 60 | | | |
|
||||
| using O5 and O6 | 568 | | | |
|
||||
| LUT as Shift Register | 1046 | 0 | | |
|
||||
| using O5 output only | 2 | | | |
|
||||
| using O6 output only | 996 | | | |
|
||||
| using O5 and O6 | 48 | | | |
|
||||
| Slice Registers | 38619 | 0 | 267600 | 14.43 |
|
||||
| Register driven from within the Slice | 24282 | | | |
|
||||
| Register driven from outside the Slice | 14337 | | | |
|
||||
| LUT in front of the register is unused | 5492 | | | |
|
||||
| LUT in front of the register is used | 8845 | | | |
|
||||
| Unique Control Sets | 1413 | | 33450 | 4.22 |
|
||||
+--------------------------------------------+-------+-------+-----------+-------+
|
||||
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
|
||||
|
||||
|
||||
3. Memory
|
||||
---------
|
||||
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 25.5 | 0 | 365 | 6.99 |
|
||||
| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 |
|
||||
| RAMB36E1 only | 10 | | | |
|
||||
| RAMB18 | 31 | 0 | 730 | 4.25 |
|
||||
| RAMB18E1 only | 31 | | | |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
4. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 740 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 202 | 202 | 400 | 50.50 |
|
||||
| IOB Master Pads | 97 | | | |
|
||||
| IOB Slave Pads | 102 | | | |
|
||||
| Bonded IPADs | 0 | 0 | 26 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 16 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 10 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 384 | 0.00 |
|
||||
| GTPE2_CHANNEL | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 400 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 400 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 5 | 0 | 32 | 15.63 |
|
||||
| BUFIO | 0 | 0 | 40 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| PLLE2_ADV | 1 | 0 | 10 | 10.00 |
|
||||
| BUFMRCE | 0 | 0 | 20 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 120 | 0.00 |
|
||||
| BUFR | 0 | 0 | 40 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
8. Primitives
|
||||
-------------
|
||||
|
||||
+-----------+-------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+-----------+-------+---------------------+
|
||||
| LUT6 | 35769 | LUT |
|
||||
| FDCE | 25523 | Flop & Latch |
|
||||
| LUT5 | 15462 | LUT |
|
||||
| LUT3 | 13062 | LUT |
|
||||
| FDRE | 12861 | Flop & Latch |
|
||||
| LUT4 | 12795 | LUT |
|
||||
| LUT2 | 9006 | LUT |
|
||||
| MUXF7 | 4261 | MuxFx |
|
||||
| CARRY4 | 3590 | CarryLogic |
|
||||
| MUXF8 | 1403 | MuxFx |
|
||||
| SRLC32E | 992 | Distributed Memory |
|
||||
| RAMD32 | 892 | Distributed Memory |
|
||||
| LUT1 | 768 | LUT |
|
||||
| RAMS32 | 272 | Distributed Memory |
|
||||
| FDSE | 134 | Flop & Latch |
|
||||
| IBUF | 104 | IO |
|
||||
| SRL16E | 102 | Distributed Memory |
|
||||
| FDPE | 101 | Flop & Latch |
|
||||
| OBUF | 98 | IO |
|
||||
| OBUFT | 66 | IO |
|
||||
| RAMD64E | 32 | Distributed Memory |
|
||||
| RAMB18E1 | 31 | Block Memory |
|
||||
| RAMB36E1 | 10 | Block Memory |
|
||||
| BUFG | 5 | Clock |
|
||||
| PLLE2_ADV | 1 | Clock |
|
||||
+-----------+-------+---------------------+
|
||||
|
||||
|
||||
9. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
10. Instantiated Netlists
|
||||
-------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
| clk_pll | 1 |
|
||||
+----------+------+
|
||||
|
||||
|
||||
@@ -1,256 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Sun Jul 5 23:45:46 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_utilization -hierarchical -hierarchical_depth 10 -file ./vivado_reports_impl/routed_utilization_hier.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200tfbg676-1
|
||||
| Design State : Routed
|
||||
---------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Utilization by Hierarchy
|
||||
|
||||
1. Utilization by Hierarchy
|
||||
---------------------------
|
||||
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks |
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
| soc_top | (top) | 74191 | 72517 | 628 | 1046 | 38619 | 10 | 31 | 0 |
|
||||
| (soc_top) | (top) | 2094 | 2038 | 56 | 0 | 4 | 0 | 0 | 0 |
|
||||
| pll_clk.u_clk_pll | clk_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| inst | clk_pll_clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_sys | rst_sync_0 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 518 | 518 | 0 | 0 | 151 | 0 | 0 | 0 |
|
||||
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 8 | 8 | 0 | 0 | 24 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_67 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_50 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_66 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_51 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_65 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_52 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_64 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 31 | 31 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_61 | 25 | 25 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_62 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_63 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_58 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_59 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_60 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_55 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_56 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_57 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 60 | 60 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7 | 48 | 48 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 89 | 89 | 0 | 0 | 25 | 0 | 0 | 0 |
|
||||
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 73 | 73 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4ReadOnlyErrorSlave_1_54 | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 |
|
||||
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4WriteOnlyErrorSlave_1_53 | 20 | 20 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 181 | 181 | 0 | 0 | 17 | 0 | 0 | 0 |
|
||||
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 165 | 165 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4ReadOnlyErrorSlave_1 | 16 | 16 | 0 | 0 | 9 | 0 | 0 | 0 |
|
||||
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 26 | 26 | 0 | 0 | 14 | 0 | 0 | 0 |
|
||||
| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 19 | 19 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 7 | 7 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| u_Axi_CDC | Axi_CDC | 495 | 367 | 128 | 0 | 309 | 0 | 0 | 0 |
|
||||
| arFifo | StreamFifoCC_3 | 257 | 221 | 36 | 0 | 73 | 0 | 0 | 0 |
|
||||
| (arFifo) | StreamFifoCC_3 | 251 | 215 | 36 | 0 | 61 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9_48 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11_49 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| awFifo | StreamFifoCC | 111 | 75 | 36 | 0 | 75 | 0 | 0 | 0 |
|
||||
| (awFifo) | StreamFifoCC | 104 | 68 | 36 | 0 | 61 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| bFifo | StreamFifoCC_2 | 14 | 14 | 0 | 0 | 26 | 0 | 0 | 0 |
|
||||
| (bFifo) | StreamFifoCC_2 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_4 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_6 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| rFifo | StreamFifoCC_4 | 45 | 17 | 28 | 0 | 66 | 0 | 0 | 0 |
|
||||
| (rFifo) | StreamFifoCC_4 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_1 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| wFifo | StreamFifoCC_1 | 68 | 40 | 28 | 0 | 69 | 0 | 0 | 0 |
|
||||
| (wFifo) | StreamFifoCC_1 | 64 | 36 | 28 | 0 | 53 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_8 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_axi_axil_adapter | axi_axil_adapter | 1339 | 1339 | 0 | 0 | 161 | 0 | 0 | 0 |
|
||||
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 635 | 635 | 0 | 0 | 81 | 0 | 0 | 0 |
|
||||
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 704 | 704 | 0 | 0 | 80 | 0 | 0 | 0 |
|
||||
| u_axi_dvi | axi_dvi | 284 | 284 | 0 | 0 | 211 | 0 | 0 | 0 |
|
||||
| u_axi_ram | axi_wrap_ram_sp_external | 355 | 355 | 0 | 0 | 78 | 0 | 0 | 0 |
|
||||
| u_axi_sram_sp | axi2sram_sp_external | 355 | 355 | 0 | 0 | 78 | 0 | 0 | 0 |
|
||||
| u_axi_uart_controller | axi_uart_controller | 686 | 670 | 16 | 0 | 457 | 0 | 0 | 0 |
|
||||
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 252 | 252 | 0 | 0 | 120 | 0 | 0 | 0 |
|
||||
| uart0 | UART_TOP | 434 | 418 | 16 | 0 | 337 | 0 | 0 | 0 |
|
||||
| regs | uart_regs | 434 | 418 | 16 | 0 | 337 | 0 | 0 | 0 |
|
||||
| (regs) | uart_regs | 118 | 118 | 0 | 0 | 155 | 0 | 0 | 0 |
|
||||
| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| receiver | uart_receiver | 229 | 221 | 8 | 0 | 124 | 0 | 0 | 0 |
|
||||
| (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 |
|
||||
| fifo_rx | uart_rfifo | 161 | 153 | 8 | 0 | 70 | 0 | 0 | 0 |
|
||||
| (fifo_rx) | uart_rfifo | 143 | 143 | 0 | 0 | 62 | 0 | 0 | 0 |
|
||||
| rfifo | raminfr_47 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
||||
| transmitter | uart_transmitter | 84 | 76 | 8 | 0 | 56 | 0 | 0 | 0 |
|
||||
| (transmitter) | uart_transmitter | 41 | 41 | 0 | 0 | 35 | 0 | 0 | 0 |
|
||||
| fifo_tx | uart_tfifo | 43 | 35 | 8 | 0 | 21 | 0 | 0 | 0 |
|
||||
| (fifo_tx) | uart_tfifo | 24 | 24 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_cdma_matmul_bridge | cdma_matmul_bridge | 247 | 247 | 0 | 0 | 578 | 0 | 0 | 0 |
|
||||
| u_confreg | confreg | 390 | 390 | 0 | 0 | 476 | 0 | 0 | 0 |
|
||||
| (u_confreg) | confreg | 230 | 230 | 0 | 0 | 399 | 0 | 0 | 0 |
|
||||
| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 |
|
||||
| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 |
|
||||
| u_cpu | core_top | 8552 | 8300 | 252 | 0 | 5591 | 0 | 20 | 0 |
|
||||
| (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 |
|
||||
| addr_trans | addr_trans | 2246 | 2106 | 140 | 0 | 1244 | 0 | 0 | 0 |
|
||||
| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 |
|
||||
| tlb_entry | tlb_entry | 2246 | 2106 | 140 | 0 | 1204 | 0 | 0 | 0 |
|
||||
| axi_bridge | axi_bridge | 39 | 39 | 0 | 0 | 214 | 0 | 0 | 0 |
|
||||
| btb | btb | 1048 | 968 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
||||
| (btb) | btb | 1045 | 965 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
||||
| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| dcache | dcache | 553 | 521 | 32 | 0 | 146 | 0 | 10 | 0 |
|
||||
| (dcache) | dcache | 88 | 56 | 32 | 0 | 138 | 0 | 0 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_36 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_39 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_40 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_41 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_42 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_43 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| lfsr | lfsr_44 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| tagv_ram_way[0].u | tagv_sram_45 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| tagv_ram_way[1].u | tagv_sram_46 | 42 | 42 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| exe_stage | exe_stage | 664 | 664 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| (exe_stage) | exe_stage | 633 | 633 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| icache | icache | 235 | 235 | 0 | 0 | 55 | 0 | 10 | 0 |
|
||||
| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_29 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_30 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_31 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_32 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_33 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_34 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| tagv_ram_way[1].u | tagv_sram_35 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| id_stage | id_stage | 1050 | 1050 | 0 | 0 | 108 | 0 | 0 | 0 |
|
||||
| if_stage | if_stage | 134 | 134 | 0 | 0 | 173 | 0 | 0 | 0 |
|
||||
| mem_stage | mem_stage | 115 | 115 | 0 | 0 | 211 | 0 | 0 | 0 |
|
||||
| u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 |
|
||||
| u_div | div | 142 | 142 | 0 | 0 | 107 | 0 | 0 | 0 |
|
||||
| u_mul | mul | 935 | 935 | 0 | 0 | 592 | 0 | 0 | 0 |
|
||||
| wb_stage | wb_stage | 684 | 684 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 47584 | 46544 | 0 | 1040 | 25915 | 10 | 10 | 0 |
|
||||
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 17 | 17 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| u_fft_controller | fft_controller | 6890 | 5850 | 0 | 1040 | 1087 | 8 | 4 | 0 |
|
||||
| (u_fft_controller) | fft_controller | 90 | 90 | 0 | 0 | 104 | 0 | 0 | 0 |
|
||||
| u_FFT | FFT | 6781 | 5741 | 0 | 1040 | 983 | 8 | 0 | 0 |
|
||||
| SU1 | SdfUnit | 2145 | 1377 | 0 | 768 | 197 | 2 | 0 | 0 |
|
||||
| (SU1) | SdfUnit | 39 | 39 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_25 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer | 624 | 112 | 0 | 512 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized0 | 320 | 64 | 0 | 256 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_26 | 611 | 611 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle_27 | 543 | 543 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU2 | SdfUnit__parameterized0 | 1566 | 1374 | 0 | 192 | 197 | 2 | 0 | 0 |
|
||||
| (SU2) | SdfUnit__parameterized0 | 38 | 38 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_20 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_21 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_22 | 611 | 611 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle_23 | 541 | 541 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU3 | SdfUnit__parameterized1 | 1415 | 1367 | 0 | 48 | 197 | 2 | 0 | 0 |
|
||||
| (SU3) | SdfUnit__parameterized1 | 35 | 35 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_16 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_17 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized4 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_18 | 609 | 609 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle_19 | 539 | 539 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU4 | SdfUnit__parameterized2 | 1397 | 1365 | 0 | 32 | 197 | 2 | 0 | 0 |
|
||||
| (SU4) | SdfUnit__parameterized2 | 34 | 34 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_14 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_15 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized5 | 128 | 112 | 0 | 16 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized6 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply | 611 | 611 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle | 536 | 536 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU5 | SdfUnit__parameterized3 | 259 | 259 | 0 | 0 | 195 | 0 | 0 | 0 |
|
||||
| (SU5) | SdfUnit__parameterized3 | 35 | 35 | 0 | 0 | 99 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 |
|
||||
| u_in0 | my_bram0 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_in1 | my_bram0_11 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_out0 | my_bram0_12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_out1 | my_bram0_13 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_mlkem_axi_slave | mlkem_axi_slave | 40179 | 40179 | 0 | 0 | 24484 | 2 | 6 | 0 |
|
||||
| (u_mlkem_axi_slave) | mlkem_axi_slave | 3620 | 3620 | 0 | 0 | 1021 | 0 | 0 | 0 |
|
||||
| u_mlkem | mlkem_top | 36605 | 36605 | 0 | 0 | 23463 | 2 | 6 | 0 |
|
||||
| (u_mlkem) | mlkem_top | 2505 | 2505 | 0 | 0 | 4907 | 0 | 0 | 0 |
|
||||
| u_bank_a | sd_bram__parameterized0 | 39 | 39 | 0 | 0 | 0 | 1 | 1 | 0 |
|
||||
| u_bank_se | sd_bram__parameterized1 | 62 | 62 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| u_bank_t | sd_bram__parameterized2 | 468 | 468 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_c_in_bram | sd_bram | 1291 | 1291 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_cbd | sample_cbd_sync_shared | 2459 | 2459 | 0 | 0 | 3199 | 0 | 0 | 0 |
|
||||
| u_comp | comp_decomp_sync | 177 | 177 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| u_pipe | pipeline_reg | 177 | 177 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| u_ct_bram | sd_bram_4 | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_dkp_bram | sd_bram_5 | 100 | 100 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_ek_bram | sd_bram_6 | 225 | 225 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_keccak | keccak_core | 5240 | 5240 | 0 | 0 | 1619 | 0 | 0 | 0 |
|
||||
| u_ntt | ntt_core | 13299 | 13299 | 0 | 0 | 3354 | 0 | 0 | 0 |
|
||||
| u_pmul | poly_mul_sync | 7336 | 7336 | 0 | 0 | 6314 | 0 | 0 | 0 |
|
||||
| (u_pmul) | poly_mul_sync | 4958 | 4958 | 0 | 0 | 6314 | 0 | 0 | 0 |
|
||||
| u_bc | basecase_mul | 2378 | 2378 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| (u_bc) | basecase_mul | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_mul1 | barrett_mul | 969 | 969 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_mul2 | barrett_mul_7 | 118 | 118 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_mul3 | barrett_mul_8 | 561 | 561 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_mul4 | barrett_mul_9 | 549 | 549 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_mul_zeta | barrett_mul_10 | 129 | 129 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_sha3 | sha3_top_shared | 1970 | 1970 | 0 | 0 | 2388 | 0 | 0 | 0 |
|
||||
| u_snt | sample_ntt_sync_shared | 1433 | 1433 | 0 | 0 | 1669 | 0 | 0 | 0 |
|
||||
| u_prng_axi_slave | prng_axi_slave | 500 | 500 | 0 | 0 | 338 | 0 | 0 | 0 |
|
||||
| u_matmul_axi_slave | matmul_axi_slave | 9858 | 9676 | 176 | 6 | 3208 | 0 | 0 | 0 |
|
||||
| (u_matmul_axi_slave) | matmul_axi_slave | 5742 | 5560 | 176 | 6 | 2440 | 0 | 0 | 0 |
|
||||
| mult_inst[0].u_mult | pipelined_mult_32x32 | 1062 | 1062 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| mult_inst[1].u_mult | pipelined_mult_32x32_1 | 998 | 998 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| mult_inst[2].u_mult | pipelined_mult_32x32_2 | 1061 | 1061 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| mult_inst[3].u_mult | pipelined_mult_32x32_3 | 996 | 996 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1813 | 1813 | 0 | 0 | 1476 | 0 | 1 | 0 |
|
||||
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 604 | 604 | 0 | 0 | 1180 | 0 | 0 | 0 |
|
||||
| u_core_engine | snix_axi_mm2mm | 1211 | 1211 | 0 | 0 | 296 | 0 | 1 | 0 |
|
||||
| (u_core_engine) | snix_axi_mm2mm | 773 | 773 | 0 | 0 | 243 | 0 | 0 | 0 |
|
||||
| axis_fifo_u0 | snix_axis_fifo | 438 | 438 | 0 | 0 | 53 | 0 | 1 | 0 |
|
||||
| u_fifo | snix_sync_fifo | 438 | 438 | 0 | 0 | 53 | 0 | 1 | 0 |
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -113,7 +113,7 @@ THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// FIFO parameter defines
|
||||
|
||||
`define UART_FIFO_WIDTH 8
|
||||
`define UART_FIFO_DEPTH 16
|
||||
`define UART_FIFO_POINTER_W 4
|
||||
`define UART_FIFO_COUNTER_W 5
|
||||
`define UART_FIFO_DEPTH 32
|
||||
`define UART_FIFO_POINTER_W 5
|
||||
`define UART_FIFO_COUNTER_W 6
|
||||
`define UART_FIFO_REC_WIDTH 11
|
||||
|
||||
@@ -65,6 +65,7 @@ module axi2sram_sp_external #(
|
||||
output reg req_o,
|
||||
output reg we_o,
|
||||
output reg [AXI_ADDR_WIDTH-1:0] addr_o,
|
||||
output reg bank_o,
|
||||
output reg [AXI_DATA_WIDTH/8-1:0] be_o,
|
||||
output reg [AXI_DATA_WIDTH-1:0] data_o,
|
||||
input [AXI_DATA_WIDTH-1:0] data_i
|
||||
@@ -101,40 +102,34 @@ module axi2sram_sp_external #(
|
||||
localparam FIXED = 2'b00;
|
||||
localparam INCR = 2'b01;
|
||||
localparam WRAP = 2'b10;
|
||||
localparam [AXI_ADDR_WIDTH-1:0] ADDR_INCR =
|
||||
{{(AXI_ADDR_WIDTH-1){1'b0}}, 1'b1} << LOG_NR_BYTES;
|
||||
|
||||
reg [AXI_ADDR_WIDTH-1:0] req_addr_d, req_addr_q;
|
||||
reg [7:0] cnt_d, cnt_q;
|
||||
reg [8:0] cnt_d, cnt_q;
|
||||
reg [AXI_ADDR_WIDTH-1:0] wrap_mask_d, wrap_mask_q;
|
||||
reg req_bank_d, req_bank_q;
|
||||
reg [AXI_DATA_WIDTH-1:0] read_data_q;
|
||||
reg read_capture;
|
||||
|
||||
function automatic [AXI_ADDR_WIDTH-1:0] get_wrap_boundary;
|
||||
input [AXI_ADDR_WIDTH-1:0] unaligned_address;
|
||||
input [7:0] len;
|
||||
begin
|
||||
get_wrap_boundary = 'h0;
|
||||
// for wrapping transfers ax_len can only be of size 1, 3, 7 or 15
|
||||
if (len == 4'b1)
|
||||
get_wrap_boundary[AXI_ADDR_WIDTH-1:1+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:1+LOG_NR_BYTES];
|
||||
else if (len == 4'b11)
|
||||
get_wrap_boundary[AXI_ADDR_WIDTH-1:2+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:2+LOG_NR_BYTES];
|
||||
else if (len == 4'b111)
|
||||
get_wrap_boundary[AXI_ADDR_WIDTH-1:3+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:2+LOG_NR_BYTES];
|
||||
else if (len == 4'b1111)
|
||||
get_wrap_boundary[AXI_ADDR_WIDTH-1:4+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:4+LOG_NR_BYTES];
|
||||
end
|
||||
endfunction
|
||||
wire [AXI_ADDR_WIDTH-1:0] ar_burst_bytes =
|
||||
({{(AXI_ADDR_WIDTH-8){1'b0}}, s_arlen} + {{(AXI_ADDR_WIDTH-1){1'b0}}, 1'b1}) << LOG_NR_BYTES;
|
||||
wire [AXI_ADDR_WIDTH-1:0] aw_burst_bytes =
|
||||
({{(AXI_ADDR_WIDTH-8){1'b0}}, s_awlen} + {{(AXI_ADDR_WIDTH-1){1'b0}}, 1'b1}) << LOG_NR_BYTES;
|
||||
wire [AXI_ADDR_WIDTH-1:0] ar_wrap_mask = ar_burst_bytes - {{(AXI_ADDR_WIDTH-1){1'b0}}, 1'b1};
|
||||
wire [AXI_ADDR_WIDTH-1:0] aw_wrap_mask = aw_burst_bytes - {{(AXI_ADDR_WIDTH-1){1'b0}}, 1'b1};
|
||||
|
||||
reg [AXI_ADDR_WIDTH-1:0] aligned_address;
|
||||
reg [AXI_ADDR_WIDTH-1:0] wrap_boundary;
|
||||
reg [AXI_ADDR_WIDTH-1:0] upper_wrap_boundary;
|
||||
reg [AXI_ADDR_WIDTH-1:0] cons_addr;
|
||||
reg [AXI_ADDR_WIDTH-1:0] next_addr;
|
||||
reg [AXI_ADDR_WIDTH-1:0] seq_addr;
|
||||
|
||||
always @ (*) begin
|
||||
// address generation
|
||||
aligned_address = {ax_req_q_addr[AXI_ADDR_WIDTH-1:LOG_NR_BYTES], {{LOG_NR_BYTES}{1'b0}}};
|
||||
wrap_boundary = get_wrap_boundary(ax_req_q_addr, ax_req_q_len);
|
||||
// this will overflow
|
||||
upper_wrap_boundary = wrap_boundary + ((ax_req_q_len + 1) << LOG_NR_BYTES);
|
||||
// calculate consecutive address
|
||||
cons_addr = aligned_address + (cnt_q << LOG_NR_BYTES);
|
||||
seq_addr = req_addr_q + ADDR_INCR;
|
||||
case (ax_req_q_burst)
|
||||
FIXED: next_addr = req_addr_q;
|
||||
INCR: next_addr = seq_addr;
|
||||
WRAP: next_addr = (req_addr_q & ~wrap_mask_q) | (seq_addr & wrap_mask_q);
|
||||
default: next_addr = seq_addr;
|
||||
endcase
|
||||
|
||||
// Transaction attributes
|
||||
// default assignments
|
||||
@@ -146,12 +141,16 @@ module axi2sram_sp_external #(
|
||||
ax_req_d_burst = ax_req_q_burst;
|
||||
req_addr_d = req_addr_q;
|
||||
cnt_d = cnt_q;
|
||||
wrap_mask_d = wrap_mask_q;
|
||||
req_bank_d = req_bank_q;
|
||||
read_capture = 1'b0;
|
||||
// Memory default assignments
|
||||
data_o = s_wdata;
|
||||
be_o = s_wstrb;
|
||||
we_o = 1'b0;
|
||||
req_o = 1'b0;
|
||||
addr_o = 'h0;
|
||||
bank_o = req_bank_q;
|
||||
// AXI assignments
|
||||
// request
|
||||
s_awready = 1'b0;
|
||||
@@ -184,14 +183,17 @@ module axi2sram_sp_external #(
|
||||
ax_req_d_len = s_arlen;
|
||||
ax_req_d_size = s_arsize;
|
||||
ax_req_d_burst = s_arburst;
|
||||
state_d = READ;
|
||||
wrap_mask_d = ar_wrap_mask;
|
||||
req_bank_d = s_araddr[22];
|
||||
state_d = READ_ADDR;
|
||||
// we can request the first address, this saves us time
|
||||
req_o = 1'b1;
|
||||
addr_o = s_araddr;
|
||||
bank_o = s_araddr[22];
|
||||
// save the address
|
||||
req_addr_d = s_araddr;
|
||||
// save the ar_len
|
||||
cnt_d = 1;
|
||||
cnt_d = 0;
|
||||
// ------------
|
||||
// Write
|
||||
// ------------
|
||||
@@ -205,6 +207,9 @@ module axi2sram_sp_external #(
|
||||
ax_req_d_len = s_awlen;
|
||||
ax_req_d_size = s_awsize;
|
||||
ax_req_d_burst = s_awburst;
|
||||
wrap_mask_d = aw_wrap_mask;
|
||||
req_bank_d = s_awaddr[22];
|
||||
bank_o = s_awaddr[22];
|
||||
// we've got our first w_valid so start the write process
|
||||
if (s_wvalid) begin
|
||||
req_o = 1'b1;
|
||||
@@ -231,40 +236,52 @@ module axi2sram_sp_external #(
|
||||
end
|
||||
|
||||
READ: begin
|
||||
// keep request to memory high
|
||||
req_o = 1'b1;
|
||||
addr_o = req_addr_q;
|
||||
// send the response
|
||||
s_rvalid = 1'b1;
|
||||
s_rdata = data_i;
|
||||
s_rdata = read_data_q;
|
||||
s_rid = ax_req_q_id;
|
||||
s_rlast = (cnt_q == ax_req_q_len + 1);
|
||||
s_rlast = (cnt_q == ({1'b0, ax_req_q_len} + 9'd1));
|
||||
if (FAST_READ_BURST && !s_rlast) begin
|
||||
req_o = 1'b1;
|
||||
addr_o = next_addr;
|
||||
end
|
||||
// check that the master is ready, the slave must not wait on this
|
||||
if (s_rready) begin
|
||||
// we sent the last byte -> go back to idle
|
||||
if (s_rlast) begin
|
||||
state_d = IDLE;
|
||||
// we already got everything
|
||||
if (s_arvalid) begin
|
||||
// Accept the next burst without an intervening
|
||||
// IDLE cycle and start its SRAM address phase.
|
||||
s_arready = 1'b1;
|
||||
ax_req_d_id = s_arid;
|
||||
ax_req_d_addr = s_araddr;
|
||||
ax_req_d_len = s_arlen;
|
||||
ax_req_d_size = s_arsize;
|
||||
ax_req_d_burst = s_arburst;
|
||||
wrap_mask_d = ar_wrap_mask;
|
||||
req_bank_d = s_araddr[22];
|
||||
req_o = 1'b1;
|
||||
addr_o = s_araddr;
|
||||
bank_o = s_araddr[22];
|
||||
req_addr_d = s_araddr;
|
||||
// ARVALID was presented during the preceding
|
||||
// beat, so the async-SRAM address has a full
|
||||
// cycle to settle before this capture edge.
|
||||
read_capture = 1'b1;
|
||||
cnt_d = 1;
|
||||
state_d = READ;
|
||||
end else begin
|
||||
state_d = IDLE;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
if (FAST_READ_BURST) begin
|
||||
// Queue the next async-SRAM address for the clock
|
||||
// edge after the current read data is sampled.
|
||||
case (ax_req_q_burst)
|
||||
FIXED, INCR: req_addr_d = cons_addr;
|
||||
WRAP: begin
|
||||
if (cons_addr == upper_wrap_boundary) begin
|
||||
req_addr_d = wrap_boundary;
|
||||
end else if (cons_addr > upper_wrap_boundary) begin
|
||||
req_addr_d = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES);
|
||||
end else begin
|
||||
req_addr_d = cons_addr;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
read_capture = 1'b1;
|
||||
req_addr_d = next_addr;
|
||||
cnt_d = cnt_q + 1;
|
||||
state_d = READ;
|
||||
end else begin
|
||||
req_addr_d = next_addr;
|
||||
state_d = READ_ADDR;
|
||||
end
|
||||
end
|
||||
@@ -272,34 +289,12 @@ module axi2sram_sp_external #(
|
||||
end
|
||||
|
||||
READ_ADDR: begin
|
||||
// keep request to memory high
|
||||
// Fill the read data register after the async-SRAM address has
|
||||
// been stable for one full sys_clk cycle.
|
||||
req_o = 1'b1;
|
||||
// send the response
|
||||
s_rvalid = 1'b0;
|
||||
// ----------------------------
|
||||
// Next address generation
|
||||
// ----------------------------
|
||||
// handle the correct burst type
|
||||
case (ax_req_q_burst)
|
||||
FIXED, INCR: addr_o = cons_addr;
|
||||
WRAP: begin
|
||||
// check if the address reached warp boundary
|
||||
if (cons_addr == upper_wrap_boundary) begin
|
||||
addr_o = wrap_boundary;
|
||||
// address warped beyond boundary
|
||||
end else if (cons_addr > upper_wrap_boundary) begin
|
||||
addr_o = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES);
|
||||
// we are still in the incremental regime
|
||||
end else begin
|
||||
addr_o = cons_addr;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
// we need to change the address here for the upcoming request
|
||||
// we can decrease the counter as the master has consumed the read data
|
||||
addr_o = req_addr_q;
|
||||
read_capture = 1'b1;
|
||||
cnt_d = cnt_q + 1;
|
||||
// save the request address for the next cycle
|
||||
req_addr_d = addr_o;
|
||||
state_d = READ;
|
||||
end
|
||||
|
||||
@@ -317,24 +312,9 @@ module axi2sram_sp_external #(
|
||||
// Next address generation
|
||||
// ----------------------------
|
||||
// handle the correct burst type
|
||||
case (ax_req_q_burst)
|
||||
|
||||
FIXED, INCR: addr_o = cons_addr;
|
||||
WRAP: begin
|
||||
// check if the address reached warp boundary
|
||||
if (cons_addr == upper_wrap_boundary) begin
|
||||
addr_o = wrap_boundary;
|
||||
// address warped beyond boundary
|
||||
end else if (cons_addr > upper_wrap_boundary) begin
|
||||
addr_o = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES);
|
||||
// we are still in the incremental regime
|
||||
end else begin
|
||||
addr_o = cons_addr;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
addr_o = next_addr;
|
||||
// save the request address for the next cycle
|
||||
req_addr_d = addr_o;
|
||||
req_addr_d = next_addr;
|
||||
// we can decrease the counter as the master has consumed the read data
|
||||
cnt_d = cnt_q + 1;
|
||||
|
||||
@@ -365,7 +345,10 @@ module axi2sram_sp_external #(
|
||||
ax_req_q_len <= 8'h0;
|
||||
ax_req_q_size <= 3'h0;
|
||||
req_addr_q <= 'h0;
|
||||
cnt_q <= 8'h0;
|
||||
cnt_q <= 9'h0;
|
||||
wrap_mask_q <= 'h0;
|
||||
req_bank_q <= 1'b0;
|
||||
read_data_q <= 'h0;
|
||||
end else begin
|
||||
state_q <= state_d;
|
||||
ax_req_q_addr <= ax_req_d_addr;
|
||||
@@ -375,6 +358,10 @@ module axi2sram_sp_external #(
|
||||
ax_req_q_size <= ax_req_d_size;
|
||||
req_addr_q <= req_addr_d;
|
||||
cnt_q <= cnt_d;
|
||||
wrap_mask_q <= wrap_mask_d;
|
||||
req_bank_q <= req_bank_d;
|
||||
if (read_capture)
|
||||
read_data_q <= data_i;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
@@ -101,7 +101,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ">32.97872</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ">50.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ">59.61538</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
@@ -117,10 +117,10 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">50.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">59.61538</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">60</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">1</spirit:configurableElementValue>
|
||||
@@ -203,7 +203,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVCLK">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE1_AUTO">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">0.66</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">0.55</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">0.33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">0.33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">0.33</spirit:configurableElementValue>
|
||||
@@ -255,7 +255,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">31</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">26</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
@@ -293,7 +293,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">_cpu_clk__32.97872______0.000______50.0______130.093____123.600</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">_sys_clk__50.00000______0.000______50.0______122.035____123.600</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">_sys_clk__59.61538______0.000______50.0______118.808____123.600</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
|
||||
@@ -423,11 +423,11 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">122.035</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">118.808</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">123.600</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">60</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
|
||||
@@ -534,7 +534,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">31</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">26</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
|
||||
@@ -1,402 +0,0 @@
|
||||
// ============================================================================
|
||||
// cdma_matmul_bridge.sv
|
||||
// Matmul-specific sequencer between the generic CDMA endpoint requester and
|
||||
// the matmul local endpoint/control interface.
|
||||
//
|
||||
// AXI-Lite register map, relative to this bridge window:
|
||||
// 0x00 CTRL bit0 start, bit1 skip_result_writeback
|
||||
// 0x04 STATUS bit0 busy, bit1 done (W1C)
|
||||
// 0x08 SRC_BASE physical ExtRAM input base
|
||||
// 0x0C DST_BASE physical ExtRAM result base
|
||||
// 0x10 GROUPS
|
||||
// 0x14 MAT_BASE reserved for software compatibility
|
||||
// 0x18 SRC_STRIDE bytes, default 128
|
||||
// 0x1C DST_STRIDE bytes, default 192
|
||||
// ============================================================================
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module cdma_matmul_bridge #(
|
||||
parameter int ADDR_WIDTH = 32,
|
||||
parameter int AXIL_ADDR_WIDTH = 32,
|
||||
parameter int AXIL_DATA_WIDTH = 32
|
||||
) (
|
||||
input logic clk,
|
||||
input logic rst_n,
|
||||
|
||||
input logic [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr,
|
||||
input logic s_axil_awvalid,
|
||||
output logic s_axil_awready,
|
||||
input logic [AXIL_DATA_WIDTH-1:0] s_axil_wdata,
|
||||
input logic [AXIL_DATA_WIDTH/8-1:0] s_axil_wstrb,
|
||||
input logic s_axil_wvalid,
|
||||
output logic s_axil_wready,
|
||||
output logic [1:0] s_axil_bresp,
|
||||
output logic s_axil_bvalid,
|
||||
input logic s_axil_bready,
|
||||
input logic [AXIL_ADDR_WIDTH-1:0] s_axil_araddr,
|
||||
input logic s_axil_arvalid,
|
||||
output logic s_axil_arready,
|
||||
output logic [AXIL_DATA_WIDTH-1:0] s_axil_rdata,
|
||||
output logic [1:0] s_axil_rresp,
|
||||
output logic s_axil_rvalid,
|
||||
input logic s_axil_rready,
|
||||
|
||||
output logic cdma_rd_req_valid,
|
||||
input logic cdma_rd_req_ready,
|
||||
output logic [ADDR_WIDTH-1:0] cdma_rd_req_src,
|
||||
output logic [31:0] cdma_rd_req_bytes,
|
||||
output logic [3:0] cdma_rd_req_ep_id,
|
||||
output logic [3:0] cdma_rd_req_ep_bank,
|
||||
output logic [7:0] cdma_rd_req_ep_word_off,
|
||||
input logic cdma_rd_req_done,
|
||||
|
||||
output logic cdma_wr_req_valid,
|
||||
input logic cdma_wr_req_ready,
|
||||
output logic [ADDR_WIDTH-1:0] cdma_wr_req_dst,
|
||||
output logic [31:0] cdma_wr_req_bytes,
|
||||
output logic [3:0] cdma_wr_req_ep_id,
|
||||
output logic [3:0] cdma_wr_req_ep_bank,
|
||||
output logic [7:0] cdma_wr_req_ep_word_off,
|
||||
input logic cdma_wr_req_done,
|
||||
|
||||
output logic mat_start_valid,
|
||||
output logic mat_start_bank,
|
||||
output logic mat_done_clear,
|
||||
output logic mat_crc_clear,
|
||||
input logic mat_done,
|
||||
|
||||
output logic seq_done_irq
|
||||
);
|
||||
|
||||
localparam logic [7:0] REG_CTRL = 8'h00;
|
||||
localparam logic [7:0] REG_STATUS = 8'h04;
|
||||
localparam logic [7:0] REG_SRC_BASE = 8'h08;
|
||||
localparam logic [7:0] REG_DST_BASE = 8'h0C;
|
||||
localparam logic [7:0] REG_GROUPS = 8'h10;
|
||||
localparam logic [7:0] REG_MAT_BASE = 8'h14;
|
||||
localparam logic [7:0] REG_SRC_STRIDE = 8'h18;
|
||||
localparam logic [7:0] REG_DST_STRIDE = 8'h1C;
|
||||
|
||||
localparam logic [31:0] MAT_AB_BYTES = 32'd128;
|
||||
localparam logic [31:0] MAT_C_BYTES = 32'd192;
|
||||
|
||||
logic [31:0] seq_src_base;
|
||||
logic [31:0] seq_dst_base;
|
||||
logic [31:0] seq_groups;
|
||||
logic [31:0] seq_mat_base;
|
||||
logic [31:0] seq_src_stride;
|
||||
logic [31:0] seq_dst_stride;
|
||||
logic seq_busy;
|
||||
logic seq_done_flag;
|
||||
logic seq_skip_writeback;
|
||||
|
||||
logic [31:0] load_next_idx;
|
||||
logic [31:0] groups_retired;
|
||||
logic [1:0] bank_load_active;
|
||||
logic [1:0] bank_ab_valid;
|
||||
logic [1:0] bank_compute_active;
|
||||
logic [1:0] bank_store_pending;
|
||||
logic [1:0] bank_store_active;
|
||||
logic [31:0] bank_group_idx [2];
|
||||
logic [31:0] load_next_src_addr;
|
||||
logic [31:0] load_next_dst_addr;
|
||||
logic [31:0] bank_dst_addr [2];
|
||||
|
||||
logic rd_busy;
|
||||
logic wr_busy;
|
||||
logic rd_active_bank;
|
||||
logic wr_active_bank;
|
||||
logic [1:0] compute_q;
|
||||
logic [1:0] compute_q_count;
|
||||
logic mat_done_seen;
|
||||
|
||||
wire [7:0] wr_off = s_axil_awaddr[7:0];
|
||||
wire [7:0] rd_off = s_axil_araddr[7:0];
|
||||
wire do_write;
|
||||
wire start_req = do_write && (wr_off == REG_CTRL) && s_axil_wstrb[0] && s_axil_wdata[0];
|
||||
wire done_clear_req = do_write && (wr_off == REG_STATUS) && s_axil_wstrb[0] && s_axil_wdata[1];
|
||||
wire load_target_bank = load_next_idx[0];
|
||||
wire load_target_free = !bank_load_active[load_target_bank] &&
|
||||
!bank_ab_valid[load_target_bank] &&
|
||||
!bank_compute_active[load_target_bank] &&
|
||||
!bank_store_pending[load_target_bank] &&
|
||||
!bank_store_active[load_target_bank];
|
||||
wire bank0_start_ready = bank_ab_valid[0] && !bank_compute_active[0] &&
|
||||
!bank_store_pending[0] && !bank_store_active[0];
|
||||
wire bank1_start_ready = bank_ab_valid[1] && !bank_compute_active[1] &&
|
||||
!bank_store_pending[1] && !bank_store_active[1];
|
||||
wire start_sel_bank = bank1_start_ready &&
|
||||
(!bank0_start_ready || (bank_group_idx[1] < bank_group_idx[0]));
|
||||
wire start_ready_any = bank0_start_ready || bank1_start_ready;
|
||||
wire store_sel_bank = bank_store_pending[1] && !bank_store_active[1] &&
|
||||
!(bank_store_pending[0] && !bank_store_active[0]);
|
||||
wire store_ready_any = (bank_store_pending[0] && !bank_store_active[0]) ||
|
||||
(bank_store_pending[1] && !bank_store_active[1]);
|
||||
wire mat_done_event = mat_done && !mat_done_seen;
|
||||
wire retire_from_store = seq_busy && cdma_wr_req_done;
|
||||
wire retire_from_compute = seq_busy && seq_skip_writeback && mat_done_event && (compute_q_count != 2'd0);
|
||||
wire [31:0] retire_inc = {31'd0, retire_from_store} + {31'd0, retire_from_compute};
|
||||
|
||||
function automatic logic [31:0] apply_wstrb(
|
||||
input logic [31:0] old_val,
|
||||
input logic [31:0] new_val,
|
||||
input logic [3:0] wstrb
|
||||
);
|
||||
begin
|
||||
apply_wstrb[7:0] = wstrb[0] ? new_val[7:0] : old_val[7:0];
|
||||
apply_wstrb[15:8] = wstrb[1] ? new_val[15:8] : old_val[15:8];
|
||||
apply_wstrb[23:16] = wstrb[2] ? new_val[23:16] : old_val[23:16];
|
||||
apply_wstrb[31:24] = wstrb[3] ? new_val[31:24] : old_val[31:24];
|
||||
end
|
||||
endfunction
|
||||
|
||||
assign s_axil_bresp = 2'b00;
|
||||
assign s_axil_rresp = 2'b00;
|
||||
assign seq_done_irq = seq_done_flag;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (!rst_n) begin
|
||||
s_axil_awready <= 1'b0;
|
||||
s_axil_wready <= 1'b0;
|
||||
end else begin
|
||||
if (s_axil_awvalid && s_axil_wvalid && !s_axil_awready && (!s_axil_bvalid || s_axil_bready)) begin
|
||||
s_axil_awready <= 1'b1;
|
||||
s_axil_wready <= 1'b1;
|
||||
end else begin
|
||||
s_axil_awready <= 1'b0;
|
||||
s_axil_wready <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign do_write = s_axil_awready && s_axil_awvalid && s_axil_wready && s_axil_wvalid;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (!rst_n) begin
|
||||
s_axil_bvalid <= 1'b0;
|
||||
end else if (do_write) begin
|
||||
s_axil_bvalid <= 1'b1;
|
||||
end else if (s_axil_bready && s_axil_bvalid) begin
|
||||
s_axil_bvalid <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (!rst_n) begin
|
||||
s_axil_arready <= 1'b0;
|
||||
end else begin
|
||||
if (s_axil_arvalid && !s_axil_arready && (!s_axil_rvalid || s_axil_rready)) begin
|
||||
s_axil_arready <= 1'b1;
|
||||
end else begin
|
||||
s_axil_arready <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire do_read = s_axil_arready && s_axil_arvalid;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (!rst_n) begin
|
||||
s_axil_rvalid <= 1'b0;
|
||||
s_axil_rdata <= '0;
|
||||
end else if (do_read) begin
|
||||
s_axil_rvalid <= 1'b1;
|
||||
case (rd_off)
|
||||
REG_CTRL: s_axil_rdata <= {30'd0, seq_skip_writeback, 1'b0};
|
||||
REG_STATUS: s_axil_rdata <= {30'd0, seq_done_flag, seq_busy};
|
||||
REG_SRC_BASE: s_axil_rdata <= seq_src_base;
|
||||
REG_DST_BASE: s_axil_rdata <= seq_dst_base;
|
||||
REG_GROUPS: s_axil_rdata <= seq_groups;
|
||||
REG_MAT_BASE: s_axil_rdata <= seq_mat_base;
|
||||
REG_SRC_STRIDE: s_axil_rdata <= seq_src_stride;
|
||||
REG_DST_STRIDE: s_axil_rdata <= seq_dst_stride;
|
||||
default: s_axil_rdata <= 32'd0;
|
||||
endcase
|
||||
end else if (s_axil_rready && s_axil_rvalid) begin
|
||||
s_axil_rvalid <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (!rst_n) begin
|
||||
seq_src_base <= 32'h0;
|
||||
seq_dst_base <= 32'h0;
|
||||
seq_groups <= 32'h0;
|
||||
seq_mat_base <= 32'h1f50_0000;
|
||||
seq_src_stride <= 32'd128;
|
||||
seq_dst_stride <= 32'd192;
|
||||
end else if (do_write) begin
|
||||
case (wr_off)
|
||||
REG_SRC_BASE: if (!seq_busy) seq_src_base <= apply_wstrb(seq_src_base, s_axil_wdata, s_axil_wstrb);
|
||||
REG_DST_BASE: if (!seq_busy) seq_dst_base <= apply_wstrb(seq_dst_base, s_axil_wdata, s_axil_wstrb);
|
||||
REG_GROUPS: if (!seq_busy) seq_groups <= apply_wstrb(seq_groups, s_axil_wdata, s_axil_wstrb);
|
||||
REG_MAT_BASE: if (!seq_busy) seq_mat_base <= apply_wstrb(seq_mat_base, s_axil_wdata, s_axil_wstrb);
|
||||
REG_SRC_STRIDE: if (!seq_busy) seq_src_stride <= apply_wstrb(seq_src_stride, s_axil_wdata, s_axil_wstrb);
|
||||
REG_DST_STRIDE: if (!seq_busy) seq_dst_stride <= apply_wstrb(seq_dst_stride, s_axil_wdata, s_axil_wstrb);
|
||||
default: begin
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (!rst_n) begin
|
||||
seq_busy <= 1'b0;
|
||||
seq_done_flag <= 1'b0;
|
||||
seq_skip_writeback <= 1'b0;
|
||||
load_next_idx <= 32'd0;
|
||||
groups_retired <= 32'd0;
|
||||
bank_load_active <= 2'b00;
|
||||
bank_ab_valid <= 2'b00;
|
||||
bank_compute_active <= 2'b00;
|
||||
bank_store_pending <= 2'b00;
|
||||
bank_store_active <= 2'b00;
|
||||
bank_group_idx[0] <= 32'd0;
|
||||
bank_group_idx[1] <= 32'd0;
|
||||
load_next_src_addr <= 32'd0;
|
||||
load_next_dst_addr <= 32'd0;
|
||||
bank_dst_addr[0] <= 32'd0;
|
||||
bank_dst_addr[1] <= 32'd0;
|
||||
rd_busy <= 1'b0;
|
||||
wr_busy <= 1'b0;
|
||||
rd_active_bank <= 1'b0;
|
||||
wr_active_bank <= 1'b0;
|
||||
compute_q <= 2'b00;
|
||||
compute_q_count <= 2'd0;
|
||||
mat_done_seen <= 1'b0;
|
||||
cdma_rd_req_valid <= 1'b0;
|
||||
cdma_rd_req_src <= '0;
|
||||
cdma_rd_req_bytes <= '0;
|
||||
cdma_rd_req_ep_id <= 4'd0;
|
||||
cdma_rd_req_ep_bank <= 4'd0;
|
||||
cdma_rd_req_ep_word_off <= 8'd0;
|
||||
cdma_wr_req_valid <= 1'b0;
|
||||
cdma_wr_req_dst <= '0;
|
||||
cdma_wr_req_bytes <= '0;
|
||||
cdma_wr_req_ep_id <= 4'd0;
|
||||
cdma_wr_req_ep_bank <= 4'd0;
|
||||
cdma_wr_req_ep_word_off <= 8'd0;
|
||||
mat_start_valid <= 1'b0;
|
||||
mat_start_bank <= 1'b0;
|
||||
mat_done_clear <= 1'b0;
|
||||
mat_crc_clear <= 1'b0;
|
||||
end else begin
|
||||
mat_start_valid <= 1'b0;
|
||||
mat_done_clear <= 1'b0;
|
||||
mat_crc_clear <= 1'b0;
|
||||
|
||||
mat_done_seen <= mat_done;
|
||||
|
||||
if (done_clear_req)
|
||||
seq_done_flag <= 1'b0;
|
||||
|
||||
if (cdma_rd_req_valid && cdma_rd_req_ready)
|
||||
cdma_rd_req_valid <= 1'b0;
|
||||
|
||||
if (cdma_wr_req_valid && cdma_wr_req_ready)
|
||||
cdma_wr_req_valid <= 1'b0;
|
||||
|
||||
if (start_req && !seq_busy && (seq_groups != 32'd0)) begin
|
||||
seq_busy <= 1'b1;
|
||||
seq_done_flag <= 1'b0;
|
||||
seq_skip_writeback <= s_axil_wstrb[0] && s_axil_wdata[1];
|
||||
load_next_idx <= 32'd0;
|
||||
groups_retired <= 32'd0;
|
||||
bank_load_active <= 2'b00;
|
||||
bank_ab_valid <= 2'b00;
|
||||
bank_compute_active <= 2'b00;
|
||||
bank_store_pending <= 2'b00;
|
||||
bank_store_active <= 2'b00;
|
||||
bank_group_idx[0] <= 32'd0;
|
||||
bank_group_idx[1] <= 32'd0;
|
||||
load_next_src_addr <= seq_src_base;
|
||||
load_next_dst_addr <= seq_dst_base;
|
||||
bank_dst_addr[0] <= 32'd0;
|
||||
bank_dst_addr[1] <= 32'd0;
|
||||
rd_busy <= 1'b0;
|
||||
wr_busy <= 1'b0;
|
||||
compute_q <= 2'b00;
|
||||
compute_q_count <= 2'd0;
|
||||
mat_done_seen <= 1'b1;
|
||||
mat_crc_clear <= 1'b1;
|
||||
mat_done_clear <= 1'b1;
|
||||
cdma_rd_req_valid <= 1'b0;
|
||||
cdma_wr_req_valid <= 1'b0;
|
||||
end else if (seq_busy) begin
|
||||
if (retire_inc != 32'd0) begin
|
||||
groups_retired <= groups_retired + retire_inc;
|
||||
if ((groups_retired + retire_inc) >= seq_groups) begin
|
||||
seq_busy <= 1'b0;
|
||||
seq_done_flag <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
if (cdma_rd_req_done) begin
|
||||
rd_busy <= 1'b0;
|
||||
bank_load_active[rd_active_bank] <= 1'b0;
|
||||
bank_ab_valid[rd_active_bank] <= 1'b1;
|
||||
end
|
||||
|
||||
if (cdma_wr_req_done) begin
|
||||
wr_busy <= 1'b0;
|
||||
bank_store_active[wr_active_bank] <= 1'b0;
|
||||
end
|
||||
|
||||
if (mat_done_event && (compute_q_count != 2'd0)) begin
|
||||
mat_done_clear <= 1'b1;
|
||||
mat_done_seen <= 1'b1;
|
||||
bank_compute_active[compute_q[0]] <= 1'b0;
|
||||
if (!seq_skip_writeback) begin
|
||||
bank_store_pending[compute_q[0]] <= 1'b1;
|
||||
end
|
||||
if (compute_q_count == 2'd2)
|
||||
compute_q[0] <= compute_q[1];
|
||||
compute_q_count <= compute_q_count - 2'd1;
|
||||
end
|
||||
|
||||
if (!rd_busy && !cdma_rd_req_valid && (load_next_idx < seq_groups) && load_target_free) begin
|
||||
cdma_rd_req_src <= load_next_src_addr;
|
||||
cdma_rd_req_bytes <= MAT_AB_BYTES;
|
||||
cdma_rd_req_ep_id <= 4'd0;
|
||||
cdma_rd_req_ep_bank <= {3'b000, load_target_bank};
|
||||
cdma_rd_req_ep_word_off <= 8'd0;
|
||||
cdma_rd_req_valid <= 1'b1;
|
||||
rd_busy <= 1'b1;
|
||||
rd_active_bank <= load_target_bank;
|
||||
bank_load_active[load_target_bank] <= 1'b1;
|
||||
bank_group_idx[load_target_bank] <= load_next_idx;
|
||||
bank_dst_addr[load_target_bank] <= load_next_dst_addr;
|
||||
load_next_src_addr <= load_next_src_addr + seq_src_stride;
|
||||
load_next_dst_addr <= load_next_dst_addr + seq_dst_stride;
|
||||
load_next_idx <= load_next_idx + 32'd1;
|
||||
end
|
||||
|
||||
if (!seq_skip_writeback && !wr_busy && !cdma_wr_req_valid && store_ready_any) begin
|
||||
cdma_wr_req_dst <= bank_dst_addr[store_sel_bank];
|
||||
cdma_wr_req_bytes <= MAT_C_BYTES;
|
||||
cdma_wr_req_ep_id <= 4'd0;
|
||||
cdma_wr_req_ep_bank <= {3'b000, store_sel_bank};
|
||||
cdma_wr_req_ep_word_off <= 8'd0;
|
||||
cdma_wr_req_valid <= 1'b1;
|
||||
wr_busy <= 1'b1;
|
||||
wr_active_bank <= store_sel_bank;
|
||||
bank_store_pending[store_sel_bank] <= 1'b0;
|
||||
bank_store_active[store_sel_bank] <= 1'b1;
|
||||
end
|
||||
|
||||
if ((compute_q_count < 2'd2) && start_ready_any && !(mat_done_event && (compute_q_count != 2'd0))) begin
|
||||
mat_start_valid <= 1'b1;
|
||||
mat_start_bank <= start_sel_bank;
|
||||
bank_ab_valid[start_sel_bank] <= 1'b0;
|
||||
bank_compute_active[start_sel_bank] <= 1'b1;
|
||||
if (compute_q_count == 2'd0)
|
||||
compute_q[0] <= start_sel_bank;
|
||||
else
|
||||
compute_q[1] <= start_sel_bank;
|
||||
compute_q_count <= compute_q_count + 2'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -110,27 +110,6 @@ module snix_axil_cdma_mux #(
|
||||
output logic [7:0] ep_rd_word_addr,
|
||||
input logic [31:0] ep_rd_data,
|
||||
input logic ep_rd_ready,
|
||||
|
||||
// ==========================================
|
||||
// Generic external endpoint requester
|
||||
// ==========================================
|
||||
input logic ext_rd_req_valid,
|
||||
output logic ext_rd_req_ready,
|
||||
input logic [ADDR_WIDTH-1:0] ext_rd_req_src,
|
||||
input logic [31:0] ext_rd_req_bytes,
|
||||
input logic [3:0] ext_rd_req_ep_id,
|
||||
input logic [3:0] ext_rd_req_ep_bank,
|
||||
input logic [7:0] ext_rd_req_ep_word_off,
|
||||
output logic ext_rd_req_done,
|
||||
|
||||
input logic ext_wr_req_valid,
|
||||
output logic ext_wr_req_ready,
|
||||
input logic [ADDR_WIDTH-1:0] ext_wr_req_dst,
|
||||
input logic [31:0] ext_wr_req_bytes,
|
||||
input logic [3:0] ext_wr_req_ep_id,
|
||||
input logic [3:0] ext_wr_req_ep_bank,
|
||||
input logic [7:0] ext_wr_req_ep_word_off,
|
||||
output logic ext_wr_req_done,
|
||||
|
||||
// Global Interrupt (OR'd from all channels)
|
||||
output logic dma_finish
|
||||
@@ -144,6 +123,30 @@ module snix_axil_cdma_mux #(
|
||||
localparam logic [1:0] MODE_MEM2EP = 2'd1;
|
||||
localparam logic [1:0] MODE_EP2MEM = 2'd2;
|
||||
|
||||
localparam logic [7:0] SEQ_REG_CTRL = 8'h00;
|
||||
localparam logic [7:0] SEQ_REG_STATUS = 8'h04;
|
||||
localparam logic [7:0] SEQ_REG_SRC_BASE = 8'h08;
|
||||
localparam logic [7:0] SEQ_REG_DST_BASE = 8'h0C;
|
||||
localparam logic [7:0] SEQ_REG_GROUPS = 8'h10;
|
||||
localparam logic [7:0] SEQ_REG_MAT_BASE = 8'h14;
|
||||
localparam logic [7:0] SEQ_REG_SRC_STRIDE = 8'h18;
|
||||
localparam logic [7:0] SEQ_REG_DST_STRIDE = 8'h1C;
|
||||
|
||||
localparam logic [11:0] MAT_CTRL_OFF = 12'h000;
|
||||
localparam logic [11:0] MAT_STATUS_OFF = 12'h004;
|
||||
localparam logic [11:0] MAT_CRC_OFF = 12'h010;
|
||||
localparam logic [11:0] MAT_B0_AB_OFF = 12'h100;
|
||||
localparam logic [11:0] MAT_B0_C_OFF = 12'h180;
|
||||
localparam logic [11:0] MAT_B1_AB_OFF = 12'h300;
|
||||
localparam logic [11:0] MAT_B1_C_OFF = 12'h380;
|
||||
|
||||
localparam logic [31:0] MAT_STATUS_DONE_CLR = 32'h0000_0006;
|
||||
localparam logic [31:0] MAT_STATUS_DONE_BIT = 32'h0000_0002;
|
||||
localparam logic [31:0] MAT_CTRL_START_B0 = 32'h0000_0001;
|
||||
localparam logic [31:0] MAT_CTRL_START_B1 = 32'h0000_0002;
|
||||
localparam logic [31:0] MAT_AB_BYTES = 32'd128;
|
||||
localparam logic [31:0] MAT_C_BYTES = 32'd192;
|
||||
|
||||
// Function to safely apply WSTRB to 32-bit registers
|
||||
function automatic logic [31:0] apply_wstrb(
|
||||
input logic [31:0] old_val,
|
||||
@@ -174,6 +177,17 @@ module snix_axil_cdma_mux #(
|
||||
|
||||
logic [PORTS-1:0] arb_set_done; // From Arbiter to CSR
|
||||
|
||||
logic [31:0] seq_src_base;
|
||||
logic [31:0] seq_dst_base;
|
||||
logic [31:0] seq_groups;
|
||||
logic [31:0] seq_mat_base;
|
||||
logic [31:0] seq_src_stride;
|
||||
logic [31:0] seq_dst_stride;
|
||||
logic seq_busy;
|
||||
logic seq_done_flag;
|
||||
wire seq_start_req;
|
||||
wire seq_done_clear_req;
|
||||
|
||||
// ==========================================
|
||||
// Address Decoding (0x40 offset per channel)
|
||||
// ==========================================
|
||||
@@ -181,6 +195,14 @@ module snix_axil_cdma_mux #(
|
||||
wire [5:0] wr_reg = s_axil_awaddr[5:0];
|
||||
wire [CH_BITS-1:0] rd_ch = s_axil_araddr[6 +: CH_BITS];
|
||||
wire [5:0] rd_reg = s_axil_araddr[5:0];
|
||||
wire wr_seq_reg = (s_axil_awaddr[11:8] == 4'h2);
|
||||
wire rd_seq_reg = (s_axil_araddr[11:8] == 4'h2);
|
||||
wire [7:0] wr_seq_off = s_axil_awaddr[7:0];
|
||||
wire [7:0] rd_seq_off = s_axil_araddr[7:0];
|
||||
assign seq_start_req = do_write && wr_seq_reg && (wr_seq_off == SEQ_REG_CTRL) &&
|
||||
s_axil_wstrb[0] && s_axil_wdata[0];
|
||||
assign seq_done_clear_req = do_write && wr_seq_reg && (wr_seq_off == SEQ_REG_STATUS) &&
|
||||
s_axil_wstrb[0] && s_axil_wdata[1];
|
||||
|
||||
// ==========================================
|
||||
// AXI-Lite Slave Logic (Robust Backpressure)
|
||||
@@ -240,7 +262,19 @@ module snix_axil_cdma_mux #(
|
||||
end else begin
|
||||
if (do_read) begin
|
||||
s_axil_rvalid <= 1'b1;
|
||||
if (rd_ch < PORTS) begin
|
||||
if (rd_seq_reg) begin
|
||||
case (rd_seq_off)
|
||||
SEQ_REG_CTRL: s_axil_rdata <= {31'd0, seq_start_req};
|
||||
SEQ_REG_STATUS: s_axil_rdata <= {30'd0, seq_done_flag, seq_busy};
|
||||
SEQ_REG_SRC_BASE: s_axil_rdata <= seq_src_base;
|
||||
SEQ_REG_DST_BASE: s_axil_rdata <= seq_dst_base;
|
||||
SEQ_REG_GROUPS: s_axil_rdata <= seq_groups;
|
||||
SEQ_REG_MAT_BASE: s_axil_rdata <= seq_mat_base;
|
||||
SEQ_REG_SRC_STRIDE: s_axil_rdata <= seq_src_stride;
|
||||
SEQ_REG_DST_STRIDE: s_axil_rdata <= seq_dst_stride;
|
||||
default: s_axil_rdata <= 32'd0;
|
||||
endcase
|
||||
end else if (rd_ch < PORTS) begin
|
||||
case (rd_reg)
|
||||
6'h00: s_axil_rdata <= ch_src_addr[rd_ch];
|
||||
6'h04: s_axil_rdata <= ch_dst_addr[rd_ch];
|
||||
@@ -270,6 +304,12 @@ module snix_axil_cdma_mux #(
|
||||
if (!rst_n) begin
|
||||
ch_req <= '0;
|
||||
ch_done <= '0;
|
||||
seq_src_base <= 32'h0;
|
||||
seq_dst_base <= 32'h0;
|
||||
seq_groups <= 32'h0;
|
||||
seq_mat_base <= 32'h1f50_0000;
|
||||
seq_src_stride <= 32'd128;
|
||||
seq_dst_stride <= 32'd192;
|
||||
for (int i=0; i<PORTS; i++) begin
|
||||
ch_src_addr[i] <= '0; ch_dst_addr[i] <= '0;
|
||||
ch_len[i] <= '0; ch_tag[i] <= '0; ch_ctrl[i] <= '0;
|
||||
@@ -285,7 +325,16 @@ module snix_axil_cdma_mux #(
|
||||
end
|
||||
|
||||
// 2. Process CPU Writes
|
||||
if (do_write && wr_ch < PORTS) begin
|
||||
if (do_write && wr_seq_reg) begin
|
||||
case (wr_seq_off)
|
||||
SEQ_REG_SRC_BASE: if (!seq_busy) seq_src_base <= apply_wstrb(seq_src_base, s_axil_wdata, s_axil_wstrb);
|
||||
SEQ_REG_DST_BASE: if (!seq_busy) seq_dst_base <= apply_wstrb(seq_dst_base, s_axil_wdata, s_axil_wstrb);
|
||||
SEQ_REG_GROUPS: if (!seq_busy) seq_groups <= apply_wstrb(seq_groups, s_axil_wdata, s_axil_wstrb);
|
||||
SEQ_REG_MAT_BASE: if (!seq_busy) seq_mat_base <= apply_wstrb(seq_mat_base, s_axil_wdata, s_axil_wstrb);
|
||||
SEQ_REG_SRC_STRIDE: if (!seq_busy) seq_src_stride <= apply_wstrb(seq_src_stride, s_axil_wdata, s_axil_wstrb);
|
||||
SEQ_REG_DST_STRIDE: if (!seq_busy) seq_dst_stride <= apply_wstrb(seq_dst_stride, s_axil_wdata, s_axil_wstrb);
|
||||
endcase
|
||||
end else if (do_write && wr_ch < PORTS) begin
|
||||
case (wr_reg)
|
||||
6'h00: if (!ch_req[wr_ch]) ch_src_addr[wr_ch] <= apply_wstrb(ch_src_addr[wr_ch], s_axil_wdata, s_axil_wstrb);
|
||||
6'h04: if (!ch_req[wr_ch]) ch_dst_addr[wr_ch] <= apply_wstrb(ch_dst_addr[wr_ch], s_axil_wdata, s_axil_wstrb);
|
||||
@@ -407,35 +456,99 @@ module snix_axil_cdma_mux #(
|
||||
logic ep_arready;
|
||||
logic ep_rready;
|
||||
|
||||
typedef enum logic [2:0] {EP_IDLE, EP_AR, EP_READ, EP_AW, EP_WRITE, EP_BRESP, EP_DONE} ep_state_t;
|
||||
ep_state_t ep_state;
|
||||
logic [31:0] ep_axi_addr;
|
||||
logic [31:0] ep_bytes_left;
|
||||
logic [7:0] ep_word_addr_r;
|
||||
logic [ID_WIDTH-1:0] seq_awid;
|
||||
logic [ADDR_WIDTH-1:0] seq_awaddr;
|
||||
logic [7:0] seq_awlen;
|
||||
logic [2:0] seq_awsize;
|
||||
logic [1:0] seq_awburst;
|
||||
logic seq_awlock;
|
||||
logic [3:0] seq_awcache;
|
||||
logic [2:0] seq_awprot;
|
||||
logic [3:0] seq_awqos;
|
||||
logic [USER_WIDTH-1:0] seq_awuser;
|
||||
logic seq_awvalid;
|
||||
logic seq_awready;
|
||||
logic [DATA_WIDTH-1:0] seq_wdata;
|
||||
logic [DATA_WIDTH/8-1:0] seq_wstrb;
|
||||
logic seq_wlast;
|
||||
logic [USER_WIDTH-1:0] seq_wuser;
|
||||
logic seq_wvalid;
|
||||
logic seq_wready;
|
||||
logic seq_bready;
|
||||
logic [ID_WIDTH-1:0] seq_arid;
|
||||
logic [ADDR_WIDTH-1:0] seq_araddr;
|
||||
logic [7:0] seq_arlen;
|
||||
logic [2:0] seq_arsize;
|
||||
logic [1:0] seq_arburst;
|
||||
logic seq_arlock;
|
||||
logic [3:0] seq_arcache;
|
||||
logic [2:0] seq_arprot;
|
||||
logic [3:0] seq_arqos;
|
||||
logic [USER_WIDTH-1:0] seq_aruser;
|
||||
logic seq_arvalid;
|
||||
logic seq_arready;
|
||||
logic seq_rready;
|
||||
|
||||
typedef enum logic [1:0] {EXT_RD_IDLE, EXT_RD_AR, EXT_RD_READ} ext_rd_state_t;
|
||||
typedef enum logic [1:0] {EXT_WR_IDLE, EXT_WR_AW, EXT_WR_WRITE, EXT_WR_BRESP} ext_wr_state_t;
|
||||
// Hardware matmul loop sequencer state. Keep these declarations before the
|
||||
// DMA routing logic because Vivado does not allow forward enum references.
|
||||
typedef enum logic [4:0] {
|
||||
SQ_IDLE,
|
||||
SQ_CLEAR_CRC,
|
||||
SQ_LOAD0,
|
||||
SQ_START0,
|
||||
SQ_LOAD1,
|
||||
SQ_WAIT_DONE,
|
||||
SQ_STORE,
|
||||
SQ_CLEAR_DONE,
|
||||
SQ_START_NEXT,
|
||||
SQ_LOAD_NEXT,
|
||||
SQ_DONE
|
||||
} seq_state_t;
|
||||
|
||||
ext_rd_state_t ext_rd_state;
|
||||
ext_wr_state_t ext_wr_state;
|
||||
logic [ADDR_WIDTH-1:0] ext_rd_addr_r;
|
||||
logic [31:0] ext_rd_bytes_left;
|
||||
logic [7:0] ext_rd_word_addr_r;
|
||||
logic [3:0] ext_rd_ep_id_r;
|
||||
logic [3:0] ext_rd_ep_bank_r;
|
||||
typedef enum logic [3:0] {
|
||||
OP_IDLE,
|
||||
OP_READ_ADDR,
|
||||
OP_READ_DATA,
|
||||
OP_WRITE_ADDR,
|
||||
OP_WRITE_DATA,
|
||||
OP_WRITE_RESP,
|
||||
OP_REG_READ_ADDR,
|
||||
OP_REG_READ_DATA,
|
||||
OP_COPY_START,
|
||||
OP_COPY_WAIT
|
||||
} op_state_t;
|
||||
|
||||
logic [ADDR_WIDTH-1:0] ext_wr_addr_r;
|
||||
logic [31:0] ext_wr_bytes_left;
|
||||
logic [7:0] ext_wr_word_addr_r;
|
||||
logic [3:0] ext_wr_ep_id_r;
|
||||
logic [3:0] ext_wr_ep_bank_r;
|
||||
seq_state_t seq_state;
|
||||
op_state_t op_state;
|
||||
|
||||
wire ext_rd_active = (ext_rd_state != EXT_RD_IDLE);
|
||||
wire ext_wr_active = (ext_wr_state != EXT_WR_IDLE);
|
||||
wire ext_rd_accept = ext_rd_req_valid && ext_rd_req_ready;
|
||||
wire ext_wr_accept = ext_wr_req_valid && ext_wr_req_ready;
|
||||
wire ext_any_busy_or_req = ext_rd_active || ext_wr_active || ext_rd_req_valid || ext_wr_req_valid;
|
||||
wire use_ep_engine = ((state == RUN) && (engine_mode != MODE_MEM2MEM));
|
||||
logic op_start_copy;
|
||||
logic op_start_write;
|
||||
logic op_start_read;
|
||||
logic op_done;
|
||||
logic [31:0] op_src_addr;
|
||||
logic [31:0] op_dst_addr;
|
||||
logic [31:0] op_bytes;
|
||||
logic [31:0] op_write_addr;
|
||||
logic [31:0] op_write_data;
|
||||
logic [31:0] op_read_addr;
|
||||
logic [31:0] op_read_data;
|
||||
logic [31:0] op_src_cur;
|
||||
logic [31:0] op_dst_cur;
|
||||
logic [31:0] op_bytes_left;
|
||||
logic [31:0] op_data_buf;
|
||||
logic op_buf_valid;
|
||||
logic op_copy_store;
|
||||
|
||||
logic [31:0] seq_group_idx;
|
||||
logic [31:0] seq_load_idx;
|
||||
logic [31:0] seq_store_idx;
|
||||
logic seq_compute_bank;
|
||||
logic [31:0] seq_status_data;
|
||||
|
||||
wire use_ep_engine = (state == RUN) && (engine_mode != MODE_MEM2MEM);
|
||||
wire use_seq_engine = seq_busy && (op_state != OP_IDLE) &&
|
||||
(op_state != OP_COPY_START) && (op_state != OP_COPY_WAIT);
|
||||
wire seq_dma_active = seq_busy && ((op_state == OP_COPY_START) || (op_state == OP_COPY_WAIT));
|
||||
|
||||
// Dynamic routing to the engine based on current active channel
|
||||
assign engine_src = ch_src_addr[cur_ch];
|
||||
@@ -451,44 +564,47 @@ module snix_axil_cdma_mux #(
|
||||
assign mm2mm_start = engine_start && (engine_mode == MODE_MEM2MEM);
|
||||
assign ep_start = engine_start && (engine_mode != MODE_MEM2MEM);
|
||||
|
||||
assign core_awready = (!ext_wr_active && !use_ep_engine) && mm2mm_awready;
|
||||
assign core_wready = (!ext_wr_active && !use_ep_engine) && mm2mm_wready;
|
||||
assign core_arready = (!ext_rd_active && !use_ep_engine) && mm2mm_arready;
|
||||
assign ep_awready = (!ext_wr_active && use_ep_engine) && mm2mm_awready;
|
||||
assign ep_wready = (!ext_wr_active && use_ep_engine) && mm2mm_wready;
|
||||
assign ep_arready = (!ext_rd_active && use_ep_engine) && mm2mm_arready;
|
||||
assign core_awready = (!use_seq_engine && !use_ep_engine) && mm2mm_awready;
|
||||
assign core_wready = (!use_seq_engine && !use_ep_engine) && mm2mm_wready;
|
||||
assign core_arready = (!use_seq_engine && !use_ep_engine) && mm2mm_arready;
|
||||
assign ep_awready = (!use_seq_engine && use_ep_engine) && mm2mm_awready;
|
||||
assign ep_wready = (!use_seq_engine && use_ep_engine) && mm2mm_wready;
|
||||
assign ep_arready = (!use_seq_engine && use_ep_engine) && mm2mm_arready;
|
||||
assign seq_awready = use_seq_engine && mm2mm_awready;
|
||||
assign seq_wready = use_seq_engine && mm2mm_wready;
|
||||
assign seq_arready = use_seq_engine && mm2mm_arready;
|
||||
|
||||
assign mm2mm_awid = ext_wr_active ? '0 : (use_ep_engine ? ep_awid : core_awid);
|
||||
assign mm2mm_awaddr = ext_wr_active ? ext_wr_addr_r : (use_ep_engine ? ep_awaddr : core_awaddr);
|
||||
assign mm2mm_awlen = ext_wr_active ? (((ext_wr_bytes_left[31:2] == 30'd0) ? 8'd1 : ext_wr_bytes_left[9:2]) - 8'd1) : (use_ep_engine ? ep_awlen : core_awlen);
|
||||
assign mm2mm_awsize = ext_wr_active ? 3'd2 : (use_ep_engine ? ep_awsize : core_awsize);
|
||||
assign mm2mm_awburst = ext_wr_active ? 2'b01 : (use_ep_engine ? ep_awburst : core_awburst);
|
||||
assign mm2mm_awlock = ext_wr_active ? 1'b0 : (use_ep_engine ? ep_awlock : core_awlock);
|
||||
assign mm2mm_awcache = ext_wr_active ? 4'b0 : (use_ep_engine ? ep_awcache : core_awcache);
|
||||
assign mm2mm_awprot = ext_wr_active ? 3'b0 : (use_ep_engine ? ep_awprot : core_awprot);
|
||||
assign mm2mm_awqos = ext_wr_active ? 4'b0 : (use_ep_engine ? ep_awqos : core_awqos);
|
||||
assign mm2mm_awuser = ext_wr_active ? '0 : (use_ep_engine ? ep_awuser : core_awuser);
|
||||
assign mm2mm_awvalid = ext_wr_active ? (ext_wr_state == EXT_WR_AW) : (use_ep_engine ? ep_awvalid : core_awvalid);
|
||||
assign mm2mm_awid = use_seq_engine ? seq_awid : (use_ep_engine ? ep_awid : core_awid);
|
||||
assign mm2mm_awaddr = use_seq_engine ? seq_awaddr : (use_ep_engine ? ep_awaddr : core_awaddr);
|
||||
assign mm2mm_awlen = use_seq_engine ? seq_awlen : (use_ep_engine ? ep_awlen : core_awlen);
|
||||
assign mm2mm_awsize = use_seq_engine ? seq_awsize : (use_ep_engine ? ep_awsize : core_awsize);
|
||||
assign mm2mm_awburst = use_seq_engine ? seq_awburst : (use_ep_engine ? ep_awburst : core_awburst);
|
||||
assign mm2mm_awlock = use_seq_engine ? seq_awlock : (use_ep_engine ? ep_awlock : core_awlock);
|
||||
assign mm2mm_awcache = use_seq_engine ? seq_awcache : (use_ep_engine ? ep_awcache : core_awcache);
|
||||
assign mm2mm_awprot = use_seq_engine ? seq_awprot : (use_ep_engine ? ep_awprot : core_awprot);
|
||||
assign mm2mm_awqos = use_seq_engine ? seq_awqos : (use_ep_engine ? ep_awqos : core_awqos);
|
||||
assign mm2mm_awuser = use_seq_engine ? seq_awuser : (use_ep_engine ? ep_awuser : core_awuser);
|
||||
assign mm2mm_awvalid = use_seq_engine ? seq_awvalid : (use_ep_engine ? ep_awvalid : core_awvalid);
|
||||
|
||||
assign mm2mm_wdata = ext_wr_active ? ep_rd_data : (use_ep_engine ? ep_wdata : core_wdata);
|
||||
assign mm2mm_wstrb = ext_wr_active ? {{(DATA_WIDTH/8){1'b1}}} : (use_ep_engine ? ep_wstrb : core_wstrb);
|
||||
assign mm2mm_wlast = ext_wr_active ? ((ext_wr_bytes_left <= 32'd4) && mm2mm_wvalid) : (use_ep_engine ? ep_wlast : core_wlast);
|
||||
assign mm2mm_wuser = ext_wr_active ? '0 : (use_ep_engine ? ep_wuser : core_wuser);
|
||||
assign mm2mm_wvalid = ext_wr_active ? ((ext_wr_state == EXT_WR_WRITE) && ep_rd_ready) : (use_ep_engine ? ep_wvalid : core_wvalid);
|
||||
assign mm2mm_bready = ext_wr_active ? (ext_wr_state == EXT_WR_BRESP) : (use_ep_engine ? ep_bready : core_bready);
|
||||
assign mm2mm_wdata = use_seq_engine ? seq_wdata : (use_ep_engine ? ep_wdata : core_wdata);
|
||||
assign mm2mm_wstrb = use_seq_engine ? seq_wstrb : (use_ep_engine ? ep_wstrb : core_wstrb);
|
||||
assign mm2mm_wlast = use_seq_engine ? seq_wlast : (use_ep_engine ? ep_wlast : core_wlast);
|
||||
assign mm2mm_wuser = use_seq_engine ? seq_wuser : (use_ep_engine ? ep_wuser : core_wuser);
|
||||
assign mm2mm_wvalid = use_seq_engine ? seq_wvalid : (use_ep_engine ? ep_wvalid : core_wvalid);
|
||||
assign mm2mm_bready = use_seq_engine ? seq_bready : (use_ep_engine ? ep_bready : core_bready);
|
||||
|
||||
assign mm2mm_arid = ext_rd_active ? '0 : (use_ep_engine ? ep_arid : core_arid);
|
||||
assign mm2mm_araddr = ext_rd_active ? ext_rd_addr_r : (use_ep_engine ? ep_araddr : core_araddr);
|
||||
assign mm2mm_arlen = ext_rd_active ? (((ext_rd_bytes_left[31:2] == 30'd0) ? 8'd1 : ext_rd_bytes_left[9:2]) - 8'd1) : (use_ep_engine ? ep_arlen : core_arlen);
|
||||
assign mm2mm_arsize = ext_rd_active ? 3'd2 : (use_ep_engine ? ep_arsize : core_arsize);
|
||||
assign mm2mm_arburst = ext_rd_active ? 2'b01 : (use_ep_engine ? ep_arburst : core_arburst);
|
||||
assign mm2mm_arlock = ext_rd_active ? 1'b0 : (use_ep_engine ? ep_arlock : core_arlock);
|
||||
assign mm2mm_arcache = ext_rd_active ? 4'b0 : (use_ep_engine ? ep_arcache : core_arcache);
|
||||
assign mm2mm_arprot = ext_rd_active ? 3'b0 : (use_ep_engine ? ep_arprot : core_arprot);
|
||||
assign mm2mm_arqos = ext_rd_active ? 4'b0 : (use_ep_engine ? ep_arqos : core_arqos);
|
||||
assign mm2mm_aruser = ext_rd_active ? '0 : (use_ep_engine ? ep_aruser : core_aruser);
|
||||
assign mm2mm_arvalid = ext_rd_active ? (ext_rd_state == EXT_RD_AR) : (use_ep_engine ? ep_arvalid : core_arvalid);
|
||||
assign mm2mm_rready = ext_rd_active ? ((ext_rd_state == EXT_RD_READ) && ep_wr_ready) : (use_ep_engine ? ep_rready : core_rready);
|
||||
assign mm2mm_arid = use_seq_engine ? seq_arid : (use_ep_engine ? ep_arid : core_arid);
|
||||
assign mm2mm_araddr = use_seq_engine ? seq_araddr : (use_ep_engine ? ep_araddr : core_araddr);
|
||||
assign mm2mm_arlen = use_seq_engine ? seq_arlen : (use_ep_engine ? ep_arlen : core_arlen);
|
||||
assign mm2mm_arsize = use_seq_engine ? seq_arsize : (use_ep_engine ? ep_arsize : core_arsize);
|
||||
assign mm2mm_arburst = use_seq_engine ? seq_arburst : (use_ep_engine ? ep_arburst : core_arburst);
|
||||
assign mm2mm_arlock = use_seq_engine ? seq_arlock : (use_ep_engine ? ep_arlock : core_arlock);
|
||||
assign mm2mm_arcache = use_seq_engine ? seq_arcache : (use_ep_engine ? ep_arcache : core_arcache);
|
||||
assign mm2mm_arprot = use_seq_engine ? seq_arprot : (use_ep_engine ? ep_arprot : core_arprot);
|
||||
assign mm2mm_arqos = use_seq_engine ? seq_arqos : (use_ep_engine ? ep_arqos : core_arqos);
|
||||
assign mm2mm_aruser = use_seq_engine ? seq_aruser : (use_ep_engine ? ep_aruser : core_aruser);
|
||||
assign mm2mm_arvalid = use_seq_engine ? seq_arvalid : (use_ep_engine ? ep_arvalid : core_arvalid);
|
||||
assign mm2mm_rready = use_seq_engine ? seq_rready : (use_ep_engine ? ep_rready : core_rready);
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (!rst_n) begin
|
||||
@@ -503,7 +619,7 @@ module snix_axil_cdma_mux #(
|
||||
|
||||
case (state)
|
||||
IDLE: begin
|
||||
if (ext_any_busy_or_req) begin
|
||||
if (seq_busy) begin
|
||||
state <= IDLE;
|
||||
end else for (int i = 0; i < PORTS; i++) begin
|
||||
logic [CH_BITS:0] check_ch_ext;
|
||||
@@ -550,13 +666,13 @@ module snix_axil_cdma_mux #(
|
||||
) u_core_engine (
|
||||
.clk (clk),
|
||||
.rst_n (rst_n),
|
||||
.ctrl_start (mm2mm_start),
|
||||
.ctrl_start ((op_state == OP_COPY_START) ? 1'b1 : mm2mm_start),
|
||||
.ctrl_stop (1'b0), // Tied off; can be wired if global abort is needed
|
||||
.ctrl_src_addr (engine_src),
|
||||
.ctrl_dst_addr (engine_dst),
|
||||
.ctrl_len (engine_len),
|
||||
.ctrl_size (engine_size),
|
||||
.ctrl_transfer_len (engine_bytes),
|
||||
.ctrl_src_addr (seq_dma_active ? op_src_cur : engine_src),
|
||||
.ctrl_dst_addr (seq_dma_active ? op_dst_cur : engine_dst),
|
||||
.ctrl_len (seq_dma_active ? 8'd63 : engine_len),
|
||||
.ctrl_size (seq_dma_active ? 3'd2 : engine_size),
|
||||
.ctrl_transfer_len (seq_dma_active ? op_bytes_left : engine_bytes),
|
||||
.ctrl_done (mm2mm_done),
|
||||
// AXI4 Port Connections
|
||||
.mm2mm_awid (core_awid), .mm2mm_awaddr (core_awaddr),
|
||||
@@ -583,106 +699,320 @@ module snix_axil_cdma_mux #(
|
||||
.mm2mm_rready (core_rready)
|
||||
);
|
||||
|
||||
wire [7:0] ep_beats_total = (engine_bytes[31:2] == 30'd0) ? 8'd1 : engine_bytes[9:2];
|
||||
wire [7:0] ep_axi_len = ep_beats_total - 8'd1;
|
||||
wire ep_mode_mem2ep = (engine_mode == MODE_MEM2EP);
|
||||
wire ep_mode_ep2mem = (engine_mode == MODE_EP2MEM);
|
||||
wire ep_rd_done_fire = (ep_state == EP_READ) && mm2mm_rvalid && ep_rready && mm2mm_rlast;
|
||||
wire ep_wr_done_fire = (ep_state == EP_BRESP) && mm2mm_bvalid && ep_bready;
|
||||
wire ep_done_fast = ep_rd_done_fire || ep_wr_done_fire;
|
||||
wire ext_rd_done_fire = (ext_rd_state == EXT_RD_READ) && mm2mm_rvalid && mm2mm_rready && mm2mm_rlast;
|
||||
wire ext_wr_done_fire = (ext_wr_state == EXT_WR_BRESP) && mm2mm_bvalid && mm2mm_bready;
|
||||
wire ext_wr_w_fire = (ext_wr_state == EXT_WR_WRITE) && mm2mm_wvalid && mm2mm_wready;
|
||||
// ==========================================
|
||||
// Hardware matmul loop sequencer
|
||||
// ==========================================
|
||||
wire seq_has_more_load = (seq_load_idx < seq_groups);
|
||||
wire [31:0] seq_src_addr_for_load = seq_src_base + (seq_load_idx * seq_src_stride);
|
||||
wire [31:0] seq_dst_addr_for_load = seq_mat_base + (seq_load_idx[0] ? MAT_B1_AB_OFF : MAT_B0_AB_OFF);
|
||||
wire [31:0] seq_src_addr_for_store = seq_mat_base + (seq_store_idx[0] ? MAT_B1_C_OFF : MAT_B0_C_OFF);
|
||||
wire [31:0] seq_dst_addr_for_store = seq_dst_base + (seq_store_idx * seq_dst_stride);
|
||||
wire [31:0] seq_start_value_for_bank = seq_compute_bank ? MAT_CTRL_START_B1 : MAT_CTRL_START_B0;
|
||||
wire [31:0] seq_start_value_for_loaded_bank =
|
||||
(seq_load_idx[0] == 1'b0) ? MAT_CTRL_START_B1 : MAT_CTRL_START_B0;
|
||||
|
||||
// ==========================================
|
||||
// Generic external endpoint requester
|
||||
// ==========================================
|
||||
assign ext_rd_req_ready = (state == IDLE) && (ep_state == EP_IDLE) && !ext_rd_active;
|
||||
assign ext_wr_req_ready = (state == IDLE) && (ep_state == EP_IDLE) && !ext_wr_active;
|
||||
assign ext_rd_req_done = ext_rd_done_fire;
|
||||
assign ext_wr_req_done = ext_wr_done_fire;
|
||||
assign seq_awid = '0;
|
||||
assign seq_awsize = 3'd2;
|
||||
assign seq_awburst = 2'b01;
|
||||
assign seq_awlock = 1'b0;
|
||||
assign seq_awcache = 4'b0;
|
||||
assign seq_awprot = 3'b0;
|
||||
assign seq_awqos = 4'b0;
|
||||
assign seq_awuser = '0;
|
||||
assign seq_wstrb = {{(DATA_WIDTH/8){1'b1}}};
|
||||
assign seq_wuser = '0;
|
||||
assign seq_arid = '0;
|
||||
assign seq_arsize = 3'd2;
|
||||
assign seq_arburst = 2'b01;
|
||||
assign seq_arlock = 1'b0;
|
||||
assign seq_arcache = 4'b0;
|
||||
assign seq_arprot = 3'b0;
|
||||
assign seq_arqos = 4'b0;
|
||||
assign seq_aruser = '0;
|
||||
|
||||
assign seq_araddr = (op_state == OP_REG_READ_ADDR) ? op_read_addr : op_src_cur;
|
||||
assign seq_arlen = (op_state == OP_REG_READ_ADDR) ? 8'd0 : 8'd0;
|
||||
assign seq_arvalid = (op_state == OP_READ_ADDR) || (op_state == OP_REG_READ_ADDR);
|
||||
assign seq_rready = (op_state == OP_REG_READ_DATA) ||
|
||||
((op_state == OP_READ_DATA) && !op_buf_valid);
|
||||
|
||||
assign seq_awaddr = (op_state == OP_WRITE_ADDR && op_copy_store) ? op_dst_cur : op_write_addr;
|
||||
assign seq_awlen = 8'd0;
|
||||
assign seq_awvalid = (op_state == OP_WRITE_ADDR);
|
||||
assign seq_wdata = op_copy_store ? op_data_buf : op_write_data;
|
||||
assign seq_wlast = 1'b1;
|
||||
assign seq_wvalid = (op_state == OP_WRITE_DATA) && (!op_copy_store || op_buf_valid);
|
||||
assign seq_bready = (op_state == OP_WRITE_RESP);
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (!rst_n) begin
|
||||
ext_rd_state <= EXT_RD_IDLE;
|
||||
ext_rd_addr_r <= '0;
|
||||
ext_rd_bytes_left <= '0;
|
||||
ext_rd_word_addr_r <= '0;
|
||||
ext_rd_ep_id_r <= '0;
|
||||
ext_rd_ep_bank_r <= '0;
|
||||
op_state <= OP_IDLE;
|
||||
op_done <= 1'b0;
|
||||
op_src_cur <= '0;
|
||||
op_dst_cur <= '0;
|
||||
op_bytes_left <= '0;
|
||||
op_data_buf <= '0;
|
||||
op_buf_valid <= 1'b0;
|
||||
op_copy_store <= 1'b0;
|
||||
op_read_data <= '0;
|
||||
end else begin
|
||||
case (ext_rd_state)
|
||||
EXT_RD_IDLE: begin
|
||||
if (ext_rd_accept) begin
|
||||
ext_rd_addr_r <= ext_rd_req_src;
|
||||
ext_rd_bytes_left <= ext_rd_req_bytes;
|
||||
ext_rd_word_addr_r <= ext_rd_req_ep_word_off;
|
||||
ext_rd_ep_id_r <= ext_rd_req_ep_id;
|
||||
ext_rd_ep_bank_r <= ext_rd_req_ep_bank;
|
||||
ext_rd_state <= EXT_RD_AR;
|
||||
op_done <= 1'b0;
|
||||
|
||||
case (op_state)
|
||||
OP_IDLE: begin
|
||||
op_buf_valid <= 1'b0;
|
||||
if (op_start_copy) begin
|
||||
op_src_cur <= op_src_addr;
|
||||
op_dst_cur <= op_dst_addr;
|
||||
op_bytes_left <= op_bytes;
|
||||
op_copy_store <= 1'b1;
|
||||
op_state <= OP_COPY_START;
|
||||
end else if (op_start_write) begin
|
||||
op_copy_store <= 1'b0;
|
||||
op_state <= OP_WRITE_ADDR;
|
||||
end else if (op_start_read) begin
|
||||
op_copy_store <= 1'b0;
|
||||
op_state <= OP_REG_READ_ADDR;
|
||||
end
|
||||
end
|
||||
|
||||
EXT_RD_AR: begin
|
||||
if (mm2mm_arvalid && mm2mm_arready)
|
||||
ext_rd_state <= EXT_RD_READ;
|
||||
OP_READ_ADDR: begin
|
||||
if (seq_arvalid && seq_arready)
|
||||
op_state <= OP_READ_DATA;
|
||||
end
|
||||
|
||||
EXT_RD_READ: begin
|
||||
if (mm2mm_rvalid && mm2mm_rready) begin
|
||||
ext_rd_word_addr_r <= ext_rd_word_addr_r + 8'd1;
|
||||
ext_rd_bytes_left <= (ext_rd_bytes_left > 32'd4) ? (ext_rd_bytes_left - 32'd4) : 32'd0;
|
||||
if (mm2mm_rlast)
|
||||
ext_rd_state <= EXT_RD_IDLE;
|
||||
OP_READ_DATA: begin
|
||||
if (mm2mm_rvalid && seq_rready) begin
|
||||
op_data_buf <= mm2mm_rdata;
|
||||
op_buf_valid <= 1'b1;
|
||||
op_state <= OP_WRITE_ADDR;
|
||||
end
|
||||
end
|
||||
|
||||
default: ext_rd_state <= EXT_RD_IDLE;
|
||||
OP_WRITE_ADDR: begin
|
||||
if (seq_awvalid && seq_awready)
|
||||
op_state <= OP_WRITE_DATA;
|
||||
end
|
||||
|
||||
OP_WRITE_DATA: begin
|
||||
if (seq_wvalid && seq_wready) begin
|
||||
op_buf_valid <= 1'b0;
|
||||
op_state <= OP_WRITE_RESP;
|
||||
end
|
||||
end
|
||||
|
||||
OP_WRITE_RESP: begin
|
||||
if (mm2mm_bvalid && seq_bready) begin
|
||||
if (op_copy_store && (op_bytes_left > 32'd4)) begin
|
||||
op_src_cur <= op_src_cur + 32'd4;
|
||||
op_dst_cur <= op_dst_cur + 32'd4;
|
||||
op_bytes_left <= op_bytes_left - 32'd4;
|
||||
op_state <= OP_READ_ADDR;
|
||||
end else begin
|
||||
op_done <= 1'b1;
|
||||
op_state <= OP_IDLE;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
OP_REG_READ_ADDR: begin
|
||||
if (seq_arvalid && seq_arready)
|
||||
op_state <= OP_REG_READ_DATA;
|
||||
end
|
||||
|
||||
OP_REG_READ_DATA: begin
|
||||
if (mm2mm_rvalid && seq_rready) begin
|
||||
op_read_data <= mm2mm_rdata;
|
||||
op_done <= 1'b1;
|
||||
op_state <= OP_IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
OP_COPY_START: begin
|
||||
op_state <= OP_COPY_WAIT;
|
||||
end
|
||||
|
||||
OP_COPY_WAIT: begin
|
||||
if (mm2mm_done) begin
|
||||
op_done <= 1'b1;
|
||||
op_state <= OP_IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
default: op_state <= OP_IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (!rst_n) begin
|
||||
ext_wr_state <= EXT_WR_IDLE;
|
||||
ext_wr_addr_r <= '0;
|
||||
ext_wr_bytes_left <= '0;
|
||||
ext_wr_word_addr_r <= '0;
|
||||
ext_wr_ep_id_r <= '0;
|
||||
ext_wr_ep_bank_r <= '0;
|
||||
seq_state <= SQ_IDLE;
|
||||
seq_busy <= 1'b0;
|
||||
seq_done_flag <= 1'b0;
|
||||
op_start_copy <= 1'b0;
|
||||
op_start_write <= 1'b0;
|
||||
op_start_read <= 1'b0;
|
||||
op_src_addr <= '0;
|
||||
op_dst_addr <= '0;
|
||||
op_bytes <= '0;
|
||||
op_write_addr <= '0;
|
||||
op_write_data <= '0;
|
||||
op_read_addr <= '0;
|
||||
seq_group_idx <= '0;
|
||||
seq_load_idx <= '0;
|
||||
seq_store_idx <= '0;
|
||||
seq_compute_bank <= 1'b0;
|
||||
seq_status_data <= '0;
|
||||
end else begin
|
||||
case (ext_wr_state)
|
||||
EXT_WR_IDLE: begin
|
||||
if (ext_wr_accept) begin
|
||||
ext_wr_addr_r <= ext_wr_req_dst;
|
||||
ext_wr_bytes_left <= ext_wr_req_bytes;
|
||||
ext_wr_word_addr_r <= ext_wr_req_ep_word_off;
|
||||
ext_wr_ep_id_r <= ext_wr_req_ep_id;
|
||||
ext_wr_ep_bank_r <= ext_wr_req_ep_bank;
|
||||
ext_wr_state <= EXT_WR_AW;
|
||||
op_start_copy <= 1'b0;
|
||||
op_start_write <= 1'b0;
|
||||
op_start_read <= 1'b0;
|
||||
|
||||
if (seq_done_clear_req)
|
||||
seq_done_flag <= 1'b0;
|
||||
|
||||
case (seq_state)
|
||||
SQ_IDLE: begin
|
||||
seq_busy <= 1'b0;
|
||||
if (seq_start_req && (seq_groups != 32'd0)) begin
|
||||
seq_busy <= 1'b1;
|
||||
seq_done_flag <= 1'b0;
|
||||
seq_group_idx <= 32'd0;
|
||||
seq_load_idx <= 32'd0;
|
||||
seq_store_idx <= 32'd0;
|
||||
seq_compute_bank <= 1'b0;
|
||||
op_write_addr <= seq_mat_base + MAT_CRC_OFF;
|
||||
op_write_data <= 32'd0;
|
||||
op_start_write <= 1'b1;
|
||||
seq_state <= SQ_CLEAR_CRC;
|
||||
end
|
||||
end
|
||||
|
||||
EXT_WR_AW: begin
|
||||
if (mm2mm_awvalid && mm2mm_awready)
|
||||
ext_wr_state <= EXT_WR_WRITE;
|
||||
end
|
||||
|
||||
EXT_WR_WRITE: begin
|
||||
if (ext_wr_w_fire) begin
|
||||
ext_wr_word_addr_r <= ext_wr_word_addr_r + 8'd1;
|
||||
ext_wr_bytes_left <= (ext_wr_bytes_left > 32'd4) ? (ext_wr_bytes_left - 32'd4) : 32'd0;
|
||||
if (mm2mm_wlast)
|
||||
ext_wr_state <= EXT_WR_BRESP;
|
||||
SQ_CLEAR_CRC: begin
|
||||
if (op_done) begin
|
||||
op_src_addr <= seq_src_base;
|
||||
op_dst_addr <= seq_mat_base + MAT_B0_AB_OFF;
|
||||
op_bytes <= MAT_AB_BYTES;
|
||||
op_start_copy <= 1'b1;
|
||||
seq_load_idx <= 32'd1;
|
||||
seq_state <= SQ_LOAD0;
|
||||
end
|
||||
end
|
||||
|
||||
EXT_WR_BRESP: begin
|
||||
if (mm2mm_bvalid && mm2mm_bready)
|
||||
ext_wr_state <= EXT_WR_IDLE;
|
||||
SQ_LOAD0: begin
|
||||
if (op_done) begin
|
||||
op_write_addr <= seq_mat_base + MAT_CTRL_OFF;
|
||||
op_write_data <= MAT_CTRL_START_B0;
|
||||
op_start_write <= 1'b1;
|
||||
seq_state <= SQ_START0;
|
||||
end
|
||||
end
|
||||
|
||||
default: ext_wr_state <= EXT_WR_IDLE;
|
||||
SQ_START0: begin
|
||||
if (op_done) begin
|
||||
if (seq_load_idx < seq_groups) begin
|
||||
op_src_addr <= seq_src_base + (seq_load_idx * seq_src_stride);
|
||||
op_dst_addr <= seq_mat_base + MAT_B1_AB_OFF;
|
||||
op_bytes <= MAT_AB_BYTES;
|
||||
op_start_copy <= 1'b1;
|
||||
seq_load_idx <= seq_load_idx + 32'd1;
|
||||
seq_state <= SQ_LOAD1;
|
||||
end else begin
|
||||
op_read_addr <= seq_mat_base + MAT_STATUS_OFF;
|
||||
op_start_read <= 1'b1;
|
||||
seq_state <= SQ_WAIT_DONE;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
SQ_LOAD1: begin
|
||||
if (op_done) begin
|
||||
op_write_addr <= seq_mat_base + MAT_CTRL_OFF;
|
||||
op_write_data <= seq_start_value_for_loaded_bank;
|
||||
op_start_write <= 1'b1;
|
||||
seq_state <= SQ_START_NEXT;
|
||||
end
|
||||
end
|
||||
|
||||
SQ_WAIT_DONE: begin
|
||||
if (op_done) begin
|
||||
seq_status_data <= op_read_data;
|
||||
if ((op_read_data & MAT_STATUS_DONE_BIT) != 32'd0) begin
|
||||
seq_store_idx <= seq_group_idx;
|
||||
if ((seq_group_idx + 32'd1) >= seq_groups) begin
|
||||
op_src_addr <= seq_mat_base + (seq_compute_bank ? MAT_B1_C_OFF : MAT_B0_C_OFF);
|
||||
op_dst_addr <= seq_dst_base + (seq_group_idx * seq_dst_stride);
|
||||
op_bytes <= MAT_C_BYTES;
|
||||
op_start_copy <= 1'b1;
|
||||
seq_state <= SQ_STORE;
|
||||
end else begin
|
||||
op_write_addr <= seq_mat_base + MAT_STATUS_OFF;
|
||||
op_write_data <= MAT_STATUS_DONE_CLR;
|
||||
op_start_write <= 1'b1;
|
||||
seq_state <= SQ_CLEAR_DONE;
|
||||
end
|
||||
end else begin
|
||||
op_read_addr <= seq_mat_base + MAT_STATUS_OFF;
|
||||
op_start_read <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
SQ_STORE: begin
|
||||
if (op_done) begin
|
||||
if ((seq_store_idx + 32'd1) >= seq_groups) begin
|
||||
seq_state <= SQ_DONE;
|
||||
end else if (seq_has_more_load) begin
|
||||
op_src_addr <= seq_src_addr_for_load;
|
||||
op_dst_addr <= seq_dst_addr_for_load;
|
||||
op_bytes <= MAT_AB_BYTES;
|
||||
op_start_copy <= 1'b1;
|
||||
seq_load_idx <= seq_load_idx + 32'd1;
|
||||
seq_state <= SQ_LOAD_NEXT;
|
||||
end else begin
|
||||
op_read_addr <= seq_mat_base + MAT_STATUS_OFF;
|
||||
op_start_read <= 1'b1;
|
||||
seq_state <= SQ_WAIT_DONE;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
SQ_CLEAR_DONE: begin
|
||||
if (op_done) begin
|
||||
seq_group_idx <= seq_group_idx + 32'd1;
|
||||
seq_compute_bank <= ~seq_compute_bank;
|
||||
op_src_addr <= seq_src_addr_for_store;
|
||||
op_dst_addr <= seq_dst_addr_for_store;
|
||||
op_bytes <= MAT_C_BYTES;
|
||||
op_start_copy <= 1'b1;
|
||||
seq_state <= SQ_STORE;
|
||||
end
|
||||
end
|
||||
|
||||
SQ_START_NEXT: begin
|
||||
if (op_done) begin
|
||||
op_read_addr <= seq_mat_base + MAT_STATUS_OFF;
|
||||
op_start_read <= 1'b1;
|
||||
seq_state <= SQ_WAIT_DONE;
|
||||
end
|
||||
end
|
||||
|
||||
SQ_LOAD_NEXT: begin
|
||||
if (op_done) begin
|
||||
op_write_addr <= seq_mat_base + MAT_CTRL_OFF;
|
||||
op_write_data <= seq_start_value_for_loaded_bank;
|
||||
op_start_write <= 1'b1;
|
||||
seq_state <= SQ_START_NEXT;
|
||||
end
|
||||
end
|
||||
|
||||
SQ_DONE: begin
|
||||
seq_busy <= 1'b0;
|
||||
seq_done_flag <= 1'b1;
|
||||
seq_state <= SQ_IDLE;
|
||||
end
|
||||
|
||||
default: seq_state <= SQ_IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
@@ -690,6 +1020,17 @@ module snix_axil_cdma_mux #(
|
||||
// ==========================================
|
||||
// Endpoint transfer engine (32-bit only in this SoC integration)
|
||||
// ==========================================
|
||||
typedef enum logic [2:0] {EP_IDLE, EP_AR, EP_READ, EP_AW, EP_WRITE, EP_BRESP, EP_DONE} ep_state_t;
|
||||
ep_state_t ep_state;
|
||||
logic [31:0] ep_axi_addr;
|
||||
logic [31:0] ep_bytes_left;
|
||||
logic [7:0] ep_word_addr_r;
|
||||
|
||||
wire [7:0] ep_beats_total = (engine_bytes[31:2] == 30'd0) ? 8'd1 : engine_bytes[9:2];
|
||||
wire [7:0] ep_axi_len = ep_beats_total - 8'd1;
|
||||
wire ep_mode_mem2ep = (engine_mode == MODE_MEM2EP);
|
||||
wire ep_mode_ep2mem = (engine_mode == MODE_EP2MEM);
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (!rst_n) begin
|
||||
ep_state <= EP_IDLE;
|
||||
@@ -719,10 +1060,8 @@ module snix_axil_cdma_mux #(
|
||||
if (mm2mm_rvalid && ep_rready) begin
|
||||
ep_word_addr_r <= ep_word_addr_r + 8'd1;
|
||||
ep_bytes_left <= (ep_bytes_left > 32'd4) ? (ep_bytes_left - 32'd4) : 32'd0;
|
||||
if (mm2mm_rlast) begin
|
||||
ep_done <= 1'b1;
|
||||
ep_state <= EP_IDLE;
|
||||
end
|
||||
if (mm2mm_rlast)
|
||||
ep_state <= EP_DONE;
|
||||
end
|
||||
end
|
||||
|
||||
@@ -741,10 +1080,8 @@ module snix_axil_cdma_mux #(
|
||||
end
|
||||
|
||||
EP_BRESP: begin
|
||||
if (mm2mm_bvalid && ep_bready) begin
|
||||
ep_done <= 1'b1;
|
||||
ep_state <= EP_IDLE;
|
||||
end
|
||||
if (mm2mm_bvalid && ep_bready)
|
||||
ep_state <= EP_DONE;
|
||||
end
|
||||
|
||||
EP_DONE: begin
|
||||
@@ -770,11 +1107,10 @@ module snix_axil_cdma_mux #(
|
||||
assign ep_arvalid = (ep_state == EP_AR);
|
||||
assign ep_rready = (ep_state == EP_READ) && ep_wr_ready;
|
||||
|
||||
assign ep_wr_valid = ext_rd_active ? ((ext_rd_state == EXT_RD_READ) && mm2mm_rvalid) :
|
||||
((ep_state == EP_READ) && mm2mm_rvalid && ep_mode_mem2ep);
|
||||
assign ep_wr_id = ext_rd_active ? ext_rd_ep_id_r : engine_ep_id;
|
||||
assign ep_wr_bank = ext_rd_active ? ext_rd_ep_bank_r : engine_ep_bank;
|
||||
assign ep_wr_word_addr = ext_rd_active ? ext_rd_word_addr_r : ep_word_addr_r;
|
||||
assign ep_wr_valid = (ep_state == EP_READ) && mm2mm_rvalid && ep_mode_mem2ep;
|
||||
assign ep_wr_id = engine_ep_id;
|
||||
assign ep_wr_bank = engine_ep_bank;
|
||||
assign ep_wr_word_addr = ep_word_addr_r;
|
||||
assign ep_wr_data = mm2mm_rdata[31:0];
|
||||
|
||||
assign ep_awid = '0;
|
||||
@@ -795,10 +1131,9 @@ module snix_axil_cdma_mux #(
|
||||
assign ep_wvalid = (ep_state == EP_WRITE) && ep_mode_ep2mem && ep_rd_ready;
|
||||
assign ep_bready = (ep_state == EP_BRESP);
|
||||
|
||||
assign ep_rd_valid = ext_wr_active ? ((ext_wr_state == EXT_WR_WRITE) && mm2mm_wready) :
|
||||
((ep_state == EP_WRITE) && ep_mode_ep2mem && ep_wready);
|
||||
assign ep_rd_id = ext_wr_active ? ext_wr_ep_id_r : engine_ep_id;
|
||||
assign ep_rd_bank = ext_wr_active ? ext_wr_ep_bank_r : engine_ep_bank;
|
||||
assign ep_rd_word_addr = ext_wr_active ? ext_wr_word_addr_r : ep_word_addr_r;
|
||||
assign ep_rd_valid = (ep_state == EP_WRITE) && ep_mode_ep2mem && ep_wready;
|
||||
assign ep_rd_id = engine_ep_id;
|
||||
assign ep_rd_bank = engine_ep_bank;
|
||||
assign ep_rd_word_addr = ep_word_addr_r;
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,32 +0,0 @@
|
||||
//----------------------------------------------------------------------
|
||||
// Butterfly: Add/Sub and Scaling
|
||||
//----------------------------------------------------------------------
|
||||
module Butterfly #(
|
||||
parameter WIDTH = 16,
|
||||
parameter RH = 0 // Round Half Up
|
||||
)(
|
||||
input signed [WIDTH-1:0] x0_re, // Input Data #0 (Real)
|
||||
input signed [WIDTH-1:0] x0_im, // Input Data #0 (Imag)
|
||||
input signed [WIDTH-1:0] x1_re, // Input Data #1 (Real)
|
||||
input signed [WIDTH-1:0] x1_im, // Input Data #1 (Imag)
|
||||
output signed [WIDTH-1:0] y0_re, // Output Data #0 (Real)
|
||||
output signed [WIDTH-1:0] y0_im, // Output Data #0 (Imag)
|
||||
output signed [WIDTH-1:0] y1_re, // Output Data #1 (Real)
|
||||
output signed [WIDTH-1:0] y1_im // Output Data #1 (Imag)
|
||||
);
|
||||
|
||||
wire signed [WIDTH:0] add_re, add_im, sub_re, sub_im;
|
||||
|
||||
// Add/Sub
|
||||
assign add_re = x0_re + x1_re;
|
||||
assign add_im = x0_im + x1_im;
|
||||
assign sub_re = x0_re - x1_re;
|
||||
assign sub_im = x0_im - x1_im;
|
||||
|
||||
// Scaling
|
||||
assign y0_re = (add_re + RH) >>> 1;
|
||||
assign y0_im = (add_im + RH) >>> 1;
|
||||
assign y1_re = (sub_re + RH) >>> 1;
|
||||
assign y1_im = (sub_im + RH) >>> 1;
|
||||
|
||||
endmodule
|
||||
@@ -1,34 +0,0 @@
|
||||
//----------------------------------------------------------------------
|
||||
// DelayBuffer: Generate Constant Delay
|
||||
//----------------------------------------------------------------------
|
||||
module DelayBuffer #(
|
||||
parameter DEPTH = 32,
|
||||
parameter WIDTH = 16
|
||||
)(
|
||||
input clock, // Master Clock
|
||||
input [WIDTH-1:0] di_re, // Data Input (Real)
|
||||
input [WIDTH-1:0] di_im, // Data Input (Imag)
|
||||
output [WIDTH-1:0] do_re, // Data Output (Real)
|
||||
output [WIDTH-1:0] do_im // Data Output (Imag)
|
||||
);
|
||||
|
||||
reg [WIDTH-1:0] buf_re[0:DEPTH-1];
|
||||
reg [WIDTH-1:0] buf_im[0:DEPTH-1];
|
||||
integer n;
|
||||
|
||||
// Shift Buffer
|
||||
/* verilator lint_off BLKLOOPINIT */
|
||||
always @(posedge clock) begin
|
||||
for (n = DEPTH-1; n > 0; n = n - 1) begin
|
||||
buf_re[n] <= buf_re[n-1];
|
||||
buf_im[n] <= buf_im[n-1];
|
||||
end
|
||||
buf_re[0] <= di_re;
|
||||
buf_im[0] <= di_im;
|
||||
end
|
||||
/* verilator lint_on BLKLOOPINIT */
|
||||
|
||||
assign do_re = buf_re[DEPTH-1];
|
||||
assign do_im = buf_im[DEPTH-1];
|
||||
|
||||
endmodule
|
||||
@@ -1,90 +0,0 @@
|
||||
//----------------------------------------------------------------------
|
||||
// FFT: 1024-Point FFT Using Radix-2^2 Single-Path Delay Feedback
|
||||
//----------------------------------------------------------------------
|
||||
(* use_dsp = "no" *)
|
||||
module FFT #(
|
||||
parameter WIDTH = 32
|
||||
)(
|
||||
input clock, // Master Clock
|
||||
input reset, // Active High Asynchronous Reset
|
||||
input di_en, // Input Data Enable
|
||||
input [WIDTH-1:0] di_re, // Input Data (Real)
|
||||
input [WIDTH-1:0] di_im, // Input Data (Imag)
|
||||
output do_en, // Output Data Enable
|
||||
output [WIDTH-1:0] do_re, // Output Data (Real)
|
||||
output [WIDTH-1:0] do_im // Output Data (Imag)
|
||||
);
|
||||
//----------------------------------------------------------------------
|
||||
// Data must be input consecutively in natural order.
|
||||
// The result is scaled to 1/N and output in bit-reversed order.
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
wire su1_do_en;
|
||||
wire[WIDTH-1:0] su1_do_re;
|
||||
wire[WIDTH-1:0] su1_do_im;
|
||||
wire su2_do_en;
|
||||
wire[WIDTH-1:0] su2_do_re;
|
||||
wire[WIDTH-1:0] su2_do_im;
|
||||
wire su3_do_en;
|
||||
wire[WIDTH-1:0] su3_do_re;
|
||||
wire[WIDTH-1:0] su3_do_im;
|
||||
wire su4_do_en;
|
||||
wire[WIDTH-1:0] su4_do_re;
|
||||
wire[WIDTH-1:0] su4_do_im;
|
||||
|
||||
SdfUnit #(.N(1024),.M(1024),.WIDTH(WIDTH)) SU1 (
|
||||
.clock (clock ), // i
|
||||
.reset (reset ), // i
|
||||
.di_en (di_en ), // i
|
||||
.di_re (di_re ), // i
|
||||
.di_im (di_im ), // i
|
||||
.do_en (su1_do_en ), // o
|
||||
.do_re (su1_do_re ), // o
|
||||
.do_im (su1_do_im ) // o
|
||||
);
|
||||
|
||||
SdfUnit #(.N(1024),.M(256),.WIDTH(WIDTH)) SU2 (
|
||||
.clock (clock ), // i
|
||||
.reset (reset ), // i
|
||||
.di_en (su1_do_en ), // i
|
||||
.di_re (su1_do_re ), // i
|
||||
.di_im (su1_do_im ), // i
|
||||
.do_en (su2_do_en ), // o
|
||||
.do_re (su2_do_re ), // o
|
||||
.do_im (su2_do_im ) // o
|
||||
);
|
||||
|
||||
SdfUnit #(.N(1024),.M(64),.WIDTH(WIDTH)) SU3 (
|
||||
.clock (clock ), // i
|
||||
.reset (reset ), // i
|
||||
.di_en (su2_do_en ), // i
|
||||
.di_re (su2_do_re ), // i
|
||||
.di_im (su2_do_im ), // i
|
||||
.do_en (su3_do_en ), // o
|
||||
.do_re (su3_do_re ), // o
|
||||
.do_im (su3_do_im ) // o
|
||||
);
|
||||
|
||||
SdfUnit #(.N(1024),.M(16),.WIDTH(WIDTH)) SU4 (
|
||||
.clock (clock ), // i
|
||||
.reset (reset ), // i
|
||||
.di_en (su3_do_en ), // i
|
||||
.di_re (su3_do_re ), // i
|
||||
.di_im (su3_do_im ), // i
|
||||
.do_en (su4_do_en ), // o
|
||||
.do_re (su4_do_re ), // o
|
||||
.do_im (su4_do_im ) // o
|
||||
);
|
||||
|
||||
SdfUnit #(.N(1024),.M(4),.WIDTH(WIDTH)) SU5 (
|
||||
.clock (clock ), // i
|
||||
.reset (reset ), // i
|
||||
.di_en (su4_do_en ), // i
|
||||
.di_re (su4_do_re ), // i
|
||||
.di_im (su4_do_im ), // i
|
||||
.do_en (do_en ), // o
|
||||
.do_re (do_re ), // o
|
||||
.do_im (do_im ) // o
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -1,36 +0,0 @@
|
||||
//----------------------------------------------------------------------
|
||||
// Multiply: Complex Multiplier
|
||||
//----------------------------------------------------------------------
|
||||
(* use_dsp = "no" *)
|
||||
module Multiply #(
|
||||
parameter WIDTH = 16
|
||||
)(
|
||||
input signed [WIDTH-1:0] a_re,
|
||||
input signed [WIDTH-1:0] a_im,
|
||||
input signed [WIDTH-1:0] b_re,
|
||||
input signed [WIDTH-1:0] b_im,
|
||||
output signed [WIDTH-1:0] m_re,
|
||||
output signed [WIDTH-1:0] m_im
|
||||
);
|
||||
|
||||
(* use_dsp = "no" *) wire signed [WIDTH*2-1:0] arbr, arbi, aibr, aibi;
|
||||
wire signed [WIDTH-1:0] sc_arbr, sc_arbi, sc_aibr, sc_aibi;
|
||||
|
||||
// Signed Multiplication
|
||||
assign arbr = a_re * b_re;
|
||||
assign arbi = a_re * b_im;
|
||||
assign aibr = a_im * b_re;
|
||||
assign aibi = a_im * b_im;
|
||||
|
||||
// Scaling
|
||||
assign sc_arbr = arbr >>> (WIDTH-1);
|
||||
assign sc_arbi = arbi >>> (WIDTH-1);
|
||||
assign sc_aibr = aibr >>> (WIDTH-1);
|
||||
assign sc_aibi = aibi >>> (WIDTH-1);
|
||||
|
||||
// Sub/Add
|
||||
// These sub/add may overflow if unnormalized data is input.
|
||||
assign m_re = sc_arbr - sc_aibi;
|
||||
assign m_im = sc_arbi + sc_aibr;
|
||||
|
||||
endmodule
|
||||
@@ -1,280 +0,0 @@
|
||||
//----------------------------------------------------------------------
|
||||
// SdfUnit: Radix-2^2 Single-Path Delay Feedback Unit for N-Point FFT
|
||||
//----------------------------------------------------------------------
|
||||
(* use_dsp = "no" *)
|
||||
module SdfUnit #(
|
||||
parameter N = 64, // Number of FFT Point
|
||||
parameter M = 64, // Twiddle Resolution
|
||||
parameter WIDTH = 16 // Data Bit Length
|
||||
)(
|
||||
input clock, // Master Clock
|
||||
input reset, // Active High Asynchronous Reset
|
||||
input di_en, // Input Data Enable
|
||||
input [WIDTH-1:0] di_re, // Input Data (Real)
|
||||
input [WIDTH-1:0] di_im, // Input Data (Imag)
|
||||
output do_en, // Output Data Enable
|
||||
output [WIDTH-1:0] do_re, // Output Data (Real)
|
||||
output [WIDTH-1:0] do_im // Output Data (Imag)
|
||||
);
|
||||
|
||||
// log2 constant function
|
||||
function integer log2;
|
||||
input integer x;
|
||||
integer value;
|
||||
begin
|
||||
value = x-1;
|
||||
for (log2=0; value>0; log2=log2+1)
|
||||
value = value>>1;
|
||||
end
|
||||
endfunction
|
||||
|
||||
localparam LOG_N = log2(N); // Bit Length of N
|
||||
localparam LOG_M = log2(M); // Bit Length of M
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Internal Regs and Nets
|
||||
//----------------------------------------------------------------------
|
||||
// 1st Butterfly
|
||||
reg [LOG_N-1:0] di_count; // Input Data Count
|
||||
wire bf1_bf; // Butterfly Add/Sub Enable
|
||||
wire[WIDTH-1:0] bf1_x0_re; // Data #0 to Butterfly (Real)
|
||||
wire[WIDTH-1:0] bf1_x0_im; // Data #0 to Butterfly (Imag)
|
||||
wire[WIDTH-1:0] bf1_x1_re; // Data #1 to Butterfly (Real)
|
||||
wire[WIDTH-1:0] bf1_x1_im; // Data #1 to Butterfly (Imag)
|
||||
wire[WIDTH-1:0] bf1_y0_re; // Data #0 from Butterfly (Real)
|
||||
wire[WIDTH-1:0] bf1_y0_im; // Data #0 from Butterfly (Imag)
|
||||
wire[WIDTH-1:0] bf1_y1_re; // Data #1 from Butterfly (Real)
|
||||
wire[WIDTH-1:0] bf1_y1_im; // Data #1 from Butterfly (Imag)
|
||||
wire[WIDTH-1:0] db1_di_re; // Data to DelayBuffer (Real)
|
||||
wire[WIDTH-1:0] db1_di_im; // Data to DelayBuffer (Imag)
|
||||
wire[WIDTH-1:0] db1_do_re; // Data from DelayBuffer (Real)
|
||||
wire[WIDTH-1:0] db1_do_im; // Data from DelayBuffer (Imag)
|
||||
wire[WIDTH-1:0] bf1_sp_re; // Single-Path Data Output (Real)
|
||||
wire[WIDTH-1:0] bf1_sp_im; // Single-Path Data Output (Imag)
|
||||
reg bf1_sp_en; // Single-Path Data Enable
|
||||
reg [LOG_N-1:0] bf1_count; // Single-Path Data Count
|
||||
wire bf1_start; // Single-Path Output Trigger
|
||||
wire bf1_end; // End of Single-Path Data
|
||||
wire bf1_mj; // Twiddle (-j) Enable
|
||||
reg [WIDTH-1:0] bf1_do_re; // 1st Butterfly Output Data (Real)
|
||||
reg [WIDTH-1:0] bf1_do_im; // 1st Butterfly Output Data (Imag)
|
||||
|
||||
// 2nd Butterfly
|
||||
reg bf2_bf; // Butterfly Add/Sub Enable
|
||||
wire[WIDTH-1:0] bf2_x0_re; // Data #0 to Butterfly (Real)
|
||||
wire[WIDTH-1:0] bf2_x0_im; // Data #0 to Butterfly (Imag)
|
||||
wire[WIDTH-1:0] bf2_x1_re; // Data #1 to Butterfly (Real)
|
||||
wire[WIDTH-1:0] bf2_x1_im; // Data #1 to Butterfly (Imag)
|
||||
wire[WIDTH-1:0] bf2_y0_re; // Data #0 from Butterfly (Real)
|
||||
wire[WIDTH-1:0] bf2_y0_im; // Data #0 from Butterfly (Imag)
|
||||
wire[WIDTH-1:0] bf2_y1_re; // Data #1 from Butterfly (Real)
|
||||
wire[WIDTH-1:0] bf2_y1_im; // Data #1 from Butterfly (Imag)
|
||||
wire[WIDTH-1:0] db2_di_re; // Data to DelayBuffer (Real)
|
||||
wire[WIDTH-1:0] db2_di_im; // Data to DelayBuffer (Imag)
|
||||
wire[WIDTH-1:0] db2_do_re; // Data from DelayBuffer (Real)
|
||||
wire[WIDTH-1:0] db2_do_im; // Data from DelayBuffer (Imag)
|
||||
wire[WIDTH-1:0] bf2_sp_re; // Single-Path Data Output (Real)
|
||||
wire[WIDTH-1:0] bf2_sp_im; // Single-Path Data Output (Imag)
|
||||
reg bf2_sp_en; // Single-Path Data Enable
|
||||
reg [LOG_N-1:0] bf2_count; // Single-Path Data Count
|
||||
reg bf2_start; // Single-Path Output Trigger
|
||||
wire bf2_end; // End of Single-Path Data
|
||||
reg [WIDTH-1:0] bf2_do_re; // 2nd Butterfly Output Data (Real)
|
||||
reg [WIDTH-1:0] bf2_do_im; // 2nd Butterfly Output Data (Imag)
|
||||
reg bf2_do_en; // 2nd Butterfly Output Data Enable
|
||||
|
||||
// Multiplication
|
||||
wire[1:0] tw_sel; // Twiddle Select (2n/n/3n)
|
||||
wire[LOG_N-3:0] tw_num; // Twiddle Number (n)
|
||||
(* use_dsp = "no" *) wire[LOG_N-1:0] tw_addr; // Twiddle Table Address
|
||||
wire[WIDTH-1:0] tw_re; // Twiddle Factor (Real)
|
||||
wire[WIDTH-1:0] tw_im; // Twiddle Factor (Imag)
|
||||
reg mu_en; // Multiplication Enable
|
||||
wire[WIDTH-1:0] mu_a_re; // Multiplier Input (Real)
|
||||
wire[WIDTH-1:0] mu_a_im; // Multiplier Input (Imag)
|
||||
wire[WIDTH-1:0] mu_m_re; // Multiplier Output (Real)
|
||||
wire[WIDTH-1:0] mu_m_im; // Multiplier Output (Imag)
|
||||
reg [WIDTH-1:0] mu_do_re; // Multiplication Output Data (Real)
|
||||
reg [WIDTH-1:0] mu_do_im; // Multiplication Output Data (Imag)
|
||||
reg mu_do_en; // Multiplication Output Data Enable
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// 1st Butterfly
|
||||
//----------------------------------------------------------------------
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
di_count <= {LOG_N{1'b0}};
|
||||
end else begin
|
||||
di_count <= di_en ? (di_count + 1'b1) : {LOG_N{1'b0}};
|
||||
end
|
||||
end
|
||||
assign bf1_bf = di_count[LOG_M-1];
|
||||
|
||||
// Set unknown value x for verification
|
||||
assign bf1_x0_re = bf1_bf ? db1_do_re : {WIDTH{1'bx}};
|
||||
assign bf1_x0_im = bf1_bf ? db1_do_im : {WIDTH{1'bx}};
|
||||
assign bf1_x1_re = bf1_bf ? di_re : {WIDTH{1'bx}};
|
||||
assign bf1_x1_im = bf1_bf ? di_im : {WIDTH{1'bx}};
|
||||
|
||||
Butterfly #(.WIDTH(WIDTH),.RH(0)) BF1 (
|
||||
.x0_re (bf1_x0_re ), // i
|
||||
.x0_im (bf1_x0_im ), // i
|
||||
.x1_re (bf1_x1_re ), // i
|
||||
.x1_im (bf1_x1_im ), // i
|
||||
.y0_re (bf1_y0_re ), // o
|
||||
.y0_im (bf1_y0_im ), // o
|
||||
.y1_re (bf1_y1_re ), // o
|
||||
.y1_im (bf1_y1_im ) // o
|
||||
);
|
||||
|
||||
DelayBuffer #(.DEPTH(2**(LOG_M-1)),.WIDTH(WIDTH)) DB1 (
|
||||
.clock (clock ), // i
|
||||
.di_re (db1_di_re ), // i
|
||||
.di_im (db1_di_im ), // i
|
||||
.do_re (db1_do_re ), // o
|
||||
.do_im (db1_do_im ) // o
|
||||
);
|
||||
|
||||
assign db1_di_re = bf1_bf ? bf1_y1_re : di_re;
|
||||
assign db1_di_im = bf1_bf ? bf1_y1_im : di_im;
|
||||
assign bf1_sp_re = bf1_bf ? bf1_y0_re : bf1_mj ? db1_do_im : db1_do_re;
|
||||
assign bf1_sp_im = bf1_bf ? bf1_y0_im : bf1_mj ? -db1_do_re : db1_do_im;
|
||||
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
bf1_sp_en <= 1'b0;
|
||||
bf1_count <= {LOG_N{1'b0}};
|
||||
end else begin
|
||||
bf1_sp_en <= bf1_start ? 1'b1 : bf1_end ? 1'b0 : bf1_sp_en;
|
||||
bf1_count <= bf1_sp_en ? (bf1_count + 1'b1) : {LOG_N{1'b0}};
|
||||
end
|
||||
end
|
||||
assign bf1_start = (di_count == (2**(LOG_M-1)-1));
|
||||
assign bf1_end = (bf1_count == (2**LOG_N-1));
|
||||
assign bf1_mj = (bf1_count[LOG_M-1:LOG_M-2] == 2'd3);
|
||||
|
||||
always @(posedge clock) begin
|
||||
bf1_do_re <= bf1_sp_re;
|
||||
bf1_do_im <= bf1_sp_im;
|
||||
end
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// 2nd Butterfly
|
||||
//----------------------------------------------------------------------
|
||||
always @(posedge clock) begin
|
||||
bf2_bf <= bf1_count[LOG_M-2];
|
||||
end
|
||||
|
||||
// Set unknown value x for verification
|
||||
assign bf2_x0_re = bf2_bf ? db2_do_re : {WIDTH{1'bx}};
|
||||
assign bf2_x0_im = bf2_bf ? db2_do_im : {WIDTH{1'bx}};
|
||||
assign bf2_x1_re = bf2_bf ? bf1_do_re : {WIDTH{1'bx}};
|
||||
assign bf2_x1_im = bf2_bf ? bf1_do_im : {WIDTH{1'bx}};
|
||||
|
||||
// Negative bias occurs when RH=0 and positive bias occurs when RH=1.
|
||||
// Using both alternately reduces the overall rounding error.
|
||||
Butterfly #(.WIDTH(WIDTH),.RH(1)) BF2 (
|
||||
.x0_re (bf2_x0_re ), // i
|
||||
.x0_im (bf2_x0_im ), // i
|
||||
.x1_re (bf2_x1_re ), // i
|
||||
.x1_im (bf2_x1_im ), // i
|
||||
.y0_re (bf2_y0_re ), // o
|
||||
.y0_im (bf2_y0_im ), // o
|
||||
.y1_re (bf2_y1_re ), // o
|
||||
.y1_im (bf2_y1_im ) // o
|
||||
);
|
||||
|
||||
DelayBuffer #(.DEPTH(2**(LOG_M-2)),.WIDTH(WIDTH)) DB2 (
|
||||
.clock (clock ), // i
|
||||
.di_re (db2_di_re ), // i
|
||||
.di_im (db2_di_im ), // i
|
||||
.do_re (db2_do_re ), // o
|
||||
.do_im (db2_do_im ) // o
|
||||
);
|
||||
|
||||
assign db2_di_re = bf2_bf ? bf2_y1_re : bf1_do_re;
|
||||
assign db2_di_im = bf2_bf ? bf2_y1_im : bf1_do_im;
|
||||
assign bf2_sp_re = bf2_bf ? bf2_y0_re : db2_do_re;
|
||||
assign bf2_sp_im = bf2_bf ? bf2_y0_im : db2_do_im;
|
||||
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
bf2_sp_en <= 1'b0;
|
||||
bf2_count <= {LOG_N{1'b0}};
|
||||
end else begin
|
||||
bf2_sp_en <= bf2_start ? 1'b1 : bf2_end ? 1'b0 : bf2_sp_en;
|
||||
bf2_count <= bf2_sp_en ? (bf2_count + 1'b1) : {LOG_N{1'b0}};
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clock) begin
|
||||
bf2_start <= (bf1_count == (2**(LOG_M-2)-1)) & bf1_sp_en;
|
||||
end
|
||||
assign bf2_end = (bf2_count == (2**LOG_N-1));
|
||||
|
||||
always @(posedge clock) begin
|
||||
bf2_do_re <= bf2_sp_re;
|
||||
bf2_do_im <= bf2_sp_im;
|
||||
end
|
||||
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
bf2_do_en <= 1'b0;
|
||||
end else begin
|
||||
bf2_do_en <= bf2_sp_en;
|
||||
end
|
||||
end
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Multiplication
|
||||
//----------------------------------------------------------------------
|
||||
assign tw_sel[1] = bf2_count[LOG_M-2];
|
||||
assign tw_sel[0] = bf2_count[LOG_M-1];
|
||||
assign tw_num = bf2_count << (LOG_N-LOG_M);
|
||||
assign tw_addr = tw_num * tw_sel;
|
||||
|
||||
Twiddle #(
|
||||
.WIDTH (WIDTH)
|
||||
) TW (
|
||||
.clock (clock ), // i
|
||||
.addr (tw_addr), // i
|
||||
.tw_re (tw_re ), // o
|
||||
.tw_im (tw_im ) // o
|
||||
);
|
||||
|
||||
// Multiplication is bypassed when twiddle address is 0.
|
||||
always @(posedge clock) begin
|
||||
mu_en <= (tw_addr != {LOG_N{1'b0}});
|
||||
end
|
||||
// Set unknown value x for verification
|
||||
assign mu_a_re = mu_en ? bf2_do_re : {WIDTH{1'bx}};
|
||||
assign mu_a_im = mu_en ? bf2_do_im : {WIDTH{1'bx}};
|
||||
|
||||
Multiply #(.WIDTH(WIDTH)) MU (
|
||||
.a_re (mu_a_re), // i
|
||||
.a_im (mu_a_im), // i
|
||||
.b_re (tw_re ), // i
|
||||
.b_im (tw_im ), // i
|
||||
.m_re (mu_m_re), // o
|
||||
.m_im (mu_m_im) // o
|
||||
);
|
||||
|
||||
always @(posedge clock) begin
|
||||
mu_do_re <= mu_en ? mu_m_re : bf2_do_re;
|
||||
mu_do_im <= mu_en ? mu_m_im : bf2_do_im;
|
||||
end
|
||||
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
mu_do_en <= 1'b0;
|
||||
end else begin
|
||||
mu_do_en <= bf2_do_en;
|
||||
end
|
||||
end
|
||||
|
||||
// No multiplication required at final stage
|
||||
assign do_en = (LOG_M == 2) ? bf2_do_en : mu_do_en;
|
||||
assign do_re = (LOG_M == 2) ? bf2_do_re : mu_do_re;
|
||||
assign do_im = (LOG_M == 2) ? bf2_do_im : mu_do_im;
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,399 +0,0 @@
|
||||
`define FFT_CSR_ADDR 16'hc000
|
||||
`define FFT_IN_RE_BASE 16'h8000
|
||||
`define FFT_IN_IM_BASE 16'h9000
|
||||
`define FFT_OUT_RE_BASE 16'ha000
|
||||
`define FFT_OUT_IM_BASE 16'hb000
|
||||
|
||||
(* use_dsp = "no" *)
|
||||
module fft_controller #(
|
||||
parameter FFT_LEN = 1024, // FFT处理长度
|
||||
parameter BRAM_RD_LATENCY = 2, // 适配 BRAM 的读延迟 (通常 Block RAM 开启输出寄存器为 2)
|
||||
parameter FFT_DATA_WIDTH = 16
|
||||
)(
|
||||
input aclk,
|
||||
input aresetn,
|
||||
|
||||
// AXI Lite / AXI4 Wrapper ports
|
||||
input [4 :0] s_awid,
|
||||
input [31:0] s_awaddr,
|
||||
input [7 :0] s_awlen,
|
||||
input [2 :0] s_awsize,
|
||||
input [1 :0] s_awburst,
|
||||
input s_awlock,
|
||||
input [3 :0] s_awcache,
|
||||
input [2 :0] s_awprot,
|
||||
input s_awvalid,
|
||||
output reg s_awready,
|
||||
input [4 :0] s_wid,
|
||||
input [31:0] s_wdata,
|
||||
input [3 :0] s_wstrb,
|
||||
input s_wlast,
|
||||
input s_wvalid,
|
||||
output reg s_wready,
|
||||
output [4 :0] s_bid,
|
||||
output [1 :0] s_bresp,
|
||||
output reg s_bvalid,
|
||||
input s_bready,
|
||||
|
||||
input [4 :0] s_arid,
|
||||
input [31:0] s_araddr,
|
||||
input [7 :0] s_arlen,
|
||||
input [2 :0] s_arsize,
|
||||
input [1 :0] s_arburst,
|
||||
input s_arlock,
|
||||
input [3 :0] s_arcache,
|
||||
input [2 :0] s_arprot,
|
||||
input s_arvalid,
|
||||
output reg s_arready,
|
||||
output [4 :0] s_rid,
|
||||
output reg [31:0] s_rdata,
|
||||
output [1 :0] s_rresp,
|
||||
output reg s_rlast,
|
||||
output reg s_rvalid,
|
||||
input s_rready,
|
||||
|
||||
output fft_finish
|
||||
);
|
||||
|
||||
// AXI Burst 内部寄存器
|
||||
reg [31:0] aw_addr_reg;
|
||||
reg [1 :0] aw_burst_reg;
|
||||
reg [4 :0] aw_id_reg;
|
||||
|
||||
reg [31:0] ar_addr_reg;
|
||||
reg [7 :0] ar_len_reg;
|
||||
reg [1 :0] ar_burst_reg;
|
||||
reg [4 :0] ar_id_reg;
|
||||
reg [7 :0] ar_cnt;
|
||||
|
||||
// 写通道状态机 (AW, W, B)
|
||||
localparam W_IDLE = 2'd0;
|
||||
localparam W_DATA = 2'd1;
|
||||
localparam W_RESP = 2'd2;
|
||||
reg [1:0] w_state;
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
w_state <= W_IDLE;
|
||||
s_awready <= 1'b1;
|
||||
s_wready <= 1'b0;
|
||||
s_bvalid <= 1'b0;
|
||||
aw_addr_reg <= 32'h0;
|
||||
aw_burst_reg <= 2'h0;
|
||||
aw_id_reg <= 5'h0;
|
||||
end else begin
|
||||
case (w_state)
|
||||
W_IDLE: begin
|
||||
s_awready <= 1'b1;
|
||||
if (s_awvalid && s_awready) begin
|
||||
s_awready <= 1'b0;
|
||||
s_wready <= 1'b1;
|
||||
aw_addr_reg <= s_awaddr;
|
||||
aw_burst_reg <= s_awburst;
|
||||
aw_id_reg <= s_awid;
|
||||
w_state <= W_DATA;
|
||||
end
|
||||
end
|
||||
W_DATA: begin
|
||||
// 接收到有效写数据
|
||||
if (s_wvalid && s_wready) begin
|
||||
// INCR 模式下地址递增
|
||||
if (aw_burst_reg == 2'b01) begin
|
||||
aw_addr_reg <= aw_addr_reg + 4;
|
||||
end
|
||||
// 若是最后一拍，跳转到发送响应
|
||||
if (s_wlast) begin
|
||||
s_wready <= 1'b0;
|
||||
s_bvalid <= 1'b1;
|
||||
w_state <= W_RESP;
|
||||
end
|
||||
end
|
||||
end
|
||||
W_RESP: begin
|
||||
if (s_bvalid && s_bready) begin
|
||||
s_bvalid <= 1'b0;
|
||||
s_awready <= 1'b1; // 准备接收下一次写请求
|
||||
w_state <= W_IDLE;
|
||||
end
|
||||
end
|
||||
default: w_state <= W_IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// 产生有效的写动作脉冲，用于触发 BRAM 写使能
|
||||
wire w_active = (w_state == W_DATA) && s_wvalid && s_wready;
|
||||
assign s_bid = aw_id_reg;
|
||||
assign s_bresp = 2'b00;
|
||||
|
||||
// 读通道状态机(AR, R)
|
||||
localparam R_IDLE = 2'd0;
|
||||
localparam R_WAIT = 2'd1;
|
||||
localparam R_DATA = 2'd2;
|
||||
reg [1:0] r_state;
|
||||
reg [3:0] r_wait_cnt;
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
r_state <= R_IDLE;
|
||||
s_arready <= 1'b1;
|
||||
s_rvalid <= 1'b0;
|
||||
s_rlast <= 1'b0;
|
||||
ar_addr_reg <= 32'h0;
|
||||
ar_len_reg <= 8'h0;
|
||||
ar_burst_reg <= 2'h0;
|
||||
ar_id_reg <= 5'h0;
|
||||
ar_cnt <= 8'h0;
|
||||
r_wait_cnt <= 4'h0;
|
||||
end else begin
|
||||
case (r_state)
|
||||
R_IDLE: begin
|
||||
s_arready <= 1'b1;
|
||||
if (s_arvalid && s_arready) begin
|
||||
s_arready <= 1'b0;
|
||||
ar_addr_reg <= s_araddr;
|
||||
ar_len_reg <= s_arlen;
|
||||
ar_burst_reg <= s_arburst;
|
||||
ar_id_reg <= s_arid;
|
||||
ar_cnt <= 8'h0;
|
||||
r_wait_cnt <= BRAM_RD_LATENCY;
|
||||
r_state <= R_WAIT; // 进入等待以拉取第一笔 BRAM 数据
|
||||
end
|
||||
end
|
||||
R_WAIT: begin
|
||||
// 等待 BRAM 固定潜伏期结束
|
||||
if (r_wait_cnt <= 1) begin
|
||||
s_rvalid <= 1'b1;
|
||||
s_rlast <= (ar_cnt == ar_len_reg);
|
||||
r_state <= R_DATA;
|
||||
r_wait_cnt <= 4'h0;
|
||||
end else begin
|
||||
r_wait_cnt <= r_wait_cnt - 1;
|
||||
end
|
||||
end
|
||||
R_DATA: begin
|
||||
// 数据被总线成功读取
|
||||
if (s_rvalid && s_rready) begin
|
||||
if (ar_cnt == ar_len_reg) begin
|
||||
// Burst 结束
|
||||
s_rvalid <= 1'b0;
|
||||
s_rlast <= 1'b0;
|
||||
s_arready <= 1'b1;
|
||||
r_state <= R_IDLE;
|
||||
end else begin
|
||||
// 准备读取下一拍数据
|
||||
ar_cnt <= ar_cnt + 1;
|
||||
// INCR 模式下地址递增
|
||||
if (ar_burst_reg == 2'b01) begin
|
||||
ar_addr_reg <= ar_addr_reg + 4;
|
||||
end
|
||||
s_rvalid <= 1'b0;
|
||||
s_rlast <= 1'b0;
|
||||
r_wait_cnt <= BRAM_RD_LATENCY;
|
||||
r_state <= R_WAIT; // 再次进入等待状态
|
||||
end
|
||||
end
|
||||
end
|
||||
default: r_state <= R_IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
assign s_rid = ar_id_reg;
|
||||
assign s_rresp = 2'b00;
|
||||
|
||||
// 地址译码
|
||||
wire hit_in_re = (aw_addr_reg[15:12] == 4'h8);
|
||||
wire hit_in_im = (aw_addr_reg[15:12] == 4'h9);
|
||||
wire hit_out_re = (ar_addr_reg[15:12] == 4'ha);
|
||||
wire hit_out_im = (ar_addr_reg[15:12] == 4'hb);
|
||||
|
||||
// 寄存器控制
|
||||
reg [3:0] fft_ctrl;
|
||||
reg [3:0] fft_status;
|
||||
|
||||
wire [31:0] fft_csr = {24'h0, fft_ctrl, fft_status};
|
||||
// 只有发生有效的写握手且地址对应 CSR 时，才写入控制寄存器
|
||||
wire write_fft_csr = w_active && (aw_addr_reg[15:0] == `FFT_CSR_ADDR);
|
||||
|
||||
// 状态机
|
||||
localparam IDLE = 2'd0;
|
||||
localparam LOAD = 2'd1;
|
||||
localparam WAIT_OUT = 2'd2;
|
||||
localparam DONE = 2'd3;
|
||||
|
||||
reg [1:0] state, next_state;
|
||||
reg [10:0] in_cnt;
|
||||
reg [10:0] out_cnt;
|
||||
|
||||
wire do_en;
|
||||
wire [FFT_DATA_WIDTH-1:0] do_re;
|
||||
wire [FFT_DATA_WIDTH-1:0] do_im;
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) state <= IDLE;
|
||||
else state <= next_state;
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
case (state)
|
||||
IDLE: if (fft_ctrl[0]) next_state = LOAD; else next_state = IDLE;
|
||||
LOAD: if (in_cnt == FFT_LEN - 1) next_state = WAIT_OUT; else next_state = LOAD;
|
||||
WAIT_OUT: if (do_en && out_cnt == FFT_LEN - 1) next_state = DONE; else next_state = WAIT_OUT;
|
||||
DONE: next_state = IDLE;
|
||||
default: next_state = IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
in_cnt <= 0;
|
||||
out_cnt <= 0;
|
||||
end else if (state == IDLE) begin
|
||||
in_cnt <= 0;
|
||||
out_cnt <= 0;
|
||||
end else begin
|
||||
if (state == LOAD) in_cnt <= in_cnt + 1;
|
||||
if (do_en) out_cnt <= out_cnt + 1;
|
||||
end
|
||||
end
|
||||
|
||||
// 更新寄存器与状态
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
fft_ctrl <= 4'h0;
|
||||
fft_status <= 4'h0;
|
||||
end else begin
|
||||
if (write_fft_csr) begin
|
||||
fft_ctrl <= s_wdata[7:4];
|
||||
end else if (state != IDLE) begin
|
||||
fft_ctrl[0] <= 1'b0;
|
||||
end
|
||||
|
||||
fft_status[0] <= (state != IDLE && state != DONE);
|
||||
|
||||
if (write_fft_csr && s_wdata[4]) begin
|
||||
fft_status[1] <= 1'b0;
|
||||
end else if (state == DONE) begin
|
||||
fft_status[1] <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign fft_finish = fft_status[1];
|
||||
|
||||
// BRAM 接口连线
|
||||
wire [FFT_DATA_WIDTH-1:0] in_re_dout;
|
||||
wire [FFT_DATA_WIDTH-1:0] in_im_dout;
|
||||
wire [FFT_DATA_WIDTH-1:0] out_re_dout;
|
||||
wire [FFT_DATA_WIDTH-1:0] out_im_dout;
|
||||
wire [31:0] out_re_sx = {{(32-FFT_DATA_WIDTH){out_re_dout[FFT_DATA_WIDTH-1]}}, out_re_dout};
|
||||
wire [31:0] out_im_sx = {{(32-FFT_DATA_WIDTH){out_im_dout[FFT_DATA_WIDTH-1]}}, out_im_dout};
|
||||
|
||||
my_bram0 #(
|
||||
.DATA_WIDTH (FFT_DATA_WIDTH),
|
||||
.ADDR_WIDTH (10)
|
||||
) u_in0(
|
||||
.clka (aclk),
|
||||
.ena (w_active && hit_in_re), // 由 burst写逻辑产生
|
||||
.wea (1'b1),
|
||||
.addra (aw_addr_reg[11:2]), // 取当前递增的突发写地址
|
||||
.dina (s_wdata[FFT_DATA_WIDTH-1:0]),
|
||||
|
||||
.clkb (aclk),
|
||||
.enb (state == LOAD),
|
||||
.addrb (in_cnt[9:0]),
|
||||
.doutb (in_re_dout)
|
||||
);
|
||||
|
||||
my_bram0 #(
|
||||
.DATA_WIDTH (FFT_DATA_WIDTH),
|
||||
.ADDR_WIDTH (10)
|
||||
) u_in1(
|
||||
.clka (aclk),
|
||||
.ena (w_active && hit_in_im),
|
||||
.wea (1'b1),
|
||||
.addra (aw_addr_reg[11:2]),
|
||||
.dina (s_wdata[FFT_DATA_WIDTH-1:0]),
|
||||
|
||||
.clkb (aclk),
|
||||
.enb (state == LOAD),
|
||||
.addrb (in_cnt[9:0]),
|
||||
.doutb (in_im_dout)
|
||||
);
|
||||
|
||||
// 对于输出 BRAM，采用原先的位反转（Bit-reverse）读取逻辑
|
||||
wire [9:0] b_rd_addr = ar_addr_reg[11:2];
|
||||
wire [9:0] bit_reversed_index = {
|
||||
b_rd_addr[0], b_rd_addr[1], b_rd_addr[2], b_rd_addr[3], b_rd_addr[4],
|
||||
b_rd_addr[5], b_rd_addr[6], b_rd_addr[7], b_rd_addr[8], b_rd_addr[9]
|
||||
};
|
||||
|
||||
my_bram0 #(
|
||||
.DATA_WIDTH (FFT_DATA_WIDTH),
|
||||
.ADDR_WIDTH (10)
|
||||
) u_out0(
|
||||
.clka (aclk),
|
||||
.ena (do_en),
|
||||
.wea (1'b1),
|
||||
.addra (out_cnt[9:0]),
|
||||
.dina (do_re),
|
||||
|
||||
.clkb (aclk),
|
||||
.enb (r_state != R_IDLE), // 当处于读突发事务时始终使能 BRAM
|
||||
.addrb (bit_reversed_index),
|
||||
.doutb (out_re_dout)
|
||||
);
|
||||
|
||||
my_bram0 #(
|
||||
.DATA_WIDTH (FFT_DATA_WIDTH),
|
||||
.ADDR_WIDTH (10)
|
||||
) u_out1(
|
||||
.clka (aclk),
|
||||
.ena (do_en),
|
||||
.wea (1'b1),
|
||||
.addra (out_cnt[9:0]),
|
||||
.dina (do_im),
|
||||
|
||||
.clkb (aclk),
|
||||
.enb (r_state != R_IDLE),
|
||||
.addrb (bit_reversed_index),
|
||||
.doutb (out_im_dout)
|
||||
);
|
||||
|
||||
// 支持 1 到 N 拍的读延迟，让 di_en 严格对齐 BRAM 的吐出数据
|
||||
reg [3:0] di_en_shift;
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) di_en_shift <= 0;
|
||||
else di_en_shift <= {di_en_shift[2:0], (state == LOAD)};
|
||||
end
|
||||
|
||||
wire di_en_r = (BRAM_RD_LATENCY == 1) ? di_en_shift[0] :
|
||||
(BRAM_RD_LATENCY == 2) ? di_en_shift[1] :
|
||||
(BRAM_RD_LATENCY == 3) ? di_en_shift[2] : di_en_shift[3];
|
||||
|
||||
FFT #(
|
||||
.WIDTH(FFT_DATA_WIDTH)
|
||||
) u_FFT (
|
||||
.clock (aclk),
|
||||
.reset (~aresetn),
|
||||
.di_en (di_en_r),
|
||||
.di_re (in_re_dout),
|
||||
.di_im (in_im_dout),
|
||||
.do_en (do_en),
|
||||
.do_re (do_re),
|
||||
.do_im (do_im)
|
||||
);
|
||||
|
||||
// 读取返回数据选择
|
||||
wire [31:0] rdata_d =
|
||||
(ar_addr_reg[15:0] == `FFT_CSR_ADDR) ? fft_csr :
|
||||
hit_out_re ? out_re_sx :
|
||||
hit_out_im ? out_im_sx :
|
||||
32'h0;
|
||||
|
||||
always @(*) begin
|
||||
s_rdata = rdata_d;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,8 +1,6 @@
|
||||
// ═══════════════════════════════════════════════════════
|
||||
// 3-stage pipelined multiplier (LUT-based, no DSP)
|
||||
// latency=3, throughput=1 result/cycle
|
||||
// ═══════════════════════════════════════════════════════
|
||||
(* use_dsp = "no" *)
|
||||
// 3-stage pipelined multiplier (LUT-based, no DSP)
|
||||
// latency=3, throughput=1 result/cycle
|
||||
(* use_dsp = "no", use_dsp48 = "no", syn_multstyle = "logic" *)
|
||||
module pipelined_mult_32x32 (
|
||||
input clk,
|
||||
input rstn,
|
||||
@@ -11,7 +9,23 @@ module pipelined_mult_32x32 (
|
||||
output reg [63:0] p
|
||||
);
|
||||
reg [31:0] a_r, b_r;
|
||||
(* use_dsp = "no", use_dsp48 = "no", syn_multstyle = "logic" *)
|
||||
reg [63:0] prod;
|
||||
|
||||
function automatic [63:0] lut_mul32;
|
||||
input [31:0] lhs;
|
||||
input [31:0] rhs;
|
||||
integer bit_idx;
|
||||
reg [63:0] acc;
|
||||
begin
|
||||
acc = 64'b0;
|
||||
for (bit_idx = 0; bit_idx < 32; bit_idx = bit_idx + 1) begin
|
||||
if (rhs[bit_idx])
|
||||
acc = acc + ({32'b0, lhs} << bit_idx);
|
||||
end
|
||||
lut_mul32 = acc;
|
||||
end
|
||||
endfunction
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!rstn) begin
|
||||
@@ -20,16 +34,14 @@ module pipelined_mult_32x32 (
|
||||
end else begin
|
||||
a_r <= a; // Stage 1: register inputs
|
||||
b_r <= b;
|
||||
prod <= a_r * b_r; // Stage 2: LUT-based multiply
|
||||
prod <= lut_mul32(a_r, b_r); // Stage 2: LUT-based multiply
|
||||
p <= prod; // Stage 3: register output
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
// ═══════════════════════════════════════════════════════
|
||||
// 矩阵乘法器顶层模块 (AXI Burst Slave + Ping-Pong + Stream CRC32)
|
||||
// ═══════════════════════════════════════════════════════
|
||||
// AXI Burst Slave + Ping-Pong + Stream CRC32
|
||||
module matmul_axi_slave (
|
||||
input clk,
|
||||
input resetn,
|
||||
@@ -80,38 +92,63 @@ module matmul_axi_slave (
|
||||
output reg s_axi_rvalid,
|
||||
input s_axi_rready,
|
||||
|
||||
// CDMA local endpoint port
|
||||
input ep_wr_valid,
|
||||
input [3:0] ep_wr_id,
|
||||
input [3:0] ep_wr_bank,
|
||||
input [7:0] ep_wr_word_addr,
|
||||
input [31:0] ep_wr_data,
|
||||
output ep_wr_ready,
|
||||
// AXI master port for autonomous matrix stream load/store
|
||||
output reg [3:0] m_axi_awid,
|
||||
output reg [31:0] m_axi_awaddr,
|
||||
output reg [7:0] m_axi_awlen,
|
||||
output reg [2:0] m_axi_awsize,
|
||||
output reg [1:0] m_axi_awburst,
|
||||
output reg m_axi_awlock,
|
||||
output reg [3:0] m_axi_awcache,
|
||||
output reg [2:0] m_axi_awprot,
|
||||
output reg m_axi_awvalid,
|
||||
input m_axi_awready,
|
||||
|
||||
input ep_rd_valid,
|
||||
input [3:0] ep_rd_id,
|
||||
input [3:0] ep_rd_bank,
|
||||
input [7:0] ep_rd_word_addr,
|
||||
output reg [31:0] ep_rd_data,
|
||||
output ep_rd_ready,
|
||||
output reg [31:0] m_axi_wdata,
|
||||
output reg [3:0] m_axi_wstrb,
|
||||
output reg m_axi_wlast,
|
||||
output reg m_axi_wvalid,
|
||||
input m_axi_wready,
|
||||
|
||||
// Direct control from the CDMA/matmul bridge
|
||||
input mat_start_valid,
|
||||
input mat_start_bank,
|
||||
input mat_done_clear,
|
||||
input mat_crc_clear,
|
||||
output mat_done,
|
||||
input [3:0] m_axi_bid,
|
||||
input [1:0] m_axi_bresp,
|
||||
input m_axi_bvalid,
|
||||
output reg m_axi_bready,
|
||||
|
||||
output reg [3:0] m_axi_arid,
|
||||
output reg [31:0] m_axi_araddr,
|
||||
output reg [7:0] m_axi_arlen,
|
||||
output reg [2:0] m_axi_arsize,
|
||||
output reg [1:0] m_axi_arburst,
|
||||
output reg m_axi_arlock,
|
||||
output reg [3:0] m_axi_arcache,
|
||||
output reg [2:0] m_axi_arprot,
|
||||
output reg m_axi_arvalid,
|
||||
input m_axi_arready,
|
||||
|
||||
input [3:0] m_axi_rid,
|
||||
input [31:0] m_axi_rdata,
|
||||
input [1:0] m_axi_rresp,
|
||||
input m_axi_rlast,
|
||||
input m_axi_rvalid,
|
||||
output reg m_axi_rready,
|
||||
|
||||
// Interrupt output (active high level, pulsed by calc_done)
|
||||
output intr
|
||||
);
|
||||
|
||||
// ==========================================
|
||||
// 内存地址映射 (Memory Map)
|
||||
// Memory Map
|
||||
// ==========================================
|
||||
localparam ADDR_CTRL = 12'h000;
|
||||
localparam ADDR_STATUS = 12'h004;
|
||||
localparam ADDR_CRC = 12'h010;
|
||||
localparam ADDR_DMA_SRC_BASE = 12'h020;
|
||||
localparam ADDR_DMA_DST_BASE = 12'h024;
|
||||
localparam ADDR_DMA_GROUPS = 12'h028;
|
||||
localparam ADDR_DMA_SRC_STRIDE = 12'h02C;
|
||||
localparam ADDR_DMA_DST_STRIDE = 12'h030;
|
||||
localparam ADDR_DMA_CYCLES = 12'h034;
|
||||
|
||||
localparam ADDR_B0_A = 12'h100;
|
||||
localparam ADDR_B0_B = 12'h140;
|
||||
@@ -122,12 +159,13 @@ module matmul_axi_slave (
|
||||
localparam ADDR_B1_C = 12'h380;
|
||||
|
||||
// ==========================================
|
||||
// 寄存器与数据缓冲
|
||||
// Registers and data buffers
|
||||
// ==========================================
|
||||
reg req_0, req_1;
|
||||
reg busy;
|
||||
reg done;
|
||||
reg [1:0] done_count;
|
||||
reg error;
|
||||
wire done = (done_count != 2'd0);
|
||||
|
||||
reg [31:0] b0_a [0:15];
|
||||
reg [31:0] b0_b [0:15];
|
||||
@@ -137,32 +175,73 @@ module matmul_axi_slave (
|
||||
reg [31:0] b1_b [0:15];
|
||||
reg [65:0] b1_c [0:15];
|
||||
|
||||
assign ep_wr_ready = 1'b1;
|
||||
assign ep_rd_ready = 1'b1;
|
||||
assign mat_done = done;
|
||||
reg [31:0] dma_src_base;
|
||||
reg [31:0] dma_dst_base;
|
||||
reg [31:0] dma_groups;
|
||||
reg [31:0] dma_src_stride;
|
||||
reg [31:0] dma_dst_stride;
|
||||
// Full sys_clk cycles spent in dma_busy; held after DMA completion.
|
||||
reg [31:0] dma_cycle_count;
|
||||
reg dma_busy;
|
||||
reg dma_done;
|
||||
reg dma_compute_complete;
|
||||
reg [31:0] load_group;
|
||||
reg [31:0] store_group;
|
||||
reg [31:0] dma_next_rd_addr;
|
||||
reg [31:0] dma_next_wr_addr;
|
||||
reg [31:0] completed_groups;
|
||||
reg [1:0] bank_loaded;
|
||||
reg [1:0] bank_store_pending;
|
||||
reg [1:0] bank_storing;
|
||||
reg [1:0] bank_compute_pending;
|
||||
reg dma_compute_bank;
|
||||
reg dma_load_bank;
|
||||
reg dma_store_bank;
|
||||
reg dma_start_pulse;
|
||||
reg dma_done_clear_pulse;
|
||||
reg dma_req0_pulse;
|
||||
reg dma_req1_pulse;
|
||||
|
||||
wire [3:0] ep_wr_idx = ep_wr_word_addr[3:0];
|
||||
wire [7:0] ep_rd_elem_raw = ep_rd_word_addr / 8'd3;
|
||||
wire [7:0] ep_rd_part_raw = ep_rd_word_addr % 8'd3;
|
||||
wire [3:0] ep_rd_elem = ep_rd_elem_raw[3:0];
|
||||
wire [1:0] ep_rd_part = ep_rd_part_raw[1:0];
|
||||
wire [65:0] ep_rd_c0 = b0_c[ep_rd_elem];
|
||||
wire [65:0] ep_rd_c1 = b1_c[ep_rd_elem];
|
||||
|
||||
always @(*) begin
|
||||
ep_rd_data = 32'b0;
|
||||
if (ep_rd_word_addr < 8'd48) begin
|
||||
if (ep_rd_bank[0] == 1'b0) begin
|
||||
if (ep_rd_part == 2'd0) ep_rd_data = ep_rd_c0[31:0];
|
||||
else if (ep_rd_part == 2'd1) ep_rd_data = ep_rd_c0[63:32];
|
||||
else ep_rd_data = {30'b0, ep_rd_c0[65:64]};
|
||||
end else begin
|
||||
if (ep_rd_part == 2'd0) ep_rd_data = ep_rd_c1[31:0];
|
||||
else if (ep_rd_part == 2'd1) ep_rd_data = ep_rd_c1[63:32];
|
||||
else ep_rd_data = {30'b0, ep_rd_c1[65:64]};
|
||||
end
|
||||
function [3:0] c_elem_from_word;
|
||||
input [5:0] word_idx;
|
||||
begin
|
||||
case (word_idx)
|
||||
6'd0, 6'd1, 6'd2: c_elem_from_word = 4'd0;
|
||||
6'd3, 6'd4, 6'd5: c_elem_from_word = 4'd1;
|
||||
6'd6, 6'd7, 6'd8: c_elem_from_word = 4'd2;
|
||||
6'd9, 6'd10, 6'd11: c_elem_from_word = 4'd3;
|
||||
6'd12, 6'd13, 6'd14: c_elem_from_word = 4'd4;
|
||||
6'd15, 6'd16, 6'd17: c_elem_from_word = 4'd5;
|
||||
6'd18, 6'd19, 6'd20: c_elem_from_word = 4'd6;
|
||||
6'd21, 6'd22, 6'd23: c_elem_from_word = 4'd7;
|
||||
6'd24, 6'd25, 6'd26: c_elem_from_word = 4'd8;
|
||||
6'd27, 6'd28, 6'd29: c_elem_from_word = 4'd9;
|
||||
6'd30, 6'd31, 6'd32: c_elem_from_word = 4'd10;
|
||||
6'd33, 6'd34, 6'd35: c_elem_from_word = 4'd11;
|
||||
6'd36, 6'd37, 6'd38: c_elem_from_word = 4'd12;
|
||||
6'd39, 6'd40, 6'd41: c_elem_from_word = 4'd13;
|
||||
6'd42, 6'd43, 6'd44: c_elem_from_word = 4'd14;
|
||||
default: c_elem_from_word = 4'd15;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [1:0] c_part_from_word;
|
||||
input [5:0] word_idx;
|
||||
begin
|
||||
case (word_idx)
|
||||
6'd0, 6'd3, 6'd6, 6'd9,
|
||||
6'd12, 6'd15, 6'd18, 6'd21,
|
||||
6'd24, 6'd27, 6'd30, 6'd33,
|
||||
6'd36, 6'd39, 6'd42, 6'd45: c_part_from_word = 2'd0;
|
||||
6'd1, 6'd4, 6'd7, 6'd10,
|
||||
6'd13, 6'd16, 6'd19, 6'd22,
|
||||
6'd25, 6'd28, 6'd31, 6'd34,
|
||||
6'd37, 6'd40, 6'd43, 6'd46: c_part_from_word = 2'd1;
|
||||
default: c_part_from_word = 2'd2;
|
||||
endcase
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [31:0] apply_wstrb;
|
||||
input [31:0] old_value;
|
||||
@@ -179,26 +258,71 @@ module matmul_axi_slave (
|
||||
|
||||
// ==========================================
|
||||
// CRC32 Engine (IEEE 802.3, polynomial 0xEDB88320)
|
||||
//
|
||||
// AXI-stream: single-cycle crc32_update_word (4 LUT lookup depth, ok for
|
||||
// AXI timing—the bus runs at or below internal compute rate).
|
||||
// DMA-calc: two 6-byte CRC steps per 66-bit C-element. A result FIFO
|
||||
// absorbs the 16-cycle compute burst so the recursive CRC state never
|
||||
// backpressures the multiplier under the normal DMA load cadence.
|
||||
// ==========================================
|
||||
reg [31:0] crc32_table [0:255];
|
||||
reg [31:0] crc_reg;
|
||||
|
||||
function [31:0] crc32_word_next;
|
||||
// ---- AXI-stream CRC (single-cycle) ----------------------------------
|
||||
wire [31:0] crc_stream_data = s_axi_rdata;
|
||||
wire crc_axi_valid = (r_state == R_DATA) && s_axi_rvalid && s_axi_rready &&
|
||||
((r_offset >= ADDR_B0_C && r_offset < (ADDR_B0_C + 12'h0C0)) ||
|
||||
(r_offset >= ADDR_B1_C && r_offset < (ADDR_B1_C + 12'h0C0)));
|
||||
wire crc_stream_valid = crc_axi_valid;
|
||||
wire [31:0] crc_next = crc32_update_word(crc_reg, crc_stream_data);
|
||||
|
||||
function [31:0] crc32_update_word;
|
||||
input [31:0] crc_in;
|
||||
input [31:0] data_in;
|
||||
reg [31:0] t0, c0, t1, c1, t2, c2, t3;
|
||||
reg [31:0] c0;
|
||||
reg [31:0] c1;
|
||||
reg [31:0] c2;
|
||||
begin
|
||||
t0 = crc32_table[(crc_in[7:0] ^ data_in[7:0])];
|
||||
c0 = t0 ^ {8'h00, crc_in[31:8]};
|
||||
t1 = crc32_table[(c0[7:0] ^ data_in[15:8])];
|
||||
c1 = t1 ^ {8'h00, c0[31:8]};
|
||||
t2 = crc32_table[(c1[7:0] ^ data_in[23:16])];
|
||||
c2 = t2 ^ {8'h00, c1[31:8]};
|
||||
t3 = crc32_table[(c2[7:0] ^ data_in[31:24])];
|
||||
crc32_word_next = t3 ^ {8'h00, c2[31:8]};
|
||||
c0 = crc32_table[(crc_in[7:0] ^ data_in[7:0])] ^ {8'h00, crc_in[31:8]};
|
||||
c1 = crc32_table[(c0[7:0] ^ data_in[15:8])] ^ {8'h00, c0[31:8]};
|
||||
c2 = crc32_table[(c1[7:0] ^ data_in[23:16])] ^ {8'h00, c1[31:8]};
|
||||
crc32_update_word = crc32_table[(c2[7:0] ^ data_in[31:24])] ^ {8'h00, c2[31:8]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [31:0] crc32_update_6bytes;
|
||||
input [31:0] crc_in;
|
||||
input [47:0] data_in;
|
||||
reg [31:0] c;
|
||||
integer byte_idx;
|
||||
begin
|
||||
c = crc_in;
|
||||
for (byte_idx = 0; byte_idx < 6; byte_idx = byte_idx + 1)
|
||||
c = crc32_table[(c[7:0] ^ data_in[byte_idx*8 +: 8])] ^
|
||||
{8'h00, c[31:8]};
|
||||
crc32_update_6bytes = c;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// ---- DMA result FIFO and two-cycle recursive CRC consumer -----------
|
||||
localparam CRC_FIFO_DEPTH = 32;
|
||||
reg [65:0] crc_fifo [0:CRC_FIFO_DEPTH-1];
|
||||
reg [4:0] crc_fifo_wr_ptr;
|
||||
reg [4:0] crc_fifo_rd_ptr;
|
||||
reg [5:0] crc_fifo_count;
|
||||
reg crc_c66_busy;
|
||||
reg [65:0] crc_c66_data;
|
||||
reg [31:0] crc_c66_half;
|
||||
|
||||
wire crc_fifo_empty = (crc_fifo_count == 6'd0);
|
||||
wire crc_fifo_push = dma_busy && acc_valid_d4;
|
||||
wire crc_fifo_pop = !crc_c66_busy && !crc_fifo_empty;
|
||||
wire [31:0] crc_c66_first_next =
|
||||
crc32_update_6bytes(crc_reg, crc_fifo[crc_fifo_rd_ptr][47:0]);
|
||||
wire [47:0] crc_c66_second_data = {30'b0, crc_c66_data[65:48]};
|
||||
wire [31:0] crc_c66_final_next =
|
||||
crc32_update_6bytes(crc_c66_half, crc_c66_second_data);
|
||||
|
||||
initial begin
|
||||
crc32_table[0 ] = 32'h00000000; crc32_table[1 ] = 32'h77073096;
|
||||
crc32_table[2 ] = 32'hEE0E612C; crc32_table[3 ] = 32'h990951BA;
|
||||
@@ -331,7 +455,7 @@ module matmul_axi_slave (
|
||||
end
|
||||
|
||||
// ==========================================
|
||||
// AXI Write 通道逻辑 (支持 INCR Burst)
|
||||
// AXI Write (INCR Burst)
|
||||
// ==========================================
|
||||
localparam W_IDLE = 2'd0;
|
||||
localparam W_DATA = 2'd1;
|
||||
@@ -347,16 +471,40 @@ module matmul_axi_slave (
|
||||
assign s_axi_bid = w_id;
|
||||
assign s_axi_bresp = 2'b00;
|
||||
|
||||
// 前向声明引擎的状态
|
||||
localparam C_IDLE = 2'd0;
|
||||
localparam C_RUN = 2'd1;
|
||||
reg [1:0] state;
|
||||
reg cur_bank;
|
||||
reg calc_done_pulse;
|
||||
|
||||
// 【修改点 1】单独引出一个写脉冲信号给 CRC 清零用
|
||||
wire crc_clear_pulse = ((w_state == W_DATA) && s_axi_wvalid && s_axi_wready && (w_offset == ADDR_CRC)) ||
|
||||
mat_crc_clear;
|
||||
|
||||
localparam DMA_RD_IDLE = 2'd0;
|
||||
localparam DMA_RD_ADDR = 2'd1;
|
||||
localparam DMA_RD_DATA = 2'd2;
|
||||
reg [1:0] dma_rd_state;
|
||||
reg [7:0] dma_rd_count;
|
||||
reg dma_rd_bank;
|
||||
wire [4:0] dma_rd_group_word_idx = dma_rd_count[4:0];
|
||||
wire [3:0] dma_rd_word_idx = dma_rd_count[3:0];
|
||||
wire dma_rd_fill_bank = dma_rd_bank ^ dma_rd_count[5];
|
||||
wire dma_rd_commit = (dma_rd_state == DMA_RD_DATA) && m_axi_rvalid && m_axi_rready;
|
||||
wire dma_bank0_free = !bank_loaded[0] && !bank_compute_pending[0] && !req_0 &&
|
||||
!(state == C_RUN && cur_bank == 1'b0);
|
||||
wire dma_bank1_free = !bank_loaded[1] && !bank_compute_pending[1] && !req_1 &&
|
||||
!(state == C_RUN && cur_bank == 1'b1);
|
||||
wire dma_load_bank_free = dma_load_bank ? dma_bank1_free : dma_bank0_free;
|
||||
wire dma_rd_fill_bank_free = dma_rd_fill_bank ? dma_bank1_free : dma_bank0_free;
|
||||
wire dma_rd_next_bank_free = dma_rd_fill_bank ? dma_bank0_free : dma_bank1_free;
|
||||
|
||||
localparam DMA_WR_IDLE = 2'd0;
|
||||
localparam DMA_WR_ADDR = 2'd1;
|
||||
localparam DMA_WR_DATA = 2'd2;
|
||||
localparam DMA_WR_RESP = 2'd3;
|
||||
reg [1:0] dma_wr_state;
|
||||
reg [5:0] dma_wr_count;
|
||||
|
||||
wire crc_clear_pulse = (w_state == W_DATA) && s_axi_wvalid && s_axi_wready && (w_offset == ADDR_CRC);
|
||||
wire done_clear_pulse = (w_state == W_DATA) && s_axi_wvalid && s_axi_wready &&
|
||||
(w_offset == ADDR_STATUS) && s_axi_wdata[1];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!resetn) begin
|
||||
@@ -366,39 +514,37 @@ module matmul_axi_slave (
|
||||
s_axi_bvalid <= 1'b0;
|
||||
req_0 <= 1'b0;
|
||||
req_1 <= 1'b0;
|
||||
done <= 1'b0;
|
||||
done_count <= 2'd0;
|
||||
error <= 1'b0;
|
||||
dma_src_base <= 32'd0;
|
||||
dma_dst_base <= 32'd0;
|
||||
dma_groups <= 32'd0;
|
||||
dma_src_stride <= 32'd128;
|
||||
dma_dst_stride <= 32'd192;
|
||||
dma_start_pulse <= 1'b0;
|
||||
dma_done_clear_pulse <= 1'b0;
|
||||
end else begin
|
||||
if (req_0 && state == C_RUN && cur_bank == 1'b0) req_0 <= 1'b0;
|
||||
if (req_1 && state == C_RUN && cur_bank == 1'b1) req_1 <= 1'b0;
|
||||
dma_start_pulse <= 1'b0;
|
||||
dma_done_clear_pulse <= 1'b0;
|
||||
|
||||
if (mat_start_valid) begin
|
||||
if (mat_start_bank) req_1 <= 1'b1;
|
||||
else req_0 <= 1'b1;
|
||||
end
|
||||
|
||||
if (calc_done_pulse) begin
|
||||
done <= 1'b1;
|
||||
end
|
||||
|
||||
if (mat_done_clear) begin
|
||||
done <= 1'b0;
|
||||
error <= 1'b0;
|
||||
end
|
||||
|
||||
if (ep_wr_valid && ep_wr_ready) begin
|
||||
if (ep_wr_word_addr < 8'd16) begin
|
||||
if (ep_wr_bank[0] == 1'b0)
|
||||
b0_a[ep_wr_idx] <= ep_wr_data;
|
||||
if (dma_rd_commit) begin
|
||||
if (dma_rd_fill_bank == 1'b0) begin
|
||||
if (dma_rd_group_word_idx < 5'd16)
|
||||
b0_a[dma_rd_word_idx] <= m_axi_rdata;
|
||||
else
|
||||
b1_a[ep_wr_idx] <= ep_wr_data;
|
||||
end else if (ep_wr_word_addr < 8'd32) begin
|
||||
if (ep_wr_bank[0] == 1'b0)
|
||||
b0_b[ep_wr_idx] <= ep_wr_data;
|
||||
b0_b[dma_rd_word_idx] <= m_axi_rdata;
|
||||
end else begin
|
||||
if (dma_rd_group_word_idx < 5'd16)
|
||||
b1_a[dma_rd_word_idx] <= m_axi_rdata;
|
||||
else
|
||||
b1_b[ep_wr_idx] <= ep_wr_data;
|
||||
b1_b[dma_rd_word_idx] <= m_axi_rdata;
|
||||
end
|
||||
end
|
||||
|
||||
if (req_0 && state == C_RUN && cur_bank == 1'b0) req_0 <= 1'b0;
|
||||
if (req_1 && state == C_RUN && cur_bank == 1'b1) req_1 <= 1'b0;
|
||||
if (dma_req0_pulse) req_0 <= 1'b1;
|
||||
if (dma_req1_pulse) req_1 <= 1'b1;
|
||||
|
||||
case (w_state)
|
||||
W_IDLE: begin
|
||||
@@ -417,12 +563,23 @@ module matmul_axi_slave (
|
||||
if (w_offset == ADDR_CTRL) begin
|
||||
if (s_axi_wdata[0]) req_0 <= 1'b1;
|
||||
if (s_axi_wdata[1]) req_1 <= 1'b1;
|
||||
if (s_axi_wdata[8]) dma_start_pulse <= 1'b1;
|
||||
end
|
||||
else if (w_offset == ADDR_STATUS) begin
|
||||
if (s_axi_wdata[1]) done <= 1'b0;
|
||||
if (s_axi_wdata[2]) error <= 1'b0;
|
||||
if (s_axi_wdata[4]) dma_done_clear_pulse <= 1'b1;
|
||||
end
|
||||
// 【修改点 2】删除 else if (w_offset == ADDR_CRC) { crc_reg <= ... } 防止多重驱动
|
||||
else if (w_offset == ADDR_DMA_SRC_BASE)
|
||||
dma_src_base <= apply_wstrb(dma_src_base, s_axi_wdata, s_axi_wstrb);
|
||||
else if (w_offset == ADDR_DMA_DST_BASE)
|
||||
dma_dst_base <= apply_wstrb(dma_dst_base, s_axi_wdata, s_axi_wstrb);
|
||||
else if (w_offset == ADDR_DMA_GROUPS)
|
||||
dma_groups <= apply_wstrb(dma_groups, s_axi_wdata, s_axi_wstrb);
|
||||
else if (w_offset == ADDR_DMA_SRC_STRIDE)
|
||||
dma_src_stride <= apply_wstrb(dma_src_stride, s_axi_wdata, s_axi_wstrb);
|
||||
else if (w_offset == ADDR_DMA_DST_STRIDE)
|
||||
dma_dst_stride <= apply_wstrb(dma_dst_stride, s_axi_wdata, s_axi_wstrb);
|
||||
// CRC register is now managed by the pipelined CRC engine
|
||||
else if (w_offset >= ADDR_B0_A && w_offset < ADDR_B0_B)
|
||||
b0_a[(w_offset - ADDR_B0_A) >> 2] <= apply_wstrb(b0_a[(w_offset - ADDR_B0_A) >> 2], s_axi_wdata, s_axi_wstrb);
|
||||
else if (w_offset >= ADDR_B0_B && w_offset < ADDR_B0_C)
|
||||
@@ -453,11 +610,17 @@ module matmul_axi_slave (
|
||||
end
|
||||
default: w_state <= W_IDLE;
|
||||
endcase
|
||||
|
||||
case ({calc_done_pulse, done_clear_pulse})
|
||||
2'b10: if (done_count != 2'd3) done_count <= done_count + 2'd1;
|
||||
2'b01: if (done_count != 2'd0) done_count <= done_count - 2'd1;
|
||||
default: done_count <= done_count;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// ==========================================
|
||||
// AXI Read 通道逻辑 (支持 INCR Burst)
|
||||
// AXI Read (INCR Burst)
|
||||
// ==========================================
|
||||
localparam R_IDLE = 2'd0;
|
||||
localparam R_DATA = 2'd1;
|
||||
@@ -472,13 +635,13 @@ module matmul_axi_slave (
|
||||
assign s_axi_rresp = 2'b00;
|
||||
|
||||
wire [5:0] c0_offset = (r_offset - ADDR_B0_C) >> 2;
|
||||
wire [3:0] c0_elem = c0_offset / 3;
|
||||
wire [1:0] c0_part = c0_offset % 3;
|
||||
wire [3:0] c0_elem = c_elem_from_word(c0_offset);
|
||||
wire [1:0] c0_part = c_part_from_word(c0_offset);
|
||||
wire [65:0] target_c0 = b0_c[c0_elem];
|
||||
|
||||
wire [5:0] c1_offset = (r_offset - ADDR_B1_C) >> 2;
|
||||
wire [3:0] c1_elem = c1_offset / 3;
|
||||
wire [1:0] c1_part = c1_offset % 3;
|
||||
wire [3:0] c1_elem = c_elem_from_word(c1_offset);
|
||||
wire [1:0] c1_part = c_part_from_word(c1_offset);
|
||||
wire [65:0] target_c1 = b1_c[c1_elem];
|
||||
|
||||
wire crc_read_en = (r_offset >= ADDR_B0_C && r_offset < (ADDR_B0_C + 12'h0C0)) ||
|
||||
@@ -509,7 +672,6 @@ module matmul_axi_slave (
|
||||
end
|
||||
R_DATA: begin
|
||||
if (s_axi_rvalid && s_axi_rready) begin
|
||||
// CRC is updated from completed compute results, not from C reads.
|
||||
if (r_cnt == r_len) begin
|
||||
s_axi_rvalid <= 1'b0;
|
||||
s_axi_rlast <= 1'b0;
|
||||
@@ -537,7 +699,20 @@ module matmul_axi_slave (
|
||||
else if (current_r_offset == ADDR_CRC)
|
||||
s_axi_rdata = crc_reg ^ 32'hFFFFFFFF;
|
||||
else if (current_r_offset == ADDR_STATUS)
|
||||
s_axi_rdata = {29'b0, error, done, busy};
|
||||
s_axi_rdata = {26'b0, (crc_c66_busy || !crc_fifo_empty),
|
||||
dma_done, dma_busy, error, done, busy};
|
||||
else if (current_r_offset == ADDR_DMA_SRC_BASE)
|
||||
s_axi_rdata = dma_src_base;
|
||||
else if (current_r_offset == ADDR_DMA_DST_BASE)
|
||||
s_axi_rdata = dma_dst_base;
|
||||
else if (current_r_offset == ADDR_DMA_GROUPS)
|
||||
s_axi_rdata = dma_groups;
|
||||
else if (current_r_offset == ADDR_DMA_SRC_STRIDE)
|
||||
s_axi_rdata = dma_src_stride;
|
||||
else if (current_r_offset == ADDR_DMA_DST_STRIDE)
|
||||
s_axi_rdata = dma_dst_stride;
|
||||
else if (current_r_offset == ADDR_DMA_CYCLES)
|
||||
s_axi_rdata = dma_cycle_count;
|
||||
else if (current_r_offset >= ADDR_B0_A && current_r_offset < ADDR_B0_B)
|
||||
s_axi_rdata = b0_a[(current_r_offset - ADDR_B0_A) >> 2];
|
||||
else if (current_r_offset >= ADDR_B0_B && current_r_offset < ADDR_B0_C)
|
||||
@@ -560,7 +735,7 @@ module matmul_axi_slave (
|
||||
end
|
||||
|
||||
// ==========================================
|
||||
// 计算引擎 (Compute FSM)
|
||||
// Compute FSM
|
||||
// ==========================================
|
||||
wire [63:0] mult_p [0:3];
|
||||
reg [31:0] m_in_a [0:3];
|
||||
@@ -584,22 +759,66 @@ module matmul_axi_slave (
|
||||
reg acc_bank_d1, acc_bank_d2, acc_bank_d3, acc_bank_d4;
|
||||
reg acc_valid_d1, acc_valid_d2, acc_valid_d3, acc_valid_d4;
|
||||
reg [4:0] pipe_cnt;
|
||||
wire [65:0] calc_c_result = ({2'b0, mult_p[0]} + {2'b0, mult_p[1]}) +
|
||||
({2'b0, mult_p[2]} + {2'b0, mult_p[3]});
|
||||
wire calc_crc_valid = acc_valid_d4;
|
||||
wire [31:0] crc_calc_0 = crc32_word_next(crc_reg, calc_c_result[31:0]);
|
||||
wire [31:0] crc_calc_1 = crc32_word_next(crc_calc_0, calc_c_result[63:32]);
|
||||
wire [31:0] crc_calc_2 = crc32_word_next(crc_calc_1, {30'b0, calc_c_result[65:64]});
|
||||
wire [65:0] acc_result = ({2'b0, mult_p[0]} + {2'b0, mult_p[1]}) +
|
||||
({2'b0, mult_p[2]} + {2'b0, mult_p[3]});
|
||||
|
||||
// Leave eight entries for results already in the multiplier pipeline.
|
||||
// Under the normal DMA cadence the FIFO stays well below this threshold.
|
||||
wire dma_crc_issue_ready = !dma_busy || (crc_fifo_count < 6'd24);
|
||||
|
||||
// DMA CRC takes priority over the software-driven AXI read stream.
|
||||
always @(posedge clk) begin
|
||||
if (!resetn) begin
|
||||
crc_reg <= 32'hFFFFFFFF;
|
||||
crc_fifo_wr_ptr <= 5'd0;
|
||||
crc_fifo_rd_ptr <= 5'd0;
|
||||
crc_fifo_count <= 6'd0;
|
||||
crc_c66_busy <= 1'b0;
|
||||
crc_c66_data <= 66'd0;
|
||||
crc_c66_half <= 32'd0;
|
||||
end else if (crc_clear_pulse) begin
|
||||
crc_reg <= 32'hFFFFFFFF;
|
||||
crc_fifo_wr_ptr <= 5'd0;
|
||||
crc_fifo_rd_ptr <= 5'd0;
|
||||
crc_fifo_count <= 6'd0;
|
||||
crc_c66_busy <= 1'b0;
|
||||
crc_c66_data <= 66'd0;
|
||||
crc_c66_half <= 32'd0;
|
||||
end else begin
|
||||
if (crc_fifo_push) begin
|
||||
crc_fifo[crc_fifo_wr_ptr] <= acc_result;
|
||||
crc_fifo_wr_ptr <= crc_fifo_wr_ptr + 5'd1;
|
||||
end
|
||||
|
||||
case ({crc_fifo_push, crc_fifo_pop})
|
||||
2'b10: crc_fifo_count <= crc_fifo_count + 6'd1;
|
||||
2'b01: crc_fifo_count <= crc_fifo_count - 6'd1;
|
||||
default: crc_fifo_count <= crc_fifo_count;
|
||||
endcase
|
||||
|
||||
if (crc_c66_busy) begin
|
||||
crc_reg <= crc_c66_final_next;
|
||||
crc_c66_busy <= 1'b0;
|
||||
end else if (crc_fifo_pop) begin
|
||||
crc_c66_data <= crc_fifo[crc_fifo_rd_ptr];
|
||||
crc_c66_half <= crc_c66_first_next;
|
||||
crc_c66_busy <= 1'b1;
|
||||
crc_fifo_rd_ptr <= crc_fifo_rd_ptr + 5'd1;
|
||||
end else if (crc_stream_valid) begin
|
||||
crc_reg <= crc_next;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
task start_calc_bank;
|
||||
input bank;
|
||||
begin
|
||||
cur_bank <= bank;
|
||||
busy <= 1'b1;
|
||||
state <= C_RUN;
|
||||
pipe_cnt <= 5'd1;
|
||||
acc_idx_d1 <= 4'd0;
|
||||
acc_bank_d1 <= bank;
|
||||
cur_bank <= bank;
|
||||
busy <= 1'b1;
|
||||
state <= C_RUN;
|
||||
pipe_cnt <= 5'd1;
|
||||
acc_idx_d1 <= 4'd0;
|
||||
acc_bank_d1 <= bank;
|
||||
acc_valid_d1 <= 1'b1;
|
||||
if (bank == 1'b0) begin
|
||||
m_in_a[0] <= b0_a[4'd0]; m_in_b[0] <= b0_b[4'd0];
|
||||
@@ -615,17 +834,6 @@ module matmul_axi_slave (
|
||||
end
|
||||
endtask
|
||||
|
||||
// CRC tracks completed C elements directly, independent of result writeback.
|
||||
always @(posedge clk) begin
|
||||
if (!resetn) begin
|
||||
crc_reg <= 32'hFFFFFFFF;
|
||||
end else if (crc_clear_pulse) begin
|
||||
crc_reg <= 32'hFFFFFFFF;
|
||||
end else if (calc_crc_valid) begin
|
||||
crc_reg <= crc_calc_2;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!resetn) begin
|
||||
state <= C_IDLE;
|
||||
@@ -648,7 +856,7 @@ module matmul_axi_slave (
|
||||
end else begin
|
||||
calc_done_pulse <= 1'b0;
|
||||
|
||||
// Pipeline shift: issue_idx → d1 → d2 → d3 → d4 (4 cycles total)
|
||||
// Pipeline shift (4 cycles total)
|
||||
acc_idx_d4 <= acc_idx_d3;
|
||||
acc_idx_d3 <= acc_idx_d2;
|
||||
acc_idx_d2 <= acc_idx_d1;
|
||||
@@ -675,53 +883,300 @@ module matmul_axi_slave (
|
||||
end
|
||||
|
||||
C_RUN: begin
|
||||
// Issue 4 new operands every cycle (pipe_cnt 0-15, 16 rounds)
|
||||
// Issue one C element per cycle unless the CRC FIFO is
|
||||
// approaching capacity.
|
||||
if (pipe_cnt < 5'd16) begin
|
||||
acc_idx_d1 <= pipe_cnt[3:0];
|
||||
acc_bank_d1 <= cur_bank;
|
||||
acc_valid_d1 <= 1'b1;
|
||||
if (cur_bank == 1'b0) begin
|
||||
m_in_a[0] <= b0_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b0_b[{2'd0, pipe_cnt[1:0]}];
|
||||
m_in_a[1] <= b0_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b0_b[{2'd1, pipe_cnt[1:0]}];
|
||||
m_in_a[2] <= b0_a[{pipe_cnt[3:2], 2'd2}]; m_in_b[2] <= b0_b[{2'd2, pipe_cnt[1:0]}];
|
||||
m_in_a[3] <= b0_a[{pipe_cnt[3:2], 2'd3}]; m_in_b[3] <= b0_b[{2'd3, pipe_cnt[1:0]}];
|
||||
end else begin
|
||||
m_in_a[0] <= b1_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b1_b[{2'd0, pipe_cnt[1:0]}];
|
||||
m_in_a[1] <= b1_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b1_b[{2'd1, pipe_cnt[1:0]}];
|
||||
m_in_a[2] <= b1_a[{pipe_cnt[3:2], 2'd2}]; m_in_b[2] <= b1_b[{2'd2, pipe_cnt[1:0]}];
|
||||
m_in_a[3] <= b1_a[{pipe_cnt[3:2], 2'd3}]; m_in_b[3] <= b1_b[{2'd3, pipe_cnt[1:0]}];
|
||||
if (dma_crc_issue_ready) begin
|
||||
acc_idx_d1 <= pipe_cnt[3:0];
|
||||
acc_bank_d1 <= cur_bank;
|
||||
acc_valid_d1 <= 1'b1;
|
||||
if (cur_bank == 1'b0) begin
|
||||
m_in_a[0] <= b0_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b0_b[{2'd0, pipe_cnt[1:0]}];
|
||||
m_in_a[1] <= b0_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b0_b[{2'd1, pipe_cnt[1:0]}];
|
||||
m_in_a[2] <= b0_a[{pipe_cnt[3:2], 2'd2}]; m_in_b[2] <= b0_b[{2'd2, pipe_cnt[1:0]}];
|
||||
m_in_a[3] <= b0_a[{pipe_cnt[3:2], 2'd3}]; m_in_b[3] <= b0_b[{2'd3, pipe_cnt[1:0]}];
|
||||
end else begin
|
||||
m_in_a[0] <= b1_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b1_b[{2'd0, pipe_cnt[1:0]}];
|
||||
m_in_a[1] <= b1_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b1_b[{2'd1, pipe_cnt[1:0]}];
|
||||
m_in_a[2] <= b1_a[{pipe_cnt[3:2], 2'd2}]; m_in_b[2] <= b1_b[{2'd2, pipe_cnt[1:0]}];
|
||||
m_in_a[3] <= b1_a[{pipe_cnt[3:2], 2'd3}]; m_in_b[3] <= b1_b[{2'd3, pipe_cnt[1:0]}];
|
||||
end
|
||||
pipe_cnt <= pipe_cnt + 5'd1;
|
||||
end
|
||||
end
|
||||
|
||||
// Accumulate results from 4 cycles ago.
|
||||
if (acc_valid_d4) begin
|
||||
if (acc_bank_d4 == 1'b0)
|
||||
b0_c[acc_idx_d4] <= calc_c_result;
|
||||
b0_c[acc_idx_d4] <= acc_result;
|
||||
else
|
||||
b1_c[acc_idx_d4] <= calc_c_result;
|
||||
b1_c[acc_idx_d4] <= acc_result;
|
||||
end
|
||||
|
||||
if (acc_valid_d4 && acc_idx_d4 == 4'd15) begin
|
||||
calc_done_pulse <= 1'b1;
|
||||
end
|
||||
|
||||
if (pipe_cnt < 5'd16) begin
|
||||
pipe_cnt <= pipe_cnt + 5'd1;
|
||||
end else if (cur_bank == 1'b0 && req_1) begin
|
||||
start_calc_bank(1'b1);
|
||||
end else if (cur_bank == 1'b1 && req_0) begin
|
||||
start_calc_bank(1'b0);
|
||||
end else if (acc_valid_d4 && acc_idx_d4 == 4'd15) begin
|
||||
busy <= 1'b0;
|
||||
state <= C_IDLE;
|
||||
end else begin
|
||||
pipe_cnt <= pipe_cnt + 5'd1;
|
||||
if (pipe_cnt >= 5'd16) begin
|
||||
if (dma_busy) begin
|
||||
if (acc_valid_d4 && acc_idx_d4 == 4'd15) begin
|
||||
if (cur_bank == 1'b0 && req_1)
|
||||
start_calc_bank(1'b1);
|
||||
else if (cur_bank == 1'b1 && req_0)
|
||||
start_calc_bank(1'b0);
|
||||
else begin
|
||||
busy <= 1'b0;
|
||||
state <= C_IDLE;
|
||||
end
|
||||
end else begin
|
||||
pipe_cnt <= pipe_cnt + 5'd1;
|
||||
end
|
||||
end else if (cur_bank == 1'b0 && req_1) begin
|
||||
start_calc_bank(1'b1);
|
||||
end else if (cur_bank == 1'b1 && req_0) begin
|
||||
start_calc_bank(1'b0);
|
||||
end else if (acc_valid_d4 && acc_idx_d4 == 4'd15) begin
|
||||
busy <= 1'b0;
|
||||
state <= C_IDLE;
|
||||
end else begin
|
||||
pipe_cnt <= pipe_cnt + 5'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// ==========================================
|
||||
// Autonomous AXI master loader with inline result CRC.
|
||||
// ==========================================
|
||||
always @(posedge clk) begin
|
||||
if (!resetn) begin
|
||||
dma_busy <= 1'b0;
|
||||
dma_done <= 1'b0;
|
||||
dma_compute_complete <= 1'b0;
|
||||
dma_cycle_count <= 32'd0;
|
||||
load_group <= 32'd0;
|
||||
store_group <= 32'd0;
|
||||
dma_next_rd_addr <= 32'd0;
|
||||
dma_next_wr_addr <= 32'd0;
|
||||
completed_groups <= 32'd0;
|
||||
bank_loaded <= 2'b00;
|
||||
bank_store_pending <= 2'b00;
|
||||
bank_storing <= 2'b00;
|
||||
bank_compute_pending <= 2'b00;
|
||||
dma_compute_bank <= 1'b0;
|
||||
dma_load_bank <= 1'b0;
|
||||
dma_store_bank <= 1'b0;
|
||||
dma_rd_state <= DMA_RD_IDLE;
|
||||
dma_rd_count <= 8'd0;
|
||||
dma_rd_bank <= 1'b0;
|
||||
dma_wr_state <= DMA_WR_IDLE;
|
||||
dma_wr_count <= 6'd0;
|
||||
|
||||
m_axi_arid <= 4'd0;
|
||||
m_axi_araddr <= 32'd0;
|
||||
m_axi_arlen <= 8'd31;
|
||||
m_axi_arsize <= 3'd2;
|
||||
m_axi_arburst <= 2'b01;
|
||||
m_axi_arlock <= 1'b0;
|
||||
m_axi_arcache <= 4'b0;
|
||||
m_axi_arprot <= 3'b0;
|
||||
m_axi_arvalid <= 1'b0;
|
||||
m_axi_rready <= 1'b0;
|
||||
|
||||
m_axi_awid <= 4'd0;
|
||||
m_axi_awaddr <= 32'd0;
|
||||
m_axi_awlen <= 8'd47;
|
||||
m_axi_awsize <= 3'd2;
|
||||
m_axi_awburst <= 2'b01;
|
||||
m_axi_awlock <= 1'b0;
|
||||
m_axi_awcache <= 4'b0;
|
||||
m_axi_awprot <= 3'b0;
|
||||
m_axi_awvalid <= 1'b0;
|
||||
m_axi_wdata <= 32'd0;
|
||||
m_axi_wstrb <= 4'hF;
|
||||
m_axi_wlast <= 1'b0;
|
||||
m_axi_wvalid <= 1'b0;
|
||||
m_axi_bready <= 1'b0;
|
||||
dma_req0_pulse <= 1'b0;
|
||||
dma_req1_pulse <= 1'b0;
|
||||
end else begin
|
||||
dma_req0_pulse <= 1'b0;
|
||||
dma_req1_pulse <= 1'b0;
|
||||
|
||||
if (dma_done_clear_pulse)
|
||||
dma_done <= 1'b0;
|
||||
|
||||
if (dma_start_pulse && !dma_busy && dma_groups != 32'd0) begin
|
||||
dma_busy <= 1'b1;
|
||||
dma_done <= 1'b0;
|
||||
dma_compute_complete <= 1'b0;
|
||||
dma_cycle_count <= 32'd0;
|
||||
load_group <= 32'd0;
|
||||
store_group <= 32'd0;
|
||||
dma_next_rd_addr <= dma_src_base;
|
||||
dma_next_wr_addr <= dma_dst_base;
|
||||
completed_groups <= 32'd0;
|
||||
bank_loaded <= 2'b00;
|
||||
bank_store_pending <= 2'b00;
|
||||
bank_storing <= 2'b00;
|
||||
bank_compute_pending <= 2'b00;
|
||||
dma_compute_bank <= 1'b0;
|
||||
dma_load_bank <= 1'b0;
|
||||
dma_store_bank <= 1'b0;
|
||||
dma_rd_state <= DMA_RD_IDLE;
|
||||
dma_wr_state <= DMA_WR_IDLE;
|
||||
end else if (dma_busy) begin
|
||||
dma_cycle_count <= dma_cycle_count + 32'd1;
|
||||
end
|
||||
|
||||
if (dma_busy) begin
|
||||
if (state == C_RUN)
|
||||
bank_compute_pending[cur_bank] <= 1'b0;
|
||||
|
||||
if (bank_loaded[0] && !req_0 &&
|
||||
!bank_compute_pending[0] && !(state == C_RUN && cur_bank == 1'b0)) begin
|
||||
dma_req0_pulse <= 1'b1;
|
||||
bank_loaded[0] <= 1'b0;
|
||||
bank_compute_pending[0] <= 1'b1;
|
||||
dma_compute_bank <= 1'b0;
|
||||
end else if (bank_loaded[1] && !req_1 &&
|
||||
!bank_compute_pending[1] && !(state == C_RUN && cur_bank == 1'b1)) begin
|
||||
dma_req1_pulse <= 1'b1;
|
||||
bank_loaded[1] <= 1'b0;
|
||||
bank_compute_pending[1] <= 1'b1;
|
||||
dma_compute_bank <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
if (calc_done_pulse && dma_busy) begin
|
||||
store_group <= store_group + 32'd1;
|
||||
completed_groups <= completed_groups + 32'd1;
|
||||
if ((completed_groups + 32'd1) >= dma_groups)
|
||||
dma_compute_complete <= 1'b1;
|
||||
end
|
||||
|
||||
if (dma_compute_complete && crc_fifo_empty && !crc_c66_busy) begin
|
||||
dma_busy <= 1'b0;
|
||||
dma_done <= 1'b1;
|
||||
dma_compute_complete <= 1'b0;
|
||||
end
|
||||
|
||||
case (dma_rd_state)
|
||||
DMA_RD_IDLE: begin
|
||||
m_axi_arvalid <= 1'b0;
|
||||
m_axi_rready <= 1'b0;
|
||||
if (dma_busy && load_group < dma_groups && dma_load_bank_free) begin
|
||||
dma_rd_bank <= dma_load_bank;
|
||||
dma_rd_count <= 8'd0;
|
||||
m_axi_araddr <= dma_next_rd_addr;
|
||||
m_axi_arlen <= ((dma_src_stride == 32'd128) &&
|
||||
((dma_groups - load_group) >= 32'd8)) ? 8'd255 : 8'd31;
|
||||
m_axi_arsize <= 3'd2;
|
||||
m_axi_arburst <= 2'b01;
|
||||
m_axi_arvalid <= 1'b1;
|
||||
dma_rd_state <= DMA_RD_ADDR;
|
||||
end
|
||||
end
|
||||
DMA_RD_ADDR: begin
|
||||
if (m_axi_arvalid && m_axi_arready) begin
|
||||
m_axi_arvalid <= 1'b0;
|
||||
m_axi_rready <= 1'b1;
|
||||
dma_rd_state <= DMA_RD_DATA;
|
||||
end
|
||||
end
|
||||
DMA_RD_DATA: begin
|
||||
if (!m_axi_rready && dma_rd_fill_bank_free)
|
||||
m_axi_rready <= 1'b1;
|
||||
|
||||
if (m_axi_rvalid && m_axi_rready) begin
|
||||
// Present the next request one beat early so the SRAM
|
||||
// slave can accept it together with the current RLAST.
|
||||
if ((dma_rd_count == 8'd254) && dma_busy &&
|
||||
((load_group + 32'd1) < dma_groups) && dma_rd_next_bank_free) begin
|
||||
m_axi_araddr <= dma_next_rd_addr + dma_src_stride;
|
||||
m_axi_arlen <= ((dma_src_stride == 32'd128) &&
|
||||
((dma_groups - (load_group + 32'd1)) >= 32'd8)) ?
|
||||
8'd255 : 8'd31;
|
||||
m_axi_arvalid <= 1'b1;
|
||||
end
|
||||
|
||||
if (dma_rd_group_word_idx == 5'd31) begin
|
||||
bank_loaded[dma_rd_fill_bank] <= 1'b1;
|
||||
load_group <= load_group + 32'd1;
|
||||
dma_next_rd_addr <= dma_next_rd_addr + dma_src_stride;
|
||||
dma_load_bank <= ~dma_load_bank;
|
||||
end
|
||||
|
||||
if (m_axi_rlast) begin
|
||||
m_axi_rready <= 1'b0;
|
||||
if (dma_busy && ((load_group + 32'd1) < dma_groups) &&
|
||||
dma_rd_next_bank_free) begin
|
||||
dma_rd_bank <= ~dma_rd_fill_bank;
|
||||
dma_rd_count <= 8'd0;
|
||||
if (m_axi_arvalid && m_axi_arready) begin
|
||||
m_axi_arvalid <= 1'b0;
|
||||
m_axi_rready <= 1'b1;
|
||||
dma_rd_state <= DMA_RD_DATA;
|
||||
end else begin
|
||||
m_axi_araddr <= dma_next_rd_addr + dma_src_stride;
|
||||
m_axi_arlen <= ((dma_src_stride == 32'd128) &&
|
||||
((dma_groups - (load_group + 32'd1)) >= 32'd8)) ?
|
||||
8'd255 : 8'd31;
|
||||
m_axi_arvalid <= 1'b1;
|
||||
dma_rd_state <= DMA_RD_ADDR;
|
||||
end
|
||||
end else begin
|
||||
m_axi_arvalid <= 1'b0;
|
||||
dma_rd_state <= DMA_RD_IDLE;
|
||||
end
|
||||
end else begin
|
||||
dma_rd_count <= dma_rd_count + 8'd1;
|
||||
if ((dma_rd_group_word_idx == 5'd31) && !dma_rd_next_bank_free)
|
||||
m_axi_rready <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
default: dma_rd_state <= DMA_RD_IDLE;
|
||||
endcase
|
||||
|
||||
case (dma_wr_state)
|
||||
DMA_WR_IDLE: begin
|
||||
m_axi_awvalid <= 1'b0;
|
||||
m_axi_wvalid <= 1'b0;
|
||||
m_axi_bready <= 1'b0;
|
||||
end
|
||||
DMA_WR_ADDR: begin
|
||||
m_axi_awvalid <= 1'b0;
|
||||
dma_wr_state <= DMA_WR_DATA;
|
||||
end
|
||||
DMA_WR_DATA: begin
|
||||
m_axi_wvalid <= 1'b0;
|
||||
m_axi_wlast <= 1'b0;
|
||||
if (dma_wr_count == 6'd47) begin
|
||||
bank_storing[dma_store_bank] <= 1'b0;
|
||||
dma_store_bank <= ~dma_store_bank;
|
||||
store_group <= store_group + 32'd1;
|
||||
completed_groups <= completed_groups + 32'd1;
|
||||
if ((completed_groups + 32'd1) >= dma_groups) begin
|
||||
dma_busy <= 1'b0;
|
||||
dma_done <= 1'b1;
|
||||
end
|
||||
dma_wr_state <= DMA_WR_IDLE;
|
||||
end else begin
|
||||
dma_wr_count <= dma_wr_count + 6'd1;
|
||||
end
|
||||
end
|
||||
DMA_WR_RESP: begin
|
||||
m_axi_bready <= 1'b0;
|
||||
dma_wr_state <= DMA_WR_IDLE;
|
||||
end
|
||||
default: dma_wr_state <= DMA_WR_IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
assign intr = done;
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,307 +0,0 @@
|
||||
// Shared AXI slave for the legacy FFT accelerator and the ML-KEM accelerator.
|
||||
//
|
||||
// Both software stacks use the same base address, 0xbf400000. Their internal
|
||||
// maps do not overlap:
|
||||
// ML-KEM: 0x0000..0x3fff
|
||||
// FFT: 0x8000..0xcfff
|
||||
// PRNG: 0xd000..0xd0ff
|
||||
// Route the low ML-KEM block to ML-KEM, the high FFT block to FFT, and the
|
||||
// following 0xdxxx block to PRNG.
|
||||
module fft_mlkem_axi_slave (
|
||||
input clk,
|
||||
input resetn,
|
||||
|
||||
input [4:0] s_axi_awid,
|
||||
input [31:0] s_axi_awaddr,
|
||||
input [7:0] s_axi_awlen,
|
||||
input [2:0] s_axi_awsize,
|
||||
input [1:0] s_axi_awburst,
|
||||
input s_axi_awlock,
|
||||
input [3:0] s_axi_awcache,
|
||||
input [2:0] s_axi_awprot,
|
||||
input s_axi_awvalid,
|
||||
output s_axi_awready,
|
||||
|
||||
input [4:0] s_axi_wid,
|
||||
input [31:0] s_axi_wdata,
|
||||
input [3:0] s_axi_wstrb,
|
||||
input s_axi_wlast,
|
||||
input s_axi_wvalid,
|
||||
output s_axi_wready,
|
||||
|
||||
output [4:0] s_axi_bid,
|
||||
output [1:0] s_axi_bresp,
|
||||
output s_axi_bvalid,
|
||||
input s_axi_bready,
|
||||
|
||||
input [4:0] s_axi_arid,
|
||||
input [31:0] s_axi_araddr,
|
||||
input [7:0] s_axi_arlen,
|
||||
input [2:0] s_axi_arsize,
|
||||
input [1:0] s_axi_arburst,
|
||||
input s_axi_arlock,
|
||||
input [3:0] s_axi_arcache,
|
||||
input [2:0] s_axi_arprot,
|
||||
input s_axi_arvalid,
|
||||
output s_axi_arready,
|
||||
|
||||
output [4:0] s_axi_rid,
|
||||
output [31:0] s_axi_rdata,
|
||||
output [1:0] s_axi_rresp,
|
||||
output s_axi_rlast,
|
||||
output s_axi_rvalid,
|
||||
input s_axi_rready,
|
||||
|
||||
output fft_finish,
|
||||
output mlkem_intr
|
||||
);
|
||||
|
||||
localparam SEL_MLKEM = 2'd0;
|
||||
localparam SEL_FFT = 2'd1;
|
||||
localparam SEL_PRNG = 2'd2;
|
||||
|
||||
wire aw_to_mlkem = (s_axi_awaddr[15:12] <= 4'h3);
|
||||
wire aw_to_prng = (s_axi_awaddr[15:12] == 4'hd);
|
||||
wire ar_to_mlkem = (s_axi_araddr[15:12] <= 4'h3);
|
||||
wire ar_to_prng = (s_axi_araddr[15:12] == 4'hd);
|
||||
|
||||
wire [1:0] aw_sel = aw_to_mlkem ? SEL_MLKEM :
|
||||
aw_to_prng ? SEL_PRNG : SEL_FFT;
|
||||
wire [1:0] ar_sel = ar_to_mlkem ? SEL_MLKEM :
|
||||
ar_to_prng ? SEL_PRNG : SEL_FFT;
|
||||
|
||||
reg [1:0] write_sel;
|
||||
reg write_active;
|
||||
reg [1:0] read_sel;
|
||||
reg read_active;
|
||||
|
||||
wire mlkem_awready, mlkem_wready, mlkem_bvalid;
|
||||
wire [4:0] mlkem_bid;
|
||||
wire [1:0] mlkem_bresp;
|
||||
wire mlkem_arready, mlkem_rvalid, mlkem_rlast;
|
||||
wire [4:0] mlkem_rid;
|
||||
wire [31:0] mlkem_rdata;
|
||||
wire [1:0] mlkem_rresp;
|
||||
|
||||
wire fft_awready, fft_wready, fft_bvalid;
|
||||
wire [4:0] fft_bid;
|
||||
wire [1:0] fft_bresp;
|
||||
wire fft_arready, fft_rvalid, fft_rlast;
|
||||
wire [4:0] fft_rid;
|
||||
wire [31:0] fft_rdata;
|
||||
wire [1:0] fft_rresp;
|
||||
|
||||
wire prng_awready, prng_wready, prng_bvalid;
|
||||
wire [4:0] prng_bid;
|
||||
wire [1:0] prng_bresp;
|
||||
wire prng_arready, prng_rvalid, prng_rlast;
|
||||
wire [4:0] prng_rid;
|
||||
wire [31:0] prng_rdata;
|
||||
wire [1:0] prng_rresp;
|
||||
|
||||
wire [1:0] sel_w = write_active ? write_sel : aw_sel;
|
||||
wire [1:0] sel_r = read_active ? read_sel : ar_sel;
|
||||
|
||||
assign s_axi_awready = !write_active && (
|
||||
(aw_sel == SEL_MLKEM) ? mlkem_awready :
|
||||
(aw_sel == SEL_PRNG) ? prng_awready :
|
||||
fft_awready);
|
||||
assign s_axi_wready = (sel_w == SEL_MLKEM) ? mlkem_wready :
|
||||
(sel_w == SEL_PRNG) ? prng_wready :
|
||||
fft_wready;
|
||||
assign s_axi_bvalid = (sel_w == SEL_MLKEM) ? mlkem_bvalid :
|
||||
(sel_w == SEL_PRNG) ? prng_bvalid :
|
||||
fft_bvalid;
|
||||
assign s_axi_bid = (sel_w == SEL_MLKEM) ? mlkem_bid :
|
||||
(sel_w == SEL_PRNG) ? prng_bid :
|
||||
fft_bid;
|
||||
assign s_axi_bresp = (sel_w == SEL_MLKEM) ? mlkem_bresp :
|
||||
(sel_w == SEL_PRNG) ? prng_bresp :
|
||||
fft_bresp;
|
||||
|
||||
assign s_axi_arready = !read_active && (
|
||||
(ar_sel == SEL_MLKEM) ? mlkem_arready :
|
||||
(ar_sel == SEL_PRNG) ? prng_arready :
|
||||
fft_arready);
|
||||
assign s_axi_rvalid = (sel_r == SEL_MLKEM) ? mlkem_rvalid :
|
||||
(sel_r == SEL_PRNG) ? prng_rvalid :
|
||||
fft_rvalid;
|
||||
assign s_axi_rlast = (sel_r == SEL_MLKEM) ? mlkem_rlast :
|
||||
(sel_r == SEL_PRNG) ? prng_rlast :
|
||||
fft_rlast;
|
||||
assign s_axi_rid = (sel_r == SEL_MLKEM) ? mlkem_rid :
|
||||
(sel_r == SEL_PRNG) ? prng_rid :
|
||||
fft_rid;
|
||||
assign s_axi_rdata = (sel_r == SEL_MLKEM) ? mlkem_rdata :
|
||||
(sel_r == SEL_PRNG) ? prng_rdata :
|
||||
fft_rdata;
|
||||
assign s_axi_rresp = (sel_r == SEL_MLKEM) ? mlkem_rresp :
|
||||
(sel_r == SEL_PRNG) ? prng_rresp :
|
||||
fft_rresp;
|
||||
|
||||
always @(posedge clk or negedge resetn) begin
|
||||
if (!resetn) begin
|
||||
write_active <= 1'b0;
|
||||
write_sel <= SEL_MLKEM;
|
||||
read_active <= 1'b0;
|
||||
read_sel <= SEL_MLKEM;
|
||||
end else begin
|
||||
if (!write_active && s_axi_awvalid && s_axi_awready) begin
|
||||
write_active <= 1'b1;
|
||||
write_sel <= aw_sel;
|
||||
end else if (write_active && s_axi_bvalid && s_axi_bready) begin
|
||||
write_active <= 1'b0;
|
||||
end
|
||||
|
||||
if (!read_active && s_axi_arvalid && s_axi_arready) begin
|
||||
read_active <= 1'b1;
|
||||
read_sel <= ar_sel;
|
||||
end else if (read_active && s_axi_rvalid && s_axi_rready && s_axi_rlast) begin
|
||||
read_active <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
mlkem_axi_slave u_mlkem_axi_slave (
|
||||
.clk (clk),
|
||||
.resetn (resetn),
|
||||
|
||||
.s_axi_awid (s_axi_awid),
|
||||
.s_axi_awaddr (s_axi_awaddr),
|
||||
.s_axi_awlen (s_axi_awlen),
|
||||
.s_axi_awsize (s_axi_awsize),
|
||||
.s_axi_awburst (s_axi_awburst),
|
||||
.s_axi_awlock (s_axi_awlock),
|
||||
.s_axi_awcache (s_axi_awcache),
|
||||
.s_axi_awprot (s_axi_awprot),
|
||||
.s_axi_awvalid (s_axi_awvalid && !write_active && (aw_sel == SEL_MLKEM)),
|
||||
.s_axi_awready (mlkem_awready),
|
||||
|
||||
.s_axi_wid (s_axi_wid),
|
||||
.s_axi_wdata (s_axi_wdata),
|
||||
.s_axi_wstrb (s_axi_wstrb),
|
||||
.s_axi_wlast (s_axi_wlast),
|
||||
.s_axi_wvalid (s_axi_wvalid && (sel_w == SEL_MLKEM)),
|
||||
.s_axi_wready (mlkem_wready),
|
||||
|
||||
.s_axi_bid (mlkem_bid),
|
||||
.s_axi_bresp (mlkem_bresp),
|
||||
.s_axi_bvalid (mlkem_bvalid),
|
||||
.s_axi_bready (s_axi_bready && (sel_w == SEL_MLKEM)),
|
||||
|
||||
.s_axi_arid (s_axi_arid),
|
||||
.s_axi_araddr (s_axi_araddr),
|
||||
.s_axi_arlen (s_axi_arlen),
|
||||
.s_axi_arsize (s_axi_arsize),
|
||||
.s_axi_arburst (s_axi_arburst),
|
||||
.s_axi_arlock (s_axi_arlock),
|
||||
.s_axi_arcache (s_axi_arcache),
|
||||
.s_axi_arprot (s_axi_arprot),
|
||||
.s_axi_arvalid (s_axi_arvalid && !read_active && (ar_sel == SEL_MLKEM)),
|
||||
.s_axi_arready (mlkem_arready),
|
||||
|
||||
.s_axi_rid (mlkem_rid),
|
||||
.s_axi_rdata (mlkem_rdata),
|
||||
.s_axi_rresp (mlkem_rresp),
|
||||
.s_axi_rlast (mlkem_rlast),
|
||||
.s_axi_rvalid (mlkem_rvalid),
|
||||
.s_axi_rready (s_axi_rready && (sel_r == SEL_MLKEM)),
|
||||
|
||||
.intr (mlkem_intr)
|
||||
);
|
||||
|
||||
fft_controller u_fft_controller (
|
||||
.aclk (clk),
|
||||
.aresetn (resetn),
|
||||
|
||||
.s_awid (s_axi_awid),
|
||||
.s_awaddr (s_axi_awaddr),
|
||||
.s_awlen (s_axi_awlen),
|
||||
.s_awsize (s_axi_awsize),
|
||||
.s_awburst (s_axi_awburst),
|
||||
.s_awlock (s_axi_awlock),
|
||||
.s_awcache (s_axi_awcache),
|
||||
.s_awprot (s_axi_awprot),
|
||||
.s_awvalid (s_axi_awvalid && !write_active && (aw_sel == SEL_FFT)),
|
||||
.s_awready (fft_awready),
|
||||
|
||||
.s_wid (s_axi_wid),
|
||||
.s_wdata (s_axi_wdata),
|
||||
.s_wstrb (s_axi_wstrb),
|
||||
.s_wlast (s_axi_wlast),
|
||||
.s_wvalid (s_axi_wvalid && (sel_w == SEL_FFT)),
|
||||
.s_wready (fft_wready),
|
||||
|
||||
.s_bid (fft_bid),
|
||||
.s_bresp (fft_bresp),
|
||||
.s_bvalid (fft_bvalid),
|
||||
.s_bready (s_axi_bready && (sel_w == SEL_FFT)),
|
||||
|
||||
.s_arid (s_axi_arid),
|
||||
.s_araddr (s_axi_araddr),
|
||||
.s_arlen (s_axi_arlen),
|
||||
.s_arsize (s_axi_arsize),
|
||||
.s_arburst (s_axi_arburst),
|
||||
.s_arlock (s_axi_arlock),
|
||||
.s_arcache (s_axi_arcache),
|
||||
.s_arprot (s_axi_arprot),
|
||||
.s_arvalid (s_axi_arvalid && !read_active && (ar_sel == SEL_FFT)),
|
||||
.s_arready (fft_arready),
|
||||
|
||||
.s_rid (fft_rid),
|
||||
.s_rdata (fft_rdata),
|
||||
.s_rresp (fft_rresp),
|
||||
.s_rlast (fft_rlast),
|
||||
.s_rvalid (fft_rvalid),
|
||||
.s_rready (s_axi_rready && (sel_r == SEL_FFT)),
|
||||
|
||||
.fft_finish (fft_finish)
|
||||
);
|
||||
|
||||
prng_axi_slave u_prng_axi_slave (
|
||||
.clk (clk),
|
||||
.resetn (resetn),
|
||||
|
||||
.s_axi_awid (s_axi_awid),
|
||||
.s_axi_awaddr (s_axi_awaddr),
|
||||
.s_axi_awlen (s_axi_awlen),
|
||||
.s_axi_awsize (s_axi_awsize),
|
||||
.s_axi_awburst (s_axi_awburst),
|
||||
.s_axi_awlock (s_axi_awlock),
|
||||
.s_axi_awcache (s_axi_awcache),
|
||||
.s_axi_awprot (s_axi_awprot),
|
||||
.s_axi_awvalid (s_axi_awvalid && !write_active && (aw_sel == SEL_PRNG)),
|
||||
.s_axi_awready (prng_awready),
|
||||
|
||||
.s_axi_wid (s_axi_wid),
|
||||
.s_axi_wdata (s_axi_wdata),
|
||||
.s_axi_wstrb (s_axi_wstrb),
|
||||
.s_axi_wlast (s_axi_wlast),
|
||||
.s_axi_wvalid (s_axi_wvalid && (sel_w == SEL_PRNG)),
|
||||
.s_axi_wready (prng_wready),
|
||||
|
||||
.s_axi_bid (prng_bid),
|
||||
.s_axi_bresp (prng_bresp),
|
||||
.s_axi_bvalid (prng_bvalid),
|
||||
.s_axi_bready (s_axi_bready && (sel_w == SEL_PRNG)),
|
||||
|
||||
.s_axi_arid (s_axi_arid),
|
||||
.s_axi_araddr (s_axi_araddr),
|
||||
.s_axi_arlen (s_axi_arlen),
|
||||
.s_axi_arsize (s_axi_arsize),
|
||||
.s_axi_arburst (s_axi_arburst),
|
||||
.s_axi_arlock (s_axi_arlock),
|
||||
.s_axi_arcache (s_axi_arcache),
|
||||
.s_axi_arprot (s_axi_arprot),
|
||||
.s_axi_arvalid (s_axi_arvalid && !read_active && (ar_sel == SEL_PRNG)),
|
||||
.s_axi_arready (prng_arready),
|
||||
|
||||
.s_axi_rid (prng_rid),
|
||||
.s_axi_rdata (prng_rdata),
|
||||
.s_axi_rresp (prng_rresp),
|
||||
.s_axi_rlast (prng_rlast),
|
||||
.s_axi_rvalid (prng_rvalid),
|
||||
.s_axi_rready (s_axi_rready && (sel_r == SEL_PRNG))
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -24,9 +24,6 @@
|
||||
// 0x10C RDBK_SEL RW 0=ek 1=dk_pke 2=full-dk 3=ciphertext
|
||||
// 0x110 RDBK_ADDR RW output byte index
|
||||
// 0x114 RDBK_DATA R selected readback-tap byte (low 8 bits)
|
||||
// 0x1000..0x1FFF EK W: preload ek_in, R: read generated ek
|
||||
// 0x2000..0x2FFF DK W: preload dk_in, R: read generated full dk
|
||||
// 0x3000..0x3FFF CT W: preload c_in, R: read generated ciphertext
|
||||
module mlkem_axi_slave (
|
||||
input clk, // sys_clk (AXI bus clock, 50 MHz)
|
||||
input resetn, // sys_resetn (active low, already synchronized)
|
||||
@@ -97,9 +94,6 @@ module mlkem_axi_slave (
|
||||
localparam ADDR_RDB_SEL = 12'h10C;
|
||||
localparam ADDR_RDB_ADR = 12'h110;
|
||||
localparam ADDR_RDB_DAT = 12'h114;
|
||||
localparam WIN_EK = 4'h1;
|
||||
localparam WIN_DK = 4'h2;
|
||||
localparam WIN_CT = 4'h3;
|
||||
|
||||
assign s_axi_bresp = 2'b00;
|
||||
assign s_axi_rresp = 2'b00;
|
||||
@@ -117,41 +111,6 @@ module mlkem_axi_slave (
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [7:0] select_byte;
|
||||
input [31:0] word;
|
||||
input [1:0] lane;
|
||||
begin
|
||||
case (lane)
|
||||
2'd0: select_byte = word[7:0];
|
||||
2'd1: select_byte = word[15:8];
|
||||
2'd2: select_byte = word[23:16];
|
||||
default: select_byte = word[31:24];
|
||||
endcase
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [1:0] window_preload_sel;
|
||||
input [3:0] window;
|
||||
begin
|
||||
case (window)
|
||||
WIN_DK: window_preload_sel = 2'd1;
|
||||
WIN_CT: window_preload_sel = 2'd2;
|
||||
default: window_preload_sel = 2'd0;
|
||||
endcase
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [1:0] window_readback_sel;
|
||||
input [3:0] window;
|
||||
begin
|
||||
case (window)
|
||||
WIN_DK: window_readback_sel = 2'd2; // full dk
|
||||
WIN_CT: window_readback_sel = 2'd3; // ciphertext
|
||||
default: window_readback_sel = 2'd0; // ek
|
||||
endcase
|
||||
end
|
||||
endfunction
|
||||
|
||||
// ==========================================
|
||||
// mlkem_clk = sys_clk / 2 (25 MHz) via toggle FF.
|
||||
// ==========================================
|
||||
@@ -225,25 +184,19 @@ module mlkem_axi_slave (
|
||||
reg [1:0] pre_sel_l;
|
||||
reg [11:0] pre_addr_l;
|
||||
reg [7:0] pre_byte_l;
|
||||
reg pre_auto_inc_l;
|
||||
|
||||
// ==========================================
|
||||
// mlkem_top instance
|
||||
// ==========================================
|
||||
wire [7:0] dbg_byte_o, dbg_dk_o, dbg_ct_o;
|
||||
wire [255:0] ss_o;
|
||||
wire bulk_read_active;
|
||||
wire [1:0] bulk_rdb_sel;
|
||||
wire [11:0] bulk_rdb_addr;
|
||||
wire [1:0] eff_rdb_sel = bulk_read_active ? bulk_rdb_sel : rdb_sel;
|
||||
wire [11:0] eff_rdb_addr = bulk_read_active ? bulk_rdb_addr : rdb_addr;
|
||||
wire dbg_byte_sel = (eff_rdb_sel == 2'd1); // 0=ek, 1=dk_pke
|
||||
wire dbg_byte_sel = (rdb_sel == 2'd1); // 0=ek, 1=dk_pke
|
||||
// The core's ek/dkp read-address muxes give dbg_dk_idx_i priority over
|
||||
// dbg_byte_idx_i whenever it lands in the ek (768..1567) or dk_pke (<768)
|
||||
// region (mlkem_top: ek_rd_addr / dkp_rd_addr). So only drive dbg_dk_idx_i
|
||||
// with the real index during a full-dk readback (rdb_sel==2); otherwise hold
|
||||
// it out of range (0xFFF) so an ek/dk_pke readback isn't corrupted.
|
||||
wire [11:0] dbg_dk_idx = (eff_rdb_sel == 2'd2) ? eff_rdb_addr : 12'hFFF;
|
||||
wire [11:0] dbg_dk_idx = (rdb_sel == 2'd2) ? rdb_addr : 12'hFFF;
|
||||
|
||||
// one-cycle write-enable pulses into the core (combinational off the synced
|
||||
// edge; pre_sel_l/pre_addr_l/pre_byte_l are stable in sys, sampled by core).
|
||||
@@ -277,7 +230,7 @@ module mlkem_axi_slave (
|
||||
// shared secret out
|
||||
.ss_o (ss_o),
|
||||
// ciphertext readback tap
|
||||
.dbg_ct_idx_i (eff_rdb_addr[10:0]),
|
||||
.dbg_ct_idx_i (rdb_addr[10:0]),
|
||||
.dbg_ct_o (dbg_ct_o),
|
||||
// coefficient debug tap (unused by CPU path; tie inputs off)
|
||||
.dbg_slot_i (6'd0),
|
||||
@@ -285,7 +238,7 @@ module mlkem_axi_slave (
|
||||
.dbg_coeff_o (/* unused */),
|
||||
// ek / dk_pke byte readback
|
||||
.dbg_byte_sel_i (dbg_byte_sel),
|
||||
.dbg_byte_idx_i (eff_rdb_addr[10:0]),
|
||||
.dbg_byte_idx_i (rdb_addr[10:0]),
|
||||
.dbg_byte_o (dbg_byte_o),
|
||||
// full-dk byte readback
|
||||
.dbg_dk_idx_i (dbg_dk_idx),
|
||||
@@ -351,27 +304,17 @@ module mlkem_axi_slave (
|
||||
// AXI Write channel (INCR burst). Preload-data beats are wait-stated until
|
||||
// the cross-domain byte handshake completes (W_PRELOAD).
|
||||
// ==========================================
|
||||
localparam W_IDLE = 3'd0;
|
||||
localparam W_DATA = 3'd1;
|
||||
localparam W_PRELOAD = 3'd2;
|
||||
localparam W_STREAM = 3'd3;
|
||||
localparam W_RESP = 3'd4;
|
||||
localparam W_IDLE = 2'd0;
|
||||
localparam W_DATA = 2'd1;
|
||||
localparam W_PRELOAD = 2'd2;
|
||||
localparam W_RESP = 2'd3;
|
||||
|
||||
reg [2:0] w_state;
|
||||
reg [1:0] w_state;
|
||||
reg [31:0] w_addr;
|
||||
reg [4:0] w_id;
|
||||
reg [1:0] w_burst;
|
||||
reg w_last_l; // saved wlast across a preload wait
|
||||
wire [11:0] w_offset = w_addr[11:0];
|
||||
wire w_stream_window = (w_addr[15:12] == WIN_EK) ||
|
||||
(w_addr[15:12] == WIN_DK) ||
|
||||
(w_addr[15:12] == WIN_CT);
|
||||
|
||||
reg [31:0] stream_wdata;
|
||||
reg [3:0] stream_wstrb;
|
||||
reg [11:0] stream_byte_addr;
|
||||
reg [2:0] stream_lane;
|
||||
reg [1:0] stream_sel;
|
||||
|
||||
assign s_axi_bid = w_id;
|
||||
|
||||
@@ -395,13 +338,7 @@ module mlkem_axi_slave (
|
||||
pre_sel_l <= 2'd0;
|
||||
pre_addr_l <= 12'd0;
|
||||
pre_byte_l <= 8'd0;
|
||||
pre_auto_inc_l <= 1'b0;
|
||||
w_last_l <= 1'b0;
|
||||
stream_wdata <= 32'd0;
|
||||
stream_wstrb <= 4'd0;
|
||||
stream_byte_addr <= 12'd0;
|
||||
stream_lane <= 3'd0;
|
||||
stream_sel <= 2'd0;
|
||||
for (wi = 0; wi < 8; wi = wi + 1) begin
|
||||
d_word[wi] = 32'd0;
|
||||
z_word[wi] = 32'd0;
|
||||
@@ -411,8 +348,7 @@ module mlkem_axi_slave (
|
||||
// clear the preload-busy flag when the mlkem domain acks the byte
|
||||
if (pre_ack_edge) begin
|
||||
pre_busy <= 1'b0;
|
||||
if (pre_auto_inc_l)
|
||||
pre_addr <= pre_addr + 12'd1; // legacy PRE_DAT auto-increment
|
||||
pre_addr <= pre_addr + 12'd1; // auto-increment for next byte
|
||||
end
|
||||
|
||||
case (w_state)
|
||||
@@ -430,21 +366,11 @@ module mlkem_axi_slave (
|
||||
|
||||
W_DATA: begin
|
||||
if (s_axi_wvalid && s_axi_wready) begin
|
||||
if (w_stream_window) begin
|
||||
stream_wdata <= s_axi_wdata;
|
||||
stream_wstrb <= s_axi_wstrb;
|
||||
stream_byte_addr <= w_offset;
|
||||
stream_lane <= 3'd0;
|
||||
stream_sel <= window_preload_sel(w_addr[15:12]);
|
||||
w_last_l <= s_axi_wlast;
|
||||
s_axi_wready <= 1'b0;
|
||||
w_state <= W_STREAM;
|
||||
end else if (w_offset == ADDR_PRE_DAT) begin
|
||||
if (w_offset == ADDR_PRE_DAT) begin
|
||||
// launch cross-domain byte write; stall the beat.
|
||||
pre_sel_l <= pre_sel;
|
||||
pre_addr_l <= pre_addr;
|
||||
pre_byte_l <= s_axi_wdata[7:0];
|
||||
pre_auto_inc_l <= 1'b1;
|
||||
pre_req_tg <= ~pre_req_tg;
|
||||
pre_busy <= 1'b1;
|
||||
w_last_l <= s_axi_wlast;
|
||||
@@ -498,31 +424,6 @@ module mlkem_axi_slave (
|
||||
end
|
||||
end
|
||||
|
||||
W_STREAM: begin
|
||||
if (!pre_busy) begin
|
||||
if (stream_lane < 3'd4 && !stream_wstrb[stream_lane[1:0]]) begin
|
||||
stream_lane <= stream_lane + 3'd1;
|
||||
end else if (stream_lane < 3'd4) begin
|
||||
pre_sel_l <= stream_sel;
|
||||
pre_addr_l <= stream_byte_addr + {10'd0, stream_lane[1:0]};
|
||||
pre_byte_l <= select_byte(stream_wdata, stream_lane[1:0]);
|
||||
pre_auto_inc_l <= 1'b0;
|
||||
pre_req_tg <= ~pre_req_tg;
|
||||
pre_busy <= 1'b1;
|
||||
stream_lane <= stream_lane + 3'd1;
|
||||
end else begin
|
||||
if (w_burst == 2'b01) w_addr <= w_addr + 32'd4;
|
||||
if (w_last_l) begin
|
||||
s_axi_bvalid <= 1'b1;
|
||||
w_state <= W_RESP;
|
||||
end else begin
|
||||
s_axi_wready <= 1'b1;
|
||||
w_state <= W_DATA;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
W_RESP: begin
|
||||
if (s_axi_bvalid && s_axi_bready) begin
|
||||
s_axi_bvalid <= 1'b0;
|
||||
@@ -538,31 +439,15 @@ module mlkem_axi_slave (
|
||||
// ==========================================
|
||||
// AXI Read channel (INCR burst).
|
||||
// ==========================================
|
||||
localparam R_IDLE = 3'd0;
|
||||
localparam R_DATA = 3'd1;
|
||||
localparam R_BULK_WAIT = 3'd2;
|
||||
localparam RDB_WAIT_CYCLES = 3'd4;
|
||||
localparam R_IDLE = 1'b0;
|
||||
localparam R_DATA = 1'b1;
|
||||
|
||||
reg [2:0] r_state;
|
||||
reg r_state;
|
||||
reg [31:0] r_addr;
|
||||
reg [7:0] r_cnt;
|
||||
reg [7:0] r_len;
|
||||
reg [1:0] r_burst;
|
||||
wire [11:0] r_offset = r_addr[11:0];
|
||||
wire ar_stream_window = (s_axi_araddr[15:12] == WIN_EK) ||
|
||||
(s_axi_araddr[15:12] == WIN_DK) ||
|
||||
(s_axi_araddr[15:12] == WIN_CT);
|
||||
|
||||
reg r_bulk;
|
||||
reg [1:0] bulk_sel_r;
|
||||
reg [11:0] bulk_addr_r;
|
||||
reg [1:0] bulk_lane;
|
||||
reg [2:0] bulk_wait;
|
||||
reg [31:0] bulk_word;
|
||||
|
||||
assign bulk_read_active = r_bulk && (r_state == R_BULK_WAIT);
|
||||
assign bulk_rdb_sel = bulk_sel_r;
|
||||
assign bulk_rdb_addr = bulk_addr_r;
|
||||
|
||||
always @(posedge clk or negedge resetn) begin
|
||||
if (!resetn) begin
|
||||
@@ -575,12 +460,6 @@ module mlkem_axi_slave (
|
||||
r_cnt <= 8'd0;
|
||||
r_len <= 8'd0;
|
||||
r_burst <= 2'd0;
|
||||
r_bulk <= 1'b0;
|
||||
bulk_sel_r <= 2'd0;
|
||||
bulk_addr_r <= 12'd0;
|
||||
bulk_lane <= 2'd0;
|
||||
bulk_wait <= 3'd0;
|
||||
bulk_word <= 32'd0;
|
||||
end else begin
|
||||
case (r_state)
|
||||
R_IDLE: begin
|
||||
@@ -591,44 +470,10 @@ module mlkem_axi_slave (
|
||||
r_len <= s_axi_arlen;
|
||||
r_burst <= s_axi_arburst;
|
||||
r_cnt <= 8'd0;
|
||||
s_axi_rvalid <= 1'b1;
|
||||
s_axi_rlast <= (s_axi_arlen == 8'd0);
|
||||
s_axi_rid <= s_axi_arid;
|
||||
r_bulk <= ar_stream_window;
|
||||
if (ar_stream_window) begin
|
||||
bulk_sel_r <= window_readback_sel(s_axi_araddr[15:12]);
|
||||
bulk_addr_r <= s_axi_araddr[11:0];
|
||||
bulk_lane <= 2'd0;
|
||||
bulk_wait <= RDB_WAIT_CYCLES;
|
||||
bulk_word <= 32'd0;
|
||||
s_axi_rvalid <= 1'b0;
|
||||
s_axi_rlast <= 1'b0;
|
||||
r_state <= R_BULK_WAIT;
|
||||
end else begin
|
||||
s_axi_rvalid <= 1'b1;
|
||||
s_axi_rlast <= (s_axi_arlen == 8'd0);
|
||||
r_state <= R_DATA;
|
||||
end
|
||||
end
|
||||
end
|
||||
R_BULK_WAIT: begin
|
||||
if (bulk_wait != 3'd0) begin
|
||||
bulk_wait <= bulk_wait - 3'd1;
|
||||
end else begin
|
||||
case (bulk_lane)
|
||||
2'd0: bulk_word[7:0] <= rdb_byte;
|
||||
2'd1: bulk_word[15:8] <= rdb_byte;
|
||||
2'd2: bulk_word[23:16] <= rdb_byte;
|
||||
default: bulk_word[31:24] <= rdb_byte;
|
||||
endcase
|
||||
|
||||
if (bulk_lane == 2'd3) begin
|
||||
s_axi_rvalid <= 1'b1;
|
||||
s_axi_rlast <= (r_cnt == r_len);
|
||||
r_state <= R_DATA;
|
||||
end else begin
|
||||
bulk_lane <= bulk_lane + 2'd1;
|
||||
bulk_addr_r <= bulk_addr_r + 12'd1;
|
||||
bulk_wait <= RDB_WAIT_CYCLES;
|
||||
end
|
||||
r_state <= R_DATA;
|
||||
end
|
||||
end
|
||||
R_DATA: begin
|
||||
@@ -637,22 +482,11 @@ module mlkem_axi_slave (
|
||||
s_axi_rvalid <= 1'b0;
|
||||
s_axi_rlast <= 1'b0;
|
||||
s_axi_arready <= 1'b1;
|
||||
r_bulk <= 1'b0;
|
||||
r_state <= R_IDLE;
|
||||
end else begin
|
||||
r_cnt <= r_cnt + 8'd1;
|
||||
s_axi_rlast <= (r_cnt + 8'd1 == r_len);
|
||||
if (r_burst == 2'b01) r_addr <= r_addr + 32'd4;
|
||||
if (r_bulk) begin
|
||||
bulk_addr_r <= (r_burst == 2'b01) ? (r_offset + 12'd4) : r_offset;
|
||||
bulk_lane <= 2'd0;
|
||||
bulk_wait <= RDB_WAIT_CYCLES;
|
||||
bulk_word <= 32'd0;
|
||||
s_axi_rvalid <= 1'b0;
|
||||
s_axi_rlast <= 1'b0;
|
||||
r_state <= R_BULK_WAIT;
|
||||
end else begin
|
||||
s_axi_rlast <= (r_cnt + 8'd1 == r_len);
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
@@ -665,14 +499,12 @@ module mlkem_axi_slave (
|
||||
// first beat is valid the cycle rvalid asserts (matches matmul style).
|
||||
wire [11:0] cur_off = (r_state == R_DATA) ? r_offset : s_axi_araddr[11:0];
|
||||
// Selected readback byte (taps are combinational over the core's BRAMs).
|
||||
wire [7:0] rdb_byte = (eff_rdb_sel == 2'd3) ? dbg_ct_o :
|
||||
(eff_rdb_sel == 2'd2) ? dbg_dk_o : dbg_byte_o;
|
||||
wire [7:0] rdb_byte = (rdb_sel == 2'd3) ? dbg_ct_o :
|
||||
(rdb_sel == 2'd2) ? dbg_dk_o : dbg_byte_o;
|
||||
|
||||
always @(*) begin
|
||||
s_axi_rdata = 32'd0;
|
||||
if (r_bulk && r_state == R_DATA) begin
|
||||
s_axi_rdata = bulk_word;
|
||||
end else if (r_state == R_DATA || (r_state == R_IDLE && s_axi_arvalid)) begin
|
||||
if (r_state == R_DATA || (r_state == R_IDLE && s_axi_arvalid)) begin
|
||||
case (1'b1)
|
||||
(cur_off == ADDR_CTRL): s_axi_rdata = 32'd0;
|
||||
(cur_off == ADDR_STATUS): s_axi_rdata = {29'd0, pre_busy, status_done, status_busy};
|
||||
|
||||
@@ -1,218 +0,0 @@
|
||||
// Lightweight AXI4 register endpoint for a pseudo-random generator.
|
||||
//
|
||||
// Register map, byte offsets within the shared accelerator window:
|
||||
// 0xd000 CTRL W bit0=mix software seed, bit1=clear counters
|
||||
// 0xd004 STATUS R bit0=ready
|
||||
// 0xd008 DATA R next 32-bit random word
|
||||
// 0xd00c COUNT R number of DATA reads
|
||||
// 0xd010 SEED W software seed/mix value
|
||||
//
|
||||
// This block is deterministic unless software mixes in an external seed. It
|
||||
// intentionally uses only flops, XORs, shifts, and adders.
|
||||
module prng_axi_slave (
|
||||
input clk,
|
||||
input resetn,
|
||||
|
||||
input [4:0] s_axi_awid,
|
||||
input [31:0] s_axi_awaddr,
|
||||
input [7:0] s_axi_awlen,
|
||||
input [2:0] s_axi_awsize,
|
||||
input [1:0] s_axi_awburst,
|
||||
input s_axi_awlock,
|
||||
input [3:0] s_axi_awcache,
|
||||
input [2:0] s_axi_awprot,
|
||||
input s_axi_awvalid,
|
||||
output s_axi_awready,
|
||||
|
||||
input [4:0] s_axi_wid,
|
||||
input [31:0] s_axi_wdata,
|
||||
input [3:0] s_axi_wstrb,
|
||||
input s_axi_wlast,
|
||||
input s_axi_wvalid,
|
||||
output s_axi_wready,
|
||||
|
||||
output [4:0] s_axi_bid,
|
||||
output [1:0] s_axi_bresp,
|
||||
output reg s_axi_bvalid,
|
||||
input s_axi_bready,
|
||||
|
||||
input [4:0] s_axi_arid,
|
||||
input [31:0] s_axi_araddr,
|
||||
input [7:0] s_axi_arlen,
|
||||
input [2:0] s_axi_arsize,
|
||||
input [1:0] s_axi_arburst,
|
||||
input s_axi_arlock,
|
||||
input [3:0] s_axi_arcache,
|
||||
input [2:0] s_axi_arprot,
|
||||
input s_axi_arvalid,
|
||||
output s_axi_arready,
|
||||
|
||||
output reg [4:0] s_axi_rid,
|
||||
output reg [31:0] s_axi_rdata,
|
||||
output [1:0] s_axi_rresp,
|
||||
output reg s_axi_rlast,
|
||||
output reg s_axi_rvalid,
|
||||
input s_axi_rready
|
||||
);
|
||||
|
||||
localparam ADDR_CTRL = 12'h000;
|
||||
localparam ADDR_STATUS = 12'h004;
|
||||
localparam ADDR_DATA = 12'h008;
|
||||
localparam ADDR_COUNT = 12'h00c;
|
||||
localparam ADDR_SEED = 12'h010;
|
||||
|
||||
assign s_axi_bresp = 2'b00;
|
||||
assign s_axi_rresp = 2'b00;
|
||||
|
||||
reg [4:0] awid_reg;
|
||||
reg [31:0] awaddr_reg;
|
||||
reg [7:0] awleft_reg;
|
||||
reg write_active;
|
||||
|
||||
assign s_axi_awready = !write_active && !s_axi_bvalid;
|
||||
assign s_axi_wready = write_active && !s_axi_bvalid;
|
||||
assign s_axi_bid = awid_reg;
|
||||
|
||||
reg [31:0] araddr_reg;
|
||||
reg [7:0] arleft_reg;
|
||||
reg read_active;
|
||||
|
||||
assign s_axi_arready = !read_active && !s_axi_rvalid;
|
||||
|
||||
reg [127:0] rng_state;
|
||||
reg [63:0] free_counter;
|
||||
reg [31:0] seed_mix;
|
||||
reg [31:0] data_reads;
|
||||
|
||||
wire lfsr_fb = rng_state[127] ^ rng_state[125] ^ rng_state[100] ^
|
||||
rng_state[98] ^ rng_state[27] ^ rng_state[0] ^
|
||||
free_counter[0];
|
||||
wire [127:0] rng_next = {rng_state[126:0], lfsr_fb} ^
|
||||
{free_counter, free_counter ^ {32'h0, seed_mix}};
|
||||
wire [31:0] rng_word = rng_state[31:0] ^ rng_state[63:32] ^
|
||||
rng_state[95:64] ^ rng_state[127:96] ^
|
||||
free_counter[31:0] ^ free_counter[63:32] ^
|
||||
seed_mix;
|
||||
|
||||
function [31:0] apply_wstrb;
|
||||
input [31:0] old_value;
|
||||
input [31:0] new_value;
|
||||
input [3:0] strobe;
|
||||
begin
|
||||
apply_wstrb = old_value;
|
||||
if (strobe[0]) apply_wstrb[7:0] = new_value[7:0];
|
||||
if (strobe[1]) apply_wstrb[15:8] = new_value[15:8];
|
||||
if (strobe[2]) apply_wstrb[23:16] = new_value[23:16];
|
||||
if (strobe[3]) apply_wstrb[31:24] = new_value[31:24];
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [31:0] read_reg;
|
||||
input [31:0] addr;
|
||||
begin
|
||||
case (addr[11:0])
|
||||
ADDR_STATUS: read_reg = 32'h00000001;
|
||||
ADDR_DATA: read_reg = rng_word;
|
||||
ADDR_COUNT: read_reg = data_reads;
|
||||
ADDR_SEED: read_reg = seed_mix;
|
||||
default: read_reg = 32'h00000000;
|
||||
endcase
|
||||
end
|
||||
endfunction
|
||||
|
||||
wire write_fire = s_axi_wvalid && s_axi_wready;
|
||||
wire read_fire = s_axi_rvalid && s_axi_rready;
|
||||
wire data_read_fire = read_fire && (araddr_reg[11:0] == ADDR_DATA);
|
||||
wire [31:0] next_araddr = araddr_reg + 32'd4;
|
||||
wire [31:0] next_awaddr = awaddr_reg + 32'd4;
|
||||
|
||||
always @(posedge clk or negedge resetn) begin
|
||||
if (!resetn) begin
|
||||
awid_reg <= 5'b0;
|
||||
awaddr_reg <= 32'b0;
|
||||
awleft_reg <= 8'b0;
|
||||
write_active <= 1'b0;
|
||||
s_axi_bvalid <= 1'b0;
|
||||
|
||||
araddr_reg <= 32'b0;
|
||||
arleft_reg <= 8'b0;
|
||||
read_active <= 1'b0;
|
||||
s_axi_rid <= 5'b0;
|
||||
s_axi_rdata <= 32'b0;
|
||||
s_axi_rlast <= 1'b0;
|
||||
s_axi_rvalid <= 1'b0;
|
||||
|
||||
rng_state <= 128'h6d5a_56c3_9e37_79b9_a5a5_3c3c_c001_c0de;
|
||||
free_counter <= 64'h1;
|
||||
seed_mix <= 32'h31415927;
|
||||
data_reads <= 32'b0;
|
||||
end else begin
|
||||
free_counter <= free_counter + 64'h9e37_79b9_7f4a_7c15;
|
||||
rng_state <= rng_next;
|
||||
|
||||
if (s_axi_awvalid && s_axi_awready) begin
|
||||
awid_reg <= s_axi_awid;
|
||||
awaddr_reg <= s_axi_awaddr;
|
||||
awleft_reg <= s_axi_awlen;
|
||||
write_active <= 1'b1;
|
||||
end
|
||||
|
||||
if (write_fire) begin
|
||||
case (awaddr_reg[11:0])
|
||||
ADDR_CTRL: begin
|
||||
if (s_axi_wdata[0]) begin
|
||||
seed_mix <= seed_mix ^ s_axi_wdata ^ free_counter[31:0];
|
||||
rng_state <= rng_next ^ {4{s_axi_wdata}};
|
||||
end
|
||||
if (s_axi_wdata[1])
|
||||
data_reads <= 32'b0;
|
||||
end
|
||||
ADDR_SEED: begin
|
||||
seed_mix <= apply_wstrb(seed_mix, s_axi_wdata, s_axi_wstrb);
|
||||
rng_state <= rng_next ^ {s_axi_wdata, free_counter, ~s_axi_wdata};
|
||||
end
|
||||
default: begin
|
||||
end
|
||||
endcase
|
||||
|
||||
if (s_axi_wlast || awleft_reg == 8'b0) begin
|
||||
write_active <= 1'b0;
|
||||
s_axi_bvalid <= 1'b1;
|
||||
end else begin
|
||||
awleft_reg <= awleft_reg - 8'd1;
|
||||
awaddr_reg <= next_awaddr;
|
||||
end
|
||||
end
|
||||
|
||||
if (s_axi_bvalid && s_axi_bready)
|
||||
s_axi_bvalid <= 1'b0;
|
||||
|
||||
if (s_axi_arvalid && s_axi_arready) begin
|
||||
read_active <= 1'b1;
|
||||
araddr_reg <= s_axi_araddr;
|
||||
arleft_reg <= s_axi_arlen;
|
||||
s_axi_rid <= s_axi_arid;
|
||||
s_axi_rdata <= read_reg(s_axi_araddr);
|
||||
s_axi_rlast <= (s_axi_arlen == 8'b0);
|
||||
s_axi_rvalid <= 1'b1;
|
||||
end else if (read_fire) begin
|
||||
if (data_read_fire) begin
|
||||
data_reads <= data_reads + 32'd1;
|
||||
rng_state <= rng_next ^ {rng_word, rng_word ^ free_counter[31:0],
|
||||
free_counter[63:32], ~rng_word};
|
||||
end
|
||||
|
||||
if (s_axi_rlast) begin
|
||||
read_active <= 1'b0;
|
||||
s_axi_rvalid <= 1'b0;
|
||||
end else begin
|
||||
araddr_reg <= next_araddr;
|
||||
arleft_reg <= arleft_reg - 8'd1;
|
||||
s_axi_rdata <= read_reg(next_araddr);
|
||||
s_axi_rlast <= (arleft_reg == 8'd1);
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -75,21 +75,21 @@ module axi_wrap_ram_sp_external (
|
||||
output axi_bvalid ,
|
||||
input axi_bready ,
|
||||
|
||||
//BaseRAM信号
|
||||
inout [31:0] base_ram_data, //BaseRAM数据，低8位与CPLD串口控制器共享
|
||||
output [19:0] base_ram_addr, //BaseRAM地址
|
||||
output [ 3:0] base_ram_be_n, //BaseRAM字节使能，低有效。如果不使用字节使能，请保持为0
|
||||
output base_ram_ce_n, //BaseRAM片选，低有效
|
||||
output base_ram_oe_n, //BaseRAM读使能，低有效
|
||||
output base_ram_we_n, //BaseRAM写使能，低有效
|
||||
// BaseRAM
|
||||
inout [31:0] base_ram_data,
|
||||
output [19:0] base_ram_addr,
|
||||
output [ 3:0] base_ram_be_n,
|
||||
output base_ram_ce_n,
|
||||
output base_ram_oe_n,
|
||||
output base_ram_we_n,
|
||||
|
||||
//ExtRAM信号
|
||||
inout [31:0] ext_ram_data, //ExtRAM数据
|
||||
output [19:0] ext_ram_addr, //ExtRAM地址
|
||||
output [ 3:0] ext_ram_be_n, //ExtRAM字节使能，低有效。如果不使用字节使能，请保持为0
|
||||
output ext_ram_ce_n, //ExtRAM片选，低有效
|
||||
output ext_ram_oe_n, //ExtRAM读使能，低有效
|
||||
output ext_ram_we_n //ExtRAM写使能，低有效
|
||||
// ExtRAM
|
||||
inout [31:0] ext_ram_data,
|
||||
output [19:0] ext_ram_addr,
|
||||
output [ 3:0] ext_ram_be_n,
|
||||
output ext_ram_ce_n,
|
||||
output ext_ram_oe_n,
|
||||
output ext_ram_we_n
|
||||
);
|
||||
|
||||
|
||||
@@ -139,6 +139,7 @@ wire ram_bready ;
|
||||
wire [31:0] soc_sram_addr;
|
||||
wire soc_sram_cs;
|
||||
wire soc_sram_we;
|
||||
wire soc_sram_bank;
|
||||
wire [3:0] soc_sram_be;
|
||||
wire [31:0] soc_sram_wdata;
|
||||
wire [31:0] soc_sram_rdata;
|
||||
@@ -188,7 +189,8 @@ assign ram_bready = axi_bready ;
|
||||
axi2sram_sp_external #(
|
||||
.AXI_ID_WIDTH ( 5 ),
|
||||
.AXI_ADDR_WIDTH ( 32 ),
|
||||
.AXI_DATA_WIDTH ( 32 ))
|
||||
.AXI_DATA_WIDTH ( 32 ),
|
||||
.FAST_READ_BURST( 1 ))
|
||||
u_axi_sram_sp (
|
||||
.clk ( aclk ),
|
||||
.resetn ( aresetn ),
|
||||
@@ -232,12 +234,13 @@ axi2sram_sp_external #(
|
||||
.req_o ( soc_sram_cs ),
|
||||
.we_o ( soc_sram_we ),
|
||||
.addr_o ( soc_sram_addr ),
|
||||
.bank_o ( soc_sram_bank ),
|
||||
.be_o ( soc_sram_be ),
|
||||
.data_o ( soc_sram_wdata ),
|
||||
.data_i ( soc_sram_rdata )
|
||||
);
|
||||
|
||||
wire choose_sram = soc_sram_addr[22];//1:ExtRAM 0:BaseRAM
|
||||
wire choose_sram = soc_sram_bank;//1:ExtRAM 0:BaseRAM
|
||||
wire [3:0] be_out = soc_sram_we ? soc_sram_be : 4'b1111;
|
||||
|
||||
assign base_ram_addr = soc_sram_addr[21:2];
|
||||
|
||||
3423
rtl/soc_top.v
3423
rtl/soc_top.v
File diff suppressed because it is too large
Load Diff
201
sdk/axi_ram.mif
Normal file
201
sdk/axi_ram.mif
Normal file
@@ -0,0 +1,201 @@
|
||||
00000011100000000010000000001100
|
||||
00000011100000000110000000001101
|
||||
00000100000000000000000110101100
|
||||
00000100000001100000000000100000
|
||||
00000100000001100000010000100000
|
||||
00000011100000000110010000001100
|
||||
00000100000001100000000000101100
|
||||
00010101010000000000000000001100
|
||||
00000011100000000010010110001100
|
||||
00000100000001100000010000101100
|
||||
00000011100000000100000000001100
|
||||
00000011100000000110000000001101
|
||||
00000100000000000000000110101100
|
||||
00000011100000000001000000001100
|
||||
00000100000000000000000110000000
|
||||
00000100000000000000010000100000
|
||||
00000100000000000001000000100000
|
||||
00010101011111100000000000001100
|
||||
00000011100000000001110000001101
|
||||
00101001000000000000100110001101
|
||||
00000011100000100000000000001101
|
||||
00101001000000000000110110001101
|
||||
00101001000000000000010110000000
|
||||
00010101011111100100000111101110
|
||||
00000011100101000000000111001110
|
||||
00101000100000000000000111001110
|
||||
00000011100000001000000000001101
|
||||
01011000000000000000100000001110
|
||||
00000011100000000000010000001101
|
||||
00101001000000000000000110001101
|
||||
00000011100000000000110000001101
|
||||
00101001000000000000110110001101
|
||||
00101001000000000001000110000000
|
||||
00011100000000000010000000000011
|
||||
00000010101111011111000001100011
|
||||
00000000000101010000000000000100
|
||||
00000000000101010000000000000101
|
||||
01010100000000000000110000000000
|
||||
01010000000000000000000000000000
|
||||
00000000000000000000000000000000
|
||||
00010101011111100000000000001100
|
||||
00000010100000010011010000001111
|
||||
00101001000000000000000110001111
|
||||
00000010100000010000010000010001
|
||||
00101001000000000000000110010001
|
||||
00000010100000010101000000010000
|
||||
00101001000000000000000110010000
|
||||
00101001000000000000000110001111
|
||||
00000010100000010101010000000101
|
||||
00101001000000000000000110000101
|
||||
00000010100000010011000000000100
|
||||
00101001000000000000000110000100
|
||||
00000010100000010111110000010100
|
||||
00101001000000000000000110010100
|
||||
00000010100000010100110000000111
|
||||
00101001000000000000000110000111
|
||||
00101001000000000000000110010000
|
||||
00101001000000000000000110010001
|
||||
00000010100000010100100000010011
|
||||
00101001000000000000000110010011
|
||||
00010101011111101010000000001110
|
||||
00101001000000000000000110010000
|
||||
00000011100000000100000111010010
|
||||
00101001100000000000001001000000
|
||||
00000010100000000101100000000110
|
||||
00000011100000000001000111001101
|
||||
00101001100000000000000110100110
|
||||
00000011100000001000000111001000
|
||||
00010100001110001000000000001001
|
||||
00010100000000000000000000110010
|
||||
00101001100000000000000100001001
|
||||
00000011100000001010000111000111
|
||||
00000011100011100010001001010010
|
||||
00101001100000000000000011110010
|
||||
00000011100000001011000111000110
|
||||
00000010100000100000000000000111
|
||||
00101001100000000000000011000111
|
||||
00000010100001000000000000001001
|
||||
00101001100000000000000111001001
|
||||
00101001000000000000000110001111
|
||||
00101001000000000000000110010001
|
||||
00101001000000000000000110010000
|
||||
00101001000000000000000110001111
|
||||
00101001000000000000000110000101
|
||||
00101001000000000000000110000100
|
||||
00101001000000000000000110010100
|
||||
00000010100000010000110000010010
|
||||
00101001000000000000000110010010
|
||||
00101001000000000000000110010011
|
||||
00101001000000000000000110010010
|
||||
00000010100000001100110000001000
|
||||
00101001000000000000000110001000
|
||||
00000010100000001100100000000111
|
||||
00000010100000001111010000000110
|
||||
00101001000000000000000110000111
|
||||
00000010101111111100000001100011
|
||||
00101001000000000000000110000110
|
||||
00101000100000000000000110101100
|
||||
00000011010000000100000110001100
|
||||
01011011111111111111100110000000
|
||||
00000010100000000100000000001111
|
||||
00000011100000000100000111001100
|
||||
00101001100000000000000110101111
|
||||
00101000100000000000000110001101
|
||||
00010101011111100000000000001110
|
||||
00000011100000000001010111001110
|
||||
00101010000000000000000111001100
|
||||
00000011010000001000000110001100
|
||||
01011011111111111111100110000000
|
||||
00000000010001001111000110101100
|
||||
00101001100000000011000001101100
|
||||
00101010000000000011000001101111
|
||||
00000010100000000010010000010000
|
||||
00000010100000010101110111101110
|
||||
01101000000000000000101000001100
|
||||
00000010100000001100000111101110
|
||||
00010101011111100000000000010000
|
||||
00000000010001001110000110101100
|
||||
00000011010000000011110110001100
|
||||
00101001000000000000001000001110
|
||||
00000010100000000010010000001111
|
||||
00000010100000010101110110001110
|
||||
01101000000000000000100111101100
|
||||
00000010100000001100000110001110
|
||||
00010101011111100000000000010000
|
||||
00000000010001001101000110101100
|
||||
00000011010000000011110110001100
|
||||
00101001000000000000001000001110
|
||||
00000010100000000010010000001111
|
||||
00000010100000010101110110001110
|
||||
01101000000000000000100111101100
|
||||
00000010100000001100000110001110
|
||||
00010101011111100000000000010000
|
||||
00000000010001001100000110101100
|
||||
00000011010000000011110110001100
|
||||
00101001000000000000001000001110
|
||||
00000010100000000010010000001111
|
||||
00000010100000010101110110001110
|
||||
01101000000000000000100111101100
|
||||
00000010100000001100000110001110
|
||||
00010101011111100000000000010000
|
||||
00000000010001001011000110101100
|
||||
00000011010000000011110110001100
|
||||
00101001000000000000001000001110
|
||||
00000010100000000010010000001111
|
||||
00000010100000010101110110001110
|
||||
01101000000000000000100111101100
|
||||
00000010100000001100000110001110
|
||||
00010101011111100000000000010000
|
||||
00000000010001001010000110101100
|
||||
00000011010000000011110110001100
|
||||
00101001000000000000001000001110
|
||||
00000010100000000010010000001111
|
||||
00000010100000010101110110001110
|
||||
01101000000000000000100111101100
|
||||
00000010100000001100000110001110
|
||||
00010101011111100000000000010000
|
||||
00000000010001001001000110101100
|
||||
00000011010000000011110110001100
|
||||
00101001000000000000001000001110
|
||||
00000010100000000010010000001111
|
||||
00000010100000010101110110001110
|
||||
01101000000000000000100111101100
|
||||
00000010100000001100000110001110
|
||||
00010101011111100000000000001111
|
||||
00000011010000000011110110101101
|
||||
00101001000000000000000111101110
|
||||
00000010100000000010010000001100
|
||||
00000010100000010101110110101110
|
||||
01101000000000000000100110001101
|
||||
00000010100000001100000110101110
|
||||
00010101011111100000000000001100
|
||||
00101001000000000000000110001110
|
||||
00000010100000010011010000001101
|
||||
00101001000000000000000110001101
|
||||
00000010100000010000010000000100
|
||||
00101001000000000000000110000100
|
||||
00000010100000010101000000000101
|
||||
00101001000000000000000110000101
|
||||
00101001000000000000000110001101
|
||||
00000010100000010101010000010100
|
||||
00101001000000000000000110010100
|
||||
00000010100000010011000000010011
|
||||
00101001000000000000000110010011
|
||||
00000010100000010111110000010010
|
||||
00101001000000000000000110010010
|
||||
00000010100000010001000000010001
|
||||
00101001000000000000000110010001
|
||||
00000010100000010011110000010000
|
||||
00101001000000000000000110010000
|
||||
00000010100000010011100000001111
|
||||
00101001000000000000000110001111
|
||||
00000010100000010001010000001110
|
||||
00101001000000000000000110001110
|
||||
00000000000101010000000000000100
|
||||
00000010100000000100000001100011
|
||||
01001100000000000000000000100000
|
||||
00000011010000000000000000000000
|
||||
00000011010000000000000000000000
|
||||
00000011010000000000000000000000
|
||||
00000011010000000000000000000000
|
||||
BIN
sdk/fft.bin
Executable file
BIN
sdk/fft.bin
Executable file
Binary file not shown.
BIN
sdk/fft_dma.bin
Executable file
BIN
sdk/fft_dma.bin
Executable file
Binary file not shown.
BIN
sdk/hello_world.bin
Executable file
BIN
sdk/hello_world.bin
Executable file
Binary file not shown.
BIN
sdk/mlkem_test.bin
Executable file
BIN
sdk/mlkem_test.bin
Executable file
Binary file not shown.
@@ -1,6 +1,6 @@
|
||||
#include "dma.h"
|
||||
|
||||
void dma_start_transfer(int ch_id, u32 src, u32 dst, u32 bytes, u32 tag) {
|
||||
void dma_start_transfer(int ch_id, uint32_t src, uint32_t dst, uint32_t bytes, uint32_t tag) {
|
||||
volatile dma_ch_regs_t* ch = DMA_CH(ch_id);
|
||||
|
||||
// 检查通道是否空闲 防止覆盖正在运行的任务
|
||||
@@ -14,12 +14,11 @@ void dma_start_transfer(int ch_id, u32 src, u32 dst, u32 bytes, u32 tag) {
|
||||
ch->DST_ADDR = dst;
|
||||
ch->LENGTH = bytes;
|
||||
ch->TAG = tag; // 可选，填入任务ID
|
||||
ch->MODE = DMA_MODE_MEM2MEM;
|
||||
|
||||
// 置 Burst 属性并触发传输
|
||||
// AXI SIZE: 2 (代表 2^2 = 4 Bytes，与 32-bit 数据线匹配)
|
||||
// AXI LEN: 15 (代表 16 beats 突发传输，最高效)
|
||||
u32 ctrl_val = CTRL_BURST_SIZE(2) | CTRL_BURST_LEN(63);
|
||||
uint32_t ctrl_val = CTRL_BURST_SIZE(2) | CTRL_BURST_LEN(15);
|
||||
|
||||
// 写入 CTRL 并拉高 Bit 0 (Start)
|
||||
ch->CTRL = ctrl_val | CTRL_START_BIT;
|
||||
@@ -35,4 +34,4 @@ void dma_wait_polling(int ch_id) {
|
||||
// 清除 Done 标志位 (Write 1 to Clear Bit 1)
|
||||
// 注意：写 1 清 0 的设计，所以我们对 bit 1 写入 1
|
||||
ch->STATUS = STATUS_DONE_BIT;
|
||||
}
|
||||
}
|
||||
14
sdk/software/bsp/drivers/fft.c
Normal file
14
sdk/software/bsp/drivers/fft.c
Normal file
@@ -0,0 +1,14 @@
|
||||
#include "fft.h"
|
||||
#include "common_func.h"
|
||||
|
||||
void fft_start() {
|
||||
RegWrite(FFT_CSR_REG, FFT_CTRL_START);
|
||||
}
|
||||
|
||||
void fft_wait() {
|
||||
while ((RegRead(FFT_CSR_REG) & FFT_STAT_DONE) == 0) {}
|
||||
}
|
||||
|
||||
unsigned int fft_get_csr() {
|
||||
return RegRead(FFT_CSR_REG);
|
||||
}
|
||||
2
sdk/software/bsp/env/start.S
vendored
2
sdk/software/bsp/env/start.S
vendored
@@ -118,7 +118,7 @@ _start:
|
||||
#WRITE(li.wne,OFS_DIVISOR_LSB, divisor & 0xff);
|
||||
li.w t3, 0xbf20f500
|
||||
ld.w t3, t3, 0
|
||||
li.w t2, 0x1b
|
||||
li.w t2, 0x20
|
||||
beq zero, t3, 1f
|
||||
li.w t2, 0x1
|
||||
1:
|
||||
|
||||
30
sdk/software/bsp/include/dma.h
Normal file
30
sdk/software/bsp/include/dma.h
Normal file
@@ -0,0 +1,30 @@
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t SRC_ADDR; // 0x00: 源地址
|
||||
volatile uint32_t DST_ADDR; // 0x04: 目的地址
|
||||
volatile uint32_t LENGTH; // 0x08: 传输总字节数
|
||||
volatile uint32_t TAG; // 0x0C: 软件 Tag (硬件不处理，留给软件标记任务用)
|
||||
volatile uint32_t CTRL; // 0x10: 控制寄存器 (配置 Burst 属性 + 启动)
|
||||
volatile uint32_t STATUS; // 0x14: 状态寄存器 (Busy, Done)
|
||||
volatile uint32_t RESV[10]; // 0x18 ~ 0x3C: 保留空间，凑齐 0x40 字节
|
||||
} dma_ch_regs_t;
|
||||
|
||||
// DMA 控制器基地址
|
||||
#define CDMA_MUX_BASE 0xbf300000
|
||||
#define DMA_CH(i) ((volatile dma_ch_regs_t*)(CDMA_MUX_BASE + (i) * 0x40))
|
||||
|
||||
// CTRL 寄存器位定义
|
||||
#define CTRL_START_BIT (1 << 0)
|
||||
#define CTRL_BURST_SIZE(x) (((x) & 0x7) << 3) // Bits [5:3]: AXI AxSIZE (0=1B, 1=2B, 2=4B, 3=8B)
|
||||
#define CTRL_BURST_LEN(x) (((x) & 0xFF) << 6) // Bits [13:6]: AXI AxLEN (0=1 beat, 15=16 beats)
|
||||
|
||||
// STATUS 寄存器位定义
|
||||
#define STATUS_BUSY_BIT (1 << 0)
|
||||
#define STATUS_DONE_BIT (1 << 1)
|
||||
|
||||
void dma_start_transfer(int ch_id, uint32_t src, uint32_t dst, uint32_t bytes, uint32_t tag);
|
||||
void dma_wait_polling(int ch_id);
|
||||
16
sdk/software/bsp/include/fft.h
Normal file
16
sdk/software/bsp/include/fft.h
Normal file
@@ -0,0 +1,16 @@
|
||||
#pragma once
|
||||
|
||||
#define FFT_BASE 0xbf400000
|
||||
#define FFT_IN_RE_BASE (FFT_BASE + 0x1000)
|
||||
#define FFT_IN_IM_BASE (FFT_BASE + 0x2000)
|
||||
#define FFT_OUT_RE_BASE (FFT_BASE + 0x3000)
|
||||
#define FFT_OUT_IM_BASE (FFT_BASE + 0x4000)
|
||||
#define FFT_CSR_REG (FFT_BASE + 0xF000)
|
||||
#define FFT_CTRL_START (1 << 4)
|
||||
#define FFT_STAT_DONE (1 << 1)
|
||||
#define FFT_STAT_BUSY (1 << 0)
|
||||
#define FFT_POINT_NUM 1024
|
||||
|
||||
void fft_start();
|
||||
void fft_wait();
|
||||
unsigned int fft_get_csr();
|
||||
@@ -1,9 +1,8 @@
|
||||
TARGET = user-sample
|
||||
|
||||
MATMUL_GROUP_NUM ?= 5000
|
||||
MATMUL_WRITEBACK_RESULTS ?= 0
|
||||
MATMUL_FAST_START ?= 1
|
||||
CFLAGS += -O3 -g -DMATMUL_GROUP_NUM=$(MATMUL_GROUP_NUM) -DMATMUL_WRITEBACK_RESULTS=$(MATMUL_WRITEBACK_RESULTS) -DMATMUL_FAST_START=$(MATMUL_FAST_START)
|
||||
CFLAGS += -O3 -g -DMATMUL_GROUP_NUM=$(MATMUL_GROUP_NUM) -DMATMUL_FAST_START=$(MATMUL_FAST_START)
|
||||
|
||||
C_SRCS := $(wildcard ./*.c )
|
||||
|
||||
@@ -19,6 +18,7 @@ BSP_USE_TRAP := 0
|
||||
BSP_USE_DRIVERS := 0
|
||||
endif
|
||||
|
||||
LA32RSOC_WINDOWS_HOME?=../../../..
|
||||
include ../../bsp/common.mk
|
||||
|
||||
# Strip picolibc: no -lc -lm -lg -lsemihost, keep -lgcc only
|
||||
|
||||
@@ -24,7 +24,7 @@ typedef struct {
|
||||
volatile u32 SRC_BASE; // 0x208
|
||||
volatile u32 DST_BASE; // 0x20C
|
||||
volatile u32 GROUPS; // 0x210
|
||||
volatile u32 MAT_BASE; // 0x214: reserved for compatibility
|
||||
volatile u32 MAT_BASE; // 0x214
|
||||
volatile u32 SRC_STRIDE; // 0x218
|
||||
volatile u32 DST_STRIDE; // 0x21C
|
||||
} dma_seq_regs_t;
|
||||
@@ -47,7 +47,6 @@ typedef struct {
|
||||
#define STATUS_DONE_BIT (1 << 1)
|
||||
|
||||
#define SEQ_START_BIT (1 << 0)
|
||||
#define SEQ_SKIP_STORE_BIT (1 << 1)
|
||||
#define SEQ_BUSY_BIT (1 << 0)
|
||||
#define SEQ_DONE_BIT (1 << 1)
|
||||
|
||||
|
||||
@@ -70,7 +70,6 @@ SECTIONS
|
||||
*(.bss.*)
|
||||
*(.dynbss)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(16);
|
||||
PROVIDE(_end = .);
|
||||
|
||||
@@ -36,7 +36,7 @@ _start:
|
||||
st.b zero, t0, 1
|
||||
li.w t2, 0xbf20f500
|
||||
ld.w t2, t2, 0
|
||||
li.w t1, 0x1b
|
||||
li.w t1, 0x20
|
||||
beq zero, t2, 1f
|
||||
li.w t1, 0x1
|
||||
1:
|
||||
|
||||
@@ -1,9 +1,7 @@
|
||||
/**
|
||||
* user-sample - CICIEC 2026 Stage 3 evaluation program
|
||||
* user-sample - CIC-IEC 2026 Stage 3 Evaluation Program
|
||||
*
|
||||
* The CDMA/matmul direct sequencer reads 5000 A/B groups from ExtRAM, writes
|
||||
* the complete C result region, and accumulates the required IEEE CRC32 in
|
||||
* hardware while the C words are streamed out of matmul.
|
||||
* Matmul AXI-master CRC-only path with fast startup and low-overhead UART output.
|
||||
*/
|
||||
|
||||
#include <dma.h>
|
||||
@@ -19,13 +17,6 @@ static inline void uart_tx(unsigned char c)
|
||||
UART_THR = c;
|
||||
}
|
||||
|
||||
static void uart_puts(const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
uart_tx((unsigned char)*s++);
|
||||
}
|
||||
}
|
||||
|
||||
static void uart_put_matmul_start_fifo(void)
|
||||
{
|
||||
UART_THR = 'M';
|
||||
@@ -42,6 +33,23 @@ static void uart_put_matmul_start_fifo(void)
|
||||
UART_THR = 'T';
|
||||
}
|
||||
|
||||
static void uart_put_crc_prefix_fifo(void)
|
||||
{
|
||||
UART_THR = 'M';
|
||||
UART_THR = 'A';
|
||||
UART_THR = 'T';
|
||||
UART_THR = 'M';
|
||||
UART_THR = 'U';
|
||||
UART_THR = 'L';
|
||||
UART_THR = '_';
|
||||
UART_THR = 'C';
|
||||
UART_THR = 'R';
|
||||
UART_THR = 'C';
|
||||
UART_THR = '3';
|
||||
UART_THR = '2';
|
||||
UART_THR = '=';
|
||||
}
|
||||
|
||||
static inline void uart_wait_tx_empty(void)
|
||||
{
|
||||
while ((UART_LSR & LSR_THRE) == 0) {
|
||||
@@ -58,24 +66,9 @@ static inline unsigned char hex_digit(unsigned int val, int shift)
|
||||
static void uart_put_result_fifo(unsigned int crc)
|
||||
{
|
||||
uart_wait_tx_empty();
|
||||
UART_THR = 'M';
|
||||
UART_THR = 'A';
|
||||
UART_THR = 'T';
|
||||
UART_THR = 'M';
|
||||
UART_THR = 'U';
|
||||
UART_THR = 'L';
|
||||
UART_THR = '_';
|
||||
UART_THR = 'C';
|
||||
UART_THR = 'R';
|
||||
UART_THR = 'C';
|
||||
UART_THR = '3';
|
||||
UART_THR = '2';
|
||||
UART_THR = '=';
|
||||
UART_THR = hex_digit(crc, 28);
|
||||
UART_THR = hex_digit(crc, 24);
|
||||
UART_THR = hex_digit(crc, 20);
|
||||
|
||||
uart_wait_tx_empty();
|
||||
UART_THR = hex_digit(crc, 16);
|
||||
UART_THR = hex_digit(crc, 12);
|
||||
UART_THR = hex_digit(crc, 8);
|
||||
@@ -98,53 +91,63 @@ static void uart_put_result_fifo(unsigned int crc)
|
||||
#define MATMUL_GROUP_NUM 5000
|
||||
#endif
|
||||
|
||||
#ifndef MATMUL_WRITEBACK_RESULTS
|
||||
#define MATMUL_WRITEBACK_RESULTS 1
|
||||
#endif
|
||||
|
||||
#if MATMUL_FAST_START == 0
|
||||
unsigned long UART_BASE = 0xbf000000;
|
||||
unsigned long UART_BASE = 0xbf000000;
|
||||
#endif
|
||||
|
||||
#define EXTRAM_BASE_PHYS 0x1c400000u
|
||||
#define SRC_BASE_WORDS 0u
|
||||
#define DST_BASE_WORDS (SRC_BASE_WORDS + MATMUL_GROUP_NUM * 32u)
|
||||
#define EXTRAM_BASE_PHYS 0x1c400000
|
||||
#define EXTRAM_BASE_UNCACHED (0xA0000000 | (EXTRAM_BASE_PHYS & 0x1FFFFFFF))
|
||||
|
||||
#define EXTRAM_PHYS_AB(g) (EXTRAM_BASE_PHYS + (SRC_BASE_WORDS * 4u) + (unsigned int)(g) * 128u)
|
||||
#define EXTRAM_PHYS_C(g) (EXTRAM_BASE_PHYS + (DST_BASE_WORDS * 4u) + (unsigned int)(g) * 192u)
|
||||
#define SRC_BASE_WORDS 0
|
||||
#define EXTRAM_PHYS_AB(g) (EXTRAM_BASE_PHYS + (SRC_BASE_WORDS * 4) + (g) * 128)
|
||||
|
||||
#define MATMUL_BASE_UNCACHED 0xbf500000u
|
||||
#define MATMUL_CRC (*(volatile unsigned int *)(MATMUL_BASE_UNCACHED + 0x010u))
|
||||
#define MATMUL_BASE_PHYS 0x1f500000
|
||||
#define MATMUL_BASE_UNCACHED 0xbf500000
|
||||
|
||||
#define MATMUL_CTRL (MATMUL_BASE_UNCACHED + 0x000)
|
||||
#define MATMUL_STATUS (MATMUL_BASE_UNCACHED + 0x004)
|
||||
#define MATMUL_DMA_SRC_BASE (MATMUL_BASE_UNCACHED + 0x020)
|
||||
#define MATMUL_DMA_GROUPS (MATMUL_BASE_UNCACHED + 0x028)
|
||||
#define MATMUL_DMA_SRC_STRIDE (MATMUL_BASE_UNCACHED + 0x02C)
|
||||
|
||||
#define CTRL_START_B0 0x1
|
||||
#define CTRL_START_B1 0x2
|
||||
#define CTRL_DMA_START (1 << 8)
|
||||
#define STATUS_DONE 0x2
|
||||
#define STATUS_ERROR 0x4
|
||||
#define STATUS_DMA_BUSY (1 << 3)
|
||||
#define STATUS_DMA_DONE (1 << 4)
|
||||
|
||||
#define MATMUL_CRC (MATMUL_BASE_UNCACHED + 0x010)
|
||||
|
||||
#define DMA_CTRL_VAL (CTRL_BURST_SIZE(2) | CTRL_BURST_LEN(63) | CTRL_START_BIT)
|
||||
#define MATMUL_EP_ID 0
|
||||
|
||||
int main(void)
|
||||
{
|
||||
unsigned int crc;
|
||||
unsigned int seq_ctrl;
|
||||
|
||||
if (MATMUL_GROUP_NUM <= 0) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
DMA_SEQ->STATUS = SEQ_DONE_BIT;
|
||||
DMA_SEQ->SRC_BASE = EXTRAM_PHYS_AB(0);
|
||||
DMA_SEQ->DST_BASE = EXTRAM_PHYS_C(0);
|
||||
DMA_SEQ->GROUPS = MATMUL_GROUP_NUM;
|
||||
DMA_SEQ->MAT_BASE = 0x1f500000u;
|
||||
DMA_SEQ->SRC_STRIDE = 128u;
|
||||
DMA_SEQ->DST_STRIDE = 192u;
|
||||
seq_ctrl = SEQ_START_BIT;
|
||||
#if MATMUL_WRITEBACK_RESULTS == 0
|
||||
seq_ctrl |= SEQ_SKIP_STORE_BIT;
|
||||
#endif
|
||||
volatile unsigned int *mat_ctrl = (volatile unsigned int *)MATMUL_CTRL;
|
||||
volatile unsigned int *mat_status = (volatile unsigned int *)MATMUL_STATUS;
|
||||
volatile unsigned int *mat_crc = (volatile unsigned int *)MATMUL_CRC;
|
||||
|
||||
unsigned int crc;
|
||||
|
||||
uart_put_matmul_start_fifo();
|
||||
DMA_SEQ->CTRL = seq_ctrl;
|
||||
|
||||
while ((DMA_SEQ->STATUS & SEQ_DONE_BIT) == 0u) {
|
||||
}
|
||||
DMA_SEQ->STATUS = SEQ_DONE_BIT;
|
||||
*(volatile unsigned int *)MATMUL_CRC = 0;
|
||||
*mat_status = STATUS_DMA_DONE | STATUS_DONE | STATUS_ERROR;
|
||||
*(volatile unsigned int *)MATMUL_DMA_SRC_BASE = EXTRAM_PHYS_AB(0);
|
||||
*(volatile unsigned int *)MATMUL_DMA_GROUPS = MATMUL_GROUP_NUM;
|
||||
*(volatile unsigned int *)MATMUL_DMA_SRC_STRIDE = 128;
|
||||
*mat_ctrl = CTRL_DMA_START;
|
||||
uart_put_crc_prefix_fifo();
|
||||
while (!(*mat_status & STATUS_DMA_DONE)) {}
|
||||
*mat_status = STATUS_DMA_DONE;
|
||||
|
||||
crc = MATMUL_CRC;
|
||||
crc = *mat_crc;
|
||||
|
||||
uart_put_result_fifo(crc);
|
||||
|
||||
|
||||
@@ -1,11 +1,11 @@
|
||||
#pragma once
|
||||
|
||||
#define FFT_BASE 0xbf400000
|
||||
#define FFT_IN_RE_BASE (FFT_BASE + 0x8000)
|
||||
#define FFT_IN_IM_BASE (FFT_BASE + 0x9000)
|
||||
#define FFT_OUT_RE_BASE (FFT_BASE + 0xA000)
|
||||
#define FFT_OUT_IM_BASE (FFT_BASE + 0xB000)
|
||||
#define FFT_CSR_REG (FFT_BASE + 0xC000)
|
||||
#define FFT_IN_RE_BASE (FFT_BASE + 0x1000)
|
||||
#define FFT_IN_IM_BASE (FFT_BASE + 0x2000)
|
||||
#define FFT_OUT_RE_BASE (FFT_BASE + 0x3000)
|
||||
#define FFT_OUT_IM_BASE (FFT_BASE + 0x4000)
|
||||
#define FFT_CSR_REG (FFT_BASE + 0xF000)
|
||||
#define FFT_CTRL_START (1 << 4)
|
||||
#define FFT_STAT_DONE (1 << 1)
|
||||
#define FFT_STAT_BUSY (1 << 0)
|
||||
@@ -13,4 +13,4 @@
|
||||
|
||||
void fft_start();
|
||||
void fft_wait();
|
||||
unsigned int fft_get_csr();
|
||||
unsigned int fft_get_csr();
|
||||
@@ -5,7 +5,6 @@
|
||||
#include <common_func.h>
|
||||
#include <confreg_time.h>
|
||||
#include <fft.h>
|
||||
#include "../fft_test_data.h"
|
||||
|
||||
// BSP板级支持包所需全局变量
|
||||
unsigned long UART_BASE = 0xbf000000;
|
||||
@@ -81,7 +80,12 @@ int main(int argc, char** argv)
|
||||
float sw_in_im[FFT_POINT_NUM];
|
||||
|
||||
for (int i = 0; i < FFT_POINT_NUM; i++) {
|
||||
sw_in_re[i] = (float)fft_test_sample((unsigned int)i);
|
||||
float dc_part = 4000.0f;
|
||||
float f10_part = 8000.0f * cos(2 * PI * 10.0 * i / FFT_POINT_NUM);
|
||||
float f200_part = 6000.0f * sin(2 * PI * 200.0 * i / FFT_POINT_NUM);
|
||||
float f400_part = 3000.0f * sin(2 * PI * 400.0 * i / FFT_POINT_NUM);
|
||||
|
||||
sw_in_re[i] = dc_part + f10_part + f200_part + f400_part;
|
||||
sw_in_im[i] = 0.0f;
|
||||
}
|
||||
|
||||
@@ -149,4 +153,4 @@ int main(int argc, char** argv)
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
@@ -1,17 +1,16 @@
|
||||
#pragma once
|
||||
|
||||
#define FFT_BASE 0xbf400000
|
||||
#define FFT_IN_RE_BASE (FFT_BASE + 0x8000)
|
||||
#define FFT_IN_IM_BASE (FFT_BASE + 0x9000)
|
||||
#define FFT_OUT_RE_BASE (FFT_BASE + 0xA000)
|
||||
#define FFT_OUT_IM_BASE (FFT_BASE + 0xB000)
|
||||
#define FFT_CSR_REG (FFT_BASE + 0xC000)
|
||||
#define FFT_IN_RE_BASE (FFT_BASE + 0x1000)
|
||||
#define FFT_IN_IM_BASE (FFT_BASE + 0x2000)
|
||||
#define FFT_OUT_RE_BASE (FFT_BASE + 0x3000)
|
||||
#define FFT_OUT_IM_BASE (FFT_BASE + 0x4000)
|
||||
#define FFT_CSR_REG (FFT_BASE + 0xF000)
|
||||
#define FFT_CTRL_START (1 << 4)
|
||||
#define FFT_STAT_DONE (1 << 1)
|
||||
#define FFT_STAT_BUSY (1 << 0)
|
||||
#define FFT_POINT_NUM 1024
|
||||
#define FFT_SAMPLE_BITS 16
|
||||
|
||||
void fft_start();
|
||||
void fft_wait();
|
||||
unsigned int fft_get_csr();
|
||||
unsigned int fft_get_csr();
|
||||
@@ -8,7 +8,6 @@
|
||||
#include <confreg_time.h>
|
||||
#include <dma.h>
|
||||
#include <fft.h>
|
||||
#include "../fft_test_data.h"
|
||||
|
||||
// BSP板级支持包所需全局变量
|
||||
unsigned long UART_BASE = 0xbf000000;
|
||||
@@ -67,8 +66,7 @@ void sw_fft(float re[], float im[], int n) {
|
||||
}
|
||||
}
|
||||
|
||||
// 全局对齐数组：作为 DMA 的源和目的内存。
|
||||
// FFT 外设仍按 32-bit AXI word 编址，每个 word 的低 16 bit 作为一个 signed 样本。
|
||||
// 全局对齐数组：作为 DMA 的源和目的内存
|
||||
int32_t hw_in_re_arr[FFT_POINT_NUM] __attribute__((aligned(64)));
|
||||
int32_t hw_in_im_arr[FFT_POINT_NUM] __attribute__((aligned(64)));
|
||||
int32_t hw_out_re_arr[FFT_POINT_NUM] __attribute__((aligned(64)));
|
||||
@@ -95,14 +93,18 @@ int main(int argc, char** argv)
|
||||
float sw_in_re[FFT_POINT_NUM];
|
||||
float sw_in_im[FFT_POINT_NUM];
|
||||
|
||||
// 初始化测试波形
|
||||
for (int i = 0; i < FFT_POINT_NUM; i++) {
|
||||
int16_t sample = (int16_t)fft_test_sample((unsigned int)i);
|
||||
|
||||
sw_in_re[i] = (float)sample;
|
||||
float dc_part = 4000.0f;
|
||||
float f10_part = 8000.0f * cos(2 * PI * 10.0 * i / FFT_POINT_NUM);
|
||||
float f200_part = 6000.0f * sin(2 * PI * 200.0 * i / FFT_POINT_NUM);
|
||||
float f400_part = 3000.0f * sin(2 * PI * 400.0 * i / FFT_POINT_NUM);
|
||||
|
||||
sw_in_re[i] = dc_part + f10_part + f200_part + f400_part;
|
||||
sw_in_im[i] = 0.0f;
|
||||
|
||||
// 硬件输入为 16-bit signed，写入 32-bit word 的低半字。
|
||||
uncached_in_re[i] = (int32_t)sample;
|
||||
// 硬件输入需要转为整数存入无缓存内存
|
||||
uncached_in_re[i] = (int32_t)sw_in_re[i];
|
||||
uncached_in_im[i] = 0;
|
||||
|
||||
// 清理输出内存以防干扰
|
||||
@@ -117,7 +119,7 @@ int main(int argc, char** argv)
|
||||
printf("\n--- Starting Hardware FFT with DMA ---\n");
|
||||
tick_start = get_ns(); // 开始计时
|
||||
|
||||
uint32_t transfer_bytes = FFT_POINT_NUM * 4; // 1024个点 * 4字节，低16位有效
|
||||
uint32_t transfer_bytes = FFT_POINT_NUM * 4; // 1024个点 * 4字节
|
||||
|
||||
// MA 将数据从内存搬运到 FFT 输入外设
|
||||
dma_start_transfer(0, ((uint32_t)hw_in_re_arr & 0x1FFFFFFF), phys_fft_in_re, transfer_bytes, 100);
|
||||
@@ -159,31 +161,19 @@ int main(int argc, char** argv)
|
||||
printf("Speedup Ratio : %.2fx\n", (float)sw_time / hw_time);
|
||||
}
|
||||
|
||||
printf("\n--- Verification (%d-bit FFT, only showing bins with energy > 10) ---\n", FFT_SAMPLE_BITS);
|
||||
int max_abs_err_re = 0;
|
||||
int max_abs_err_im = 0;
|
||||
printf("\n--- Verification (Only showing Bins with energy > 10) ---\n");
|
||||
for (int i = 0; i < FFT_POINT_NUM; i++) {
|
||||
// CPU 通过无缓存指针读取 DMA 搬运回来的结果
|
||||
int32_t hw_re = uncached_out_re[i];
|
||||
int32_t hw_im = uncached_out_im[i];
|
||||
int32_t sw_re = (int32_t)sw_in_re[i] / FFT_POINT_NUM;
|
||||
int32_t sw_im = (int32_t)sw_in_im[i] / FFT_POINT_NUM;
|
||||
int err_re = (int)(hw_re - sw_re);
|
||||
int err_im = (int)(hw_im - sw_im);
|
||||
|
||||
if (err_re < 0) err_re = -err_re;
|
||||
if (err_im < 0) err_im = -err_im;
|
||||
if (err_re > max_abs_err_re) max_abs_err_re = err_re;
|
||||
if (err_im > max_abs_err_im) max_abs_err_im = err_im;
|
||||
|
||||
if (fabs((float)hw_re) > 10 || fabs((float)hw_im) > 10) {
|
||||
printf("Bin [%4d] Hz: HW(Re:%6d, Im:%6d) | SW(Re:%6d, Im:%6d)\n",
|
||||
i,
|
||||
hw_re, hw_im,
|
||||
sw_re, sw_im);
|
||||
(int)sw_in_re[i] / FFT_POINT_NUM, (int)sw_in_im[i] / FFT_POINT_NUM);
|
||||
}
|
||||
}
|
||||
printf("Max Abs Error : Re=%d, Im=%d\n", max_abs_err_re, max_abs_err_im);
|
||||
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
@@ -1,80 +0,0 @@
|
||||
#ifndef FFT_TEST_DATA_H
|
||||
#define FFT_TEST_DATA_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define FFT_TEST_INPUT_PERIOD 512u
|
||||
|
||||
static const int16_t fft_test_input[FFT_TEST_INPUT_PERIOD] = {
|
||||
12000, 19537, 12803, 11425, 4727, 9875, 19249, 12733,
|
||||
10880, 4524, 7132, 17935, 12144, 9543, 3839, 3959,
|
||||
15687, 11133, 7594, 2745, 590, 12673, 9827, 5271,
|
||||
1362, -2720, 9126, 8377, 2848, -157, -5714, 5322,
|
||||
6938, 609, -1638, -8154, 1552, 5655, -1182, -2905,
|
||||
-9848, -1895, 4649, -2305, -3793, -10662, -4769, 4007,
|
||||
-2603, -4173, -10534, -6871, 3770, -2002, -3957, -9482,
|
||||
-8072, 3932, -516, -3110, -7598, -8327, 4441, 1752,
|
||||
-1656, -5045, -7670, 5204, 4623, 325, -2039, -6218,
|
||||
6095, 7850, 2707, 1169, -4152, 6970, 11144, 5322,
|
||||
4318, -1704, 7682, 14204, 7982, 7154, 871, 8097,
|
||||
16739, 10488, 9460, 3315, 8107, 18497, 12656, 11071,
|
||||
5391, 7640, 19290, 14327, 11890, 6906, 6674, 19009,
|
||||
15383, 11898, 7730, 5238, 17637, 15758, 11148, 7806,
|
||||
3409, 15251, 15443, 9769, 7155, 1308, 12014, 14483,
|
||||
7945, 5871, -906, 8167, 12976, 5903, 4115, -3061,
|
||||
4000, 11061, 3884, 2096, -4976, -167, 8906, 2128,
|
||||
54, -6483, -4014, 6691, 844, -1769, -7443, -7251,
|
||||
4590, 193, -3148, -7758, -9637, 2761, 269, -3898,
|
||||
-7383, -11009, 1325, 1093, -3890, -6327, -11290, 359,
|
||||
2608, -3071, -4656, -10497, -107, 4684, -1460, -2488,
|
||||
-8739, -97, 7128, 845, 17, -6204, 317, 9704,
|
||||
3681, 2677, -3144, 1029, 12152, 6830, 5292, 149,
|
||||
1904, 14218, 10039, 7674, 3376, 2795, 15670, 13045,
|
||||
9656, 6247, 3558, 16327, 15598, 11110, 8516, 4067,
|
||||
16072, 17482, 11957, 10002, 4229, 14871, 18534, 12173,
|
||||
10603, 3992, 12769, 18662, 11793, 10305, 3350, 9895,
|
||||
17848, 10905, 9182, 2344, 6447, 16154, 9638, 7390,
|
||||
1061, 2677, 13714, 8157, 5151, -377, -1126, 10720,
|
||||
6637, 2728, -1827, -4673, 7409, 5254, 405, -3133,
|
||||
-7687, 4040, 4160, -1543, -4144, -9935, 867, 3475,
|
||||
-2880, -4733, -11249, -1875, 3272, -3425, -4803, -11537,
|
||||
-3999, 3567, -3075, -4303, -10793, -5377, 4321, -1813,
|
||||
-3230, -9097, -5949, 5444, 289, -1630, -6611, -5728,
|
||||
6798, 3076, 400, -3557, -4800, 8216, 6322, 2729,
|
||||
-206, -3309, 9519, 9750, 5196, 3156, -1446, 10527,
|
||||
13061, 7627, 6247, 570, 11084, 15956, 9850, 8817,
|
||||
2519, 11072, 18167, 11711, 10670, 4193, 10422, 19478,
|
||||
13088, 11680, 5421, 9127, 19750, 13899, 11807, 6084,
|
||||
7238, 18929, 14110, 11091, 6125, 4866, 17055, 13739,
|
||||
9656, 5553, 2173, 14256, 12849, 7693, 4444, -643,
|
||||
10739, 11547, 5442, 2933, -3367, 6773, 9967, 3169,
|
||||
1196, -5781, 2663, 8263, 1141, -560, -7688, -1274,
|
||||
6589, -401, -2127, -8927, -4744, 5086, -1264, -3307,
|
||||
-9391, -7489, 3870, -1325, -3935, -9034, -9320, 3020,
|
||||
-539, -3898, -7880, -10128, 2572, 1053, -3142, -6016,
|
||||
-9894, 2517, 3328, -1682, -3589, -8688, 2801, 6090,
|
||||
403, -791, -6665, 3335, 9088, 2974, 2156, -4043,
|
||||
3999, 12043, 5843, 5025, -1088, 4664, 14665, 8791,
|
||||
7596, 1909, 5198, 16688, 11589, 9682, 4671, 5482,
|
||||
17894, 14016, 11142, 6946, 5427, 18128, 15880, 11898,
|
||||
8539, 4979, 17320, 17034, 11935, 9325, 4129, 15489,
|
||||
17391, 11307, 9264, 2913, 12744, 16927, 10127, 8401,
|
||||
1410, 9274, 15688, 8560, 6858, -263, 5336, 13781,
|
||||
6803, 4830, -1967, 1226, 11367, 5066, 2557, -3547,
|
||||
-2739, 8643, 3555, 306, -4849, -6256, 5826, 2446,
|
||||
-1656, -5739, -9055, 3133, 1874, -3091, -6110, -10929,
|
||||
761, 1915, -3807, -5899, -11750, -1127, 2578, -3680,
|
||||
-5088, -11478, -2422, 3806, -2670, -3711, -10167, -3072,
|
||||
5480, -817, -1850, -7956, -3084, 7429, 1752, 372,
|
||||
-5061, -2527, 9446, 4843, 2803, -1750, -1519, 11309,
|
||||
8206, 5270, 1677, -216, 12800, 11557, 7599, 4923,
|
||||
1201, 13728, 14611, 9630, 7710, 2555, 13949, 17097,
|
||||
11230, 9813, 3678, 13377, 18793, 12303, 11075, 4432,
|
||||
};
|
||||
|
||||
static inline int32_t fft_test_sample(unsigned int index)
|
||||
{
|
||||
return (int32_t)fft_test_input[index & (FFT_TEST_INPUT_PERIOD - 1u)];
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,88 +1,197 @@
|
||||
/**
|
||||
* matmul_test - CIC-IEC 2026 Stage 3 Evaluation Program
|
||||
*
|
||||
* Uses the CDMA-to-matmul direct endpoint sequencer. The CDMA still owns the
|
||||
* external-memory traffic, while matmul A/B/C transfers use local wires instead
|
||||
* of the AXI crossbar.
|
||||
* Reads 5000 groups of 4x4 unsigned matrix multiplications from ExtRAM,
|
||||
* computes C = A x B via the hardware matmul IP, writes results back,
|
||||
* computes CRC32 over the result region, and outputs the required identifiers.
|
||||
*
|
||||
* Data layout:
|
||||
* Input: ExtRAM word offset 0x00000000, 5000 * 32 = 160000 words
|
||||
* Result: ExtRAM word offset 0x0009C400, 5000 * 48 = 240000 words
|
||||
* CRC32 over result region byte stream (960000 bytes, little-endian)
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <dma.h>
|
||||
|
||||
/* UART 16550 direct access avoids the printf/newlib overhead on the hot path. */
|
||||
#define UART_THR (*(volatile unsigned char *)0xbf000000)
|
||||
#define UART_LSR (*(volatile unsigned char *)0xbf000005)
|
||||
#define LSR_THRE 0x20
|
||||
/* ─── BSP globals ─────────────────────────────────────────────────── */
|
||||
unsigned long UART_BASE = 0xbf000000;
|
||||
unsigned long CONFREG_TIMER_BASE = 0xbf20f100;
|
||||
unsigned long CONFREG_CLOCKS_PER_SEC = 50000000L;
|
||||
unsigned long CORE_CLOCKS_PER_SEC = 33000000L;
|
||||
|
||||
static inline void uart_tx(unsigned char c)
|
||||
/* ─── Memory layout ────────────────────────────────────────────────── */
|
||||
#define EXTRAM_BASE_PHYS 0x1c400000
|
||||
#define EXTRAM_BASE (0xA0000000 | (EXTRAM_BASE_PHYS & 0x1FFFFFFF))
|
||||
|
||||
#define SRC_BASE 0
|
||||
#define N_GROUPS 5000
|
||||
#define DST_BASE (SRC_BASE + N_GROUPS * 32) /* word offset 160000 */
|
||||
#define RESULT_WORDS (N_GROUPS * 48) /* 240000 words */
|
||||
#define RESULT_BYTES (RESULT_WORDS * 4) /* 960000 bytes */
|
||||
|
||||
/* ─── MATMUL IP registers ─────────────────────────────────────────── */
|
||||
#define MATMUL_BASE 0xbf500000
|
||||
#define MATMUL_CTRL (MATMUL_BASE + 0x000)
|
||||
#define MATMUL_STATUS (MATMUL_BASE + 0x004)
|
||||
#define MATMUL_A_BASE (MATMUL_BASE + 0x020)
|
||||
#define MATMUL_B_BASE (MATMUL_BASE + 0x060)
|
||||
#define MATMUL_C_BASE (MATMUL_BASE + 0x0a0)
|
||||
|
||||
#define CTRL_START 0x1
|
||||
#define STATUS_BUSY 0x1
|
||||
#define STATUS_DONE 0x2
|
||||
#define STATUS_ERROR 0x4
|
||||
|
||||
/* ─── Convenience macros ──────────────────────────────────────────── */
|
||||
#define REG_WR(addr, val) (*(volatile uint32_t *)(addr) = (uint32_t)(val))
|
||||
#define REG_RD(addr) (*(volatile uint32_t *)(addr))
|
||||
|
||||
/* ─── CRC32 table (IEEE 802.3, polynomial 0xEDB88320) ─────────────── */
|
||||
static const uint32_t crc32_table[256] = {
|
||||
0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
|
||||
0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
|
||||
0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
|
||||
0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
|
||||
0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
|
||||
0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
|
||||
0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
|
||||
0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
|
||||
0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
|
||||
0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
|
||||
0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
|
||||
0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
|
||||
0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
|
||||
0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
|
||||
0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
|
||||
0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
|
||||
0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
|
||||
0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
|
||||
0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
|
||||
0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
|
||||
0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
|
||||
0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
|
||||
0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
|
||||
0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
|
||||
0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
|
||||
0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
|
||||
0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
|
||||
0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
|
||||
0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
|
||||
0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
|
||||
0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
|
||||
0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
|
||||
0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
|
||||
0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
|
||||
0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
|
||||
0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
|
||||
0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
|
||||
0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
|
||||
0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
|
||||
0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
|
||||
0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
|
||||
0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
|
||||
0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
|
||||
0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
|
||||
0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
|
||||
0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
|
||||
0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB30A04,
|
||||
0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
|
||||
0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
|
||||
0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
|
||||
0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
|
||||
0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
|
||||
0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
|
||||
0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
|
||||
0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
|
||||
0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
|
||||
0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
|
||||
0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
|
||||
0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
|
||||
0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
|
||||
0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
|
||||
0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
|
||||
0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
|
||||
0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
|
||||
};
|
||||
|
||||
/* ─── Read N words from IP register space ─────────────────────────── */
|
||||
static void read_ip(uint32_t base, volatile uint32_t *dst, int n)
|
||||
{
|
||||
while (!(UART_LSR & LSR_THRE)) {
|
||||
}
|
||||
UART_THR = c;
|
||||
for (int i = 0; i < n; i++)
|
||||
dst[i] = REG_RD(base + i * 4);
|
||||
}
|
||||
|
||||
static void uart_puts(const char *s)
|
||||
/* ─── Write N words to IP register space ──────────────────────────── */
|
||||
static void write_ip(uint32_t base, const volatile uint32_t *src, int n)
|
||||
{
|
||||
while (*s) {
|
||||
uart_tx((unsigned char)*s++);
|
||||
}
|
||||
for (int i = 0; i < n; i++)
|
||||
REG_WR(base + i * 4, src[i]);
|
||||
}
|
||||
|
||||
static void uart_puthex(uint32_t val)
|
||||
/* ─── Poll IP STATUS until done or error ──────────────────────────── */
|
||||
static void wait_done(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 28; i >= 0; i -= 4) {
|
||||
unsigned char nibble = (unsigned char)((val >> i) & 0xF);
|
||||
uart_tx((unsigned char)(nibble < 10 ? ('0' + nibble) : ('a' + nibble - 10)));
|
||||
}
|
||||
uint32_t status;
|
||||
do {
|
||||
status = REG_RD(MATMUL_STATUS);
|
||||
} while (!(status & (STATUS_DONE | STATUS_ERROR)));
|
||||
}
|
||||
|
||||
#ifndef MATMUL_GROUP_NUM
|
||||
#define MATMUL_GROUP_NUM 5000
|
||||
#endif
|
||||
/* ─── CRC32 over ExtRAM result region (little-endian word → byte stream) ─ */
|
||||
static uint32_t compute_crc32(volatile uint32_t *extram)
|
||||
{
|
||||
uint32_t crc = 0xFFFFFFFF;
|
||||
uint32_t i, w;
|
||||
|
||||
unsigned long UART_BASE = 0xbf000000;
|
||||
|
||||
#define EXTRAM_BASE_PHYS 0x1c400000u
|
||||
|
||||
#define SRC_BASE_WORDS 0u
|
||||
#define DST_BASE_WORDS (SRC_BASE_WORDS + MATMUL_GROUP_NUM * 32u)
|
||||
|
||||
#define EXTRAM_PHYS_AB(g) (EXTRAM_BASE_PHYS + (SRC_BASE_WORDS * 4u) + (uint32_t)(g) * 128u)
|
||||
#define EXTRAM_PHYS_C(g) (EXTRAM_BASE_PHYS + (DST_BASE_WORDS * 4u) + (uint32_t)(g) * 192u)
|
||||
|
||||
#define MATMUL_BASE_UNCACHED 0xbf500000u
|
||||
#define MATMUL_CRC (*(volatile uint32_t *)(MATMUL_BASE_UNCACHED + 0x010u))
|
||||
for (i = 0; i < RESULT_WORDS; i++) {
|
||||
w = extram[DST_BASE + i];
|
||||
crc = crc32_table[(crc ^ (w & 0xFF)) & 0xFF] ^ (crc >> 8);
|
||||
crc = crc32_table[(crc ^ ((w >> 8) & 0xFF)) & 0xFF] ^ (crc >> 8);
|
||||
crc = crc32_table[(crc ^ ((w >> 16) & 0xFF)) & 0xFF] ^ (crc >> 8);
|
||||
crc = crc32_table[(crc ^ (w >> 24) ) & 0xFF] ^ (crc >> 8);
|
||||
}
|
||||
return crc ^ 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
/* ═══════════════════════════════════════════════════════════════════ */
|
||||
int main(void)
|
||||
{
|
||||
volatile uint32_t *extram = (volatile uint32_t *)EXTRAM_BASE;
|
||||
uint32_t a_buf[16], b_buf[16], c_buf[48];
|
||||
uint32_t crc;
|
||||
int g, i;
|
||||
|
||||
if (MATMUL_GROUP_NUM <= 0) {
|
||||
return 0;
|
||||
/* ── Start marker (must be first output) ──────────────────── */
|
||||
printf("MATMUL_START\n");
|
||||
|
||||
/* ── Process all 5000 groups ──────────────────────────────── */
|
||||
for (g = 0; g < N_GROUPS; g++) {
|
||||
/* Read A[16] + B[16] from ExtRAM */
|
||||
for (i = 0; i < 16; i++) {
|
||||
a_buf[i] = extram[SRC_BASE + g * 32 + i];
|
||||
b_buf[i] = extram[SRC_BASE + g * 32 + 16 + i];
|
||||
}
|
||||
/* Load into IP registers */
|
||||
write_ip(MATMUL_A_BASE, a_buf, 16);
|
||||
write_ip(MATMUL_B_BASE, b_buf, 16);
|
||||
/* Clear status flags, start computation */
|
||||
REG_WR(MATMUL_STATUS, STATUS_DONE | STATUS_ERROR);
|
||||
REG_WR(MATMUL_CTRL, CTRL_START);
|
||||
/* Wait for hardware to finish */
|
||||
wait_done();
|
||||
/* Read C[48] from IP, write to ExtRAM result region */
|
||||
read_ip(MATMUL_C_BASE, c_buf, 48);
|
||||
for (i = 0; i < 48; i++)
|
||||
extram[DST_BASE + g * 48 + i] = c_buf[i];
|
||||
}
|
||||
|
||||
uart_puts("MATMUL_START\n");
|
||||
/* ── CRC32 over result region ─────────────────────────────── */
|
||||
crc = compute_crc32(extram);
|
||||
|
||||
DMA_SEQ->STATUS = SEQ_DONE_BIT;
|
||||
DMA_SEQ->SRC_BASE = EXTRAM_PHYS_AB(0);
|
||||
DMA_SEQ->DST_BASE = EXTRAM_PHYS_C(0);
|
||||
DMA_SEQ->GROUPS = MATMUL_GROUP_NUM;
|
||||
DMA_SEQ->MAT_BASE = 0x1f500000u;
|
||||
DMA_SEQ->SRC_STRIDE = 128u;
|
||||
DMA_SEQ->DST_STRIDE = 192u;
|
||||
DMA_SEQ->CTRL = SEQ_START_BIT;
|
||||
|
||||
while ((DMA_SEQ->STATUS & SEQ_DONE_BIT) == 0u) {
|
||||
}
|
||||
DMA_SEQ->STATUS = SEQ_DONE_BIT;
|
||||
|
||||
crc = MATMUL_CRC;
|
||||
|
||||
uart_puts("MATMUL_CRC32=");
|
||||
uart_puthex(crc);
|
||||
uart_puts("\nMATMUL_DONE\n");
|
||||
/* ── Final markers ────────────────────────────────────────── */
|
||||
printf("MATMUL_CRC32=%08lx\n", (unsigned long)crc);
|
||||
printf("MATMUL_DONE\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1,15 +1,8 @@
|
||||
TARGET = mlkem_test
|
||||
|
||||
CFLAGS += -O3 -g
|
||||
CFLAGS += -I./mlkem_native
|
||||
CFLAGS += -DMLK_CONFIG_PARAMETER_SET=512
|
||||
CFLAGS += -DMLK_CONFIG_NAMESPACE_PREFIX=swmlkem
|
||||
CFLAGS += -DMLK_CONFIG_NO_RANDOMIZED_API
|
||||
CFLAGS += -DMLK_CONFIG_NO_ASM
|
||||
CFLAGS += -DMLK_CONFIG_FILE='"sw_mlkem_config.h"'
|
||||
|
||||
C_SRCS := $(wildcard ./*.c )
|
||||
C_SRCS += ./mlkem_native/mlkem_native.c
|
||||
|
||||
OBJDIR = obj
|
||||
COMMON_DIR = ../../bsp
|
||||
|
||||
@@ -1,55 +0,0 @@
|
||||
#pragma once
|
||||
|
||||
typedef unsigned int u32;
|
||||
|
||||
typedef struct {
|
||||
volatile u32 SRC_ADDR; // 0x00: source address
|
||||
volatile u32 DST_ADDR; // 0x04: destination address
|
||||
volatile u32 LENGTH; // 0x08: transfer byte count
|
||||
volatile u32 TAG; // 0x0C: software tag (ignored by HW)
|
||||
volatile u32 CTRL; // 0x10: control (burst config + start)
|
||||
volatile u32 STATUS; // 0x14: status (busy, done)
|
||||
volatile u32 MODE; // 0x18: 0=mem2mem, 1=mem2ep, 2=ep2mem
|
||||
volatile u32 EP_CFG; // 0x1C: [3:0]=bank, [15:8]=word offset, [19:16]=endpoint id
|
||||
volatile u32 RESV[8]; // 0x20 ~ 0x3C: padding to 0x40 bytes
|
||||
} dma_ch_regs_t;
|
||||
|
||||
// DMA 控制器基地址
|
||||
#define CDMA_MUX_BASE 0xbf300000
|
||||
#define DMA_CH(i) ((volatile dma_ch_regs_t*)(CDMA_MUX_BASE + (i) * 0x40))
|
||||
|
||||
typedef struct {
|
||||
volatile u32 CTRL; // 0x200: bit0 start
|
||||
volatile u32 STATUS; // 0x204: bit0 busy, bit1 done (W1C)
|
||||
volatile u32 SRC_BASE; // 0x208
|
||||
volatile u32 DST_BASE; // 0x20C
|
||||
volatile u32 GROUPS; // 0x210
|
||||
volatile u32 MAT_BASE; // 0x214: reserved for compatibility
|
||||
volatile u32 SRC_STRIDE; // 0x218
|
||||
volatile u32 DST_STRIDE; // 0x21C
|
||||
} dma_seq_regs_t;
|
||||
|
||||
#define DMA_SEQ ((volatile dma_seq_regs_t*)(CDMA_MUX_BASE + 0x200))
|
||||
|
||||
// CTRL 寄存器位定义
|
||||
#define CTRL_START_BIT (1 << 0)
|
||||
#define CTRL_BURST_SIZE(x) (((x) & 0x7) << 3) // Bits [5:3]: AXI AxSIZE (0=1B, 1=2B, 2=4B, 3=8B)
|
||||
#define CTRL_BURST_LEN(x) (((x) & 0xFF) << 6) // Bits [13:6]: AXI AxLEN (0=1 beat, 15=16 beats)
|
||||
|
||||
#define DMA_MODE_MEM2MEM 0
|
||||
#define DMA_MODE_MEM2EP 1
|
||||
#define DMA_MODE_EP2MEM 2
|
||||
#define DMA_EP_CFG(id, bank, word_off) \
|
||||
((((id) & 0xF) << 16) | (((word_off) & 0xFF) << 8) | ((bank) & 0xF))
|
||||
|
||||
// STATUS 寄存器位定义
|
||||
#define STATUS_BUSY_BIT (1 << 0)
|
||||
#define STATUS_DONE_BIT (1 << 1)
|
||||
|
||||
#define SEQ_START_BIT (1 << 0)
|
||||
#define SEQ_SKIP_STORE_BIT (1 << 1)
|
||||
#define SEQ_BUSY_BIT (1 << 0)
|
||||
#define SEQ_DONE_BIT (1 << 1)
|
||||
|
||||
void dma_start_transfer(int ch_id, u32 src, u32 dst, u32 bytes, u32 tag);
|
||||
void dma_wait_polling(int ch_id);
|
||||
@@ -16,15 +16,9 @@
|
||||
* automatically wait-stated on the bus).
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <confreg_time.h>
|
||||
|
||||
#include "dma.h"
|
||||
#include "mlkem_native.h"
|
||||
|
||||
/* ─── BSP globals ─────────────────────────────────────────────────── */
|
||||
unsigned long UART_BASE = 0xbf000000;
|
||||
unsigned long CONFREG_TIMER_BASE = 0xbf20f100;
|
||||
@@ -46,23 +40,10 @@ unsigned long CORE_CLOCKS_PER_SEC = 33000000L;
|
||||
#define MLKEM_RDB_SEL (MLKEM_BASE + 0x10C) /* RW 0=ek 1=dk_pke 2=dk 3=ct */
|
||||
#define MLKEM_RDB_ADR (MLKEM_BASE + 0x110) /* RW output byte index */
|
||||
#define MLKEM_RDB_DAT (MLKEM_BASE + 0x114) /* R selected byte (low 8b) */
|
||||
#define MLKEM_EK_WINDOW (MLKEM_BASE + 0x1000) /* W preload ek, R read ek */
|
||||
#define MLKEM_DK_WINDOW (MLKEM_BASE + 0x2000) /* W preload dk, R read dk */
|
||||
#define MLKEM_CT_WINDOW (MLKEM_BASE + 0x3000) /* W preload c, R read ct */
|
||||
|
||||
/* PRNG sub-window in the shared ML-KEM/FFT/PRNG AXI slave. */
|
||||
#define PRNG_BASE (MLKEM_BASE + 0xD000)
|
||||
#define PRNG_CTRL (PRNG_BASE + 0x000) /* W bit0=mix seed bit1=clr count */
|
||||
#define PRNG_STATUS (PRNG_BASE + 0x004) /* R bit0=ready */
|
||||
#define PRNG_DATA (PRNG_BASE + 0x008) /* R next pseudo-random word */
|
||||
#define PRNG_COUNT (PRNG_BASE + 0x00C) /* R data read count */
|
||||
#define PRNG_SEED (PRNG_BASE + 0x010) /* RW software seed mix value */
|
||||
|
||||
#define CTRL_START 0x1
|
||||
#define STATUS_BUSY 0x1
|
||||
#define STATUS_DONE 0x2
|
||||
#define PRNG_READY 0x1
|
||||
#define PRNG_CTRL_MIX 0x1
|
||||
|
||||
#define OP_KEYGEN 0
|
||||
#define OP_ENCAPS 1
|
||||
@@ -88,8 +69,6 @@ unsigned long CORE_CLOCKS_PER_SEC = 33000000L;
|
||||
/* ─── Convenience macros ──────────────────────────────────────────── */
|
||||
#define REG_WR(addr, val) (*(volatile uint32_t *)(addr) = (uint32_t)(val))
|
||||
#define REG_RD(addr) (*(volatile uint32_t *)(addr))
|
||||
#define PHYS_ADDR(addr) ((uint32_t)(addr) & 0x1FFFFFFFu)
|
||||
#define UNCACHED_ADDR(addr) ((PHYS_ADDR(addr)) | 0xA0000000u)
|
||||
|
||||
/* PLACEHOLDER */
|
||||
|
||||
@@ -143,44 +122,6 @@ static void read_block32(uint32_t base, uint8_t *bytes)
|
||||
}
|
||||
}
|
||||
|
||||
/* Filled from the PRNG endpoint at runtime. */
|
||||
static uint8_t SEED_D[32];
|
||||
static uint8_t SEED_Z[32];
|
||||
static uint8_t MSG_M[32];
|
||||
|
||||
static uint32_t prng_read_word(void)
|
||||
{
|
||||
while ((REG_RD(PRNG_STATUS) & PRNG_READY) == 0)
|
||||
;
|
||||
return REG_RD(PRNG_DATA);
|
||||
}
|
||||
|
||||
static void prng_mix_seed(uint32_t seed)
|
||||
{
|
||||
REG_WR(PRNG_SEED, seed);
|
||||
REG_WR(PRNG_CTRL, PRNG_CTRL_MIX);
|
||||
}
|
||||
|
||||
static void prng_fill(uint8_t *bytes, int n)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < n; i += 4) {
|
||||
uint32_t v = prng_read_word();
|
||||
bytes[i + 0] = (uint8_t)(v & 0xFF);
|
||||
if (i + 1 < n) bytes[i + 1] = (uint8_t)((v >> 8) & 0xFF);
|
||||
if (i + 2 < n) bytes[i + 2] = (uint8_t)((v >> 16) & 0xFF);
|
||||
if (i + 3 < n) bytes[i + 3] = (uint8_t)((v >> 24) & 0xFF);
|
||||
}
|
||||
}
|
||||
|
||||
static void generate_prng_inputs(void)
|
||||
{
|
||||
prng_mix_seed((uint32_t)get_clock_count());
|
||||
prng_fill(SEED_D, sizeof(SEED_D));
|
||||
prng_fill(SEED_Z, sizeof(SEED_Z));
|
||||
prng_fill(MSG_M, sizeof(MSG_M));
|
||||
}
|
||||
|
||||
/* Stream `n` bytes into a preload port. Each PRE_DAT write auto-increments
|
||||
* the preload address; the bus wait-states each write until the cross-domain
|
||||
* byte handshake completes, so a plain loop is correct. */
|
||||
@@ -207,57 +148,25 @@ static void readback(uint32_t sel, uint8_t *buf, int n)
|
||||
|
||||
/* PLACEHOLDER2 */
|
||||
|
||||
static volatile uint8_t *uncached_u8(uint8_t *buf)
|
||||
{
|
||||
return (volatile uint8_t *)UNCACHED_ADDR(buf);
|
||||
}
|
||||
/* Arbitrary but fixed test seeds / message (32 bytes each). */
|
||||
static const uint8_t SEED_D[32] = {
|
||||
0x6d,0xbb,0xc4,0x37,0x51,0x36,0xdf,0x3b,0x07,0xf7,0xc7,0x0e,0x63,0x9e,0x22,0x3e,
|
||||
0x17,0x7e,0x7f,0xd5,0x3b,0x16,0x1b,0x3f,0x4d,0x57,0x79,0x17,0x94,0xf1,0x26,0x24
|
||||
};
|
||||
static const uint8_t SEED_Z[32] = {
|
||||
0xf6,0x96,0x48,0x40,0x48,0xec,0x21,0xf9,0x6c,0xf5,0x0a,0x56,0xd0,0x75,0x9c,0x44,
|
||||
0x8f,0x37,0x79,0x75,0x2f,0x03,0x83,0xd3,0x74,0x49,0x69,0x06,0x94,0xcf,0x7a,0x68
|
||||
};
|
||||
static const uint8_t MSG_M[32] = {
|
||||
0x20,0xa7,0xb7,0xe1,0x0f,0x70,0x49,0x6c,0xc3,0x82,0x20,0xb9,0x44,0xde,0xf6,0x99,
|
||||
0xbf,0x14,0xd1,0x4e,0x55,0xcf,0x4c,0x90,0xa1,0x2c,0x1b,0x33,0xfc,0x80,0xff,0xff
|
||||
};
|
||||
|
||||
static void dma_to_mlkem(uint32_t dst_window, volatile uint8_t *src, int n)
|
||||
{
|
||||
dma_start_transfer(0, PHYS_ADDR(src), PHYS_ADDR(dst_window), (uint32_t)n, 0);
|
||||
dma_wait_polling(0);
|
||||
}
|
||||
|
||||
static void dma_from_mlkem(volatile uint8_t *dst, uint32_t src_window, int n)
|
||||
{
|
||||
dma_start_transfer(0, PHYS_ADDR(src_window), PHYS_ADDR(dst), (uint32_t)n, 0);
|
||||
dma_wait_polling(0);
|
||||
}
|
||||
|
||||
static void print_hex_uc(const char *label, volatile uint8_t *b, int n)
|
||||
{
|
||||
int i;
|
||||
printf("%s", label);
|
||||
for (i = 0; i < n; i++)
|
||||
printf("%02x", b[i]);
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
static void clear_uc(volatile uint8_t *b, int n)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < n; i++)
|
||||
b[i] = 0;
|
||||
}
|
||||
|
||||
static void copy_from_uc(uint8_t *dst, volatile uint8_t *src, int n)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < n; i++)
|
||||
dst[i] = src[i];
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
uint8_t ek[EK_BYTES] __attribute__((aligned(64)));
|
||||
uint8_t dk[DK_BYTES] __attribute__((aligned(64)));
|
||||
uint8_t ct[CT_BYTES] __attribute__((aligned(64)));
|
||||
uint8_t ss_enc[32];
|
||||
uint8_t ss_dec[32];
|
||||
} mlkem_result_t;
|
||||
|
||||
static mlkem_result_t cpu_res;
|
||||
static mlkem_result_t dma_res;
|
||||
static mlkem_result_t sw_res;
|
||||
static uint8_t ek[EK_BYTES];
|
||||
static uint8_t dk[DK_BYTES];
|
||||
static uint8_t ct[CT_BYTES];
|
||||
static uint8_t ss_enc[32];
|
||||
static uint8_t ss_dec[32];
|
||||
|
||||
static void print_hex(const char *label, const uint8_t *b, int n)
|
||||
{
|
||||
@@ -268,196 +177,44 @@ static void print_hex(const char *label, const uint8_t *b, int n)
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
static int verify_result(const mlkem_result_t *res)
|
||||
{
|
||||
int i, mismatch;
|
||||
mismatch = 0;
|
||||
for (i = 0; i < 32; i++)
|
||||
if (res->ss_enc[i] != res->ss_dec[i]) mismatch++;
|
||||
|
||||
return mismatch;
|
||||
}
|
||||
|
||||
static void clear_result_cpu(mlkem_result_t *res)
|
||||
{
|
||||
memset(res, 0, sizeof(*res));
|
||||
}
|
||||
|
||||
static void clear_result_dma(mlkem_result_t *res)
|
||||
{
|
||||
volatile uint8_t *p = (volatile uint8_t *)UNCACHED_ADDR(res);
|
||||
clear_uc(p, sizeof(*res));
|
||||
}
|
||||
|
||||
static unsigned long run_roundtrip_sw(const uint8_t *seed_d,
|
||||
const uint8_t *seed_z,
|
||||
const uint8_t *msg,
|
||||
mlkem_result_t *res,
|
||||
int *status)
|
||||
{
|
||||
unsigned long t0, t1;
|
||||
uint8_t coins[2 * MLKEM_SYMBYTES];
|
||||
int rc;
|
||||
|
||||
clear_result_cpu(res);
|
||||
memcpy(coins, seed_d, MLKEM_SYMBYTES);
|
||||
memcpy(coins + MLKEM_SYMBYTES, seed_z, MLKEM_SYMBYTES);
|
||||
|
||||
t0 = get_clock_count();
|
||||
rc = crypto_kem_keypair_derand(res->ek, res->dk, coins);
|
||||
if (rc == 0)
|
||||
rc = crypto_kem_enc_derand(res->ct, res->ss_enc, res->ek, msg);
|
||||
if (rc == 0)
|
||||
rc = crypto_kem_dec(res->ss_dec, res->ct, res->dk);
|
||||
t1 = get_clock_count();
|
||||
|
||||
*status = rc;
|
||||
return t1 - t0;
|
||||
}
|
||||
|
||||
static unsigned long run_roundtrip_cpu(const uint8_t *seed_d,
|
||||
const uint8_t *seed_z,
|
||||
const uint8_t *msg,
|
||||
mlkem_result_t *res)
|
||||
{
|
||||
unsigned long t0, t1;
|
||||
|
||||
clear_result_cpu(res);
|
||||
t0 = get_clock_count();
|
||||
|
||||
write_block32(MLKEM_D, seed_d);
|
||||
write_block32(MLKEM_Z, seed_z);
|
||||
run_op(OP_KEYGEN);
|
||||
readback(RDB_EK, res->ek, EK_BYTES);
|
||||
readback(RDB_DK, res->dk, DK_BYTES);
|
||||
|
||||
preload(PRE_EK, res->ek, EK_BYTES);
|
||||
write_block32(MLKEM_MSG, msg);
|
||||
run_op(OP_ENCAPS);
|
||||
read_block32(MLKEM_SS, res->ss_enc);
|
||||
readback(RDB_CT, res->ct, CT_BYTES);
|
||||
|
||||
preload(PRE_DK, res->dk, DK_BYTES);
|
||||
preload(PRE_C, res->ct, CT_BYTES);
|
||||
run_op(OP_DECAPS);
|
||||
read_block32(MLKEM_SS, res->ss_dec);
|
||||
|
||||
t1 = get_clock_count();
|
||||
return t1 - t0;
|
||||
}
|
||||
|
||||
static unsigned long run_roundtrip_dma(const uint8_t *seed_d,
|
||||
const uint8_t *seed_z,
|
||||
const uint8_t *msg,
|
||||
mlkem_result_t *res)
|
||||
{
|
||||
unsigned long t0, t1;
|
||||
volatile uint8_t *ek_uc = uncached_u8(res->ek);
|
||||
volatile uint8_t *dk_uc = uncached_u8(res->dk);
|
||||
volatile uint8_t *ct_uc = uncached_u8(res->ct);
|
||||
|
||||
clear_result_dma(res);
|
||||
t0 = get_clock_count();
|
||||
|
||||
write_block32(MLKEM_D, seed_d);
|
||||
write_block32(MLKEM_Z, seed_z);
|
||||
run_op(OP_KEYGEN);
|
||||
dma_from_mlkem(ek_uc, MLKEM_EK_WINDOW, EK_BYTES);
|
||||
dma_from_mlkem(dk_uc, MLKEM_DK_WINDOW, DK_BYTES);
|
||||
|
||||
dma_to_mlkem(MLKEM_EK_WINDOW, ek_uc, EK_BYTES);
|
||||
write_block32(MLKEM_MSG, msg);
|
||||
run_op(OP_ENCAPS);
|
||||
read_block32(MLKEM_SS, res->ss_enc);
|
||||
dma_from_mlkem(ct_uc, MLKEM_CT_WINDOW, CT_BYTES);
|
||||
|
||||
dma_to_mlkem(MLKEM_DK_WINDOW, dk_uc, DK_BYTES);
|
||||
dma_to_mlkem(MLKEM_CT_WINDOW, ct_uc, CT_BYTES);
|
||||
run_op(OP_DECAPS);
|
||||
read_block32(MLKEM_SS, res->ss_dec);
|
||||
|
||||
t1 = get_clock_count();
|
||||
|
||||
copy_from_uc(res->ek, ek_uc, EK_BYTES);
|
||||
copy_from_uc(res->dk, dk_uc, DK_BYTES);
|
||||
copy_from_uc(res->ct, ct_uc, CT_BYTES);
|
||||
|
||||
return t1 - t0;
|
||||
}
|
||||
|
||||
static int compare_results(const mlkem_result_t *a, const mlkem_result_t *b)
|
||||
{
|
||||
return memcmp(a->ek, b->ek, EK_BYTES) ||
|
||||
memcmp(a->dk, b->dk, DK_BYTES) ||
|
||||
memcmp(a->ct, b->ct, CT_BYTES) ||
|
||||
memcmp(a->ss_enc, b->ss_enc, sizeof(a->ss_enc)) ||
|
||||
memcmp(a->ss_dec, b->ss_dec, sizeof(a->ss_dec));
|
||||
}
|
||||
|
||||
static unsigned long cycles_to_us(unsigned long cycles)
|
||||
{
|
||||
return cycles / (CORE_CLOCKS_PER_SEC / USEC_PER_SEC);
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
int mismatch_sw, mismatch_cpu, mismatch_dma, sw_status, cpu_vs_dma_diff;
|
||||
int sw_vs_cpu_diff, sw_vs_dma_diff;
|
||||
unsigned long sw_cycles, cpu_cycles, dma_cycles;
|
||||
int i, mismatch;
|
||||
|
||||
printf("MLKEM_START\n");
|
||||
generate_prng_inputs();
|
||||
|
||||
sw_cycles = run_roundtrip_sw(SEED_D, SEED_Z, MSG_M, &sw_res, &sw_status);
|
||||
cpu_cycles = run_roundtrip_cpu(SEED_D, SEED_Z, MSG_M, &cpu_res);
|
||||
dma_cycles = run_roundtrip_dma(SEED_D, SEED_Z, MSG_M, &dma_res);
|
||||
/* ── 1. KeyGen: d,z -> ek, dk ─────────────────────────────────── */
|
||||
write_block32(MLKEM_D, SEED_D);
|
||||
write_block32(MLKEM_Z, SEED_Z);
|
||||
run_op(OP_KEYGEN);
|
||||
readback(RDB_EK, ek, EK_BYTES);
|
||||
readback(RDB_DK, dk, DK_BYTES);
|
||||
print_hex("EK32=", ek, 32); /* first 32 bytes as a fingerprint */
|
||||
|
||||
mismatch_sw = verify_result(&sw_res);
|
||||
mismatch_cpu = verify_result(&cpu_res);
|
||||
mismatch_dma = verify_result(&dma_res);
|
||||
cpu_vs_dma_diff = compare_results(&cpu_res, &dma_res);
|
||||
sw_vs_cpu_diff = compare_results(&sw_res, &cpu_res);
|
||||
sw_vs_dma_diff = compare_results(&sw_res, &dma_res);
|
||||
/* ── 2. Encaps: ek + msg -> ss, ct ────────────────────────────── */
|
||||
preload(PRE_EK, ek, EK_BYTES);
|
||||
write_block32(MLKEM_MSG, MSG_M);
|
||||
run_op(OP_ENCAPS);
|
||||
read_block32(MLKEM_SS, ss_enc);
|
||||
readback(RDB_CT, ct, CT_BYTES);
|
||||
print_hex("SS_ENC=", ss_enc, 32);
|
||||
|
||||
/* ── 3. Decaps: dk + ct -> ss' ────────────────────────────────── */
|
||||
preload(PRE_DK, dk, DK_BYTES);
|
||||
preload(PRE_C, ct, CT_BYTES);
|
||||
run_op(OP_DECAPS);
|
||||
read_block32(MLKEM_SS, ss_dec);
|
||||
print_hex("SS_DEC=", ss_dec, 32);
|
||||
|
||||
print_hex("SW_EK32=", sw_res.ek, 32);
|
||||
print_hex("SW_SS_ENC=", sw_res.ss_enc, 32);
|
||||
print_hex("SW_SS_DEC=", sw_res.ss_dec, 32);
|
||||
print_hex("CPU_EK32=", cpu_res.ek, 32);
|
||||
print_hex("CPU_SS_ENC=", cpu_res.ss_enc, 32);
|
||||
print_hex("CPU_SS_DEC=", cpu_res.ss_dec, 32);
|
||||
print_hex("DMA_EK32=", dma_res.ek, 32);
|
||||
print_hex("DMA_SS_ENC=", dma_res.ss_enc, 32);
|
||||
print_hex("DMA_SS_DEC=", dma_res.ss_dec, 32);
|
||||
/* ── 4. Verify shared secrets match ───────────────────────────── */
|
||||
mismatch = 0;
|
||||
for (i = 0; i < 32; i++)
|
||||
if (ss_enc[i] != ss_dec[i]) mismatch++;
|
||||
|
||||
printf("MLKEM_SW_STATUS=%d\n", sw_status);
|
||||
printf("MLKEM_SW_CYCLES=%lu\n", sw_cycles);
|
||||
printf("MLKEM_CPU_CYCLES=%lu\n", cpu_cycles);
|
||||
printf("MLKEM_DMA_CYCLES=%lu\n", dma_cycles);
|
||||
printf("MLKEM_SW_US=%lu\n", cycles_to_us(sw_cycles));
|
||||
printf("MLKEM_CPU_US=%lu\n", cycles_to_us(cpu_cycles));
|
||||
printf("MLKEM_DMA_US=%lu\n", cycles_to_us(dma_cycles));
|
||||
if (cpu_cycles != 0) {
|
||||
unsigned long hw_speedup_x100 = (sw_cycles * 100u) / cpu_cycles;
|
||||
printf("MLKEM_HW_VS_SW_SPEEDUP_X100=%lu\n", hw_speedup_x100);
|
||||
}
|
||||
if (dma_cycles != 0) {
|
||||
unsigned long hw_dma_speedup_x100 = (sw_cycles * 100u) / dma_cycles;
|
||||
printf("MLKEM_HW_DMA_VS_SW_SPEEDUP_X100=%lu\n", hw_dma_speedup_x100);
|
||||
}
|
||||
if (dma_cycles != 0) {
|
||||
unsigned long speedup_x100 = (cpu_cycles * 100u) / dma_cycles;
|
||||
printf("MLKEM_DMA_SPEEDUP_X100=%lu\n", speedup_x100);
|
||||
}
|
||||
|
||||
if (sw_status == 0 && mismatch_sw == 0 && mismatch_cpu == 0 &&
|
||||
mismatch_dma == 0 && cpu_vs_dma_diff == 0 &&
|
||||
sw_vs_cpu_diff == 0 && sw_vs_dma_diff == 0)
|
||||
if (mismatch == 0)
|
||||
printf("MLKEM_RESULT=PASS\n");
|
||||
else {
|
||||
printf("MLKEM_RESULT=FAIL sw_status=%d sw_mismatch=%d cpu_mismatch=%d dma_mismatch=%d cpu_dma_diff=%d sw_cpu_diff=%d sw_dma_diff=%d\n",
|
||||
sw_status, mismatch_sw, mismatch_cpu, mismatch_dma,
|
||||
cpu_vs_dma_diff, sw_vs_cpu_diff, sw_vs_dma_diff);
|
||||
}
|
||||
else
|
||||
printf("MLKEM_RESULT=FAIL (%d byte mismatch)\n", mismatch);
|
||||
|
||||
printf("MLKEM_DONE\n");
|
||||
return 0;
|
||||
|
||||
@@ -1,294 +0,0 @@
|
||||
mlkem-native is a fork of the public domain Kyber reference
|
||||
implementation, available on https://github.com/pq-crystals/kyber.
|
||||
|
||||
All source code in mlkem/* and dev/* is licensed under your choice
|
||||
of the Apache-2.0 license OR the ISC license OR the MIT license.
|
||||
These licenses are reproduced at the bottom of this file.
|
||||
The copyright holders are indicated at the top of each file.
|
||||
|
||||
The code in test/notrandombytes/* is derived from
|
||||
https://cr.yp.to/papers.html#surf and licensed under
|
||||
LicenseRef-PD-hp OR CC0-1.0 OR 0BSD OR MIT-0 OR MIT.
|
||||
It is only used for testing purposes.
|
||||
|
||||
The benchmarking code in test/hal/hal.c carries the
|
||||
MIT license. It is only used for testing purposes.
|
||||
|
||||
```
|
||||
Copyright (c) The mlkem-native project authors
|
||||
Copyright (c) 2020 Dougall Johnson
|
||||
Copyright (c) 2022 Arm Limited
|
||||
SPDX-License-Identifier: MIT
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
```
|
||||
|
||||
The tiny_sha3 implementation in examples/custom_backend/mlkem_native/mlkem/fips202/native/custom/src/
|
||||
carries the MIT license. It is only used for testing purposes.
|
||||
|
||||
```
|
||||
SPDX-License-Identifier: MIT
|
||||
|
||||
19-Nov-11 Markku-Juhani O. Saarinen <mjos@iki.fi>
|
||||
```
|
||||
|
||||
ISC license
|
||||
-----------
|
||||
|
||||
Copyright <YEAR> <OWNER>
|
||||
|
||||
Permission to use, copy, modify, and/or distribute this software for any purpose
|
||||
with or without fee is hereby granted, provided that the above copyright notice
|
||||
and this permission notice appear in all copies.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
|
||||
REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
|
||||
FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
|
||||
INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
|
||||
OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF
|
||||
THIS SOFTWARE.
|
||||
|
||||
|
||||
MIT license
|
||||
-----------
|
||||
|
||||
Copyright <YEAR> <COPYRIGHT HOLDER>
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
this software and associated documentation files (the “Software”), to deal in
|
||||
the Software without restriction, including without limitation the rights to
|
||||
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
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|
||||
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|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
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|
||||
|
||||
THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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|
||||
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Apache-2.0 license
|
||||
------------------
|
||||
|
||||
Apache License
|
||||
Version 2.0, January 2004
|
||||
http://www.apache.org/licenses/
|
||||
|
||||
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
|
||||
|
||||
1. Definitions.
|
||||
|
||||
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|
||||
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||||
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||||
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END OF TERMS AND CONDITIONS
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APPENDIX: How to apply the Apache License to your work.
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|
||||
@@ -1,23 +0,0 @@
|
||||
[//]: # (SPDX-License-Identifier: CC-BY-4.0)
|
||||
|
||||
# mlkem-native source tree
|
||||
|
||||
This is the main source tree of mlkem-native.
|
||||
|
||||
## Building
|
||||
|
||||
To build a mlkem-native for a fixed parameter set (ML-KEM-512/768/1024), build the compilation in units in `src/*` separately, and link to an RNG and your application. See [examples/basic](../examples/basic) for a simple example.
|
||||
|
||||
Alternatively, you can use the auto-geneated helper files [mlkem_native.c](mlkem_native.c) and [mlkem_native_asm.S](mlkem_native_asm.S), which bundle all *.c and *.S files together. See [examples/monolithic_build](../examples/monolithic_build) and [examples/monolithic_build_native](../examples/monolithic_build_native) for examples with and without native code.
|
||||
|
||||
## Configuration
|
||||
|
||||
The build is configured by [mlkem_native_config.h](mlkem_native_config.h), or by the file pointed to by `MLK_CONFIG_FILE`. Note in particular `MLK_CONFIG_PARAMETER_SET` and `MLK_CONFIG_NAMESPACE_PREFIX`, which set the parameter set and namespace prefix, respectively.
|
||||
|
||||
## API
|
||||
|
||||
The public API is defined in [mlkem_native.h](mlkem_native.h).
|
||||
|
||||
## Supporting multiple parameter sets
|
||||
|
||||
If you want to support multiple parameter sets, build the library once per parameter set you want to support. Set `MLK_CONFIG_MULTILEVEL_WITH_SHARED` for one of the builds, and `MLK_CONFIG_MULTILEVEL_NO_SHARED` for the others, to avoid duplicating shared functionality. Finally, link with RNG and your application as before. This is demonstrated in the examples [examples/multilevel_build](../examples/multilevel_build), [examples/multilevel_build_native](../examples/multilevel_build_native), [examples/monolithic_build_multilevel](../examples/monolithic_build_multilevel) and [examples/monolithic_build_multilevel_native](../examples/monolithic_build_multilevel_native).
|
||||
@@ -1,699 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING: This file is auto-generated from scripts/autogen
|
||||
* in the mlkem-native repository.
|
||||
* Do not modify it directly.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Single compilation unit (SCU) for fixed-level build of mlkem-native
|
||||
*
|
||||
* This compilation unit bundles together all source files for a build
|
||||
* of mlkem-native for a fixed security level (MLKEM-512/768/1024).
|
||||
*
|
||||
* # API
|
||||
*
|
||||
* The API exposed by this file is described in mlkem_native.h.
|
||||
*
|
||||
* # Multi-level build
|
||||
*
|
||||
* If you want an SCU build of mlkem-native with support for multiple security
|
||||
* levels, you need to include this file multiple times, and set
|
||||
* MLK_CONFIG_MULTILEVEL_WITH_SHARED and MLK_CONFIG_MULTILEVEL_NO_SHARED
|
||||
* appropriately. This is exemplified in examples/monolithic_build_multilevel
|
||||
* and examples/monolithic_build_multilevel_native.
|
||||
*
|
||||
* # Configuration
|
||||
*
|
||||
* The following options from the mlkem-native configuration are relevant:
|
||||
*
|
||||
* - MLK_CONFIG_FIPS202_CUSTOM_HEADER
|
||||
* Set this option if you use a custom FIPS202 implementation.
|
||||
*
|
||||
* - MLK_CONFIG_USE_NATIVE_BACKEND_ARITH
|
||||
* Set this option if you want to include the native arithmetic backends
|
||||
* in your build.
|
||||
*
|
||||
* - MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202
|
||||
* Set this option if you want to include the native FIPS202 backends
|
||||
* in your build.
|
||||
*
|
||||
* - MLK_CONFIG_MONOBUILD_KEEP_SHARED_HEADERS
|
||||
* Set this option if you want to keep the directives defined in
|
||||
* level-independent headers. This is needed for a multi-level build.
|
||||
*/
|
||||
|
||||
/* If parts of the mlkem-native source tree are not used,
|
||||
* consider reducing this header via `unifdef`.
|
||||
*
|
||||
* Example:
|
||||
* ```bash
|
||||
* unifdef -UMLK_CONFIG_USE_NATIVE_BACKEND_ARITH mlkem_native.c
|
||||
* ```
|
||||
*/
|
||||
|
||||
#include "src/common.h"
|
||||
|
||||
#include "src/compress.c"
|
||||
#include "src/debug.c"
|
||||
#include "src/indcpa.c"
|
||||
#include "src/kem.c"
|
||||
#include "src/poly.c"
|
||||
#include "src/poly_k.c"
|
||||
#include "src/sampling.c"
|
||||
#include "src/verify.c"
|
||||
|
||||
#if !defined(MLK_CONFIG_FIPS202_CUSTOM_HEADER)
|
||||
#include "src/fips202/fips202.c"
|
||||
#include "src/fips202/fips202x4.c"
|
||||
#include "src/fips202/keccakf1600.c"
|
||||
#endif
|
||||
|
||||
#if defined(MLK_CONFIG_USE_NATIVE_BACKEND_ARITH)
|
||||
#if defined(MLK_SYS_AARCH64)
|
||||
#include "src/native/aarch64/src/aarch64_zetas.c"
|
||||
#include "src/native/aarch64/src/rej_uniform_table.c"
|
||||
#endif
|
||||
#if defined(MLK_SYS_X86_64)
|
||||
#include "src/native/x86_64/src/compress_consts.c"
|
||||
#include "src/native/x86_64/src/consts.c"
|
||||
#include "src/native/x86_64/src/rej_uniform_table.c"
|
||||
#endif
|
||||
#if defined(MLK_SYS_RISCV64)
|
||||
#include "src/native/riscv64/src/rv64v_debug.c"
|
||||
#include "src/native/riscv64/src/rv64v_poly.c"
|
||||
#endif
|
||||
#if defined(MLK_SYS_PPC64LE)
|
||||
#include "src/native/ppc64le/src/consts.c"
|
||||
#endif
|
||||
#endif /* MLK_CONFIG_USE_NATIVE_BACKEND_ARITH */
|
||||
|
||||
#if defined(MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202)
|
||||
#if defined(MLK_SYS_AARCH64)
|
||||
#include "src/fips202/native/aarch64/src/keccakf1600_round_constants.c"
|
||||
#endif
|
||||
#if defined(MLK_SYS_X86_64)
|
||||
#include "src/fips202/native/x86_64/src/keccakf1600_constants.c"
|
||||
#endif
|
||||
#if defined(MLK_SYS_ARMV81M_MVE)
|
||||
#include "src/fips202/native/armv81m/src/keccak_f1600_x4_mve.c"
|
||||
#include "src/fips202/native/armv81m/src/keccakf1600_round_constants.c"
|
||||
#endif
|
||||
#endif /* MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202 */
|
||||
|
||||
/* Macro #undef's
|
||||
*
|
||||
* The following undefines macros from headers
|
||||
* included by the source files imported above.
|
||||
*
|
||||
* This is to allow building and linking multiple builds
|
||||
* of mlkem-native for varying parameter sets through concatenation
|
||||
* of this file, as if the files had been compiled separately.
|
||||
* If this is not relevant to you, you may remove the following.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Undefine macros from MLK_CONFIG_PARAMETER_SET-specific files
|
||||
*/
|
||||
/* mlkem/mlkem_native.h */
|
||||
#undef CRYPTO_BYTES
|
||||
#undef CRYPTO_CIPHERTEXTBYTES
|
||||
#undef CRYPTO_PUBLICKEYBYTES
|
||||
#undef CRYPTO_SECRETKEYBYTES
|
||||
#undef CRYPTO_SYMBYTES
|
||||
#undef MLKEM1024_BYTES
|
||||
#undef MLKEM1024_CIPHERTEXTBYTES
|
||||
#undef MLKEM1024_PUBLICKEYBYTES
|
||||
#undef MLKEM1024_SECRETKEYBYTES
|
||||
#undef MLKEM1024_SYMBYTES
|
||||
#undef MLKEM512_BYTES
|
||||
#undef MLKEM512_CIPHERTEXTBYTES
|
||||
#undef MLKEM512_PUBLICKEYBYTES
|
||||
#undef MLKEM512_SECRETKEYBYTES
|
||||
#undef MLKEM512_SYMBYTES
|
||||
#undef MLKEM768_BYTES
|
||||
#undef MLKEM768_CIPHERTEXTBYTES
|
||||
#undef MLKEM768_PUBLICKEYBYTES
|
||||
#undef MLKEM768_SECRETKEYBYTES
|
||||
#undef MLKEM768_SYMBYTES
|
||||
#undef MLKEM_BYTES
|
||||
#undef MLKEM_CIPHERTEXTBYTES
|
||||
#undef MLKEM_CIPHERTEXTBYTES_
|
||||
#undef MLKEM_PUBLICKEYBYTES
|
||||
#undef MLKEM_PUBLICKEYBYTES_
|
||||
#undef MLKEM_SECRETKEYBYTES
|
||||
#undef MLKEM_SECRETKEYBYTES_
|
||||
#undef MLKEM_SYMBYTES
|
||||
#undef MLK_API_CONCAT
|
||||
#undef MLK_API_CONCAT_
|
||||
#undef MLK_API_CONCAT_UNDERSCORE
|
||||
#undef MLK_API_LEGACY_CONFIG
|
||||
#undef MLK_API_MUST_CHECK_RETURN_VALUE
|
||||
#undef MLK_API_NAMESPACE
|
||||
#undef MLK_API_QUALIFIER
|
||||
#undef MLK_CONFIG_API_CONSTANTS_ONLY
|
||||
#undef MLK_CONFIG_API_NAMESPACE_PREFIX
|
||||
#undef MLK_CONFIG_API_NO_SUPERCOP
|
||||
#undef MLK_CONFIG_API_PARAMETER_SET
|
||||
#undef MLK_CONFIG_API_QUALIFIER
|
||||
#undef MLK_ERR_FAIL
|
||||
#undef MLK_ERR_OUT_OF_MEMORY
|
||||
#undef MLK_ERR_RNG_FAIL
|
||||
#undef MLK_H
|
||||
#undef MLK_MAX3_
|
||||
#undef MLK_TOTAL_ALLOC_1024
|
||||
#undef MLK_TOTAL_ALLOC_1024_DECAPS
|
||||
#undef MLK_TOTAL_ALLOC_1024_ENCAPS
|
||||
#undef MLK_TOTAL_ALLOC_1024_KEYPAIR
|
||||
#undef MLK_TOTAL_ALLOC_1024_KEYPAIR_NO_PCT
|
||||
#undef MLK_TOTAL_ALLOC_1024_KEYPAIR_PCT
|
||||
#undef MLK_TOTAL_ALLOC_512
|
||||
#undef MLK_TOTAL_ALLOC_512_DECAPS
|
||||
#undef MLK_TOTAL_ALLOC_512_ENCAPS
|
||||
#undef MLK_TOTAL_ALLOC_512_KEYPAIR
|
||||
#undef MLK_TOTAL_ALLOC_512_KEYPAIR_NO_PCT
|
||||
#undef MLK_TOTAL_ALLOC_512_KEYPAIR_PCT
|
||||
#undef MLK_TOTAL_ALLOC_768
|
||||
#undef MLK_TOTAL_ALLOC_768_DECAPS
|
||||
#undef MLK_TOTAL_ALLOC_768_ENCAPS
|
||||
#undef MLK_TOTAL_ALLOC_768_KEYPAIR
|
||||
#undef MLK_TOTAL_ALLOC_768_KEYPAIR_NO_PCT
|
||||
#undef MLK_TOTAL_ALLOC_768_KEYPAIR_PCT
|
||||
#undef crypto_kem_check_pk
|
||||
#undef crypto_kem_check_sk
|
||||
#undef crypto_kem_dec
|
||||
#undef crypto_kem_enc
|
||||
#undef crypto_kem_enc_derand
|
||||
#undef crypto_kem_keypair
|
||||
#undef crypto_kem_keypair_derand
|
||||
/* mlkem/src/common.h */
|
||||
#undef MLK_ADD_PARAM_SET
|
||||
#undef MLK_ALLOC
|
||||
#undef MLK_APPLY
|
||||
#undef MLK_ASM_FN_SIZE
|
||||
#undef MLK_ASM_FN_SYMBOL
|
||||
#undef MLK_ASM_NAMESPACE
|
||||
#undef MLK_BUILD_INTERNAL
|
||||
#undef MLK_COMMON_H
|
||||
#undef MLK_CONCAT
|
||||
#undef MLK_CONCAT_
|
||||
#undef MLK_CONTEXT_PARAMETERS_0
|
||||
#undef MLK_CONTEXT_PARAMETERS_1
|
||||
#undef MLK_CONTEXT_PARAMETERS_2
|
||||
#undef MLK_CONTEXT_PARAMETERS_3
|
||||
#undef MLK_CONTEXT_PARAMETERS_4
|
||||
#undef MLK_EMPTY_CU
|
||||
#undef MLK_ERR_FAIL
|
||||
#undef MLK_ERR_OUT_OF_MEMORY
|
||||
#undef MLK_ERR_RNG_FAIL
|
||||
#undef MLK_EXTERNAL_API
|
||||
#undef MLK_FIPS202X4_HEADER_FILE
|
||||
#undef MLK_FIPS202_HEADER_FILE
|
||||
#undef MLK_FREE
|
||||
#undef MLK_INTERNAL_API
|
||||
#undef MLK_INTERNAL_DATA_DECLARATION
|
||||
#undef MLK_INTERNAL_DATA_DEFINITION
|
||||
#undef MLK_NAMESPACE
|
||||
#undef MLK_NAMESPACE_K
|
||||
#undef MLK_NAMESPACE_PREFIX
|
||||
#undef MLK_NAMESPACE_PREFIX_K
|
||||
#undef mlk_memcpy
|
||||
#undef mlk_memset
|
||||
/* mlkem/src/indcpa.h */
|
||||
#undef MLK_INDCPA_H
|
||||
#undef mlk_gen_matrix
|
||||
#undef mlk_indcpa_dec
|
||||
#undef mlk_indcpa_enc
|
||||
#undef mlk_indcpa_keypair_derand
|
||||
/* mlkem/src/kem.h */
|
||||
#undef MLK_KEM_H
|
||||
#undef mlk_kem_check_pk
|
||||
#undef mlk_kem_check_sk
|
||||
#undef mlk_kem_dec
|
||||
#undef mlk_kem_enc
|
||||
#undef mlk_kem_enc_derand
|
||||
#undef mlk_kem_keypair
|
||||
#undef mlk_kem_keypair_derand
|
||||
/* mlkem/src/params.h */
|
||||
#undef MLKEM_DU
|
||||
#undef MLKEM_DV
|
||||
#undef MLKEM_ETA1
|
||||
#undef MLKEM_ETA2
|
||||
#undef MLKEM_INDCCA_CIPHERTEXTBYTES
|
||||
#undef MLKEM_INDCCA_PUBLICKEYBYTES
|
||||
#undef MLKEM_INDCCA_SECRETKEYBYTES
|
||||
#undef MLKEM_INDCPA_BYTES
|
||||
#undef MLKEM_INDCPA_MSGBYTES
|
||||
#undef MLKEM_INDCPA_PUBLICKEYBYTES
|
||||
#undef MLKEM_INDCPA_SECRETKEYBYTES
|
||||
#undef MLKEM_K
|
||||
#undef MLKEM_N
|
||||
#undef MLKEM_POLYBYTES
|
||||
#undef MLKEM_POLYCOMPRESSEDBYTES_D10
|
||||
#undef MLKEM_POLYCOMPRESSEDBYTES_D11
|
||||
#undef MLKEM_POLYCOMPRESSEDBYTES_D4
|
||||
#undef MLKEM_POLYCOMPRESSEDBYTES_D5
|
||||
#undef MLKEM_POLYCOMPRESSEDBYTES_DU
|
||||
#undef MLKEM_POLYCOMPRESSEDBYTES_DV
|
||||
#undef MLKEM_POLYVECBYTES
|
||||
#undef MLKEM_POLYVECCOMPRESSEDBYTES_DU
|
||||
#undef MLKEM_Q
|
||||
#undef MLKEM_Q_HALF
|
||||
#undef MLKEM_SSBYTES
|
||||
#undef MLKEM_SYMBYTES
|
||||
#undef MLKEM_UINT12_LIMIT
|
||||
#undef MLK_PARAMS_H
|
||||
/* mlkem/src/poly_k.h */
|
||||
#undef MLK_POLY_K_H
|
||||
#undef mlk_poly_compress_du
|
||||
#undef mlk_poly_compress_dv
|
||||
#undef mlk_poly_decompress_du
|
||||
#undef mlk_poly_decompress_dv
|
||||
#undef mlk_poly_getnoise_eta1122_4x
|
||||
#undef mlk_poly_getnoise_eta1_4x
|
||||
#undef mlk_poly_getnoise_eta2
|
||||
#undef mlk_poly_getnoise_eta2_4x
|
||||
#undef mlk_polymat
|
||||
#undef mlk_polyvec
|
||||
#undef mlk_polyvec_add
|
||||
#undef mlk_polyvec_basemul_acc_montgomery_cached
|
||||
#undef mlk_polyvec_compress_du
|
||||
#undef mlk_polyvec_decompress_du
|
||||
#undef mlk_polyvec_frombytes
|
||||
#undef mlk_polyvec_invntt_tomont
|
||||
#undef mlk_polyvec_mulcache
|
||||
#undef mlk_polyvec_mulcache_compute
|
||||
#undef mlk_polyvec_ntt
|
||||
#undef mlk_polyvec_reduce
|
||||
#undef mlk_polyvec_tobytes
|
||||
#undef mlk_polyvec_tomont
|
||||
|
||||
#if !defined(MLK_CONFIG_MONOBUILD_KEEP_SHARED_HEADERS)
|
||||
/*
|
||||
* Undefine macros from MLK_CONFIG_PARAMETER_SET-generic files
|
||||
*/
|
||||
/* mlkem/src/compress.h */
|
||||
#undef MLK_COMPRESS_H
|
||||
#undef mlk_poly_compress_d10
|
||||
#undef mlk_poly_compress_d11
|
||||
#undef mlk_poly_compress_d4
|
||||
#undef mlk_poly_compress_d5
|
||||
#undef mlk_poly_decompress_d10
|
||||
#undef mlk_poly_decompress_d11
|
||||
#undef mlk_poly_decompress_d4
|
||||
#undef mlk_poly_decompress_d5
|
||||
#undef mlk_poly_frombytes
|
||||
#undef mlk_poly_frommsg
|
||||
#undef mlk_poly_tobytes
|
||||
#undef mlk_poly_tomsg
|
||||
/* mlkem/src/debug.h */
|
||||
#undef MLK_DEBUG_H
|
||||
#undef mlk_assert
|
||||
#undef mlk_assert_abs_bound
|
||||
#undef mlk_assert_abs_bound_2d
|
||||
#undef mlk_assert_bound
|
||||
#undef mlk_assert_bound_2d
|
||||
#undef mlk_debug_check_assert
|
||||
#undef mlk_debug_check_bounds
|
||||
/* mlkem/src/poly.h */
|
||||
#undef MLK_INVNTT_BOUND
|
||||
#undef MLK_NTT_BOUND
|
||||
#undef MLK_POLY_H
|
||||
#undef mlk_poly_add
|
||||
#undef mlk_poly_invntt_tomont
|
||||
#undef mlk_poly_mulcache_compute
|
||||
#undef mlk_poly_ntt
|
||||
#undef mlk_poly_reduce
|
||||
#undef mlk_poly_sub
|
||||
#undef mlk_poly_tomont
|
||||
/* mlkem/src/randombytes.h */
|
||||
#undef MLK_RANDOMBYTES_H
|
||||
/* mlkem/src/sampling.h */
|
||||
#undef MLK_SAMPLING_H
|
||||
#undef mlk_poly_cbd2
|
||||
#undef mlk_poly_cbd3
|
||||
#undef mlk_poly_rej_uniform
|
||||
#undef mlk_poly_rej_uniform_x4
|
||||
/* mlkem/src/symmetric.h */
|
||||
#undef MLK_SYMMETRIC_H
|
||||
#undef MLK_XOF_RATE
|
||||
#undef mlk_hash_g
|
||||
#undef mlk_hash_h
|
||||
#undef mlk_hash_j
|
||||
#undef mlk_prf_eta
|
||||
#undef mlk_prf_eta1
|
||||
#undef mlk_prf_eta1_x4
|
||||
#undef mlk_prf_eta2
|
||||
#undef mlk_xof_absorb
|
||||
#undef mlk_xof_ctx
|
||||
#undef mlk_xof_init
|
||||
#undef mlk_xof_release
|
||||
#undef mlk_xof_squeezeblocks
|
||||
#undef mlk_xof_x4_absorb
|
||||
#undef mlk_xof_x4_ctx
|
||||
#undef mlk_xof_x4_init
|
||||
#undef mlk_xof_x4_release
|
||||
#undef mlk_xof_x4_squeezeblocks
|
||||
/* mlkem/src/sys.h */
|
||||
#undef MLK_ALIGN
|
||||
#undef MLK_ALIGN_UP
|
||||
#undef MLK_ALWAYS_INLINE
|
||||
#undef MLK_CET_ENDBR
|
||||
#undef MLK_CT_TESTING_DECLASSIFY
|
||||
#undef MLK_CT_TESTING_SECRET
|
||||
#undef MLK_DEFAULT_ALIGN
|
||||
#undef MLK_HAVE_INLINE_ASM
|
||||
#undef MLK_INLINE
|
||||
#undef MLK_MUST_CHECK_RETURN_VALUE
|
||||
#undef MLK_NOINLINE
|
||||
#undef MLK_RESTRICT
|
||||
#undef MLK_STATIC_TESTABLE
|
||||
#undef MLK_SYSV_ABI
|
||||
#undef MLK_SYSV_ABI_SUPPORTED
|
||||
#undef MLK_SYS_AARCH64
|
||||
#undef MLK_SYS_AARCH64_EB
|
||||
#undef MLK_SYS_APPLE
|
||||
#undef MLK_SYS_ARMV81M_MVE
|
||||
#undef MLK_SYS_BIG_ENDIAN
|
||||
#undef MLK_SYS_H
|
||||
#undef MLK_SYS_LINUX
|
||||
#undef MLK_SYS_LITTLE_ENDIAN
|
||||
#undef MLK_SYS_PPC64LE
|
||||
#undef MLK_SYS_RISCV32
|
||||
#undef MLK_SYS_RISCV64
|
||||
#undef MLK_SYS_RISCV64_RVV
|
||||
#undef MLK_SYS_WINDOWS
|
||||
#undef MLK_SYS_X86_64
|
||||
#undef MLK_SYS_X86_64_AVX2
|
||||
/* mlkem/src/verify.h */
|
||||
#undef MLK_USE_ASM_VALUE_BARRIER
|
||||
#undef MLK_VERIFY_H
|
||||
#undef mlk_ct_opt_blocker_u64
|
||||
/* mlkem/src/cbmc.h */
|
||||
#undef MLK_CBMC_H
|
||||
#undef __contract__
|
||||
#undef __loop__
|
||||
|
||||
#if !defined(MLK_CONFIG_FIPS202_CUSTOM_HEADER)
|
||||
/*
|
||||
* Undefine macros from FIPS-202 files
|
||||
*/
|
||||
/* mlkem/src/fips202/fips202.h */
|
||||
#undef FIPS202_X4_DEFAULT_IMPLEMENTATION
|
||||
#undef MLK_FIPS202_FIPS202_H
|
||||
#undef SHA3_256_HASHBYTES
|
||||
#undef SHA3_256_RATE
|
||||
#undef SHA3_384_RATE
|
||||
#undef SHA3_512_HASHBYTES
|
||||
#undef SHA3_512_RATE
|
||||
#undef SHAKE128_RATE
|
||||
#undef SHAKE256_RATE
|
||||
#undef mlk_sha3_256
|
||||
#undef mlk_sha3_512
|
||||
#undef mlk_shake128_absorb_once
|
||||
#undef mlk_shake128_init
|
||||
#undef mlk_shake128_release
|
||||
#undef mlk_shake128_squeezeblocks
|
||||
#undef mlk_shake256
|
||||
/* mlkem/src/fips202/fips202x4.h */
|
||||
#undef MLK_FIPS202_FIPS202X4_H
|
||||
#undef mlk_shake128x4_absorb_once
|
||||
#undef mlk_shake128x4_init
|
||||
#undef mlk_shake128x4_release
|
||||
#undef mlk_shake128x4_squeezeblocks
|
||||
#undef mlk_shake256x4
|
||||
/* mlkem/src/fips202/keccakf1600.h */
|
||||
#undef MLK_FIPS202_KECCAKF1600_H
|
||||
#undef MLK_KECCAK_LANES
|
||||
#undef MLK_KECCAK_WAY
|
||||
#undef mlk_keccakf1600_extract_bytes
|
||||
#undef mlk_keccakf1600_permute
|
||||
#undef mlk_keccakf1600_xor_bytes
|
||||
#undef mlk_keccakf1600x4_extract_bytes
|
||||
#undef mlk_keccakf1600x4_permute
|
||||
#undef mlk_keccakf1600x4_xor_bytes
|
||||
#endif /* !MLK_CONFIG_FIPS202_CUSTOM_HEADER */
|
||||
|
||||
#if defined(MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202)
|
||||
/* mlkem/src/fips202/native/api.h */
|
||||
#undef MLK_FIPS202_NATIVE_API_H
|
||||
#undef MLK_NATIVE_FUNC_FALLBACK
|
||||
#undef MLK_NATIVE_FUNC_SUCCESS
|
||||
/* mlkem/src/fips202/native/auto.h */
|
||||
#undef MLK_FIPS202_NATIVE_AUTO_H
|
||||
#if defined(MLK_SYS_AARCH64)
|
||||
/*
|
||||
* Undefine macros from native code (FIPS202, AArch64)
|
||||
*/
|
||||
/* mlkem/src/fips202/native/aarch64/auto.h */
|
||||
#undef MLK_FIPS202_NATIVE_AARCH64_AUTO_H
|
||||
/* mlkem/src/fips202/native/aarch64/src/fips202_native_aarch64.h */
|
||||
#undef MLK_FIPS202_NATIVE_AARCH64_SRC_FIPS202_NATIVE_AARCH64_H
|
||||
#undef mlk_keccak_f1600_x1_scalar_aarch64_asm
|
||||
#undef mlk_keccak_f1600_x1_v84a_aarch64_asm
|
||||
#undef mlk_keccak_f1600_x2_v84a_aarch64_asm
|
||||
#undef mlk_keccak_f1600_x4_v8a_scalar_hybrid_aarch64_asm
|
||||
#undef mlk_keccak_f1600_x4_v8a_v84a_scalar_hybrid_aarch64_asm
|
||||
#undef mlk_keccakf1600_round_constants
|
||||
/* mlkem/src/fips202/native/aarch64/x1_scalar.h */
|
||||
#undef MLK_FIPS202_AARCH64_NEED_X1_SCALAR
|
||||
#undef MLK_FIPS202_NATIVE_AARCH64_X1_SCALAR_H
|
||||
#undef MLK_USE_FIPS202_X1_NATIVE
|
||||
/* mlkem/src/fips202/native/aarch64/x1_v84a.h */
|
||||
#undef MLK_FIPS202_AARCH64_NEED_X1_V84A
|
||||
#undef MLK_FIPS202_NATIVE_AARCH64_X1_V84A_H
|
||||
#undef MLK_USE_FIPS202_X1_NATIVE
|
||||
/* mlkem/src/fips202/native/aarch64/x2_v84a.h */
|
||||
#undef MLK_FIPS202_AARCH64_NEED_X2_V84A
|
||||
#undef MLK_FIPS202_NATIVE_AARCH64_X2_V84A_H
|
||||
#undef MLK_USE_FIPS202_X4_NATIVE
|
||||
/* mlkem/src/fips202/native/aarch64/x4_v8a_scalar.h */
|
||||
#undef MLK_FIPS202_AARCH64_NEED_X4_V8A_SCALAR_HYBRID
|
||||
#undef MLK_FIPS202_NATIVE_AARCH64_X4_V8A_SCALAR_H
|
||||
#undef MLK_USE_FIPS202_X4_NATIVE
|
||||
/* mlkem/src/fips202/native/aarch64/x4_v8a_v84a_scalar.h */
|
||||
#undef MLK_FIPS202_AARCH64_NEED_X4_V8A_V84A_SCALAR_HYBRID
|
||||
#undef MLK_FIPS202_NATIVE_AARCH64_X4_V8A_V84A_SCALAR_H
|
||||
#undef MLK_USE_FIPS202_X4_NATIVE
|
||||
#endif /* MLK_SYS_AARCH64 */
|
||||
#if defined(MLK_SYS_X86_64)
|
||||
/*
|
||||
* Undefine macros from native code (FIPS202, x86_64)
|
||||
*/
|
||||
/* mlkem/src/fips202/native/x86_64/keccak_f1600_x4_avx2.h */
|
||||
#undef MLK_FIPS202_NATIVE_X86_64_KECCAK_F1600_X4_AVX2_H
|
||||
#undef MLK_FIPS202_X86_64_NEED_X4_AVX2
|
||||
#undef MLK_USE_FIPS202_X4_NATIVE
|
||||
/* mlkem/src/fips202/native/x86_64/src/fips202_native_x86_64.h */
|
||||
#undef MLK_FIPS202_NATIVE_X86_64_SRC_FIPS202_NATIVE_X86_64_H
|
||||
#undef mlk_keccak_f1600_x4_avx2_asm
|
||||
#undef mlk_keccak_rho56
|
||||
#undef mlk_keccak_rho8
|
||||
#undef mlk_keccakf1600_round_constants
|
||||
#endif /* MLK_SYS_X86_64 */
|
||||
#if defined(MLK_SYS_ARMV81M_MVE)
|
||||
/*
|
||||
* Undefine macros from native code (FIPS202, Armv8.1-M)
|
||||
*/
|
||||
/* mlkem/src/fips202/native/armv81m/mve.h */
|
||||
#undef MLK_FIPS202_ARMV81M_NEED_X4
|
||||
#undef MLK_FIPS202_NATIVE_ARMV81M
|
||||
#undef MLK_FIPS202_NATIVE_ARMV81M_MVE_H
|
||||
#undef MLK_USE_FIPS202_X4_EXTRACT_BYTES_NATIVE
|
||||
#undef MLK_USE_FIPS202_X4_NATIVE
|
||||
#undef MLK_USE_FIPS202_X4_XOR_BYTES_NATIVE
|
||||
#undef mlk_keccak_f1600_x4_native_impl
|
||||
/* mlkem/src/fips202/native/armv81m/src/fips202_native_armv81m.h */
|
||||
#undef MLK_FIPS202_NATIVE_ARMV81M_SRC_FIPS202_NATIVE_ARMV81M_H
|
||||
#undef mlk_keccak_f1600_x4_mve_asm
|
||||
#undef mlk_keccak_f1600_x4_state_extract_bytes_asm
|
||||
#undef mlk_keccak_f1600_x4_state_xor_bytes_asm
|
||||
#undef mlk_keccakf1600_round_constants
|
||||
#endif /* MLK_SYS_ARMV81M_MVE */
|
||||
#endif /* MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202 */
|
||||
#if defined(MLK_CONFIG_USE_NATIVE_BACKEND_ARITH)
|
||||
/* mlkem/src/native/api.h */
|
||||
#undef MLK_INVNTT_BOUND
|
||||
#undef MLK_NATIVE_API_H
|
||||
#undef MLK_NATIVE_FUNC_FALLBACK
|
||||
#undef MLK_NATIVE_FUNC_SUCCESS
|
||||
#undef MLK_NTT_BOUND
|
||||
/* mlkem/src/native/meta.h */
|
||||
#undef MLK_NATIVE_META_H
|
||||
#if defined(MLK_SYS_AARCH64)
|
||||
/*
|
||||
* Undefine macros from native code (Arith, AArch64)
|
||||
*/
|
||||
/* mlkem/src/native/aarch64/meta.h */
|
||||
#undef MLK_ARITH_BACKEND_AARCH64
|
||||
#undef MLK_NATIVE_AARCH64_META_H
|
||||
#undef MLK_USE_NATIVE_INTT
|
||||
#undef MLK_USE_NATIVE_NTT
|
||||
#undef MLK_USE_NATIVE_POLYVEC_BASEMUL_ACC_MONTGOMERY_CACHED
|
||||
#undef MLK_USE_NATIVE_POLY_MULCACHE_COMPUTE
|
||||
#undef MLK_USE_NATIVE_POLY_REDUCE
|
||||
#undef MLK_USE_NATIVE_POLY_TOBYTES
|
||||
#undef MLK_USE_NATIVE_POLY_TOMONT
|
||||
#undef MLK_USE_NATIVE_REJ_UNIFORM
|
||||
/* mlkem/src/native/aarch64/src/arith_native_aarch64.h */
|
||||
#undef MLK_NATIVE_AARCH64_SRC_ARITH_NATIVE_AARCH64_H
|
||||
#undef mlk_aarch64_invntt_zetas_layer12345
|
||||
#undef mlk_aarch64_invntt_zetas_layer67
|
||||
#undef mlk_aarch64_ntt_zetas_layer12345
|
||||
#undef mlk_aarch64_ntt_zetas_layer67
|
||||
#undef mlk_aarch64_zetas_mulcache_native
|
||||
#undef mlk_aarch64_zetas_mulcache_twisted_native
|
||||
#undef mlk_intt_aarch64_asm
|
||||
#undef mlk_ntt_aarch64_asm
|
||||
#undef mlk_poly_mulcache_compute_aarch64_asm
|
||||
#undef mlk_poly_reduce_aarch64_asm
|
||||
#undef mlk_poly_tobytes_aarch64_asm
|
||||
#undef mlk_poly_tomont_aarch64_asm
|
||||
#undef mlk_polyvec_basemul_acc_montgomery_cached_k2_aarch64_asm
|
||||
#undef mlk_polyvec_basemul_acc_montgomery_cached_k3_aarch64_asm
|
||||
#undef mlk_polyvec_basemul_acc_montgomery_cached_k4_aarch64_asm
|
||||
#undef mlk_rej_uniform_aarch64_asm
|
||||
#undef mlk_rej_uniform_table
|
||||
#endif /* MLK_SYS_AARCH64 */
|
||||
#if defined(MLK_SYS_X86_64)
|
||||
/*
|
||||
* Undefine macros from native code (Arith, X86_64)
|
||||
*/
|
||||
/* mlkem/src/native/x86_64/meta.h */
|
||||
#undef MLK_ARITH_BACKEND_X86_64_DEFAULT
|
||||
#undef MLK_NATIVE_X86_64_META_H
|
||||
#undef MLK_USE_NATIVE_INTT
|
||||
#undef MLK_USE_NATIVE_NTT
|
||||
#undef MLK_USE_NATIVE_NTT_CUSTOM_ORDER
|
||||
#undef MLK_USE_NATIVE_POLYVEC_BASEMUL_ACC_MONTGOMERY_CACHED
|
||||
#undef MLK_USE_NATIVE_POLY_COMPRESS_D10
|
||||
#undef MLK_USE_NATIVE_POLY_COMPRESS_D11
|
||||
#undef MLK_USE_NATIVE_POLY_COMPRESS_D4
|
||||
#undef MLK_USE_NATIVE_POLY_COMPRESS_D5
|
||||
#undef MLK_USE_NATIVE_POLY_DECOMPRESS_D10
|
||||
#undef MLK_USE_NATIVE_POLY_DECOMPRESS_D11
|
||||
#undef MLK_USE_NATIVE_POLY_DECOMPRESS_D4
|
||||
#undef MLK_USE_NATIVE_POLY_DECOMPRESS_D5
|
||||
#undef MLK_USE_NATIVE_POLY_FROMBYTES
|
||||
#undef MLK_USE_NATIVE_POLY_MULCACHE_COMPUTE
|
||||
#undef MLK_USE_NATIVE_POLY_REDUCE
|
||||
#undef MLK_USE_NATIVE_POLY_TOBYTES
|
||||
#undef MLK_USE_NATIVE_POLY_TOMONT
|
||||
#undef MLK_USE_NATIVE_REJ_UNIFORM
|
||||
/* mlkem/src/native/x86_64/src/arith_native_x86_64.h */
|
||||
#undef MLK_AVX2_REJ_UNIFORM_BUFLEN
|
||||
#undef MLK_NATIVE_X86_64_SRC_ARITH_NATIVE_X86_64_H
|
||||
#undef mlk_invntt_avx2_asm
|
||||
#undef mlk_ntt_avx2_asm
|
||||
#undef mlk_nttfrombytes_avx2_asm
|
||||
#undef mlk_ntttobytes_avx2_asm
|
||||
#undef mlk_nttunpack_avx2_asm
|
||||
#undef mlk_poly_compress_d10_avx2_asm
|
||||
#undef mlk_poly_compress_d11_avx2_asm
|
||||
#undef mlk_poly_compress_d4_avx2_asm
|
||||
#undef mlk_poly_compress_d5_avx2_asm
|
||||
#undef mlk_poly_decompress_d10_avx2_asm
|
||||
#undef mlk_poly_decompress_d11_avx2_asm
|
||||
#undef mlk_poly_decompress_d4_avx2_asm
|
||||
#undef mlk_poly_decompress_d5_avx2_asm
|
||||
#undef mlk_poly_mulcache_compute_avx2_asm
|
||||
#undef mlk_polyvec_basemul_acc_montgomery_cached_k2_avx2_asm
|
||||
#undef mlk_polyvec_basemul_acc_montgomery_cached_k3_avx2_asm
|
||||
#undef mlk_polyvec_basemul_acc_montgomery_cached_k4_avx2_asm
|
||||
#undef mlk_reduce_avx2_asm
|
||||
#undef mlk_rej_uniform_avx2_asm
|
||||
#undef mlk_rej_uniform_table
|
||||
#undef mlk_tomont_avx2_asm
|
||||
/* mlkem/src/native/x86_64/src/compress_consts.h */
|
||||
#undef MLK_NATIVE_X86_64_SRC_COMPRESS_CONSTS_H
|
||||
#undef mlk_compress_d10_data
|
||||
#undef mlk_compress_d11_data
|
||||
#undef mlk_compress_d4_data
|
||||
#undef mlk_compress_d5_data
|
||||
#undef mlk_decompress_d10_data
|
||||
#undef mlk_decompress_d11_data
|
||||
#undef mlk_decompress_d4_data
|
||||
#undef mlk_decompress_d5_data
|
||||
/* mlkem/src/native/x86_64/src/consts.h */
|
||||
#undef MLK_AVX2_BACKEND_DATA_OFFSET_MULCACHE_TWIDDLES
|
||||
#undef MLK_AVX2_BACKEND_DATA_OFFSET_REVIDXB
|
||||
#undef MLK_AVX2_BACKEND_DATA_OFFSET_REVIDXD
|
||||
#undef MLK_AVX2_BACKEND_DATA_OFFSET_ZETAS_EXP
|
||||
#undef MLK_NATIVE_X86_64_SRC_CONSTS_H
|
||||
#undef mlk_qdata
|
||||
#endif /* MLK_SYS_X86_64 */
|
||||
#if defined(MLK_SYS_RISCV64)
|
||||
/*
|
||||
* Undefine macros from native code (Arith, RISC-V 64)
|
||||
*/
|
||||
/* mlkem/src/native/riscv64/meta.h */
|
||||
#undef MLK_ARITH_BACKEND_RISCV64
|
||||
#undef MLK_NATIVE_RISCV64_META_H
|
||||
#undef MLK_USE_NATIVE_INTT
|
||||
#undef MLK_USE_NATIVE_NTT
|
||||
#undef MLK_USE_NATIVE_POLYVEC_BASEMUL_ACC_MONTGOMERY_CACHED
|
||||
#undef MLK_USE_NATIVE_POLY_MULCACHE_COMPUTE
|
||||
#undef MLK_USE_NATIVE_POLY_REDUCE
|
||||
#undef MLK_USE_NATIVE_POLY_TOMONT
|
||||
#undef MLK_USE_NATIVE_REJ_UNIFORM
|
||||
/* mlkem/src/native/riscv64/src/arith_native_riscv64.h */
|
||||
#undef MLK_NATIVE_RISCV64_SRC_ARITH_NATIVE_RISCV64_H
|
||||
#undef mlk_rv64v_poly_add
|
||||
#undef mlk_rv64v_poly_basemul_mont_add_k2
|
||||
#undef mlk_rv64v_poly_basemul_mont_add_k3
|
||||
#undef mlk_rv64v_poly_basemul_mont_add_k4
|
||||
#undef mlk_rv64v_poly_invntt_tomont
|
||||
#undef mlk_rv64v_poly_ntt
|
||||
#undef mlk_rv64v_poly_reduce
|
||||
#undef mlk_rv64v_poly_sub
|
||||
#undef mlk_rv64v_poly_tomont
|
||||
#undef mlk_rv64v_rej_uniform
|
||||
/* mlkem/src/native/riscv64/src/rv64v_debug.h */
|
||||
#undef MLK_NATIVE_RISCV64_SRC_RV64V_DEBUG_H
|
||||
#undef mlk_assert_abs_bound_int16m1
|
||||
#undef mlk_assert_abs_bound_int16m2
|
||||
#undef mlk_assert_bound_int16m1
|
||||
#undef mlk_assert_bound_int16m2
|
||||
#undef mlk_debug_check_bounds_int16m1
|
||||
#undef mlk_debug_check_bounds_int16m2
|
||||
#endif /* MLK_SYS_RISCV64 */
|
||||
#if defined(MLK_SYS_PPC64LE)
|
||||
/*
|
||||
* Undefine macros from native code (Arith, PPC64LE)
|
||||
*/
|
||||
/* mlkem/src/native/ppc64le/meta.h */
|
||||
#undef MLK_ARITH_BACKEND_NAME
|
||||
#undef MLK_ARITH_BACKEND_PPC64LE_DEFAULT
|
||||
#undef MLK_NATIVE_PPC64LE_META_H
|
||||
#undef MLK_USE_NATIVE_INTT
|
||||
#undef MLK_USE_NATIVE_NTT
|
||||
#undef MLK_USE_NATIVE_POLY_REDUCE
|
||||
#undef MLK_USE_NATIVE_POLY_TOMONT
|
||||
/* mlkem/src/native/ppc64le/src/arith_native_ppc64le.h */
|
||||
#undef MLK_NATIVE_PPC64LE_SRC_ARITH_NATIVE_PPC64LE_H
|
||||
#undef mlk_intt_ppc_asm
|
||||
#undef mlk_ntt_ppc_asm
|
||||
#undef mlk_poly_tomont_ppc_asm
|
||||
#undef mlk_reduce_ppc_asm
|
||||
/* mlkem/src/native/ppc64le/src/consts.h */
|
||||
#undef MLK_NATIVE_PPC64LE_SRC_CONSTS_H
|
||||
#undef MLK_PPC_C20159_OFFSET
|
||||
#undef MLK_PPC_NQ_OFFSET
|
||||
#undef MLK_PPC_N_INV_OFFSET
|
||||
#undef MLK_PPC_N_INV_TW_OFFSET
|
||||
#undef MLK_PPC_Q_OFFSET
|
||||
#undef MLK_PPC_TOMONT_OFFSET
|
||||
#undef MLK_PPC_TOMONT_TW_OFFSET
|
||||
#undef MLK_PPC_ZETA_INTT_OFFSET
|
||||
#undef MLK_PPC_ZETA_INTT_TW_OFFSET
|
||||
#undef MLK_PPC_ZETA_NTT_OFFSET
|
||||
#undef MLK_PPC_ZETA_NTT_TW_OFFSET
|
||||
#undef mlk_ppc_qdata
|
||||
#endif /* MLK_SYS_PPC64LE */
|
||||
#endif /* MLK_CONFIG_USE_NATIVE_BACKEND_ARITH */
|
||||
#endif /* !MLK_CONFIG_MONOBUILD_KEEP_SHARED_HEADERS */
|
||||
@@ -1,527 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
|
||||
/* References
|
||||
* ==========
|
||||
*
|
||||
* - [FIPS203]
|
||||
* FIPS 203 Module-Lattice-Based Key-Encapsulation Mechanism Standard
|
||||
* National Institute of Standards and Technology
|
||||
* https://csrc.nist.gov/pubs/fips/203/final
|
||||
*/
|
||||
|
||||
#ifndef MLK_H
|
||||
#define MLK_H
|
||||
|
||||
/*
|
||||
* Public API for mlkem-native.
|
||||
*
|
||||
* This header defines the public API of a single build of mlkem-native.
|
||||
*
|
||||
* Make sure the configuration file is in the include path
|
||||
* (this is "mlkem_native_config.h" by default, or MLK_CONFIG_FILE if defined).
|
||||
*
|
||||
* # Multi-level builds
|
||||
*
|
||||
* This header specifies a build of mlkem-native for a fixed security level.
|
||||
* If you need multiple security levels, leave the security level unspecified
|
||||
* in the configuration file and include this header multiple times, setting
|
||||
* MLK_CONFIG_PARAMETER_SET accordingly for each, and #undef'ing the MLK_H
|
||||
* guard to allow multiple inclusions.
|
||||
*
|
||||
* # Legacy configuration (deprecated)
|
||||
*
|
||||
* Instead of providing the config file used for the build, you can
|
||||
* alternatively set the following configuration options prior to
|
||||
* including this header.
|
||||
*
|
||||
* This method of configuration is deprecated.
|
||||
* It will be removed in mlkem-native-v2.
|
||||
*
|
||||
* - MLK_CONFIG_API_PARAMETER_SET [required]
|
||||
*
|
||||
* The parameter set used for the build; 512, 768, or 1024.
|
||||
*
|
||||
* - MLK_CONFIG_API_NAMESPACE_PREFIX [required]
|
||||
*
|
||||
* The namespace prefix used for the build.
|
||||
*
|
||||
* NOTE:
|
||||
* For a multi-level build, you must include the 512/768/1024 suffixes
|
||||
* in MLK_CONFIG_API_NAMESPACE_PREFIX.
|
||||
*
|
||||
* - MLK_CONFIG_API_NO_SUPERCOP [optional]
|
||||
*
|
||||
* By default, this header will also expose the mlkem-native API in the
|
||||
* SUPERCOP naming convention crypto_kem_xxx. If you don't want/need this,
|
||||
* set MLK_CONFIG_API_NO_SUPERCOP. You must set this for a multi-level build.
|
||||
*
|
||||
* - MLK_CONFIG_API_CONSTANTS_ONLY [optional]
|
||||
*
|
||||
* If you don't want this header to expose any function declarations,
|
||||
* but only constants for the sizes of key material, set
|
||||
* MLK_CONFIG_API_CONSTANTS_ONLY. In this case, you don't need to set
|
||||
* MLK_CONFIG_API_PARAMETER_SET or MLK_CONFIG_API_NAMESPACE_PREFIX,
|
||||
* nor include a configuration.
|
||||
*
|
||||
* - MLK_CONFIG_API_QUALIFIER [optional]
|
||||
*
|
||||
* Qualifier to apply to external API.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************* Key sizes ************************************/
|
||||
|
||||
/* Sizes of cryptographic material, per parameter set */
|
||||
/* See mlkem/common.h for the arithmetic expressions giving rise to these */
|
||||
/* check-magic: off */
|
||||
#define MLKEM512_SECRETKEYBYTES 1632
|
||||
#define MLKEM512_PUBLICKEYBYTES 800
|
||||
#define MLKEM512_CIPHERTEXTBYTES 768
|
||||
|
||||
#define MLKEM768_SECRETKEYBYTES 2400
|
||||
#define MLKEM768_PUBLICKEYBYTES 1184
|
||||
#define MLKEM768_CIPHERTEXTBYTES 1088
|
||||
|
||||
#define MLKEM1024_SECRETKEYBYTES 3168
|
||||
#define MLKEM1024_PUBLICKEYBYTES 1568
|
||||
#define MLKEM1024_CIPHERTEXTBYTES 1568
|
||||
/* check-magic: on */
|
||||
|
||||
/* Size of randomness coins in bytes (level-independent) */
|
||||
#define MLKEM_SYMBYTES 32
|
||||
#define MLKEM512_SYMBYTES MLKEM_SYMBYTES
|
||||
#define MLKEM768_SYMBYTES MLKEM_SYMBYTES
|
||||
#define MLKEM1024_SYMBYTES MLKEM_SYMBYTES
|
||||
/* Size of shared secret in bytes (level-independent) */
|
||||
#define MLKEM_BYTES 32
|
||||
#define MLKEM512_BYTES MLKEM_BYTES
|
||||
#define MLKEM768_BYTES MLKEM_BYTES
|
||||
#define MLKEM1024_BYTES MLKEM_BYTES
|
||||
|
||||
/* Sizes of cryptographic material, as a function of LVL=512,768,1024 */
|
||||
#define MLKEM_SECRETKEYBYTES_(LVL) MLKEM##LVL##_SECRETKEYBYTES
|
||||
#define MLKEM_PUBLICKEYBYTES_(LVL) MLKEM##LVL##_PUBLICKEYBYTES
|
||||
#define MLKEM_CIPHERTEXTBYTES_(LVL) MLKEM##LVL##_CIPHERTEXTBYTES
|
||||
#define MLKEM_SECRETKEYBYTES(LVL) MLKEM_SECRETKEYBYTES_(LVL)
|
||||
#define MLKEM_PUBLICKEYBYTES(LVL) MLKEM_PUBLICKEYBYTES_(LVL)
|
||||
#define MLKEM_CIPHERTEXTBYTES(LVL) MLKEM_CIPHERTEXTBYTES_(LVL)
|
||||
|
||||
/****************************** Error codes ***********************************/
|
||||
|
||||
/* Generic failure condition */
|
||||
#define MLK_ERR_FAIL (-1)
|
||||
/* An allocation failed. This can only happen if MLK_CONFIG_CUSTOM_ALLOC_FREE
|
||||
* is defined and the provided MLK_CUSTOM_ALLOC can fail. */
|
||||
#define MLK_ERR_OUT_OF_MEMORY (-2)
|
||||
/* An rng failure occured. Might be due to insufficient entropy or
|
||||
* system misconfiguration. */
|
||||
#define MLK_ERR_RNG_FAIL (-3)
|
||||
|
||||
/****************************** Function API **********************************/
|
||||
|
||||
#define MLK_API_CONCAT_(x, y) x##y
|
||||
#define MLK_API_CONCAT(x, y) MLK_API_CONCAT_(x, y)
|
||||
#define MLK_API_CONCAT_UNDERSCORE(x, y) MLK_API_CONCAT(MLK_API_CONCAT(x, _), y)
|
||||
|
||||
#if !defined(MLK_CONFIG_API_PARAMETER_SET)
|
||||
/* Recommended configuration via same config file as used for the build. */
|
||||
|
||||
/* For now, we derive the legacy API configuration MLK_CONFIG_API_XXX from
|
||||
* the config file. In mlkem-native-v2, this will be removed and we will
|
||||
* exclusively work with MLK_CONFIG_XXX. */
|
||||
|
||||
/* You need to make sure the config file is in the include path. */
|
||||
#if defined(MLK_CONFIG_FILE)
|
||||
#include MLK_CONFIG_FILE
|
||||
#else
|
||||
#include "mlkem_native_config.h"
|
||||
#endif
|
||||
|
||||
#define MLK_CONFIG_API_PARAMETER_SET MLK_CONFIG_PARAMETER_SET
|
||||
|
||||
#if defined(MLK_CONFIG_MULTILEVEL_BUILD)
|
||||
#define MLK_CONFIG_API_NAMESPACE_PREFIX \
|
||||
MLK_API_CONCAT(MLK_CONFIG_NAMESPACE_PREFIX, MLK_CONFIG_PARAMETER_SET)
|
||||
#else
|
||||
#define MLK_CONFIG_API_NAMESPACE_PREFIX MLK_CONFIG_NAMESPACE_PREFIX
|
||||
#endif
|
||||
|
||||
#if defined(MLK_CONFIG_NO_SUPERCOP)
|
||||
#define MLK_CONFIG_API_NO_SUPERCOP
|
||||
#endif
|
||||
|
||||
#if defined(MLK_CONFIG_CONSTANTS_ONLY)
|
||||
#define MLK_CONFIG_API_CONSTANTS_ONLY
|
||||
#endif
|
||||
|
||||
#if defined(MLK_CONFIG_EXTERNAL_API_QUALIFIER)
|
||||
#define MLK_CONFIG_API_QUALIFIER MLK_CONFIG_EXTERNAL_API_QUALIFIER
|
||||
#endif
|
||||
|
||||
#else /* !MLK_CONFIG_API_PARAMETER_SET */
|
||||
|
||||
#define MLK_API_LEGACY_CONFIG
|
||||
|
||||
#endif /* MLK_CONFIG_API_PARAMETER_SET */
|
||||
|
||||
#define MLK_API_NAMESPACE(sym) \
|
||||
MLK_API_CONCAT_UNDERSCORE(MLK_CONFIG_API_NAMESPACE_PREFIX, sym)
|
||||
|
||||
#if defined(__GNUC__) || defined(__clang__)
|
||||
#define MLK_API_MUST_CHECK_RETURN_VALUE __attribute__((warn_unused_result))
|
||||
#else
|
||||
#define MLK_API_MUST_CHECK_RETURN_VALUE
|
||||
#endif
|
||||
|
||||
#if defined(MLK_CONFIG_API_QUALIFIER)
|
||||
#define MLK_API_QUALIFIER MLK_CONFIG_API_QUALIFIER
|
||||
#else
|
||||
#define MLK_API_QUALIFIER
|
||||
#endif
|
||||
|
||||
#if !defined(MLK_CONFIG_API_CONSTANTS_ONLY)
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Generate a public/private keypair for the ML-KEM key encapsulation mechanism.
|
||||
*
|
||||
* @spec{Implements @[FIPS203, Algorithm 16, ML-KEM.KeyGen_Internal].}
|
||||
*
|
||||
* @param[out] pk Output public key, an array of
|
||||
* MLKEM{512,768,1024}_PUBLICKEYBYTES bytes.
|
||||
* @param[out] sk Output private key, an array of
|
||||
* MLKEM{512,768,1024}_SECRETKEYBYTES bytes.
|
||||
* @param[in] coins Input randomness, an array of 2*MLKEM_SYMBYTES uniformly
|
||||
* random bytes.
|
||||
* @param context Application context. Only present when
|
||||
* MLK_CONFIG_CONTEXT_PARAMETER is defined; type set by
|
||||
* MLK_CONFIG_CONTEXT_PARAMETER_TYPE.
|
||||
*
|
||||
* @retval 0 Success.
|
||||
* @retval MLK_ERR_FAIL MLK_CONFIG_KEYGEN_PCT enabled and PCT failed.
|
||||
* @retval MLK_ERR_OUT_OF_MEMORY MLK_CONFIG_CUSTOM_ALLOC_FREE was used and
|
||||
* MLK_CUSTOM_ALLOC returned NULL.
|
||||
*/
|
||||
MLK_API_QUALIFIER
|
||||
MLK_API_MUST_CHECK_RETURN_VALUE
|
||||
int MLK_API_NAMESPACE(keypair_derand)(
|
||||
uint8_t pk[MLKEM_PUBLICKEYBYTES(MLK_CONFIG_API_PARAMETER_SET)],
|
||||
uint8_t sk[MLKEM_SECRETKEYBYTES(MLK_CONFIG_API_PARAMETER_SET)],
|
||||
const uint8_t coins[2 * MLKEM_SYMBYTES]
|
||||
#ifdef MLK_CONFIG_CONTEXT_PARAMETER
|
||||
,
|
||||
MLK_CONFIG_CONTEXT_PARAMETER_TYPE context
|
||||
#endif
|
||||
);
|
||||
|
||||
|
||||
#if !defined(MLK_CONFIG_NO_RANDOMIZED_API)
|
||||
/**
|
||||
* Generate a public/private keypair for the ML-KEM key encapsulation mechanism.
|
||||
*
|
||||
* @spec{Implements @[FIPS203, Algorithm 19, ML-KEM.KeyGen].}
|
||||
*
|
||||
* @param[out] pk Output public key, an array of
|
||||
* MLKEM{512,768,1024}_PUBLICKEYBYTES bytes.
|
||||
* @param[out] sk Output private key, an array of
|
||||
* MLKEM{512,768,1024}_SECRETKEYBYTES bytes.
|
||||
* @param context Application context. Only present when
|
||||
* MLK_CONFIG_CONTEXT_PARAMETER is defined; type set by
|
||||
* MLK_CONFIG_CONTEXT_PARAMETER_TYPE.
|
||||
*
|
||||
* @retval 0 Success.
|
||||
* @retval MLK_ERR_FAIL MLK_CONFIG_KEYGEN_PCT enabled and PCT failed.
|
||||
* @retval MLK_ERR_OUT_OF_MEMORY MLK_CONFIG_CUSTOM_ALLOC_FREE was used and
|
||||
* MLK_CUSTOM_ALLOC returned NULL.
|
||||
* @retval MLK_ERR_RNG_FAIL Random number generation failed.
|
||||
*/
|
||||
MLK_API_QUALIFIER
|
||||
MLK_API_MUST_CHECK_RETURN_VALUE
|
||||
int MLK_API_NAMESPACE(keypair)(
|
||||
uint8_t pk[MLKEM_PUBLICKEYBYTES(MLK_CONFIG_API_PARAMETER_SET)],
|
||||
uint8_t sk[MLKEM_SECRETKEYBYTES(MLK_CONFIG_API_PARAMETER_SET)]
|
||||
#ifdef MLK_CONFIG_CONTEXT_PARAMETER
|
||||
,
|
||||
MLK_CONFIG_CONTEXT_PARAMETER_TYPE context
|
||||
#endif
|
||||
);
|
||||
#endif /* !MLK_CONFIG_NO_RANDOMIZED_API */
|
||||
|
||||
/**
|
||||
* Generate ciphertext and shared secret for a given public key.
|
||||
*
|
||||
* @spec{Implements @[FIPS203, Algorithm 17, ML-KEM.Encaps_Internal].}
|
||||
*
|
||||
* @param[out] ct Output ciphertext, an array of
|
||||
* MLKEM{512,768,1024}_CIPHERTEXTBYTES bytes.
|
||||
* @param[out] ss Output shared secret, an array of MLKEM_BYTES bytes.
|
||||
* @param[in] pk Input public key, an array of
|
||||
* MLKEM{512,768,1024}_PUBLICKEYBYTES bytes.
|
||||
* @param[in] coins Input randomness, an array of MLKEM_SYMBYTES bytes.
|
||||
* @param context Application context. Only present when
|
||||
* MLK_CONFIG_CONTEXT_PARAMETER is defined; type set by
|
||||
* MLK_CONFIG_CONTEXT_PARAMETER_TYPE.
|
||||
*
|
||||
* @retval 0 Success.
|
||||
* @retval MLK_ERR_FAIL The 'modulus check' @[FIPS203, Section 7.2]
|
||||
* for the public key failed.
|
||||
* @retval MLK_ERR_OUT_OF_MEMORY MLK_CONFIG_CUSTOM_ALLOC_FREE was used and
|
||||
* MLK_CUSTOM_ALLOC returned NULL.
|
||||
*/
|
||||
MLK_API_QUALIFIER
|
||||
MLK_API_MUST_CHECK_RETURN_VALUE
|
||||
int MLK_API_NAMESPACE(enc_derand)(
|
||||
uint8_t ct[MLKEM_CIPHERTEXTBYTES(MLK_CONFIG_API_PARAMETER_SET)],
|
||||
uint8_t ss[MLKEM_BYTES],
|
||||
const uint8_t pk[MLKEM_PUBLICKEYBYTES(MLK_CONFIG_API_PARAMETER_SET)],
|
||||
const uint8_t coins[MLKEM_SYMBYTES]
|
||||
#ifdef MLK_CONFIG_CONTEXT_PARAMETER
|
||||
,
|
||||
MLK_CONFIG_CONTEXT_PARAMETER_TYPE context
|
||||
#endif
|
||||
);
|
||||
|
||||
#if !defined(MLK_CONFIG_NO_RANDOMIZED_API)
|
||||
/**
|
||||
* Generate ciphertext and shared secret for a given public key.
|
||||
*
|
||||
* @spec{Implements @[FIPS203, Algorithm 20, ML-KEM.Encaps].}
|
||||
*
|
||||
* @param[out] ct Output ciphertext, an array of
|
||||
* MLKEM{512,768,1024}_CIPHERTEXTBYTES bytes.
|
||||
* @param[out] ss Output shared secret, an array of MLKEM_BYTES bytes.
|
||||
* @param[in] pk Input public key, an array of
|
||||
* MLKEM{512,768,1024}_PUBLICKEYBYTES bytes.
|
||||
* @param context Application context. Only present when
|
||||
* MLK_CONFIG_CONTEXT_PARAMETER is defined; type set by
|
||||
* MLK_CONFIG_CONTEXT_PARAMETER_TYPE.
|
||||
*
|
||||
* @retval 0 Success.
|
||||
* @retval MLK_ERR_FAIL The 'modulus check' @[FIPS203, Section 7.2]
|
||||
* for the public key failed.
|
||||
* @retval MLK_ERR_OUT_OF_MEMORY MLK_CONFIG_CUSTOM_ALLOC_FREE was used and
|
||||
* MLK_CUSTOM_ALLOC returned NULL.
|
||||
* @retval MLK_ERR_RNG_FAIL Random number generation failed.
|
||||
*/
|
||||
MLK_API_QUALIFIER
|
||||
MLK_API_MUST_CHECK_RETURN_VALUE
|
||||
int MLK_API_NAMESPACE(enc)(
|
||||
uint8_t ct[MLKEM_CIPHERTEXTBYTES(MLK_CONFIG_API_PARAMETER_SET)],
|
||||
uint8_t ss[MLKEM_BYTES],
|
||||
const uint8_t pk[MLKEM_PUBLICKEYBYTES(MLK_CONFIG_API_PARAMETER_SET)]
|
||||
#ifdef MLK_CONFIG_CONTEXT_PARAMETER
|
||||
,
|
||||
MLK_CONFIG_CONTEXT_PARAMETER_TYPE context
|
||||
#endif
|
||||
);
|
||||
#endif /* !MLK_CONFIG_NO_RANDOMIZED_API */
|
||||
|
||||
/**
|
||||
* Generate shared secret for a given ciphertext and private key.
|
||||
*
|
||||
* @spec{Implements @[FIPS203, Algorithm 21, ML-KEM.Decaps].}
|
||||
*
|
||||
* @param[out] ss Output shared secret, an array of MLKEM_BYTES bytes.
|
||||
* @param[in] ct Input ciphertext, an array of
|
||||
* MLKEM{512,768,1024}_CIPHERTEXTBYTES bytes.
|
||||
* @param[in] sk Input private key, an array of
|
||||
* MLKEM{512,768,1024}_SECRETKEYBYTES bytes.
|
||||
* @param context Application context. Only present when
|
||||
* MLK_CONFIG_CONTEXT_PARAMETER is defined; type set by
|
||||
* MLK_CONFIG_CONTEXT_PARAMETER_TYPE.
|
||||
*
|
||||
* @retval 0 Success.
|
||||
* @retval MLK_ERR_FAIL The 'hash check' @[FIPS203, Section 7.3]
|
||||
* for the secret key failed.
|
||||
* @retval MLK_ERR_OUT_OF_MEMORY MLK_CONFIG_CUSTOM_ALLOC_FREE was used and
|
||||
* MLK_CUSTOM_ALLOC returned NULL.
|
||||
*/
|
||||
MLK_API_QUALIFIER
|
||||
MLK_API_MUST_CHECK_RETURN_VALUE
|
||||
int MLK_API_NAMESPACE(dec)(
|
||||
uint8_t ss[MLKEM_BYTES],
|
||||
const uint8_t ct[MLKEM_CIPHERTEXTBYTES(MLK_CONFIG_API_PARAMETER_SET)],
|
||||
const uint8_t sk[MLKEM_SECRETKEYBYTES(MLK_CONFIG_API_PARAMETER_SET)]
|
||||
#ifdef MLK_CONFIG_CONTEXT_PARAMETER
|
||||
,
|
||||
MLK_CONFIG_CONTEXT_PARAMETER_TYPE context
|
||||
#endif
|
||||
);
|
||||
|
||||
|
||||
/**
|
||||
* Implements modulus check mandated by FIPS 203, i.e., ensures that
|
||||
* coefficients are in [0,q-1].
|
||||
*
|
||||
* @spec{Implements @[FIPS203, Section 7.2, 'modulus check'].}
|
||||
*
|
||||
* @param[in] pk Input public key, an array of
|
||||
* MLKEM{512,768,1024}_PUBLICKEYBYTES bytes.
|
||||
* @param context Application context. Only present when
|
||||
* MLK_CONFIG_CONTEXT_PARAMETER is defined; type set by
|
||||
* MLK_CONFIG_CONTEXT_PARAMETER_TYPE.
|
||||
*
|
||||
* @retval 0 Success.
|
||||
* @retval MLK_ERR_FAIL Modulus check failed.
|
||||
* @retval MLK_ERR_OUT_OF_MEMORY MLK_CONFIG_CUSTOM_ALLOC_FREE was used and
|
||||
* MLK_CUSTOM_ALLOC returned NULL.
|
||||
*/
|
||||
MLK_API_QUALIFIER
|
||||
MLK_API_MUST_CHECK_RETURN_VALUE
|
||||
int MLK_API_NAMESPACE(check_pk)(
|
||||
const uint8_t pk[MLKEM_PUBLICKEYBYTES(MLK_CONFIG_API_PARAMETER_SET)]
|
||||
#ifdef MLK_CONFIG_CONTEXT_PARAMETER
|
||||
,
|
||||
MLK_CONFIG_CONTEXT_PARAMETER_TYPE context
|
||||
#endif
|
||||
);
|
||||
|
||||
/**
|
||||
* Implements public key hash check mandated by FIPS 203, i.e., ensures that
|
||||
* sk[768𝑘+32 ∶ 768𝑘+64] = H(pk) = H(sk[384𝑘 : 768𝑘+32]).
|
||||
*
|
||||
* @spec{Implements @[FIPS203, Section 7.3, 'hash check'].}
|
||||
*
|
||||
* @param[in] sk Input private key, an array of
|
||||
* MLKEM{512,768,1024}_SECRETKEYBYTES bytes.
|
||||
* @param context Application context. Only present when
|
||||
* MLK_CONFIG_CONTEXT_PARAMETER is defined; type set by
|
||||
* MLK_CONFIG_CONTEXT_PARAMETER_TYPE.
|
||||
*
|
||||
* @retval 0 Success.
|
||||
* @retval MLK_ERR_FAIL Public key hash check failed.
|
||||
* @retval MLK_ERR_OUT_OF_MEMORY MLK_CONFIG_CUSTOM_ALLOC_FREE was used and
|
||||
* MLK_CUSTOM_ALLOC returned NULL.
|
||||
*/
|
||||
MLK_API_QUALIFIER
|
||||
MLK_API_MUST_CHECK_RETURN_VALUE
|
||||
int MLK_API_NAMESPACE(check_sk)(
|
||||
const uint8_t sk[MLKEM_SECRETKEYBYTES(MLK_CONFIG_API_PARAMETER_SET)]
|
||||
#ifdef MLK_CONFIG_CONTEXT_PARAMETER
|
||||
,
|
||||
MLK_CONFIG_CONTEXT_PARAMETER_TYPE context
|
||||
#endif
|
||||
);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************** SUPERCOP API *********************************/
|
||||
|
||||
#if !defined(MLK_CONFIG_API_NO_SUPERCOP)
|
||||
/* Export API in SUPERCOP naming scheme CRYPTO_xxx / crypto_kem_xxx */
|
||||
#define CRYPTO_SECRETKEYBYTES MLKEM_SECRETKEYBYTES(MLK_CONFIG_API_PARAMETER_SET)
|
||||
#define CRYPTO_PUBLICKEYBYTES MLKEM_PUBLICKEYBYTES(MLK_CONFIG_API_PARAMETER_SET)
|
||||
#define CRYPTO_CIPHERTEXTBYTES \
|
||||
MLKEM_CIPHERTEXTBYTES(MLK_CONFIG_API_PARAMETER_SET)
|
||||
#define CRYPTO_SYMBYTES MLKEM_SYMBYTES
|
||||
#define CRYPTO_BYTES MLKEM_BYTES
|
||||
|
||||
#define crypto_kem_keypair_derand MLK_API_NAMESPACE(keypair_derand)
|
||||
#define crypto_kem_keypair MLK_API_NAMESPACE(keypair)
|
||||
#define crypto_kem_enc_derand MLK_API_NAMESPACE(enc_derand)
|
||||
#define crypto_kem_enc MLK_API_NAMESPACE(enc)
|
||||
#define crypto_kem_dec MLK_API_NAMESPACE(dec)
|
||||
#define crypto_kem_check_pk MLK_API_NAMESPACE(check_pk)
|
||||
#define crypto_kem_check_sk MLK_API_NAMESPACE(check_sk)
|
||||
|
||||
#else /* !MLK_CONFIG_API_NO_SUPERCOP */
|
||||
|
||||
/* If the SUPERCOP API is not needed, we can undefine the various helper macros
|
||||
* above. Otherwise, they are needed for lazy evaluation of crypto_kem_xxx. */
|
||||
#if !defined(MLK_API_LEGACY_CONFIG)
|
||||
#undef MLK_CONFIG_API_PARAMETER_SET
|
||||
#undef MLK_CONFIG_API_NAMESPACE_PREFIX
|
||||
#undef MLK_CONFIG_API_NO_SUPERCOP
|
||||
#undef MLK_CONFIG_API_CONSTANTS_ONLY
|
||||
#undef MLK_CONFIG_API_QUALIFIER
|
||||
#endif /* !MLK_API_LEGACY_CONFIG */
|
||||
|
||||
#undef MLK_API_CONCAT
|
||||
#undef MLK_API_CONCAT_
|
||||
#undef MLK_API_CONCAT_UNDERSCORE
|
||||
#undef MLK_API_NAMESPACE
|
||||
#undef MLK_API_MUST_CHECK_RETURN_VALUE
|
||||
#undef MLK_API_QUALIFIER
|
||||
|
||||
#endif /* MLK_CONFIG_API_NO_SUPERCOP */
|
||||
#endif /* !MLK_CONFIG_API_CONSTANTS_ONLY */
|
||||
|
||||
|
||||
/***************************** Memory Usage **********************************/
|
||||
|
||||
/*
|
||||
* By default mlkem-native performs all memory allocations on the stack.
|
||||
* Alternatively, mlkem-native supports custom allocation of large structures
|
||||
* through the `MLK_CONFIG_CUSTOM_ALLOC_FREE` configuration option.
|
||||
* See mlkem_native_config.h for details.
|
||||
*
|
||||
* `MLK_TOTAL_ALLOC_{512,768,1024}_{KEYPAIR,ENCAPS,DECAPS}` indicates the
|
||||
* maximum (accumulative) allocation via MLK_ALLOC for each parameter set and
|
||||
* operation. Note that some stack allocation remains even when using custom
|
||||
* allocators, so these values are lower than total stack usage with the default
|
||||
* stack-only allocation.
|
||||
*
|
||||
* These constants may be used to implement custom allocations using a
|
||||
* fixed-sized buffer and a simple allocator (e.g., bump allocator).
|
||||
*/
|
||||
/* check-magic: off */
|
||||
#define MLK_TOTAL_ALLOC_512_KEYPAIR_NO_PCT 5824
|
||||
#define MLK_TOTAL_ALLOC_512_KEYPAIR_PCT 10048
|
||||
#define MLK_TOTAL_ALLOC_512_ENCAPS 8384
|
||||
#define MLK_TOTAL_ALLOC_512_DECAPS 9152
|
||||
#define MLK_TOTAL_ALLOC_768_KEYPAIR_NO_PCT 10176
|
||||
#define MLK_TOTAL_ALLOC_768_KEYPAIR_PCT 15552
|
||||
#define MLK_TOTAL_ALLOC_768_ENCAPS 13248
|
||||
#define MLK_TOTAL_ALLOC_768_DECAPS 14336
|
||||
#define MLK_TOTAL_ALLOC_1024_KEYPAIR_NO_PCT 15552
|
||||
#define MLK_TOTAL_ALLOC_1024_KEYPAIR_PCT 22400
|
||||
#define MLK_TOTAL_ALLOC_1024_ENCAPS 19136
|
||||
#define MLK_TOTAL_ALLOC_1024_DECAPS 20704
|
||||
/* check-magic: on */
|
||||
|
||||
/*
|
||||
* MLK_TOTAL_ALLOC_*_KEYPAIR adapts based on MLK_CONFIG_KEYGEN_PCT.
|
||||
* For legacy config, we don't know which options are used, so assume
|
||||
* the worst case (PCT enabled).
|
||||
*/
|
||||
#if defined(MLK_API_LEGACY_CONFIG) || defined(MLK_CONFIG_KEYGEN_PCT)
|
||||
#define MLK_TOTAL_ALLOC_512_KEYPAIR MLK_TOTAL_ALLOC_512_KEYPAIR_PCT
|
||||
#define MLK_TOTAL_ALLOC_768_KEYPAIR MLK_TOTAL_ALLOC_768_KEYPAIR_PCT
|
||||
#define MLK_TOTAL_ALLOC_1024_KEYPAIR MLK_TOTAL_ALLOC_1024_KEYPAIR_PCT
|
||||
#else
|
||||
#define MLK_TOTAL_ALLOC_512_KEYPAIR MLK_TOTAL_ALLOC_512_KEYPAIR_NO_PCT
|
||||
#define MLK_TOTAL_ALLOC_768_KEYPAIR MLK_TOTAL_ALLOC_768_KEYPAIR_NO_PCT
|
||||
#define MLK_TOTAL_ALLOC_1024_KEYPAIR MLK_TOTAL_ALLOC_1024_KEYPAIR_NO_PCT
|
||||
#endif
|
||||
|
||||
#define MLK_MAX3_(a, b, c) \
|
||||
((a) > (b) ? ((a) > (c) ? (a) : (c)) : ((b) > (c) ? (b) : (c)))
|
||||
|
||||
/*
|
||||
* `MLK_TOTAL_ALLOC_{512,768,1024}` is the maximum across all operations for
|
||||
* each parameter set.
|
||||
*/
|
||||
#define MLK_TOTAL_ALLOC_512 \
|
||||
MLK_MAX3_(MLK_TOTAL_ALLOC_512_KEYPAIR, MLK_TOTAL_ALLOC_512_ENCAPS, \
|
||||
MLK_TOTAL_ALLOC_512_DECAPS)
|
||||
#define MLK_TOTAL_ALLOC_768 \
|
||||
MLK_MAX3_(MLK_TOTAL_ALLOC_768_KEYPAIR, MLK_TOTAL_ALLOC_768_ENCAPS, \
|
||||
MLK_TOTAL_ALLOC_768_DECAPS)
|
||||
#define MLK_TOTAL_ALLOC_1024 \
|
||||
MLK_MAX3_(MLK_TOTAL_ALLOC_1024_KEYPAIR, MLK_TOTAL_ALLOC_1024_ENCAPS, \
|
||||
MLK_TOTAL_ALLOC_1024_DECAPS)
|
||||
|
||||
#undef MLK_API_LEGACY_CONFIG
|
||||
|
||||
#endif /* !MLK_H */
|
||||
@@ -1,723 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING: This file is auto-generated from scripts/autogen
|
||||
* in the mlkem-native repository.
|
||||
* Do not modify it directly.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Single assembly unit for fixed-level build of mlkem-native
|
||||
*
|
||||
* This assembly unit bundles together all assembly files for a build
|
||||
* of mlkem-native for a fixed security level (MLKEM-512/768/1024).
|
||||
*
|
||||
* # Multi-level build
|
||||
*
|
||||
* If you want an SCU build of mlkem-native with support for multiple security
|
||||
* levels, you should include this file once with
|
||||
* MLK_CONFIG_MULTILEVEL_WITH_SHARED set.
|
||||
*
|
||||
* (You could also follow the same pattern as for mlkem_native_monobuild.c
|
||||
* and include it for every level, setting MLK_CONFIG_MULTILEVEL_NO_SHARED
|
||||
* for all but one. For builds with MLK_CONFIG_MULTILEVEL_NO_SHARED, this
|
||||
* file will then be ignored.)
|
||||
*
|
||||
* # Configuration
|
||||
*
|
||||
* The following options from the mlkem-native configuration are relevant:
|
||||
*
|
||||
* - MLK_CONFIG_FIPS202_CUSTOM_HEADER
|
||||
* Set this option if you use a custom FIPS202 implementation.
|
||||
*
|
||||
* - MLK_CONFIG_USE_NATIVE_BACKEND_ARITH
|
||||
* Set this option if you want to include the native arithmetic backends
|
||||
* in your build.
|
||||
*
|
||||
* - MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202
|
||||
* Set this option if you want to include the native FIPS202 backends
|
||||
* in your build.
|
||||
*
|
||||
* - MLK_CONFIG_MONOBUILD_KEEP_SHARED_HEADERS
|
||||
* Set this option if you want to keep the directives defined in
|
||||
* level-independent headers. This is needed for a multi-level build.
|
||||
*/
|
||||
|
||||
/* If parts of the mlkem-native source tree are not used,
|
||||
* consider reducing this header via `unifdef`.
|
||||
*
|
||||
* Example:
|
||||
* ```bash
|
||||
* unifdef -UMLK_CONFIG_USE_NATIVE_BACKEND_ARITH mlkem_native_asm.S
|
||||
* ```
|
||||
*/
|
||||
|
||||
#include "src/common.h"
|
||||
|
||||
#if defined(MLK_CONFIG_USE_NATIVE_BACKEND_ARITH)
|
||||
#if defined(MLK_SYS_AARCH64)
|
||||
#include "src/native/aarch64/src/intt_aarch64_asm.S"
|
||||
#include "src/native/aarch64/src/ntt_aarch64_asm.S"
|
||||
#include "src/native/aarch64/src/poly_mulcache_compute_aarch64_asm.S"
|
||||
#include "src/native/aarch64/src/poly_reduce_aarch64_asm.S"
|
||||
#include "src/native/aarch64/src/poly_tobytes_aarch64_asm.S"
|
||||
#include "src/native/aarch64/src/poly_tomont_aarch64_asm.S"
|
||||
#include "src/native/aarch64/src/polyvec_basemul_acc_montgomery_cached_k2_aarch64_asm.S"
|
||||
#include "src/native/aarch64/src/polyvec_basemul_acc_montgomery_cached_k3_aarch64_asm.S"
|
||||
#include "src/native/aarch64/src/polyvec_basemul_acc_montgomery_cached_k4_aarch64_asm.S"
|
||||
#include "src/native/aarch64/src/rej_uniform_aarch64_asm.S"
|
||||
#endif /* MLK_SYS_AARCH64 */
|
||||
#if defined(MLK_SYS_X86_64)
|
||||
#include "src/native/x86_64/src/intt_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/ntt_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/nttfrombytes_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/ntttobytes_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/nttunpack_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/poly_compress_d10_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/poly_compress_d11_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/poly_compress_d4_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/poly_compress_d5_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/poly_decompress_d10_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/poly_decompress_d11_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/poly_decompress_d4_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/poly_decompress_d5_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/poly_mulcache_compute_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/polyvec_basemul_acc_montgomery_cached_k2_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/polyvec_basemul_acc_montgomery_cached_k3_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/polyvec_basemul_acc_montgomery_cached_k4_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/reduce_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/rej_uniform_avx2_asm.S"
|
||||
#include "src/native/x86_64/src/tomont_avx2_asm.S"
|
||||
#endif /* MLK_SYS_X86_64 */
|
||||
#if defined(MLK_SYS_RISCV64)
|
||||
#endif
|
||||
#if defined(MLK_SYS_PPC64LE)
|
||||
#include "src/native/ppc64le/src/intt_ppc_asm.S"
|
||||
#include "src/native/ppc64le/src/ntt_ppc_asm.S"
|
||||
#include "src/native/ppc64le/src/poly_tomont_ppc_asm.S"
|
||||
#include "src/native/ppc64le/src/reduce_ppc_asm.S"
|
||||
#endif /* MLK_SYS_PPC64LE */
|
||||
#endif /* MLK_CONFIG_USE_NATIVE_BACKEND_ARITH */
|
||||
|
||||
#if defined(MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202)
|
||||
#if defined(MLK_SYS_AARCH64)
|
||||
#include "src/fips202/native/aarch64/src/keccak_f1600_x1_scalar_aarch64_asm.S"
|
||||
#include "src/fips202/native/aarch64/src/keccak_f1600_x1_v84a_aarch64_asm.S"
|
||||
#include "src/fips202/native/aarch64/src/keccak_f1600_x2_v84a_aarch64_asm.S"
|
||||
#include "src/fips202/native/aarch64/src/keccak_f1600_x4_v8a_scalar_hybrid_aarch64_asm.S"
|
||||
#include "src/fips202/native/aarch64/src/keccak_f1600_x4_v8a_v84a_scalar_hybrid_aarch64_asm.S"
|
||||
#endif /* MLK_SYS_AARCH64 */
|
||||
#if defined(MLK_SYS_X86_64)
|
||||
#include "src/fips202/native/x86_64/src/keccak_f1600_x4_avx2_asm.S"
|
||||
#endif
|
||||
#if defined(MLK_SYS_ARMV81M_MVE)
|
||||
#include "src/fips202/native/armv81m/src/keccak_f1600_x4_mve.S"
|
||||
#include "src/fips202/native/armv81m/src/state_extract_bytes_x4_mve.S"
|
||||
#include "src/fips202/native/armv81m/src/state_xor_bytes_x4_mve.S"
|
||||
#endif
|
||||
#endif /* MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202 */
|
||||
|
||||
|
||||
/* Macro #undef's
|
||||
*
|
||||
* The following undefines macros from headers
|
||||
* included by the source files imported above.
|
||||
*
|
||||
* This is to allow building and linking multiple builds
|
||||
* of mlkem-native for varying parameter sets through concatenation
|
||||
* of this file, as if the files had been compiled separately.
|
||||
* If this is not relevant to you, you may remove the following.
|
||||
*
|
||||
* NOTE: This is not needed for the assembly SCU since, at present,
|
||||
* there is no need to include it multiple times.
|
||||
* We keep it for uniformity with mlkem_native.c only.
|
||||
*
|
||||
* NOTE: To avoid having to distinguish between which headers are included
|
||||
* from the assembly files, we #undef the same set of directives
|
||||
* as in mlkem_native.c
|
||||
*/
|
||||
|
||||
/*
|
||||
* Undefine macros from MLK_CONFIG_PARAMETER_SET-specific files
|
||||
*/
|
||||
/* mlkem/mlkem_native.h */
|
||||
#undef CRYPTO_BYTES
|
||||
#undef CRYPTO_CIPHERTEXTBYTES
|
||||
#undef CRYPTO_PUBLICKEYBYTES
|
||||
#undef CRYPTO_SECRETKEYBYTES
|
||||
#undef CRYPTO_SYMBYTES
|
||||
#undef MLKEM1024_BYTES
|
||||
#undef MLKEM1024_CIPHERTEXTBYTES
|
||||
#undef MLKEM1024_PUBLICKEYBYTES
|
||||
#undef MLKEM1024_SECRETKEYBYTES
|
||||
#undef MLKEM1024_SYMBYTES
|
||||
#undef MLKEM512_BYTES
|
||||
#undef MLKEM512_CIPHERTEXTBYTES
|
||||
#undef MLKEM512_PUBLICKEYBYTES
|
||||
#undef MLKEM512_SECRETKEYBYTES
|
||||
#undef MLKEM512_SYMBYTES
|
||||
#undef MLKEM768_BYTES
|
||||
#undef MLKEM768_CIPHERTEXTBYTES
|
||||
#undef MLKEM768_PUBLICKEYBYTES
|
||||
#undef MLKEM768_SECRETKEYBYTES
|
||||
#undef MLKEM768_SYMBYTES
|
||||
#undef MLKEM_BYTES
|
||||
#undef MLKEM_CIPHERTEXTBYTES
|
||||
#undef MLKEM_CIPHERTEXTBYTES_
|
||||
#undef MLKEM_PUBLICKEYBYTES
|
||||
#undef MLKEM_PUBLICKEYBYTES_
|
||||
#undef MLKEM_SECRETKEYBYTES
|
||||
#undef MLKEM_SECRETKEYBYTES_
|
||||
#undef MLKEM_SYMBYTES
|
||||
#undef MLK_API_CONCAT
|
||||
#undef MLK_API_CONCAT_
|
||||
#undef MLK_API_CONCAT_UNDERSCORE
|
||||
#undef MLK_API_LEGACY_CONFIG
|
||||
#undef MLK_API_MUST_CHECK_RETURN_VALUE
|
||||
#undef MLK_API_NAMESPACE
|
||||
#undef MLK_API_QUALIFIER
|
||||
#undef MLK_CONFIG_API_CONSTANTS_ONLY
|
||||
#undef MLK_CONFIG_API_NAMESPACE_PREFIX
|
||||
#undef MLK_CONFIG_API_NO_SUPERCOP
|
||||
#undef MLK_CONFIG_API_PARAMETER_SET
|
||||
#undef MLK_CONFIG_API_QUALIFIER
|
||||
#undef MLK_ERR_FAIL
|
||||
#undef MLK_ERR_OUT_OF_MEMORY
|
||||
#undef MLK_ERR_RNG_FAIL
|
||||
#undef MLK_H
|
||||
#undef MLK_MAX3_
|
||||
#undef MLK_TOTAL_ALLOC_1024
|
||||
#undef MLK_TOTAL_ALLOC_1024_DECAPS
|
||||
#undef MLK_TOTAL_ALLOC_1024_ENCAPS
|
||||
#undef MLK_TOTAL_ALLOC_1024_KEYPAIR
|
||||
#undef MLK_TOTAL_ALLOC_1024_KEYPAIR_NO_PCT
|
||||
#undef MLK_TOTAL_ALLOC_1024_KEYPAIR_PCT
|
||||
#undef MLK_TOTAL_ALLOC_512
|
||||
#undef MLK_TOTAL_ALLOC_512_DECAPS
|
||||
#undef MLK_TOTAL_ALLOC_512_ENCAPS
|
||||
#undef MLK_TOTAL_ALLOC_512_KEYPAIR
|
||||
#undef MLK_TOTAL_ALLOC_512_KEYPAIR_NO_PCT
|
||||
#undef MLK_TOTAL_ALLOC_512_KEYPAIR_PCT
|
||||
#undef MLK_TOTAL_ALLOC_768
|
||||
#undef MLK_TOTAL_ALLOC_768_DECAPS
|
||||
#undef MLK_TOTAL_ALLOC_768_ENCAPS
|
||||
#undef MLK_TOTAL_ALLOC_768_KEYPAIR
|
||||
#undef MLK_TOTAL_ALLOC_768_KEYPAIR_NO_PCT
|
||||
#undef MLK_TOTAL_ALLOC_768_KEYPAIR_PCT
|
||||
#undef crypto_kem_check_pk
|
||||
#undef crypto_kem_check_sk
|
||||
#undef crypto_kem_dec
|
||||
#undef crypto_kem_enc
|
||||
#undef crypto_kem_enc_derand
|
||||
#undef crypto_kem_keypair
|
||||
#undef crypto_kem_keypair_derand
|
||||
/* mlkem/src/common.h */
|
||||
#undef MLK_ADD_PARAM_SET
|
||||
#undef MLK_ALLOC
|
||||
#undef MLK_APPLY
|
||||
#undef MLK_ASM_FN_SIZE
|
||||
#undef MLK_ASM_FN_SYMBOL
|
||||
#undef MLK_ASM_NAMESPACE
|
||||
#undef MLK_BUILD_INTERNAL
|
||||
#undef MLK_COMMON_H
|
||||
#undef MLK_CONCAT
|
||||
#undef MLK_CONCAT_
|
||||
#undef MLK_CONTEXT_PARAMETERS_0
|
||||
#undef MLK_CONTEXT_PARAMETERS_1
|
||||
#undef MLK_CONTEXT_PARAMETERS_2
|
||||
#undef MLK_CONTEXT_PARAMETERS_3
|
||||
#undef MLK_CONTEXT_PARAMETERS_4
|
||||
#undef MLK_EMPTY_CU
|
||||
#undef MLK_ERR_FAIL
|
||||
#undef MLK_ERR_OUT_OF_MEMORY
|
||||
#undef MLK_ERR_RNG_FAIL
|
||||
#undef MLK_EXTERNAL_API
|
||||
#undef MLK_FIPS202X4_HEADER_FILE
|
||||
#undef MLK_FIPS202_HEADER_FILE
|
||||
#undef MLK_FREE
|
||||
#undef MLK_INTERNAL_API
|
||||
#undef MLK_INTERNAL_DATA_DECLARATION
|
||||
#undef MLK_INTERNAL_DATA_DEFINITION
|
||||
#undef MLK_NAMESPACE
|
||||
#undef MLK_NAMESPACE_K
|
||||
#undef MLK_NAMESPACE_PREFIX
|
||||
#undef MLK_NAMESPACE_PREFIX_K
|
||||
#undef mlk_memcpy
|
||||
#undef mlk_memset
|
||||
/* mlkem/src/indcpa.h */
|
||||
#undef MLK_INDCPA_H
|
||||
#undef mlk_gen_matrix
|
||||
#undef mlk_indcpa_dec
|
||||
#undef mlk_indcpa_enc
|
||||
#undef mlk_indcpa_keypair_derand
|
||||
/* mlkem/src/kem.h */
|
||||
#undef MLK_KEM_H
|
||||
#undef mlk_kem_check_pk
|
||||
#undef mlk_kem_check_sk
|
||||
#undef mlk_kem_dec
|
||||
#undef mlk_kem_enc
|
||||
#undef mlk_kem_enc_derand
|
||||
#undef mlk_kem_keypair
|
||||
#undef mlk_kem_keypair_derand
|
||||
/* mlkem/src/params.h */
|
||||
#undef MLKEM_DU
|
||||
#undef MLKEM_DV
|
||||
#undef MLKEM_ETA1
|
||||
#undef MLKEM_ETA2
|
||||
#undef MLKEM_INDCCA_CIPHERTEXTBYTES
|
||||
#undef MLKEM_INDCCA_PUBLICKEYBYTES
|
||||
#undef MLKEM_INDCCA_SECRETKEYBYTES
|
||||
#undef MLKEM_INDCPA_BYTES
|
||||
#undef MLKEM_INDCPA_MSGBYTES
|
||||
#undef MLKEM_INDCPA_PUBLICKEYBYTES
|
||||
#undef MLKEM_INDCPA_SECRETKEYBYTES
|
||||
#undef MLKEM_K
|
||||
#undef MLKEM_N
|
||||
#undef MLKEM_POLYBYTES
|
||||
#undef MLKEM_POLYCOMPRESSEDBYTES_D10
|
||||
#undef MLKEM_POLYCOMPRESSEDBYTES_D11
|
||||
#undef MLKEM_POLYCOMPRESSEDBYTES_D4
|
||||
#undef MLKEM_POLYCOMPRESSEDBYTES_D5
|
||||
#undef MLKEM_POLYCOMPRESSEDBYTES_DU
|
||||
#undef MLKEM_POLYCOMPRESSEDBYTES_DV
|
||||
#undef MLKEM_POLYVECBYTES
|
||||
#undef MLKEM_POLYVECCOMPRESSEDBYTES_DU
|
||||
#undef MLKEM_Q
|
||||
#undef MLKEM_Q_HALF
|
||||
#undef MLKEM_SSBYTES
|
||||
#undef MLKEM_SYMBYTES
|
||||
#undef MLKEM_UINT12_LIMIT
|
||||
#undef MLK_PARAMS_H
|
||||
/* mlkem/src/poly_k.h */
|
||||
#undef MLK_POLY_K_H
|
||||
#undef mlk_poly_compress_du
|
||||
#undef mlk_poly_compress_dv
|
||||
#undef mlk_poly_decompress_du
|
||||
#undef mlk_poly_decompress_dv
|
||||
#undef mlk_poly_getnoise_eta1122_4x
|
||||
#undef mlk_poly_getnoise_eta1_4x
|
||||
#undef mlk_poly_getnoise_eta2
|
||||
#undef mlk_poly_getnoise_eta2_4x
|
||||
#undef mlk_polymat
|
||||
#undef mlk_polyvec
|
||||
#undef mlk_polyvec_add
|
||||
#undef mlk_polyvec_basemul_acc_montgomery_cached
|
||||
#undef mlk_polyvec_compress_du
|
||||
#undef mlk_polyvec_decompress_du
|
||||
#undef mlk_polyvec_frombytes
|
||||
#undef mlk_polyvec_invntt_tomont
|
||||
#undef mlk_polyvec_mulcache
|
||||
#undef mlk_polyvec_mulcache_compute
|
||||
#undef mlk_polyvec_ntt
|
||||
#undef mlk_polyvec_reduce
|
||||
#undef mlk_polyvec_tobytes
|
||||
#undef mlk_polyvec_tomont
|
||||
|
||||
#if !defined(MLK_CONFIG_MONOBUILD_KEEP_SHARED_HEADERS)
|
||||
/*
|
||||
* Undefine macros from MLK_CONFIG_PARAMETER_SET-generic files
|
||||
*/
|
||||
/* mlkem/src/compress.h */
|
||||
#undef MLK_COMPRESS_H
|
||||
#undef mlk_poly_compress_d10
|
||||
#undef mlk_poly_compress_d11
|
||||
#undef mlk_poly_compress_d4
|
||||
#undef mlk_poly_compress_d5
|
||||
#undef mlk_poly_decompress_d10
|
||||
#undef mlk_poly_decompress_d11
|
||||
#undef mlk_poly_decompress_d4
|
||||
#undef mlk_poly_decompress_d5
|
||||
#undef mlk_poly_frombytes
|
||||
#undef mlk_poly_frommsg
|
||||
#undef mlk_poly_tobytes
|
||||
#undef mlk_poly_tomsg
|
||||
/* mlkem/src/debug.h */
|
||||
#undef MLK_DEBUG_H
|
||||
#undef mlk_assert
|
||||
#undef mlk_assert_abs_bound
|
||||
#undef mlk_assert_abs_bound_2d
|
||||
#undef mlk_assert_bound
|
||||
#undef mlk_assert_bound_2d
|
||||
#undef mlk_debug_check_assert
|
||||
#undef mlk_debug_check_bounds
|
||||
/* mlkem/src/poly.h */
|
||||
#undef MLK_INVNTT_BOUND
|
||||
#undef MLK_NTT_BOUND
|
||||
#undef MLK_POLY_H
|
||||
#undef mlk_poly_add
|
||||
#undef mlk_poly_invntt_tomont
|
||||
#undef mlk_poly_mulcache_compute
|
||||
#undef mlk_poly_ntt
|
||||
#undef mlk_poly_reduce
|
||||
#undef mlk_poly_sub
|
||||
#undef mlk_poly_tomont
|
||||
/* mlkem/src/randombytes.h */
|
||||
#undef MLK_RANDOMBYTES_H
|
||||
/* mlkem/src/sampling.h */
|
||||
#undef MLK_SAMPLING_H
|
||||
#undef mlk_poly_cbd2
|
||||
#undef mlk_poly_cbd3
|
||||
#undef mlk_poly_rej_uniform
|
||||
#undef mlk_poly_rej_uniform_x4
|
||||
/* mlkem/src/symmetric.h */
|
||||
#undef MLK_SYMMETRIC_H
|
||||
#undef MLK_XOF_RATE
|
||||
#undef mlk_hash_g
|
||||
#undef mlk_hash_h
|
||||
#undef mlk_hash_j
|
||||
#undef mlk_prf_eta
|
||||
#undef mlk_prf_eta1
|
||||
#undef mlk_prf_eta1_x4
|
||||
#undef mlk_prf_eta2
|
||||
#undef mlk_xof_absorb
|
||||
#undef mlk_xof_ctx
|
||||
#undef mlk_xof_init
|
||||
#undef mlk_xof_release
|
||||
#undef mlk_xof_squeezeblocks
|
||||
#undef mlk_xof_x4_absorb
|
||||
#undef mlk_xof_x4_ctx
|
||||
#undef mlk_xof_x4_init
|
||||
#undef mlk_xof_x4_release
|
||||
#undef mlk_xof_x4_squeezeblocks
|
||||
/* mlkem/src/sys.h */
|
||||
#undef MLK_ALIGN
|
||||
#undef MLK_ALIGN_UP
|
||||
#undef MLK_ALWAYS_INLINE
|
||||
#undef MLK_CET_ENDBR
|
||||
#undef MLK_CT_TESTING_DECLASSIFY
|
||||
#undef MLK_CT_TESTING_SECRET
|
||||
#undef MLK_DEFAULT_ALIGN
|
||||
#undef MLK_HAVE_INLINE_ASM
|
||||
#undef MLK_INLINE
|
||||
#undef MLK_MUST_CHECK_RETURN_VALUE
|
||||
#undef MLK_NOINLINE
|
||||
#undef MLK_RESTRICT
|
||||
#undef MLK_STATIC_TESTABLE
|
||||
#undef MLK_SYSV_ABI
|
||||
#undef MLK_SYSV_ABI_SUPPORTED
|
||||
#undef MLK_SYS_AARCH64
|
||||
#undef MLK_SYS_AARCH64_EB
|
||||
#undef MLK_SYS_APPLE
|
||||
#undef MLK_SYS_ARMV81M_MVE
|
||||
#undef MLK_SYS_BIG_ENDIAN
|
||||
#undef MLK_SYS_H
|
||||
#undef MLK_SYS_LINUX
|
||||
#undef MLK_SYS_LITTLE_ENDIAN
|
||||
#undef MLK_SYS_PPC64LE
|
||||
#undef MLK_SYS_RISCV32
|
||||
#undef MLK_SYS_RISCV64
|
||||
#undef MLK_SYS_RISCV64_RVV
|
||||
#undef MLK_SYS_WINDOWS
|
||||
#undef MLK_SYS_X86_64
|
||||
#undef MLK_SYS_X86_64_AVX2
|
||||
/* mlkem/src/verify.h */
|
||||
#undef MLK_USE_ASM_VALUE_BARRIER
|
||||
#undef MLK_VERIFY_H
|
||||
#undef mlk_ct_opt_blocker_u64
|
||||
/* mlkem/src/cbmc.h */
|
||||
#undef MLK_CBMC_H
|
||||
#undef __contract__
|
||||
#undef __loop__
|
||||
|
||||
#if !defined(MLK_CONFIG_FIPS202_CUSTOM_HEADER)
|
||||
/*
|
||||
* Undefine macros from FIPS-202 files
|
||||
*/
|
||||
/* mlkem/src/fips202/fips202.h */
|
||||
#undef FIPS202_X4_DEFAULT_IMPLEMENTATION
|
||||
#undef MLK_FIPS202_FIPS202_H
|
||||
#undef SHA3_256_HASHBYTES
|
||||
#undef SHA3_256_RATE
|
||||
#undef SHA3_384_RATE
|
||||
#undef SHA3_512_HASHBYTES
|
||||
#undef SHA3_512_RATE
|
||||
#undef SHAKE128_RATE
|
||||
#undef SHAKE256_RATE
|
||||
#undef mlk_sha3_256
|
||||
#undef mlk_sha3_512
|
||||
#undef mlk_shake128_absorb_once
|
||||
#undef mlk_shake128_init
|
||||
#undef mlk_shake128_release
|
||||
#undef mlk_shake128_squeezeblocks
|
||||
#undef mlk_shake256
|
||||
/* mlkem/src/fips202/fips202x4.h */
|
||||
#undef MLK_FIPS202_FIPS202X4_H
|
||||
#undef mlk_shake128x4_absorb_once
|
||||
#undef mlk_shake128x4_init
|
||||
#undef mlk_shake128x4_release
|
||||
#undef mlk_shake128x4_squeezeblocks
|
||||
#undef mlk_shake256x4
|
||||
/* mlkem/src/fips202/keccakf1600.h */
|
||||
#undef MLK_FIPS202_KECCAKF1600_H
|
||||
#undef MLK_KECCAK_LANES
|
||||
#undef MLK_KECCAK_WAY
|
||||
#undef mlk_keccakf1600_extract_bytes
|
||||
#undef mlk_keccakf1600_permute
|
||||
#undef mlk_keccakf1600_xor_bytes
|
||||
#undef mlk_keccakf1600x4_extract_bytes
|
||||
#undef mlk_keccakf1600x4_permute
|
||||
#undef mlk_keccakf1600x4_xor_bytes
|
||||
#endif /* !MLK_CONFIG_FIPS202_CUSTOM_HEADER */
|
||||
|
||||
#if defined(MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202)
|
||||
/* mlkem/src/fips202/native/api.h */
|
||||
#undef MLK_FIPS202_NATIVE_API_H
|
||||
#undef MLK_NATIVE_FUNC_FALLBACK
|
||||
#undef MLK_NATIVE_FUNC_SUCCESS
|
||||
/* mlkem/src/fips202/native/auto.h */
|
||||
#undef MLK_FIPS202_NATIVE_AUTO_H
|
||||
#if defined(MLK_SYS_AARCH64)
|
||||
/*
|
||||
* Undefine macros from native code (FIPS202, AArch64)
|
||||
*/
|
||||
/* mlkem/src/fips202/native/aarch64/auto.h */
|
||||
#undef MLK_FIPS202_NATIVE_AARCH64_AUTO_H
|
||||
/* mlkem/src/fips202/native/aarch64/src/fips202_native_aarch64.h */
|
||||
#undef MLK_FIPS202_NATIVE_AARCH64_SRC_FIPS202_NATIVE_AARCH64_H
|
||||
#undef mlk_keccak_f1600_x1_scalar_aarch64_asm
|
||||
#undef mlk_keccak_f1600_x1_v84a_aarch64_asm
|
||||
#undef mlk_keccak_f1600_x2_v84a_aarch64_asm
|
||||
#undef mlk_keccak_f1600_x4_v8a_scalar_hybrid_aarch64_asm
|
||||
#undef mlk_keccak_f1600_x4_v8a_v84a_scalar_hybrid_aarch64_asm
|
||||
#undef mlk_keccakf1600_round_constants
|
||||
/* mlkem/src/fips202/native/aarch64/x1_scalar.h */
|
||||
#undef MLK_FIPS202_AARCH64_NEED_X1_SCALAR
|
||||
#undef MLK_FIPS202_NATIVE_AARCH64_X1_SCALAR_H
|
||||
#undef MLK_USE_FIPS202_X1_NATIVE
|
||||
/* mlkem/src/fips202/native/aarch64/x1_v84a.h */
|
||||
#undef MLK_FIPS202_AARCH64_NEED_X1_V84A
|
||||
#undef MLK_FIPS202_NATIVE_AARCH64_X1_V84A_H
|
||||
#undef MLK_USE_FIPS202_X1_NATIVE
|
||||
/* mlkem/src/fips202/native/aarch64/x2_v84a.h */
|
||||
#undef MLK_FIPS202_AARCH64_NEED_X2_V84A
|
||||
#undef MLK_FIPS202_NATIVE_AARCH64_X2_V84A_H
|
||||
#undef MLK_USE_FIPS202_X4_NATIVE
|
||||
/* mlkem/src/fips202/native/aarch64/x4_v8a_scalar.h */
|
||||
#undef MLK_FIPS202_AARCH64_NEED_X4_V8A_SCALAR_HYBRID
|
||||
#undef MLK_FIPS202_NATIVE_AARCH64_X4_V8A_SCALAR_H
|
||||
#undef MLK_USE_FIPS202_X4_NATIVE
|
||||
/* mlkem/src/fips202/native/aarch64/x4_v8a_v84a_scalar.h */
|
||||
#undef MLK_FIPS202_AARCH64_NEED_X4_V8A_V84A_SCALAR_HYBRID
|
||||
#undef MLK_FIPS202_NATIVE_AARCH64_X4_V8A_V84A_SCALAR_H
|
||||
#undef MLK_USE_FIPS202_X4_NATIVE
|
||||
#endif /* MLK_SYS_AARCH64 */
|
||||
#if defined(MLK_SYS_X86_64)
|
||||
/*
|
||||
* Undefine macros from native code (FIPS202, x86_64)
|
||||
*/
|
||||
/* mlkem/src/fips202/native/x86_64/keccak_f1600_x4_avx2.h */
|
||||
#undef MLK_FIPS202_NATIVE_X86_64_KECCAK_F1600_X4_AVX2_H
|
||||
#undef MLK_FIPS202_X86_64_NEED_X4_AVX2
|
||||
#undef MLK_USE_FIPS202_X4_NATIVE
|
||||
/* mlkem/src/fips202/native/x86_64/src/fips202_native_x86_64.h */
|
||||
#undef MLK_FIPS202_NATIVE_X86_64_SRC_FIPS202_NATIVE_X86_64_H
|
||||
#undef mlk_keccak_f1600_x4_avx2_asm
|
||||
#undef mlk_keccak_rho56
|
||||
#undef mlk_keccak_rho8
|
||||
#undef mlk_keccakf1600_round_constants
|
||||
#endif /* MLK_SYS_X86_64 */
|
||||
#if defined(MLK_SYS_ARMV81M_MVE)
|
||||
/*
|
||||
* Undefine macros from native code (FIPS202, Armv8.1-M)
|
||||
*/
|
||||
/* mlkem/src/fips202/native/armv81m/mve.h */
|
||||
#undef MLK_FIPS202_ARMV81M_NEED_X4
|
||||
#undef MLK_FIPS202_NATIVE_ARMV81M
|
||||
#undef MLK_FIPS202_NATIVE_ARMV81M_MVE_H
|
||||
#undef MLK_USE_FIPS202_X4_EXTRACT_BYTES_NATIVE
|
||||
#undef MLK_USE_FIPS202_X4_NATIVE
|
||||
#undef MLK_USE_FIPS202_X4_XOR_BYTES_NATIVE
|
||||
#undef mlk_keccak_f1600_x4_native_impl
|
||||
/* mlkem/src/fips202/native/armv81m/src/fips202_native_armv81m.h */
|
||||
#undef MLK_FIPS202_NATIVE_ARMV81M_SRC_FIPS202_NATIVE_ARMV81M_H
|
||||
#undef mlk_keccak_f1600_x4_mve_asm
|
||||
#undef mlk_keccak_f1600_x4_state_extract_bytes_asm
|
||||
#undef mlk_keccak_f1600_x4_state_xor_bytes_asm
|
||||
#undef mlk_keccakf1600_round_constants
|
||||
#endif /* MLK_SYS_ARMV81M_MVE */
|
||||
#endif /* MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202 */
|
||||
#if defined(MLK_CONFIG_USE_NATIVE_BACKEND_ARITH)
|
||||
/* mlkem/src/native/api.h */
|
||||
#undef MLK_INVNTT_BOUND
|
||||
#undef MLK_NATIVE_API_H
|
||||
#undef MLK_NATIVE_FUNC_FALLBACK
|
||||
#undef MLK_NATIVE_FUNC_SUCCESS
|
||||
#undef MLK_NTT_BOUND
|
||||
/* mlkem/src/native/meta.h */
|
||||
#undef MLK_NATIVE_META_H
|
||||
#if defined(MLK_SYS_AARCH64)
|
||||
/*
|
||||
* Undefine macros from native code (Arith, AArch64)
|
||||
*/
|
||||
/* mlkem/src/native/aarch64/meta.h */
|
||||
#undef MLK_ARITH_BACKEND_AARCH64
|
||||
#undef MLK_NATIVE_AARCH64_META_H
|
||||
#undef MLK_USE_NATIVE_INTT
|
||||
#undef MLK_USE_NATIVE_NTT
|
||||
#undef MLK_USE_NATIVE_POLYVEC_BASEMUL_ACC_MONTGOMERY_CACHED
|
||||
#undef MLK_USE_NATIVE_POLY_MULCACHE_COMPUTE
|
||||
#undef MLK_USE_NATIVE_POLY_REDUCE
|
||||
#undef MLK_USE_NATIVE_POLY_TOBYTES
|
||||
#undef MLK_USE_NATIVE_POLY_TOMONT
|
||||
#undef MLK_USE_NATIVE_REJ_UNIFORM
|
||||
/* mlkem/src/native/aarch64/src/arith_native_aarch64.h */
|
||||
#undef MLK_NATIVE_AARCH64_SRC_ARITH_NATIVE_AARCH64_H
|
||||
#undef mlk_aarch64_invntt_zetas_layer12345
|
||||
#undef mlk_aarch64_invntt_zetas_layer67
|
||||
#undef mlk_aarch64_ntt_zetas_layer12345
|
||||
#undef mlk_aarch64_ntt_zetas_layer67
|
||||
#undef mlk_aarch64_zetas_mulcache_native
|
||||
#undef mlk_aarch64_zetas_mulcache_twisted_native
|
||||
#undef mlk_intt_aarch64_asm
|
||||
#undef mlk_ntt_aarch64_asm
|
||||
#undef mlk_poly_mulcache_compute_aarch64_asm
|
||||
#undef mlk_poly_reduce_aarch64_asm
|
||||
#undef mlk_poly_tobytes_aarch64_asm
|
||||
#undef mlk_poly_tomont_aarch64_asm
|
||||
#undef mlk_polyvec_basemul_acc_montgomery_cached_k2_aarch64_asm
|
||||
#undef mlk_polyvec_basemul_acc_montgomery_cached_k3_aarch64_asm
|
||||
#undef mlk_polyvec_basemul_acc_montgomery_cached_k4_aarch64_asm
|
||||
#undef mlk_rej_uniform_aarch64_asm
|
||||
#undef mlk_rej_uniform_table
|
||||
#endif /* MLK_SYS_AARCH64 */
|
||||
#if defined(MLK_SYS_X86_64)
|
||||
/*
|
||||
* Undefine macros from native code (Arith, X86_64)
|
||||
*/
|
||||
/* mlkem/src/native/x86_64/meta.h */
|
||||
#undef MLK_ARITH_BACKEND_X86_64_DEFAULT
|
||||
#undef MLK_NATIVE_X86_64_META_H
|
||||
#undef MLK_USE_NATIVE_INTT
|
||||
#undef MLK_USE_NATIVE_NTT
|
||||
#undef MLK_USE_NATIVE_NTT_CUSTOM_ORDER
|
||||
#undef MLK_USE_NATIVE_POLYVEC_BASEMUL_ACC_MONTGOMERY_CACHED
|
||||
#undef MLK_USE_NATIVE_POLY_COMPRESS_D10
|
||||
#undef MLK_USE_NATIVE_POLY_COMPRESS_D11
|
||||
#undef MLK_USE_NATIVE_POLY_COMPRESS_D4
|
||||
#undef MLK_USE_NATIVE_POLY_COMPRESS_D5
|
||||
#undef MLK_USE_NATIVE_POLY_DECOMPRESS_D10
|
||||
#undef MLK_USE_NATIVE_POLY_DECOMPRESS_D11
|
||||
#undef MLK_USE_NATIVE_POLY_DECOMPRESS_D4
|
||||
#undef MLK_USE_NATIVE_POLY_DECOMPRESS_D5
|
||||
#undef MLK_USE_NATIVE_POLY_FROMBYTES
|
||||
#undef MLK_USE_NATIVE_POLY_MULCACHE_COMPUTE
|
||||
#undef MLK_USE_NATIVE_POLY_REDUCE
|
||||
#undef MLK_USE_NATIVE_POLY_TOBYTES
|
||||
#undef MLK_USE_NATIVE_POLY_TOMONT
|
||||
#undef MLK_USE_NATIVE_REJ_UNIFORM
|
||||
/* mlkem/src/native/x86_64/src/arith_native_x86_64.h */
|
||||
#undef MLK_AVX2_REJ_UNIFORM_BUFLEN
|
||||
#undef MLK_NATIVE_X86_64_SRC_ARITH_NATIVE_X86_64_H
|
||||
#undef mlk_invntt_avx2_asm
|
||||
#undef mlk_ntt_avx2_asm
|
||||
#undef mlk_nttfrombytes_avx2_asm
|
||||
#undef mlk_ntttobytes_avx2_asm
|
||||
#undef mlk_nttunpack_avx2_asm
|
||||
#undef mlk_poly_compress_d10_avx2_asm
|
||||
#undef mlk_poly_compress_d11_avx2_asm
|
||||
#undef mlk_poly_compress_d4_avx2_asm
|
||||
#undef mlk_poly_compress_d5_avx2_asm
|
||||
#undef mlk_poly_decompress_d10_avx2_asm
|
||||
#undef mlk_poly_decompress_d11_avx2_asm
|
||||
#undef mlk_poly_decompress_d4_avx2_asm
|
||||
#undef mlk_poly_decompress_d5_avx2_asm
|
||||
#undef mlk_poly_mulcache_compute_avx2_asm
|
||||
#undef mlk_polyvec_basemul_acc_montgomery_cached_k2_avx2_asm
|
||||
#undef mlk_polyvec_basemul_acc_montgomery_cached_k3_avx2_asm
|
||||
#undef mlk_polyvec_basemul_acc_montgomery_cached_k4_avx2_asm
|
||||
#undef mlk_reduce_avx2_asm
|
||||
#undef mlk_rej_uniform_avx2_asm
|
||||
#undef mlk_rej_uniform_table
|
||||
#undef mlk_tomont_avx2_asm
|
||||
/* mlkem/src/native/x86_64/src/compress_consts.h */
|
||||
#undef MLK_NATIVE_X86_64_SRC_COMPRESS_CONSTS_H
|
||||
#undef mlk_compress_d10_data
|
||||
#undef mlk_compress_d11_data
|
||||
#undef mlk_compress_d4_data
|
||||
#undef mlk_compress_d5_data
|
||||
#undef mlk_decompress_d10_data
|
||||
#undef mlk_decompress_d11_data
|
||||
#undef mlk_decompress_d4_data
|
||||
#undef mlk_decompress_d5_data
|
||||
/* mlkem/src/native/x86_64/src/consts.h */
|
||||
#undef MLK_AVX2_BACKEND_DATA_OFFSET_MULCACHE_TWIDDLES
|
||||
#undef MLK_AVX2_BACKEND_DATA_OFFSET_REVIDXB
|
||||
#undef MLK_AVX2_BACKEND_DATA_OFFSET_REVIDXD
|
||||
#undef MLK_AVX2_BACKEND_DATA_OFFSET_ZETAS_EXP
|
||||
#undef MLK_NATIVE_X86_64_SRC_CONSTS_H
|
||||
#undef mlk_qdata
|
||||
#endif /* MLK_SYS_X86_64 */
|
||||
#if defined(MLK_SYS_RISCV64)
|
||||
/*
|
||||
* Undefine macros from native code (Arith, RISC-V 64)
|
||||
*/
|
||||
/* mlkem/src/native/riscv64/meta.h */
|
||||
#undef MLK_ARITH_BACKEND_RISCV64
|
||||
#undef MLK_NATIVE_RISCV64_META_H
|
||||
#undef MLK_USE_NATIVE_INTT
|
||||
#undef MLK_USE_NATIVE_NTT
|
||||
#undef MLK_USE_NATIVE_POLYVEC_BASEMUL_ACC_MONTGOMERY_CACHED
|
||||
#undef MLK_USE_NATIVE_POLY_MULCACHE_COMPUTE
|
||||
#undef MLK_USE_NATIVE_POLY_REDUCE
|
||||
#undef MLK_USE_NATIVE_POLY_TOMONT
|
||||
#undef MLK_USE_NATIVE_REJ_UNIFORM
|
||||
/* mlkem/src/native/riscv64/src/arith_native_riscv64.h */
|
||||
#undef MLK_NATIVE_RISCV64_SRC_ARITH_NATIVE_RISCV64_H
|
||||
#undef mlk_rv64v_poly_add
|
||||
#undef mlk_rv64v_poly_basemul_mont_add_k2
|
||||
#undef mlk_rv64v_poly_basemul_mont_add_k3
|
||||
#undef mlk_rv64v_poly_basemul_mont_add_k4
|
||||
#undef mlk_rv64v_poly_invntt_tomont
|
||||
#undef mlk_rv64v_poly_ntt
|
||||
#undef mlk_rv64v_poly_reduce
|
||||
#undef mlk_rv64v_poly_sub
|
||||
#undef mlk_rv64v_poly_tomont
|
||||
#undef mlk_rv64v_rej_uniform
|
||||
/* mlkem/src/native/riscv64/src/rv64v_debug.h */
|
||||
#undef MLK_NATIVE_RISCV64_SRC_RV64V_DEBUG_H
|
||||
#undef mlk_assert_abs_bound_int16m1
|
||||
#undef mlk_assert_abs_bound_int16m2
|
||||
#undef mlk_assert_bound_int16m1
|
||||
#undef mlk_assert_bound_int16m2
|
||||
#undef mlk_debug_check_bounds_int16m1
|
||||
#undef mlk_debug_check_bounds_int16m2
|
||||
#endif /* MLK_SYS_RISCV64 */
|
||||
#if defined(MLK_SYS_PPC64LE)
|
||||
/*
|
||||
* Undefine macros from native code (Arith, PPC64LE)
|
||||
*/
|
||||
/* mlkem/src/native/ppc64le/meta.h */
|
||||
#undef MLK_ARITH_BACKEND_NAME
|
||||
#undef MLK_ARITH_BACKEND_PPC64LE_DEFAULT
|
||||
#undef MLK_NATIVE_PPC64LE_META_H
|
||||
#undef MLK_USE_NATIVE_INTT
|
||||
#undef MLK_USE_NATIVE_NTT
|
||||
#undef MLK_USE_NATIVE_POLY_REDUCE
|
||||
#undef MLK_USE_NATIVE_POLY_TOMONT
|
||||
/* mlkem/src/native/ppc64le/src/arith_native_ppc64le.h */
|
||||
#undef MLK_NATIVE_PPC64LE_SRC_ARITH_NATIVE_PPC64LE_H
|
||||
#undef mlk_intt_ppc_asm
|
||||
#undef mlk_ntt_ppc_asm
|
||||
#undef mlk_poly_tomont_ppc_asm
|
||||
#undef mlk_reduce_ppc_asm
|
||||
/* mlkem/src/native/ppc64le/src/consts.h */
|
||||
#undef MLK_NATIVE_PPC64LE_SRC_CONSTS_H
|
||||
#undef MLK_PPC_C20159_OFFSET
|
||||
#undef MLK_PPC_NQ_OFFSET
|
||||
#undef MLK_PPC_N_INV_OFFSET
|
||||
#undef MLK_PPC_N_INV_TW_OFFSET
|
||||
#undef MLK_PPC_Q_OFFSET
|
||||
#undef MLK_PPC_TOMONT_OFFSET
|
||||
#undef MLK_PPC_TOMONT_TW_OFFSET
|
||||
#undef MLK_PPC_ZETA_INTT_OFFSET
|
||||
#undef MLK_PPC_ZETA_INTT_TW_OFFSET
|
||||
#undef MLK_PPC_ZETA_NTT_OFFSET
|
||||
#undef MLK_PPC_ZETA_NTT_TW_OFFSET
|
||||
#undef mlk_ppc_qdata
|
||||
#endif /* MLK_SYS_PPC64LE */
|
||||
#endif /* MLK_CONFIG_USE_NATIVE_BACKEND_ARITH */
|
||||
#endif /* !MLK_CONFIG_MONOBUILD_KEEP_SHARED_HEADERS */
|
||||
@@ -1,645 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
|
||||
/* References
|
||||
* ==========
|
||||
*
|
||||
* - [FIPS140_3_IG]
|
||||
* Implementation Guidance for FIPS 140-3 and the Cryptographic Module
|
||||
* Validation Program
|
||||
* National Institute of Standards and Technology
|
||||
* https://csrc.nist.gov/projects/cryptographic-module-validation-program/fips-140-3-ig-announcements
|
||||
*
|
||||
* - [FIPS203]
|
||||
* FIPS 203 Module-Lattice-Based Key-Encapsulation Mechanism Standard
|
||||
* National Institute of Standards and Technology
|
||||
* https://csrc.nist.gov/pubs/fips/203/final
|
||||
*/
|
||||
|
||||
#ifndef MLK_CONFIG_H
|
||||
#define MLK_CONFIG_H
|
||||
|
||||
/**
|
||||
* Specifies the parameter set for ML-KEM:
|
||||
* - MLK_CONFIG_PARAMETER_SET=512 corresponds to ML-KEM-512
|
||||
* - MLK_CONFIG_PARAMETER_SET=768 corresponds to ML-KEM-768
|
||||
* - MLK_CONFIG_PARAMETER_SET=1024 corresponds to ML-KEM-1024
|
||||
*
|
||||
* If you want to support multiple parameter sets, build the library multiple
|
||||
* times and set MLK_CONFIG_MULTILEVEL_BUILD. See MLK_CONFIG_MULTILEVEL_BUILD
|
||||
* for how to do this while minimizing code duplication.
|
||||
*
|
||||
* This can also be set using CFLAGS.
|
||||
*/
|
||||
#ifndef MLK_CONFIG_PARAMETER_SET
|
||||
#define MLK_CONFIG_PARAMETER_SET \
|
||||
768 /* Change this for different security strengths */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_FILE
|
||||
*
|
||||
* If defined, this is a header that will be included instead of the default
|
||||
* configuration file mlkem/mlkem_native_config.h.
|
||||
*
|
||||
* When you need to build mlkem-native in multiple configurations, using
|
||||
* varying MLK_CONFIG_FILE can be more convenient than configuring everything
|
||||
* through CFLAGS.
|
||||
*
|
||||
* To use, MLK_CONFIG_FILE _must_ be defined prior to the inclusion of any
|
||||
* mlkem-native headers. For example, it can be set by passing
|
||||
* `-DMLK_CONFIG_FILE="..."` on the command line.
|
||||
*/
|
||||
/* #define MLK_CONFIG_FILE "mlkem_native_config.h" */
|
||||
|
||||
/**
|
||||
* The prefix to use to namespace global symbols from mlkem/.
|
||||
*
|
||||
* In a multi-level build, level-dependent symbols will additionally be
|
||||
* prefixed with the parameter set (512/768/1024).
|
||||
*
|
||||
* This can also be set using CFLAGS.
|
||||
*/
|
||||
#if !defined(MLK_CONFIG_NAMESPACE_PREFIX)
|
||||
#define MLK_CONFIG_NAMESPACE_PREFIX MLK_DEFAULT_NAMESPACE_PREFIX
|
||||
#endif
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_MULTILEVEL_BUILD
|
||||
*
|
||||
* Set this if the build is part of a multi-level build supporting multiple
|
||||
* parameter sets.
|
||||
*
|
||||
* If you need only a single parameter set, keep this unset.
|
||||
*
|
||||
* To build mlkem-native with support for all parameter sets, build it three
|
||||
* times -- once per parameter set -- and set the option
|
||||
* MLK_CONFIG_MULTILEVEL_WITH_SHARED for exactly one of them, and
|
||||
* MLK_CONFIG_MULTILEVEL_NO_SHARED for the others.
|
||||
* MLK_CONFIG_MULTILEVEL_BUILD should be set for all of them.
|
||||
*
|
||||
* See examples/multilevel_build for an example.
|
||||
*
|
||||
* This can also be set using CFLAGS.
|
||||
*/
|
||||
/* #define MLK_CONFIG_MULTILEVEL_BUILD */
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_EXTERNAL_API_QUALIFIER
|
||||
*
|
||||
* If set, this option provides an additional function qualifier to be added
|
||||
* to declarations of mlkem-native's public API.
|
||||
*
|
||||
* The primary use case for this option are single-CU builds where the public
|
||||
* API exposed by mlkem-native is wrapped by another API in the consuming
|
||||
* application. In this case, even mlkem-native's public API can be marked
|
||||
* `static`.
|
||||
*/
|
||||
/* #define MLK_CONFIG_EXTERNAL_API_QUALIFIER */
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_NO_RANDOMIZED_API
|
||||
*
|
||||
* If this option is set, mlkem-native will be built without the randomized
|
||||
* API functions (crypto_kem_keypair and crypto_kem_enc). This allows users
|
||||
* to build mlkem-native without providing a randombytes() implementation
|
||||
* if they only need the deterministic API (crypto_kem_keypair_derand,
|
||||
* crypto_kem_enc_derand, crypto_kem_dec).
|
||||
*
|
||||
* @note This option is incompatible with MLK_CONFIG_KEYGEN_PCT as the
|
||||
* current PCT implementation requires crypto_kem_enc().
|
||||
*/
|
||||
/* #define MLK_CONFIG_NO_RANDOMIZED_API */
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_NO_SUPERCOP
|
||||
*
|
||||
* By default, mlkem_native.h exposes the mlkem-native API in the SUPERCOP
|
||||
* naming convention (crypto_kem_xxx). If you don't need this, set
|
||||
* MLK_CONFIG_NO_SUPERCOP.
|
||||
*
|
||||
* @note You must set this for a multi-level build as the SUPERCOP naming
|
||||
* does not disambiguate between the parameter sets.
|
||||
*/
|
||||
/* #define MLK_CONFIG_NO_SUPERCOP */
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_CONSTANTS_ONLY
|
||||
*
|
||||
* If you only need the size constants (MLKEM_PUBLICKEYBYTES, etc.) but no
|
||||
* function declarations, set MLK_CONFIG_CONSTANTS_ONLY.
|
||||
*
|
||||
* This only affects the public header mlkem_native.h, not the
|
||||
* implementation.
|
||||
*/
|
||||
/* #define MLK_CONFIG_CONSTANTS_ONLY */
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Build-only configuration options
|
||||
*
|
||||
* The remaining configurations are build-options only.
|
||||
* They do not affect the API described in mlkem_native.h.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#if defined(MLK_BUILD_INTERNAL)
|
||||
/**
|
||||
* MLK_CONFIG_MULTILEVEL_WITH_SHARED
|
||||
*
|
||||
* This is for multi-level builds of mlkem-native only. If you need only a
|
||||
* single parameter set, keep this unset.
|
||||
*
|
||||
* If this is set, all MLK_CONFIG_PARAMETER_SET-independent code will be
|
||||
* included in the build, including code needed only for other parameter
|
||||
* sets.
|
||||
*
|
||||
* Example: mlk_poly_cbd3 is only needed for MLK_CONFIG_PARAMETER_SET == 512.
|
||||
* Yet, if this option is set for a build with
|
||||
* MLK_CONFIG_PARAMETER_SET == 768/1024, it would be included.
|
||||
*
|
||||
* To build mlkem-native with support for all parameter sets, build it three
|
||||
* times -- once per parameter set -- and set the option
|
||||
* MLK_CONFIG_MULTILEVEL_WITH_SHARED for exactly one of them, and
|
||||
* MLK_CONFIG_MULTILEVEL_NO_SHARED for the others.
|
||||
* MLK_CONFIG_MULTILEVEL_BUILD should be set for all of them.
|
||||
*
|
||||
* See examples/multilevel_build for an example.
|
||||
*
|
||||
* This can also be set using CFLAGS.
|
||||
*/
|
||||
/* #define MLK_CONFIG_MULTILEVEL_WITH_SHARED */
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_MULTILEVEL_NO_SHARED
|
||||
*
|
||||
* This is for multi-level builds of mlkem-native only. If you need only a
|
||||
* single parameter set, keep this unset.
|
||||
*
|
||||
* If this is set, no MLK_CONFIG_PARAMETER_SET-independent code will be
|
||||
* included in the build.
|
||||
*
|
||||
* To build mlkem-native with support for all parameter sets, build it three
|
||||
* times -- once per parameter set -- and set the option
|
||||
* MLK_CONFIG_MULTILEVEL_WITH_SHARED for exactly one of them, and
|
||||
* MLK_CONFIG_MULTILEVEL_NO_SHARED for the others.
|
||||
* MLK_CONFIG_MULTILEVEL_BUILD should be set for all of them.
|
||||
*
|
||||
* See examples/multilevel_build for an example.
|
||||
*
|
||||
* This can also be set using CFLAGS.
|
||||
*/
|
||||
/* #define MLK_CONFIG_MULTILEVEL_NO_SHARED */
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_MONOBUILD_KEEP_SHARED_HEADERS
|
||||
*
|
||||
* This is only relevant for single compilation unit (SCU) builds of
|
||||
* mlkem-native. In this case, it determines whether directives defined in
|
||||
* parameter-set-independent headers should be #undef'ined or not at the
|
||||
* end of the SCU file. This is needed in multilevel builds.
|
||||
*
|
||||
* See examples/multilevel_build_native for an example.
|
||||
*
|
||||
* This can also be set using CFLAGS.
|
||||
*/
|
||||
/* #define MLK_CONFIG_MONOBUILD_KEEP_SHARED_HEADERS */
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_USE_NATIVE_BACKEND_ARITH
|
||||
*
|
||||
* Determines whether a native arithmetic backend should be used.
|
||||
*
|
||||
* The arithmetic backend covers performance-critical functions such as the
|
||||
* number-theoretic transform (NTT).
|
||||
*
|
||||
* If this option is unset, the C backend will be used.
|
||||
*
|
||||
* If this option is set, the arithmetic backend to be used is determined
|
||||
* by MLK_CONFIG_ARITH_BACKEND_FILE: if the latter is unset, the default
|
||||
* backend for the target architecture will be used. If set, it must be the
|
||||
* name of a backend metadata file.
|
||||
*
|
||||
* This can also be set using CFLAGS.
|
||||
*/
|
||||
#if !defined(MLK_CONFIG_USE_NATIVE_BACKEND_ARITH)
|
||||
/* #define MLK_CONFIG_USE_NATIVE_BACKEND_ARITH */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_ARITH_BACKEND_FILE
|
||||
*
|
||||
* The arithmetic backend to use.
|
||||
*
|
||||
* If MLK_CONFIG_USE_NATIVE_BACKEND_ARITH is unset, this option is ignored.
|
||||
*
|
||||
* If MLK_CONFIG_USE_NATIVE_BACKEND_ARITH is set, this option must either
|
||||
* be undefined or the filename of an arithmetic backend. If unset, the
|
||||
* default backend will be used.
|
||||
*
|
||||
* This can be set using CFLAGS.
|
||||
*/
|
||||
#if defined(MLK_CONFIG_USE_NATIVE_BACKEND_ARITH) && \
|
||||
!defined(MLK_CONFIG_ARITH_BACKEND_FILE)
|
||||
#define MLK_CONFIG_ARITH_BACKEND_FILE "native/meta.h"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202
|
||||
*
|
||||
* Determines whether a native FIPS202 backend should be used.
|
||||
*
|
||||
* The FIPS202 backend covers 1x/2x/4x-fold Keccak-f1600, which is the
|
||||
* performance bottleneck of SHA3 and SHAKE.
|
||||
*
|
||||
* If this option is unset, the C backend will be used.
|
||||
*
|
||||
* If this option is set, the FIPS202 backend to be used is determined by
|
||||
* MLK_CONFIG_FIPS202_BACKEND_FILE: if the latter is unset, the default
|
||||
* backend for the target architecture will be used. If set, it must be
|
||||
* the name of a backend metadata file.
|
||||
*
|
||||
* This can also be set using CFLAGS.
|
||||
*/
|
||||
#if !defined(MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202)
|
||||
/* #define MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202 */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_FIPS202_BACKEND_FILE
|
||||
*
|
||||
* The FIPS-202 backend to use.
|
||||
*
|
||||
* If MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202 is set, this option must either
|
||||
* be undefined or the filename of a FIPS202 backend. If unset, the default
|
||||
* backend will be used.
|
||||
*
|
||||
* This can be set using CFLAGS.
|
||||
*/
|
||||
#if defined(MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202) && \
|
||||
!defined(MLK_CONFIG_FIPS202_BACKEND_FILE)
|
||||
#define MLK_CONFIG_FIPS202_BACKEND_FILE "fips202/native/auto.h"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_FIPS202_CUSTOM_HEADER
|
||||
*
|
||||
* Custom header to use for FIPS-202.
|
||||
*
|
||||
* This should only be set if you intend to use a custom FIPS-202
|
||||
* implementation, different from the one shipped with mlkem-native.
|
||||
*
|
||||
* If set, it must be the name of a file serving as the replacement for
|
||||
* mlkem/fips202/fips202.h, and exposing the same API (see FIPS202.md).
|
||||
*/
|
||||
/* #define MLK_CONFIG_FIPS202_CUSTOM_HEADER "SOME_FILE.h" */
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_FIPS202X4_CUSTOM_HEADER
|
||||
*
|
||||
* Custom header to use for FIPS-202-X4.
|
||||
*
|
||||
* This should only be set if you intend to use a custom FIPS-202
|
||||
* implementation, different from the one shipped with mlkem-native.
|
||||
*
|
||||
* If set, it must be the name of a file serving as the replacement for
|
||||
* mlkem/fips202/fips202x4.h, and exposing the same API (see FIPS202.md).
|
||||
*/
|
||||
/* #define MLK_CONFIG_FIPS202X4_CUSTOM_HEADER "SOME_FILE.h" */
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_CUSTOM_ZEROIZE
|
||||
*
|
||||
* In compliance with @[FIPS203, Section 3.3], mlkem-native zeroizes
|
||||
* intermediate stack buffers before returning from function calls.
|
||||
*
|
||||
* Set this option and define `mlk_zeroize` if you want to use a custom
|
||||
* method to zeroize intermediate stack buffers. The default implementation
|
||||
* uses SecureZeroMemory on Windows and a memset + compiler barrier
|
||||
* otherwise. If neither of those is available on the target platform,
|
||||
* compilation will fail, and you will need to use MLK_CONFIG_CUSTOM_ZEROIZE
|
||||
* to provide a custom implementation of `mlk_zeroize()`.
|
||||
*
|
||||
* @warning The explicit stack zeroization conducted by mlkem-native reduces
|
||||
* the likelihood of data leaking on the stack, but does not
|
||||
* eliminate it. The C standard makes no guarantee about where a
|
||||
* compiler allocates structures and whether/where it makes copies
|
||||
* of them. Also, in addition to entire structures, there may also
|
||||
* be potentially exploitable leakage of individual values on the
|
||||
* stack. If you need bullet-proof zeroization of the stack, you
|
||||
* need to consider additional measures instead of what this
|
||||
* feature provides. In this case, you can set mlk_zeroize to a
|
||||
* no-op.
|
||||
*/
|
||||
/* #define MLK_CONFIG_CUSTOM_ZEROIZE
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#include <stdint.h>
|
||||
#include "src/sys.h"
|
||||
static MLK_INLINE void mlk_zeroize(void *ptr, size_t len)
|
||||
{
|
||||
... your implementation ...
|
||||
}
|
||||
#endif
|
||||
*/
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_CUSTOM_RANDOMBYTES
|
||||
*
|
||||
* mlkem-native does not provide a secure randombytes implementation. Such
|
||||
* an implementation has to be provided by the consumer.
|
||||
*
|
||||
* If this option is not set, mlkem-native expects a function
|
||||
* int randombytes(uint8_t *out, size_t outlen). It is expected to return
|
||||
* zero on success, and non-zero on failure. In case of failure, the
|
||||
* top-level APIs will return an MLK_ERR_RNG_FAIL error code.
|
||||
*
|
||||
* Set this option and define `mlk_randombytes` (with the same signature
|
||||
* and behaviour) if you want to use a custom method to sample randombytes
|
||||
* with a different name or signature.
|
||||
*/
|
||||
/* #define MLK_CONFIG_CUSTOM_RANDOMBYTES
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#include <stdint.h>
|
||||
#include "src/sys.h"
|
||||
static MLK_INLINE int mlk_randombytes(uint8_t *ptr, size_t len)
|
||||
{
|
||||
... your implementation ...
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
*/
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_CUSTOM_CAPABILITY_FUNC
|
||||
*
|
||||
* mlkem-native backends may rely on specific hardware features. Those
|
||||
* backends will only be included in an mlkem-native build if support for
|
||||
* the respective features is enabled at compile-time. However, when
|
||||
* building for a heterogeneous set of CPUs to run the resulting
|
||||
* binary/library on, feature detection at _runtime_ is needed to decide
|
||||
* whether a backend can be used or not.
|
||||
*
|
||||
* Set this option and define `mlk_sys_check_capability` if you want to
|
||||
* use a custom method to dispatch between implementations.
|
||||
*
|
||||
* If this option is not set, mlkem-native uses compile-time feature
|
||||
* detection only to decide which backend to use.
|
||||
*
|
||||
* If you compile mlkem-native on a system with different capabilities
|
||||
* than the system that the resulting binary/library will be run on, you
|
||||
* must use this option.
|
||||
*/
|
||||
/* #define MLK_CONFIG_CUSTOM_CAPABILITY_FUNC
|
||||
static MLK_INLINE int mlk_sys_check_capability(mlk_sys_cap cap)
|
||||
__contract__(
|
||||
ensures(return_value == 0 || return_value == 1)
|
||||
)
|
||||
{
|
||||
... your implementation ...
|
||||
}
|
||||
*/
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_CUSTOM_ALLOC_FREE [EXPERIMENTAL]
|
||||
*
|
||||
* Set this option and define `MLK_CUSTOM_ALLOC` and `MLK_CUSTOM_FREE` if
|
||||
* you want to use custom allocation for large local structures or buffers.
|
||||
*
|
||||
* By default, all buffers/structures are allocated on the stack. If this
|
||||
* option is set, most of them will be allocated via MLK_CUSTOM_ALLOC.
|
||||
*
|
||||
* Parameters to MLK_CUSTOM_ALLOC:
|
||||
* - T* v: Target pointer to declare.
|
||||
* - T: Type of structure to be allocated.
|
||||
* - N: Number of elements to be allocated.
|
||||
*
|
||||
* Parameters to MLK_CUSTOM_FREE:
|
||||
* - T* v: Target pointer to free. May be NULL.
|
||||
* - T: Type of structure to be freed.
|
||||
* - N: Number of elements to be freed.
|
||||
*
|
||||
* @warning This option is experimental. Its scope, configuration and
|
||||
* function/macro signatures may change at any time. We expect a
|
||||
* stable API for v2.
|
||||
*
|
||||
* @note Even if this option is set, some allocations further down the call
|
||||
* stack will still be made from the stack, consuming up to 3KB of
|
||||
* stack space. Those will likely be added to the scope of this
|
||||
* option in the future.
|
||||
*
|
||||
* @note MLK_CUSTOM_ALLOC need not guarantee a successful allocation nor
|
||||
* include error handling. Upon failure, the target pointer should
|
||||
* simply be set to NULL. The calling code will handle this case and
|
||||
* invoke MLK_CUSTOM_FREE.
|
||||
*/
|
||||
/* #define MLK_CONFIG_CUSTOM_ALLOC_FREE
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#include <stdlib.h>
|
||||
#define MLK_CUSTOM_ALLOC(v, T, N) \
|
||||
T* (v) = (T *)aligned_alloc(MLK_DEFAULT_ALIGN, \
|
||||
MLK_ALIGN_UP(sizeof(T) * (N)))
|
||||
#define MLK_CUSTOM_FREE(v, T, N) free(v)
|
||||
#endif
|
||||
*/
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_CUSTOM_MEMCPY
|
||||
*
|
||||
* Set this option and define `mlk_memcpy` if you want to use a custom
|
||||
* method to copy memory instead of the standard library memcpy function.
|
||||
*
|
||||
* The custom implementation must have the same signature and behavior as
|
||||
* the standard memcpy function:
|
||||
* void *mlk_memcpy(void *dest, const void *src, size_t n)
|
||||
*/
|
||||
/* #define MLK_CONFIG_CUSTOM_MEMCPY
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#include <stdint.h>
|
||||
#include "src/sys.h"
|
||||
static MLK_INLINE void *mlk_memcpy(void *dest, const void *src, size_t n)
|
||||
{
|
||||
... your implementation ...
|
||||
}
|
||||
#endif
|
||||
*/
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_CUSTOM_MEMSET
|
||||
*
|
||||
* Set this option and define `mlk_memset` if you want to use a custom
|
||||
* method to set memory instead of the standard library memset function.
|
||||
*
|
||||
* The custom implementation must have the same signature and behavior as
|
||||
* the standard memset function:
|
||||
* void *mlk_memset(void *s, int c, size_t n)
|
||||
*/
|
||||
/* #define MLK_CONFIG_CUSTOM_MEMSET
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#include <stdint.h>
|
||||
#include "src/sys.h"
|
||||
static MLK_INLINE void *mlk_memset(void *s, int c, size_t n)
|
||||
{
|
||||
... your implementation ...
|
||||
}
|
||||
#endif
|
||||
*/
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_INTERNAL_API_QUALIFIER
|
||||
*
|
||||
* If set, this option provides an additional qualifier to be added to
|
||||
* declarations of internal API functions and data.
|
||||
*
|
||||
* The primary use case for this option are single-CU builds, in which case
|
||||
* this option can be set to `static`.
|
||||
*/
|
||||
/* #define MLK_CONFIG_INTERNAL_API_QUALIFIER */
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_CT_TESTING_ENABLED
|
||||
*
|
||||
* If set, mlkem-native annotates data as secret/public using valgrind's
|
||||
* annotations VALGRIND_MAKE_MEM_UNDEFINED and VALGRIND_MAKE_MEM_DEFINED,
|
||||
* enabling various checks for secret-dependent control flow or
|
||||
* variable-time execution (depending on the exact version of valgrind
|
||||
* installed).
|
||||
*/
|
||||
/* #define MLK_CONFIG_CT_TESTING_ENABLED */
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_NO_ASM
|
||||
*
|
||||
* If this option is set, mlkem-native will be built without use of native
|
||||
* code or inline assembly.
|
||||
*
|
||||
* By default, inline assembly is used to implement value barriers. Without
|
||||
* inline assembly, mlkem-native will use a global volatile 'opt blocker'
|
||||
* instead; see verify.h.
|
||||
*
|
||||
* Inline assembly is also used to implement a secure zeroization function
|
||||
* on non-Windows platforms. If this option is set and the target platform
|
||||
* is not Windows, you MUST set MLK_CONFIG_CUSTOM_ZEROIZE and provide a
|
||||
* custom zeroization function.
|
||||
*
|
||||
* If this option is set, MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202 and
|
||||
* MLK_CONFIG_USE_NATIVE_BACKEND_ARITH will be ignored, and no native
|
||||
* backends will be used.
|
||||
*/
|
||||
/* #define MLK_CONFIG_NO_ASM */
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_NO_ASM_VALUE_BARRIER
|
||||
*
|
||||
* If this option is set, mlkem-native will be built without use of native
|
||||
* code or inline assembly for value barriers.
|
||||
*
|
||||
* By default, inline assembly (if available) is used to implement value
|
||||
* barriers. Without inline assembly, mlkem-native will use a global
|
||||
* volatile 'opt blocker' instead; see verify.h.
|
||||
*/
|
||||
/* #define MLK_CONFIG_NO_ASM_VALUE_BARRIER */
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_KEYGEN_PCT
|
||||
*
|
||||
* Compliance with @[FIPS140_3_IG, p.87] requires a Pairwise Consistency
|
||||
* Test (PCT) to be carried out on a freshly generated keypair before it
|
||||
* can be exported.
|
||||
*
|
||||
* Set this option if such a check should be implemented. In this case,
|
||||
* crypto_kem_keypair_derand and crypto_kem_keypair will return a non-zero
|
||||
* error code if the PCT failed.
|
||||
*
|
||||
* @note This feature will drastically lower the performance of key
|
||||
* generation.
|
||||
*/
|
||||
/* #define MLK_CONFIG_KEYGEN_PCT */
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_KEYGEN_PCT_BREAKAGE_TEST
|
||||
*
|
||||
* If this option is set, the user must provide a runtime function
|
||||
* `static inline int mlk_break_pct() { ... }` to indicate whether the PCT
|
||||
* should be made to fail.
|
||||
*
|
||||
* This option only has an effect if MLK_CONFIG_KEYGEN_PCT is set.
|
||||
*/
|
||||
/* #define MLK_CONFIG_KEYGEN_PCT_BREAKAGE_TEST
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#include "src/sys.h"
|
||||
static MLK_INLINE int mlk_break_pct(void)
|
||||
{
|
||||
... return 0/1 depending on whether PCT should be broken ...
|
||||
}
|
||||
#endif
|
||||
*/
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_SERIAL_FIPS202_ONLY
|
||||
*
|
||||
* Set this to use a FIPS202 implementation with global state that supports
|
||||
* only one active Keccak computation at a time (e.g. some hardware
|
||||
* accelerators).
|
||||
*
|
||||
* If this option is set, batched Keccak operations are disabled for
|
||||
* rejection sampling during matrix generation. Instead, matrix entries
|
||||
* will be generated one at a time.
|
||||
*
|
||||
* This allows offloading Keccak computations to a hardware accelerator
|
||||
* that holds only a single Keccak state locally, rather than requiring
|
||||
* support for batched (4x) Keccak states.
|
||||
*
|
||||
* @note Depending on the target CPU, disabling batched Keccak may reduce
|
||||
* performance when using software FIPS202 implementations. Only
|
||||
* enable this when you have to.
|
||||
*/
|
||||
/* #define MLK_CONFIG_SERIAL_FIPS202_ONLY */
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_CONTEXT_PARAMETER
|
||||
*
|
||||
* Set this to add a context parameter that is provided to public API
|
||||
* functions and is then available in custom callbacks.
|
||||
*
|
||||
* The type of the context parameter is configured via
|
||||
* MLK_CONFIG_CONTEXT_PARAMETER_TYPE.
|
||||
*/
|
||||
/* #define MLK_CONFIG_CONTEXT_PARAMETER */
|
||||
|
||||
/**
|
||||
* MLK_CONFIG_CONTEXT_PARAMETER_TYPE
|
||||
*
|
||||
* Set this to define the type for the context parameter used by
|
||||
* MLK_CONFIG_CONTEXT_PARAMETER.
|
||||
*
|
||||
* This is only relevant if MLK_CONFIG_CONTEXT_PARAMETER is set.
|
||||
*/
|
||||
/* #define MLK_CONFIG_CONTEXT_PARAMETER_TYPE void* */
|
||||
|
||||
/************************* Config internals ********************************/
|
||||
|
||||
#endif /* MLK_BUILD_INTERNAL */
|
||||
|
||||
/* Default namespace
|
||||
*
|
||||
* Don't change this. If you need a different namespace, re-define
|
||||
* MLK_CONFIG_NAMESPACE_PREFIX above instead, and remove the following.
|
||||
*
|
||||
* The default MLKEM namespace is
|
||||
*
|
||||
* PQCP_MLKEM_NATIVE_MLKEM<LEVEL>_
|
||||
*
|
||||
* e.g., PQCP_MLKEM_NATIVE_MLKEM512_
|
||||
*/
|
||||
|
||||
#if MLK_CONFIG_PARAMETER_SET == 512
|
||||
#define MLK_DEFAULT_NAMESPACE_PREFIX PQCP_MLKEM_NATIVE_MLKEM512
|
||||
#elif MLK_CONFIG_PARAMETER_SET == 768
|
||||
#define MLK_DEFAULT_NAMESPACE_PREFIX PQCP_MLKEM_NATIVE_MLKEM768
|
||||
#elif MLK_CONFIG_PARAMETER_SET == 1024
|
||||
#define MLK_DEFAULT_NAMESPACE_PREFIX PQCP_MLKEM_NATIVE_MLKEM1024
|
||||
#endif
|
||||
|
||||
#endif /* !MLK_CONFIG_H */
|
||||
@@ -1,197 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
|
||||
#ifndef MLK_CBMC_H
|
||||
#define MLK_CBMC_H
|
||||
/***************************************************
|
||||
* Basic replacements for __CPROVER_XXX contracts
|
||||
***************************************************/
|
||||
/*
|
||||
* The `__contract__` / `__loop__` annotation macros use a
|
||||
* leading-double-underscore spelling in line with other CBMC macros.
|
||||
* clang-tidy flags these as reserved identifiers; we suppress the diagnostic
|
||||
* at each definition site (NOLINT) rather than disabling the check globally,
|
||||
* so it stays active for the rest of the tree.
|
||||
*/
|
||||
#ifndef CBMC
|
||||
|
||||
/* clang-format off */
|
||||
#define __contract__(x) /* NOLINT(bugprone-reserved-identifier,cert-dcl37-c,cert-dcl51-cpp) */
|
||||
#define __loop__(x) /* NOLINT(bugprone-reserved-identifier,cert-dcl37-c,cert-dcl51-cpp) */
|
||||
/* clang-format on */
|
||||
|
||||
#else /* !CBMC */
|
||||
|
||||
|
||||
/* clang-format off */
|
||||
#define __contract__(x) x /* NOLINT(bugprone-reserved-identifier,cert-dcl37-c,cert-dcl51-cpp) */
|
||||
#define __loop__(x) x /* NOLINT(bugprone-reserved-identifier,cert-dcl37-c,cert-dcl51-cpp) */
|
||||
/* clang-format on */
|
||||
|
||||
/* https://diffblue.github.io/cbmc/contracts-assigns.html */
|
||||
#define assigns(...) __CPROVER_assigns(__VA_ARGS__)
|
||||
|
||||
/* https://diffblue.github.io/cbmc/contracts-requires-ensures.html */
|
||||
#define requires(...) __CPROVER_requires(__VA_ARGS__)
|
||||
#define ensures(...) __CPROVER_ensures(__VA_ARGS__)
|
||||
/* https://diffblue.github.io/cbmc/contracts-loops.html */
|
||||
#define invariant(...) __CPROVER_loop_invariant(__VA_ARGS__)
|
||||
#define decreases(...) __CPROVER_decreases(__VA_ARGS__)
|
||||
/* cassert to avoid confusion with in-built assert */
|
||||
#define cassert(x) __CPROVER_assert(x, "cbmc assertion failed")
|
||||
#define assume(...) __CPROVER_assume(__VA_ARGS__)
|
||||
|
||||
/***************************************************
|
||||
* Macros for "expression" forms that may appear
|
||||
* _inside_ top-level contracts.
|
||||
***************************************************/
|
||||
|
||||
/*
|
||||
* function return value - useful inside ensures
|
||||
* https://diffblue.github.io/cbmc/contracts-functions.html
|
||||
*/
|
||||
#define return_value (__CPROVER_return_value)
|
||||
|
||||
/*
|
||||
* assigns l-value targets
|
||||
* https://diffblue.github.io/cbmc/contracts-assigns.html
|
||||
*/
|
||||
#define object_whole(...) __CPROVER_object_whole(__VA_ARGS__)
|
||||
#define memory_slice(...) __CPROVER_object_upto(__VA_ARGS__)
|
||||
|
||||
/*
|
||||
* Pointer-related predicates
|
||||
* https://diffblue.github.io/cbmc/contracts-memory-predicates.html
|
||||
*/
|
||||
#define memory_no_alias(...) __CPROVER_is_fresh(__VA_ARGS__)
|
||||
#define readable(...) __CPROVER_r_ok(__VA_ARGS__)
|
||||
#define writeable(...) __CPROVER_w_ok(__VA_ARGS__)
|
||||
|
||||
/* Maximum supported buffer size
|
||||
*
|
||||
* Larger buffers may be supported, but due to internal modeling constraints
|
||||
* in CBMC, the proofs of memory- and type-safety won't be able to run.
|
||||
*
|
||||
* If you find yourself in need for a buffer size larger than this,
|
||||
* please contact the maintainers, so we can prioritize work to relax
|
||||
* this somewhat artificial bound.
|
||||
*/
|
||||
#define MLK_MAX_BUFFER_SIZE (SIZE_MAX >> 12)
|
||||
|
||||
/*
|
||||
* History variables
|
||||
* https://diffblue.github.io/cbmc/contracts-history-variables.html
|
||||
*/
|
||||
#define old(...) __CPROVER_old(__VA_ARGS__)
|
||||
#define loop_entry(...) __CPROVER_loop_entry(__VA_ARGS__)
|
||||
|
||||
/*
|
||||
* Quantifiers
|
||||
* Note that the range on qvar is _exclusive_ between qvar_lb .. qvar_ub
|
||||
* https://diffblue.github.io/cbmc/contracts-quantifiers.html
|
||||
*
|
||||
* The quantified variable is declared as uint32_t, so these macros
|
||||
* quantify only over indices in [0, UINT32_MAX). Bounds larger than
|
||||
* UINT32_MAX (4 GiB) are NOT supported: the explicit (uint32_t) casts
|
||||
* on the bounds will trigger CBMC's conversion check if a wider bound
|
||||
* (e.g. a size_t > UINT32_MAX) is passed.
|
||||
*
|
||||
* Quantifying over size_t (64-bit) was found to blow up SMT proof
|
||||
* times, so we deliberately keep the index width at 32 bits. Callers
|
||||
* dealing with size_t-typed buffers must add an explicit
|
||||
* requires(len <= UINT32_MAX)
|
||||
* precondition.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Prevent clang-format from corrupting CBMC's special ==> operator
|
||||
*/
|
||||
/* clang-format off */
|
||||
#define forall(qvar, qvar_lb, qvar_ub, predicate) \
|
||||
__CPROVER_forall \
|
||||
{ \
|
||||
uint32_t qvar; \
|
||||
((uint32_t) (qvar_lb) <= (qvar) && (qvar) < (uint32_t) (qvar_ub)) ==> (predicate) \
|
||||
}
|
||||
|
||||
#define exists(qvar, qvar_lb, qvar_ub, predicate) \
|
||||
__CPROVER_exists \
|
||||
{ \
|
||||
uint32_t qvar; \
|
||||
((uint32_t) (qvar_lb) <= (qvar) && (qvar) < (uint32_t) (qvar_ub)) && (predicate) \
|
||||
}
|
||||
/* clang-format on */
|
||||
|
||||
/***************************************************
|
||||
* Convenience macros for common contract patterns
|
||||
***************************************************/
|
||||
|
||||
/*
|
||||
* Boolean-value predidate that asserts that "all values of array_var are in
|
||||
* range value_lb (inclusive) .. value_ub (exclusive)"
|
||||
* Example:
|
||||
* array_bound(a->coeffs, 0, MLKEM_N, 0, MLKEM_Q)
|
||||
* expands to
|
||||
* __CPROVER_forall { int k; (0 <= k && k <= MLKEM_N-1) ==> (
|
||||
* 0 <= a->coeffs[k]) && a->coeffs[k] < MLKEM_Q)) }
|
||||
*/
|
||||
|
||||
/*
|
||||
* Prevent clang-format from corrupting CBMC's special ==> operator
|
||||
*/
|
||||
/* clang-format off */
|
||||
#define CBMC_CONCAT_(left, right) left##right
|
||||
#define CBMC_CONCAT(left, right) CBMC_CONCAT_(left, right)
|
||||
|
||||
#define array_bound_core(qvar, qvar_lb, qvar_ub, array_var, \
|
||||
value_lb, value_ub) \
|
||||
__CPROVER_forall \
|
||||
{ \
|
||||
uint32_t qvar; \
|
||||
((uint32_t) (qvar_lb) <= (qvar) && (qvar) < (uint32_t) (qvar_ub)) ==> \
|
||||
(((int)(value_lb) <= ((array_var)[(qvar)])) && \
|
||||
(((array_var)[(qvar)]) < (int)(value_ub))) \
|
||||
}
|
||||
|
||||
#define array_bound(array_var, qvar_lb, qvar_ub, value_lb, value_ub) \
|
||||
array_bound_core(CBMC_CONCAT(_cbmc_idx, __COUNTER__), (qvar_lb), \
|
||||
(qvar_ub), (array_var), (value_lb), (value_ub))
|
||||
|
||||
#define array_unchanged_core(qvar, qvar_lb, qvar_ub, array_var) \
|
||||
__CPROVER_forall \
|
||||
{ \
|
||||
uint32_t qvar; \
|
||||
((uint32_t) (qvar_lb) <= (qvar) && (qvar) < (uint32_t) (qvar_ub)) ==> \
|
||||
((array_var)[(qvar)]) == (old(* (int16_t (*)[(qvar_ub)])(array_var)))[(qvar)] \
|
||||
}
|
||||
|
||||
#define array_unchanged(array_var, N) \
|
||||
array_unchanged_core(CBMC_CONCAT(_cbmc_idx, __COUNTER__), 0, (N), (array_var))
|
||||
|
||||
#define array_unchanged_u64_core(qvar, qvar_lb, qvar_ub, array_var) \
|
||||
__CPROVER_forall \
|
||||
{ \
|
||||
uint32_t qvar; \
|
||||
((uint32_t) (qvar_lb) <= (qvar) && (qvar) < (uint32_t) (qvar_ub)) ==> \
|
||||
((array_var)[(qvar)]) == (old(* (uint64_t (*)[(qvar_ub)])(array_var)))[(qvar)] \
|
||||
}
|
||||
|
||||
#define array_unchanged_u64(array_var, N) \
|
||||
array_unchanged_u64_core(CBMC_CONCAT(_cbmc_idx, __COUNTER__), 0, (N), (array_var))
|
||||
/* clang-format on */
|
||||
|
||||
/* Wrapper around array_bound operating on absolute values.
|
||||
*
|
||||
* The absolute value bound `k` is exclusive.
|
||||
*
|
||||
* Note that since the lower bound in array_bound is inclusive, we have to
|
||||
* raise it by 1 here.
|
||||
*/
|
||||
#define array_abs_bound(arr, lb, ub, k) \
|
||||
array_bound((arr), (lb), (ub), -((int)(k)) + 1, (k))
|
||||
|
||||
#endif /* CBMC */
|
||||
|
||||
#endif /* !MLK_CBMC_H */
|
||||
@@ -1,282 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
#ifndef MLK_COMMON_H
|
||||
#define MLK_COMMON_H
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
#define MLK_BUILD_INTERNAL
|
||||
|
||||
#if defined(MLK_CONFIG_FILE)
|
||||
#include MLK_CONFIG_FILE
|
||||
#else
|
||||
#include "mlkem_native_config.h"
|
||||
#endif
|
||||
|
||||
#include "params.h"
|
||||
#include "sys.h"
|
||||
|
||||
/* Internal and public API have external linkage by default, but
|
||||
* this can be overwritten by the user, e.g. for single-CU builds. */
|
||||
#if !defined(MLK_CONFIG_INTERNAL_API_QUALIFIER)
|
||||
#define MLK_INTERNAL_API
|
||||
#define MLK_INTERNAL_DATA_DECLARATION extern
|
||||
#define MLK_INTERNAL_DATA_DEFINITION
|
||||
#else
|
||||
#define MLK_INTERNAL_API MLK_CONFIG_INTERNAL_API_QUALIFIER
|
||||
#define MLK_INTERNAL_DATA_DECLARATION MLK_CONFIG_INTERNAL_API_QUALIFIER
|
||||
#define MLK_INTERNAL_DATA_DEFINITION MLK_CONFIG_INTERNAL_API_QUALIFIER
|
||||
#endif
|
||||
|
||||
#if !defined(MLK_CONFIG_EXTERNAL_API_QUALIFIER)
|
||||
#define MLK_EXTERNAL_API
|
||||
#else
|
||||
#define MLK_EXTERNAL_API MLK_CONFIG_EXTERNAL_API_QUALIFIER
|
||||
#endif
|
||||
|
||||
#define MLK_CONCAT_(x1, x2) x1##x2
|
||||
#define MLK_CONCAT(x1, x2) MLK_CONCAT_(x1, x2)
|
||||
|
||||
#if (defined(MLK_CONFIG_MULTILEVEL_WITH_SHARED) || \
|
||||
defined(MLK_CONFIG_MULTILEVEL_NO_SHARED))
|
||||
#define MLK_ADD_PARAM_SET(s) MLK_CONCAT(s, MLK_CONFIG_PARAMETER_SET)
|
||||
#else
|
||||
#define MLK_ADD_PARAM_SET(s) s
|
||||
#endif
|
||||
|
||||
#define MLK_NAMESPACE_PREFIX MLK_CONCAT(MLK_CONFIG_NAMESPACE_PREFIX, _)
|
||||
#define MLK_NAMESPACE_PREFIX_K \
|
||||
MLK_CONCAT(MLK_ADD_PARAM_SET(MLK_CONFIG_NAMESPACE_PREFIX), _)
|
||||
|
||||
/* Functions are prefixed by MLK_CONFIG_NAMESPACE_PREFIX.
|
||||
*
|
||||
* If multiple parameter sets are used, functions depending on the parameter
|
||||
* set are additionally prefixed with 512/768/1024. See mlkem_native_config.h.
|
||||
*
|
||||
* Example: If MLK_CONFIG_NAMESPACE_PREFIX is mlkem, then
|
||||
* MLK_NAMESPACE_K(enc) becomes mlkem512_enc/mlkem768_enc/mlkem1024_enc.
|
||||
*/
|
||||
#define MLK_NAMESPACE(s) MLK_CONCAT(MLK_NAMESPACE_PREFIX, s)
|
||||
#define MLK_NAMESPACE_K(s) MLK_CONCAT(MLK_NAMESPACE_PREFIX_K, s)
|
||||
|
||||
/* On Apple platforms, we need to emit leading underscore
|
||||
* in front of assembly symbols. We thus introducee a separate
|
||||
* namespace wrapper for ASM symbols. */
|
||||
#if !defined(__APPLE__)
|
||||
#define MLK_ASM_NAMESPACE(sym) MLK_NAMESPACE(sym)
|
||||
#else
|
||||
#define MLK_ASM_NAMESPACE(sym) MLK_CONCAT(_, MLK_NAMESPACE(sym))
|
||||
#endif
|
||||
|
||||
/*
|
||||
* On X86_64 if control-flow protections (CET) are enabled (through
|
||||
* -fcf-protection=), we add an endbr64 instruction at every global function
|
||||
* label. See sys.h for more details
|
||||
*/
|
||||
#if defined(MLK_SYS_X86_64)
|
||||
#define MLK_ASM_FN_SYMBOL(sym) MLK_ASM_NAMESPACE(sym) : MLK_CET_ENDBR
|
||||
#elif defined(MLK_SYS_ARMV81M_MVE)
|
||||
/* clang-format off */
|
||||
#define MLK_ASM_FN_SYMBOL(sym) \
|
||||
.type MLK_ASM_NAMESPACE(sym), %function; \
|
||||
MLK_ASM_NAMESPACE(sym) :
|
||||
/* clang-format on */
|
||||
#else /* !MLK_SYS_X86_64 && MLK_SYS_ARMV81M_MVE */
|
||||
#define MLK_ASM_FN_SYMBOL(sym) MLK_ASM_NAMESPACE(sym) :
|
||||
#endif /* !MLK_SYS_X86_64 && !MLK_SYS_ARMV81M_MVE */
|
||||
|
||||
/*
|
||||
* Output the size of an assembly function.
|
||||
*/
|
||||
#if defined(__ELF__)
|
||||
#define MLK_ASM_FN_SIZE(sym) \
|
||||
.size MLK_ASM_NAMESPACE(sym), .- MLK_ASM_NAMESPACE(sym)
|
||||
#else
|
||||
#define MLK_ASM_FN_SIZE(sym)
|
||||
#endif
|
||||
|
||||
/* We aim to simplify the user's life by supporting builds where
|
||||
* all source files are included, even those that are not needed.
|
||||
* Those files are appropriately guarded and will be empty when unneeded.
|
||||
* The following is to avoid compilers complaining about this. */
|
||||
#define MLK_EMPTY_CU(s) extern int MLK_NAMESPACE_K(empty_cu_##s);
|
||||
|
||||
/* MLK_CONFIG_NO_ASM takes precedence over MLK_USE_NATIVE_XXX */
|
||||
#if defined(MLK_CONFIG_NO_ASM)
|
||||
#undef MLK_CONFIG_USE_NATIVE_BACKEND_ARITH
|
||||
#undef MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202
|
||||
#endif
|
||||
|
||||
#if defined(MLK_CONFIG_USE_NATIVE_BACKEND_ARITH) && \
|
||||
!defined(MLK_CONFIG_ARITH_BACKEND_FILE)
|
||||
#error Bad configuration: MLK_CONFIG_USE_NATIVE_BACKEND_ARITH is set, but MLK_CONFIG_ARITH_BACKEND_FILE is not.
|
||||
#endif
|
||||
|
||||
#if defined(MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202) && \
|
||||
!defined(MLK_CONFIG_FIPS202_BACKEND_FILE)
|
||||
#error Bad configuration: MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202 is set, but MLK_CONFIG_FIPS202_BACKEND_FILE is not.
|
||||
#endif
|
||||
|
||||
#if defined(MLK_CONFIG_NO_RANDOMIZED_API) && defined(MLK_CONFIG_KEYGEN_PCT)
|
||||
#error Bad configuration: MLK_CONFIG_NO_RANDOMIZED_API is incompatible with MLK_CONFIG_KEYGEN_PCT as the current PCT implementation requires crypto_kem_enc()
|
||||
#endif
|
||||
|
||||
#if defined(MLK_CONFIG_USE_NATIVE_BACKEND_ARITH)
|
||||
#include MLK_CONFIG_ARITH_BACKEND_FILE
|
||||
/* Include to enforce consistency of API and implementation,
|
||||
* and conduct sanity checks on the backend.
|
||||
*
|
||||
* Keep this _after_ the inclusion of the backend; otherwise,
|
||||
* the sanity checks won't have an effect. */
|
||||
#if defined(MLK_CHECK_APIS) && !defined(__ASSEMBLER__)
|
||||
#include "native/api.h"
|
||||
#endif
|
||||
#endif /* MLK_CONFIG_USE_NATIVE_BACKEND_ARITH */
|
||||
|
||||
#if defined(MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202)
|
||||
#include MLK_CONFIG_FIPS202_BACKEND_FILE
|
||||
/* Include to enforce consistency of API and implementation,
|
||||
* and conduct sanity checks on the backend.
|
||||
*
|
||||
* Keep this _after_ the inclusion of the backend; otherwise,
|
||||
* the sanity checks won't have an effect. */
|
||||
#if defined(MLK_CHECK_APIS) && !defined(__ASSEMBLER__)
|
||||
#include "fips202/native/api.h"
|
||||
#endif
|
||||
#endif /* MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202 */
|
||||
|
||||
#if !defined(MLK_CONFIG_FIPS202_CUSTOM_HEADER)
|
||||
#define MLK_FIPS202_HEADER_FILE "fips202/fips202.h"
|
||||
#else
|
||||
#define MLK_FIPS202_HEADER_FILE MLK_CONFIG_FIPS202_CUSTOM_HEADER
|
||||
#endif
|
||||
|
||||
#if !defined(MLK_CONFIG_FIPS202X4_CUSTOM_HEADER)
|
||||
#define MLK_FIPS202X4_HEADER_FILE "fips202/fips202x4.h"
|
||||
#else
|
||||
#define MLK_FIPS202X4_HEADER_FILE MLK_CONFIG_FIPS202X4_CUSTOM_HEADER
|
||||
#endif
|
||||
|
||||
/* Standard library function replacements */
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#if !defined(MLK_CONFIG_CUSTOM_MEMCPY)
|
||||
#include <string.h>
|
||||
#define mlk_memcpy memcpy
|
||||
#endif
|
||||
|
||||
#if !defined(MLK_CONFIG_CUSTOM_MEMSET)
|
||||
#include <string.h>
|
||||
#define mlk_memset memset
|
||||
#endif
|
||||
|
||||
|
||||
/* Allocation macros for large local structures
|
||||
*
|
||||
* MLK_ALLOC(v, T, N) declares T *v and attempts to point it to an T[N]
|
||||
* MLK_FREE(v, T, N) zeroizes and frees the allocation
|
||||
*
|
||||
* Default implementation uses stack allocation.
|
||||
* Can be overridden by setting the config option MLK_CONFIG_CUSTOM_ALLOC_FREE
|
||||
* and defining MLK_CUSTOM_ALLOC and MLK_CUSTOM_FREE.
|
||||
*/
|
||||
#if defined(MLK_CONFIG_CUSTOM_ALLOC_FREE) != \
|
||||
(defined(MLK_CUSTOM_ALLOC) && defined(MLK_CUSTOM_FREE))
|
||||
#error Bad configuration: MLK_CONFIG_CUSTOM_ALLOC_FREE must be set together with MLK_CUSTOM_ALLOC and MLK_CUSTOM_FREE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* If the integration wants to provide a context parameter for use in
|
||||
* platform-specific hooks, then it should define this parameter.
|
||||
*
|
||||
* The MLK_CONTEXT_PARAMETERS_n macros are intended to be used with macros
|
||||
* defining the function names and expand to either pass or discard the context
|
||||
* argument as required by the current build. If there is no context parameter
|
||||
* requested then these are removed from the prototypes and from all calls.
|
||||
*/
|
||||
#ifdef MLK_CONFIG_CONTEXT_PARAMETER
|
||||
#define MLK_CONTEXT_PARAMETERS_0(context) (context)
|
||||
#define MLK_CONTEXT_PARAMETERS_1(arg0, context) (arg0, context)
|
||||
#define MLK_CONTEXT_PARAMETERS_2(arg0, arg1, context) (arg0, arg1, context)
|
||||
#define MLK_CONTEXT_PARAMETERS_3(arg0, arg1, arg2, context) \
|
||||
(arg0, arg1, arg2, context)
|
||||
#define MLK_CONTEXT_PARAMETERS_4(arg0, arg1, arg2, arg3, context) \
|
||||
(arg0, arg1, arg2, arg3, context)
|
||||
#else /* MLK_CONFIG_CONTEXT_PARAMETER */
|
||||
#define MLK_CONTEXT_PARAMETERS_0(context) ()
|
||||
#define MLK_CONTEXT_PARAMETERS_1(arg0, context) (arg0)
|
||||
#define MLK_CONTEXT_PARAMETERS_2(arg0, arg1, context) (arg0, arg1)
|
||||
#define MLK_CONTEXT_PARAMETERS_3(arg0, arg1, arg2, context) (arg0, arg1, arg2)
|
||||
#define MLK_CONTEXT_PARAMETERS_4(arg0, arg1, arg2, arg3, context) \
|
||||
(arg0, arg1, arg2, arg3)
|
||||
#endif /* !MLK_CONFIG_CONTEXT_PARAMETER */
|
||||
|
||||
#if defined(MLK_CONFIG_CONTEXT_PARAMETER_TYPE) != \
|
||||
defined(MLK_CONFIG_CONTEXT_PARAMETER)
|
||||
#error MLK_CONFIG_CONTEXT_PARAMETER_TYPE must be defined if and only if MLK_CONFIG_CONTEXT_PARAMETER is defined
|
||||
#endif
|
||||
|
||||
#if !defined(MLK_CONFIG_CUSTOM_ALLOC_FREE)
|
||||
/* Default: stack allocation */
|
||||
|
||||
/* This is a declaration macro, not an expression macro: T is a type and v is
|
||||
* a declarator, neither of which can be wrapped in parentheses. The
|
||||
* bugprone-macro-parentheses diagnostic is therefore a false positive here. */
|
||||
#define MLK_ALLOC(v, T, N, context) \
|
||||
MLK_ALIGN T mlk_alloc_##v[N]; \
|
||||
T *v = mlk_alloc_##v /* NOLINT(bugprone-macro-parentheses) */
|
||||
|
||||
/* The MLK_FREE macro body references mlk_zeroize(), which is declared in
|
||||
* verify.h. We deliberately do NOT include verify.h here: doing so would
|
||||
* create a circular dependency (verify.h includes common.h), and common.h
|
||||
* itself never calls mlk_zeroize() -- only the macro expansion does. Each
|
||||
* translation unit that uses MLK_FREE therefore includes verify.h directly. */
|
||||
#define MLK_FREE(v, T, N, context) \
|
||||
do \
|
||||
{ \
|
||||
mlk_zeroize(mlk_alloc_##v, sizeof(mlk_alloc_##v)); \
|
||||
(v) = NULL; \
|
||||
} while (0)
|
||||
|
||||
#else /* !MLK_CONFIG_CUSTOM_ALLOC_FREE */
|
||||
|
||||
/* Custom allocation */
|
||||
|
||||
/*
|
||||
* The indirection here is necessary to use MLK_CONTEXT_PARAMETERS_3 here.
|
||||
*/
|
||||
#define MLK_APPLY(f, args) f args
|
||||
|
||||
#define MLK_ALLOC(v, T, N, context) \
|
||||
MLK_APPLY(MLK_CUSTOM_ALLOC, MLK_CONTEXT_PARAMETERS_3(v, T, N, context))
|
||||
|
||||
#define MLK_FREE(v, T, N, context) \
|
||||
do \
|
||||
{ \
|
||||
if (v != NULL) \
|
||||
{ \
|
||||
mlk_zeroize(v, sizeof(T) * (N)); \
|
||||
MLK_APPLY(MLK_CUSTOM_FREE, MLK_CONTEXT_PARAMETERS_3(v, T, N, context)); \
|
||||
v = NULL; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#endif /* MLK_CONFIG_CUSTOM_ALLOC_FREE */
|
||||
|
||||
/****************************** Error codes ***********************************/
|
||||
|
||||
/* Generic failure condition */
|
||||
#define MLK_ERR_FAIL (-1)
|
||||
/* An allocation failed. This can only happen if MLK_CONFIG_CUSTOM_ALLOC_FREE
|
||||
* is defined and the provided MLK_CUSTOM_ALLOC can fail. */
|
||||
#define MLK_ERR_OUT_OF_MEMORY (-2)
|
||||
/* An rng failure occured. Might be due to insufficient entropy or
|
||||
* system misconfiguration. */
|
||||
#define MLK_ERR_RNG_FAIL (-3)
|
||||
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
|
||||
#endif /* !MLK_COMMON_H */
|
||||
@@ -1,743 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
|
||||
/* References
|
||||
* ==========
|
||||
*
|
||||
* - [FIPS203]
|
||||
* FIPS 203 Module-Lattice-Based Key-Encapsulation Mechanism Standard
|
||||
* National Institute of Standards and Technology
|
||||
* https://csrc.nist.gov/pubs/fips/203/final
|
||||
*
|
||||
* - [REF]
|
||||
* CRYSTALS-Kyber C reference implementation
|
||||
* Bos, Ducas, Kiltz, Lepoint, Lyubashevsky, Schanck, Schwabe, Seiler, Stehlé
|
||||
* https://github.com/pq-crystals/kyber/tree/main/ref
|
||||
*/
|
||||
|
||||
#include "common.h"
|
||||
#if !defined(MLK_CONFIG_MULTILEVEL_NO_SHARED)
|
||||
|
||||
|
||||
#include "cbmc.h"
|
||||
#include "compress.h"
|
||||
#include "debug.h"
|
||||
#include "verify.h"
|
||||
|
||||
#if defined(MLK_CONFIG_MULTILEVEL_WITH_SHARED) || (MLKEM_K == 2 || MLKEM_K == 3)
|
||||
/* Reference: `poly_compress()` in the reference implementation @[REF],
|
||||
* for ML-KEM-{512,768}.
|
||||
* - In contrast to the reference implementation, we assume
|
||||
* unsigned canonical coefficients here.
|
||||
* The reference implementation works with coefficients
|
||||
* in the range [-(MLKEM_Q-1), MLKEM_Q-1]. */
|
||||
MLK_STATIC_TESTABLE void mlk_poly_compress_d4_c(
|
||||
uint8_t r[MLKEM_POLYCOMPRESSEDBYTES_D4], const mlk_poly *a)
|
||||
__contract__(
|
||||
requires(memory_no_alias(r, MLKEM_POLYCOMPRESSEDBYTES_D4))
|
||||
requires(memory_no_alias(a, sizeof(mlk_poly)))
|
||||
requires(array_bound(a->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
assigns(memory_slice(r, MLKEM_POLYCOMPRESSEDBYTES_D4))
|
||||
)
|
||||
{
|
||||
unsigned i;
|
||||
mlk_assert_bound(a, MLKEM_N, 0, MLKEM_Q);
|
||||
|
||||
for (i = 0; i < MLKEM_N / 8; i++)
|
||||
__loop__(invariant(i <= MLKEM_N / 8)
|
||||
decreases(MLKEM_N / 8 - i))
|
||||
{
|
||||
unsigned j;
|
||||
uint8_t t[8] = {0};
|
||||
for (j = 0; j < 8; j++)
|
||||
__loop__(
|
||||
invariant(i <= MLKEM_N / 8 && j <= 8)
|
||||
invariant(array_bound(t, 0, j, 0, 16))
|
||||
decreases(8 - j))
|
||||
{
|
||||
t[j] = mlk_scalar_compress_d4(a->coeffs[8 * i + j]);
|
||||
}
|
||||
|
||||
/* All t[i] are 4-bit wide, so the truncations don't alter the value. */
|
||||
r[i * 4] = (uint8_t)(t[0] | (t[1] << 4));
|
||||
r[i * 4 + 1] = (uint8_t)(t[2] | (t[3] << 4));
|
||||
r[i * 4 + 2] = (uint8_t)(t[4] | (t[5] << 4));
|
||||
r[i * 4 + 3] = (uint8_t)(t[6] | (t[7] << 4));
|
||||
}
|
||||
}
|
||||
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_compress_d4(uint8_t r[MLKEM_POLYCOMPRESSEDBYTES_D4],
|
||||
const mlk_poly *a)
|
||||
__contract__(
|
||||
requires(memory_no_alias(r, MLKEM_POLYCOMPRESSEDBYTES_D4))
|
||||
requires(memory_no_alias(a, sizeof(mlk_poly)))
|
||||
requires(array_bound(a->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
assigns(memory_slice(r, MLKEM_POLYCOMPRESSEDBYTES_D4))
|
||||
)
|
||||
{
|
||||
#if defined(MLK_USE_NATIVE_POLY_COMPRESS_D4)
|
||||
int ret;
|
||||
mlk_assert_bound(a, MLKEM_N, 0, MLKEM_Q);
|
||||
ret = mlk_poly_compress_d4_native(r, a->coeffs);
|
||||
if (ret == MLK_NATIVE_FUNC_SUCCESS)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif /* MLK_USE_NATIVE_POLY_COMPRESS_D4 */
|
||||
|
||||
mlk_poly_compress_d4_c(r, a);
|
||||
}
|
||||
|
||||
/* Reference: Embedded into `polyvec_compress()` in the
|
||||
* reference implementation, for ML-KEM-{512,768}.
|
||||
* - In contrast to the reference implementation, we assume
|
||||
* unsigned canonical coefficients here.
|
||||
* The reference implementation works with coefficients
|
||||
* in the range [-(MLKEM_Q-1), MLKEM_Q-1]. */
|
||||
MLK_STATIC_TESTABLE void mlk_poly_compress_d10_c(
|
||||
uint8_t r[MLKEM_POLYCOMPRESSEDBYTES_D10], const mlk_poly *a)
|
||||
__contract__(
|
||||
requires(memory_no_alias(r, MLKEM_POLYCOMPRESSEDBYTES_D10))
|
||||
requires(memory_no_alias(a, sizeof(mlk_poly)))
|
||||
requires(array_bound(a->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
assigns(memory_slice(r, MLKEM_POLYCOMPRESSEDBYTES_D10))
|
||||
)
|
||||
{
|
||||
unsigned j;
|
||||
mlk_assert_bound(a, MLKEM_N, 0, MLKEM_Q);
|
||||
for (j = 0; j < MLKEM_N / 4; j++)
|
||||
__loop__(invariant(j <= MLKEM_N / 4)
|
||||
decreases(MLKEM_N / 4 - j))
|
||||
{
|
||||
unsigned k;
|
||||
uint16_t t[4];
|
||||
for (k = 0; k < 4; k++)
|
||||
__loop__(
|
||||
invariant(k <= 4)
|
||||
invariant(forall(r, 0, k, t[r] < (1u << 10)))
|
||||
decreases(4 - k))
|
||||
{
|
||||
t[k] = mlk_scalar_compress_d10(a->coeffs[4 * j + k]);
|
||||
}
|
||||
|
||||
/*
|
||||
* Make all implicit truncation explicit. No data is being
|
||||
* truncated for the LHS's since each t[i] is 10-bit in size.
|
||||
*/
|
||||
r[5 * j + 0] = (uint8_t)((t[0] >> 0) & 0xFF);
|
||||
r[5 * j + 1] = (uint8_t)((t[0] >> 8) | ((t[1] << 2) & 0xFF));
|
||||
r[5 * j + 2] = (uint8_t)((t[1] >> 6) | ((t[2] << 4) & 0xFF));
|
||||
r[5 * j + 3] = (uint8_t)((t[2] >> 4) | ((t[3] << 6) & 0xFF));
|
||||
r[5 * j + 4] = (uint8_t)(t[3] >> 2);
|
||||
}
|
||||
}
|
||||
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_compress_d10(uint8_t r[MLKEM_POLYCOMPRESSEDBYTES_D10],
|
||||
const mlk_poly *a)
|
||||
__contract__(
|
||||
requires(memory_no_alias(r, MLKEM_POLYCOMPRESSEDBYTES_D10))
|
||||
requires(memory_no_alias(a, sizeof(mlk_poly)))
|
||||
requires(array_bound(a->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
assigns(memory_slice(r, MLKEM_POLYCOMPRESSEDBYTES_D10))
|
||||
)
|
||||
{
|
||||
#if defined(MLK_USE_NATIVE_POLY_COMPRESS_D10)
|
||||
int ret;
|
||||
mlk_assert_bound(a, MLKEM_N, 0, MLKEM_Q);
|
||||
ret = mlk_poly_compress_d10_native(r, a->coeffs);
|
||||
if (ret == MLK_NATIVE_FUNC_SUCCESS)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif /* MLK_USE_NATIVE_POLY_COMPRESS_D10 */
|
||||
|
||||
mlk_poly_compress_d10_c(r, a);
|
||||
}
|
||||
|
||||
/* Reference: `poly_decompress()` in the reference implementation @[REF],
|
||||
* for ML-KEM-{512,768}. */
|
||||
MLK_STATIC_TESTABLE void mlk_poly_decompress_d4_c(
|
||||
mlk_poly *r, const uint8_t a[MLKEM_POLYCOMPRESSEDBYTES_D4])
|
||||
__contract__(
|
||||
requires(memory_no_alias(r, sizeof(mlk_poly)))
|
||||
requires(memory_no_alias(a, MLKEM_POLYCOMPRESSEDBYTES_D4))
|
||||
assigns(memory_slice(r, sizeof(mlk_poly)))
|
||||
ensures(array_bound(r->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
)
|
||||
{
|
||||
unsigned i;
|
||||
for (i = 0; i < MLKEM_N / 2; i++)
|
||||
__loop__(
|
||||
invariant(i <= MLKEM_N / 2)
|
||||
invariant(array_bound(r->coeffs, 0, 2 * i, 0, MLKEM_Q))
|
||||
decreases(MLKEM_N / 2 - i))
|
||||
{
|
||||
r->coeffs[2 * i + 0] = mlk_scalar_decompress_d4((a[i] >> 0) & 0xF);
|
||||
r->coeffs[2 * i + 1] = mlk_scalar_decompress_d4((a[i] >> 4) & 0xF);
|
||||
}
|
||||
|
||||
mlk_assert_bound(r, MLKEM_N, 0, MLKEM_Q);
|
||||
}
|
||||
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_decompress_d4(mlk_poly *r,
|
||||
const uint8_t a[MLKEM_POLYCOMPRESSEDBYTES_D4])
|
||||
__contract__(
|
||||
requires(memory_no_alias(r, sizeof(mlk_poly)))
|
||||
requires(memory_no_alias(a, MLKEM_POLYCOMPRESSEDBYTES_D4))
|
||||
assigns(memory_slice(r, sizeof(mlk_poly)))
|
||||
ensures(array_bound(r->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
)
|
||||
{
|
||||
#if defined(MLK_USE_NATIVE_POLY_DECOMPRESS_D4)
|
||||
int ret;
|
||||
ret = mlk_poly_decompress_d4_native(r->coeffs, a);
|
||||
if (ret == MLK_NATIVE_FUNC_SUCCESS)
|
||||
{
|
||||
mlk_assert_bound(r, MLKEM_N, 0, MLKEM_Q);
|
||||
return;
|
||||
}
|
||||
#endif /* MLK_USE_NATIVE_POLY_DECOMPRESS_D4 */
|
||||
|
||||
mlk_poly_decompress_d4_c(r, a);
|
||||
}
|
||||
|
||||
/* Reference: Embedded into `polyvec_decompress()` in the
|
||||
* reference implementation, for ML-KEM-{512,768}. */
|
||||
MLK_STATIC_TESTABLE void mlk_poly_decompress_d10_c(
|
||||
mlk_poly *r, const uint8_t a[MLKEM_POLYCOMPRESSEDBYTES_D10])
|
||||
__contract__(
|
||||
requires(memory_no_alias(r, sizeof(mlk_poly)))
|
||||
requires(memory_no_alias(a, MLKEM_POLYCOMPRESSEDBYTES_D10))
|
||||
assigns(memory_slice(r, sizeof(mlk_poly)))
|
||||
ensures(array_bound(r->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
)
|
||||
{
|
||||
unsigned j;
|
||||
for (j = 0; j < MLKEM_N / 4; j++)
|
||||
__loop__(
|
||||
invariant(j <= MLKEM_N / 4)
|
||||
invariant(array_bound(r->coeffs, 0, 4 * j, 0, MLKEM_Q))
|
||||
decreases(MLKEM_N / 4 - j))
|
||||
{
|
||||
unsigned k;
|
||||
uint16_t t[4];
|
||||
uint8_t const *base = &a[5 * j];
|
||||
|
||||
t[0] = 0x3FF & ((base[0] >> 0) | ((uint16_t)base[1] << 8));
|
||||
t[1] = 0x3FF & ((base[1] >> 2) | ((uint16_t)base[2] << 6));
|
||||
t[2] = 0x3FF & ((base[2] >> 4) | ((uint16_t)base[3] << 4));
|
||||
t[3] = 0x3FF & ((base[3] >> 6) | ((uint16_t)base[4] << 2));
|
||||
|
||||
for (k = 0; k < 4; k++)
|
||||
__loop__(
|
||||
invariant(k <= 4)
|
||||
invariant(array_bound(r->coeffs, 0, 4 * j + k, 0, MLKEM_Q))
|
||||
decreases(4 - k))
|
||||
{
|
||||
r->coeffs[4 * j + k] = mlk_scalar_decompress_d10(t[k]);
|
||||
}
|
||||
}
|
||||
|
||||
mlk_assert_bound(r, MLKEM_N, 0, MLKEM_Q);
|
||||
}
|
||||
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_decompress_d10(mlk_poly *r,
|
||||
const uint8_t a[MLKEM_POLYCOMPRESSEDBYTES_D10])
|
||||
__contract__(
|
||||
requires(memory_no_alias(r, sizeof(mlk_poly)))
|
||||
requires(memory_no_alias(a, MLKEM_POLYCOMPRESSEDBYTES_D10))
|
||||
assigns(memory_slice(r, sizeof(mlk_poly)))
|
||||
ensures(array_bound(r->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
)
|
||||
{
|
||||
#if defined(MLK_USE_NATIVE_POLY_DECOMPRESS_D10)
|
||||
int ret;
|
||||
ret = mlk_poly_decompress_d10_native(r->coeffs, a);
|
||||
if (ret == MLK_NATIVE_FUNC_SUCCESS)
|
||||
{
|
||||
mlk_assert_bound(r, MLKEM_N, 0, MLKEM_Q);
|
||||
return;
|
||||
}
|
||||
#endif /* MLK_USE_NATIVE_POLY_DECOMPRESS_D10 */
|
||||
|
||||
mlk_poly_decompress_d10_c(r, a);
|
||||
}
|
||||
#endif /* MLK_CONFIG_MULTILEVEL_WITH_SHARED || MLKEM_K == 2 || MLKEM_K == 3 */
|
||||
|
||||
#if defined(MLK_CONFIG_MULTILEVEL_WITH_SHARED) || MLKEM_K == 4
|
||||
/* Reference: `poly_compress()` in the reference implementation @[REF],
|
||||
* for ML-KEM-1024.
|
||||
* - In contrast to the reference implementation, we assume
|
||||
* unsigned canonical coefficients here.
|
||||
* The reference implementation works with coefficients
|
||||
* in the range [-(MLKEM_Q-1), MLKEM_Q-1]. */
|
||||
MLK_STATIC_TESTABLE void mlk_poly_compress_d5_c(
|
||||
uint8_t r[MLKEM_POLYCOMPRESSEDBYTES_D5], const mlk_poly *a)
|
||||
__contract__(
|
||||
requires(memory_no_alias(r, MLKEM_POLYCOMPRESSEDBYTES_D5))
|
||||
requires(memory_no_alias(a, sizeof(mlk_poly)))
|
||||
requires(array_bound(a->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
assigns(memory_slice(r, MLKEM_POLYCOMPRESSEDBYTES_D5))
|
||||
)
|
||||
{
|
||||
unsigned i;
|
||||
mlk_assert_bound(a, MLKEM_N, 0, MLKEM_Q);
|
||||
|
||||
for (i = 0; i < MLKEM_N / 8; i++)
|
||||
__loop__(invariant(i <= MLKEM_N / 8)
|
||||
decreases(MLKEM_N / 8 - i))
|
||||
{
|
||||
unsigned j;
|
||||
uint8_t t[8] = {0};
|
||||
for (j = 0; j < 8; j++)
|
||||
__loop__(
|
||||
invariant(i <= MLKEM_N / 8 && j <= 8)
|
||||
invariant(array_bound(t, 0, j, 0, 32))
|
||||
decreases(8 - j))
|
||||
{
|
||||
t[j] = mlk_scalar_compress_d5(a->coeffs[8 * i + j]);
|
||||
}
|
||||
|
||||
r[i * 5] = (uint8_t)(0xFF & ((t[0] >> 0) | (t[1] << 5)));
|
||||
r[i * 5 + 1] = (uint8_t)(0xFF & ((t[1] >> 3) | (t[2] << 2) | (t[3] << 7)));
|
||||
r[i * 5 + 2] = (uint8_t)(0xFF & ((t[3] >> 1) | (t[4] << 4)));
|
||||
r[i * 5 + 3] = (uint8_t)(0xFF & ((t[4] >> 4) | (t[5] << 1) | (t[6] << 6)));
|
||||
r[i * 5 + 4] = (uint8_t)(0xFF & ((t[6] >> 2) | (t[7] << 3)));
|
||||
}
|
||||
}
|
||||
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_compress_d5(uint8_t r[MLKEM_POLYCOMPRESSEDBYTES_D5],
|
||||
const mlk_poly *a)
|
||||
__contract__(
|
||||
requires(memory_no_alias(r, MLKEM_POLYCOMPRESSEDBYTES_D5))
|
||||
requires(memory_no_alias(a, sizeof(mlk_poly)))
|
||||
requires(array_bound(a->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
assigns(memory_slice(r, MLKEM_POLYCOMPRESSEDBYTES_D5))
|
||||
)
|
||||
{
|
||||
#if defined(MLK_USE_NATIVE_POLY_COMPRESS_D5)
|
||||
int ret;
|
||||
mlk_assert_bound(a, MLKEM_N, 0, MLKEM_Q);
|
||||
ret = mlk_poly_compress_d5_native(r, a->coeffs);
|
||||
if (ret == MLK_NATIVE_FUNC_SUCCESS)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif /* MLK_USE_NATIVE_POLY_COMPRESS_D5 */
|
||||
|
||||
mlk_poly_compress_d5_c(r, a);
|
||||
}
|
||||
|
||||
/* Reference: Embedded into `polyvec_compress()` in the
|
||||
* reference implementation, for ML-KEM-1024.
|
||||
* - In contrast to the reference implementation, we assume
|
||||
* unsigned canonical coefficients here.
|
||||
* The reference implementation works with coefficients
|
||||
* in the range [-(MLKEM_Q-1), MLKEM_Q-1]. */
|
||||
MLK_STATIC_TESTABLE void mlk_poly_compress_d11_c(
|
||||
uint8_t r[MLKEM_POLYCOMPRESSEDBYTES_D11], const mlk_poly *a)
|
||||
__contract__(
|
||||
requires(memory_no_alias(r, MLKEM_POLYCOMPRESSEDBYTES_D11))
|
||||
requires(memory_no_alias(a, sizeof(mlk_poly)))
|
||||
requires(array_bound(a->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
assigns(memory_slice(r, MLKEM_POLYCOMPRESSEDBYTES_D11))
|
||||
)
|
||||
{
|
||||
unsigned j;
|
||||
mlk_assert_bound(a, MLKEM_N, 0, MLKEM_Q);
|
||||
|
||||
for (j = 0; j < MLKEM_N / 8; j++)
|
||||
__loop__(invariant(j <= MLKEM_N / 8)
|
||||
decreases(MLKEM_N / 8 - j))
|
||||
{
|
||||
unsigned k;
|
||||
uint16_t t[8];
|
||||
for (k = 0; k < 8; k++)
|
||||
__loop__(
|
||||
invariant(k <= 8)
|
||||
invariant(forall(r, 0, k, t[r] < (1u << 11)))
|
||||
decreases(8 - k))
|
||||
{
|
||||
t[k] = mlk_scalar_compress_d11(a->coeffs[8 * j + k]);
|
||||
}
|
||||
|
||||
/*
|
||||
* Make all implicit truncation explicit. No data is being
|
||||
* truncated for the LHS's since each t[i] is 11-bit in size.
|
||||
*/
|
||||
r[11 * j + 0] = (uint8_t)((t[0] >> 0) & 0xFF);
|
||||
r[11 * j + 1] = (uint8_t)((t[0] >> 8) | ((t[1] << 3) & 0xFF));
|
||||
r[11 * j + 2] = (uint8_t)((t[1] >> 5) | ((t[2] << 6) & 0xFF));
|
||||
r[11 * j + 3] = (uint8_t)((t[2] >> 2) & 0xFF);
|
||||
r[11 * j + 4] = (uint8_t)((t[2] >> 10) | ((t[3] << 1) & 0xFF));
|
||||
r[11 * j + 5] = (uint8_t)((t[3] >> 7) | ((t[4] << 4) & 0xFF));
|
||||
r[11 * j + 6] = (uint8_t)((t[4] >> 4) | ((t[5] << 7) & 0xFF));
|
||||
r[11 * j + 7] = (uint8_t)((t[5] >> 1) & 0xFF);
|
||||
r[11 * j + 8] = (uint8_t)((t[5] >> 9) | ((t[6] << 2) & 0xFF));
|
||||
r[11 * j + 9] = (uint8_t)((t[6] >> 6) | ((t[7] << 5) & 0xFF));
|
||||
r[11 * j + 10] = (uint8_t)(t[7] >> 3);
|
||||
}
|
||||
}
|
||||
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_compress_d11(uint8_t r[MLKEM_POLYCOMPRESSEDBYTES_D11],
|
||||
const mlk_poly *a)
|
||||
__contract__(
|
||||
requires(memory_no_alias(r, MLKEM_POLYCOMPRESSEDBYTES_D11))
|
||||
requires(memory_no_alias(a, sizeof(mlk_poly)))
|
||||
requires(array_bound(a->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
assigns(memory_slice(r, MLKEM_POLYCOMPRESSEDBYTES_D11))
|
||||
)
|
||||
{
|
||||
#if defined(MLK_USE_NATIVE_POLY_COMPRESS_D11)
|
||||
int ret;
|
||||
mlk_assert_bound(a, MLKEM_N, 0, MLKEM_Q);
|
||||
ret = mlk_poly_compress_d11_native(r, a->coeffs);
|
||||
if (ret == MLK_NATIVE_FUNC_SUCCESS)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif /* MLK_USE_NATIVE_POLY_COMPRESS_D11 */
|
||||
|
||||
mlk_poly_compress_d11_c(r, a);
|
||||
}
|
||||
|
||||
/* Reference: `poly_decompress()` in the reference implementation @[REF],
|
||||
* for ML-KEM-1024. */
|
||||
MLK_STATIC_TESTABLE void mlk_poly_decompress_d5_c(
|
||||
mlk_poly *r, const uint8_t a[MLKEM_POLYCOMPRESSEDBYTES_D5])
|
||||
__contract__(
|
||||
requires(memory_no_alias(r, sizeof(mlk_poly)))
|
||||
requires(memory_no_alias(a, MLKEM_POLYCOMPRESSEDBYTES_D5))
|
||||
assigns(memory_slice(r, sizeof(mlk_poly)))
|
||||
ensures(array_bound(r->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
)
|
||||
{
|
||||
unsigned i;
|
||||
for (i = 0; i < MLKEM_N / 8; i++)
|
||||
__loop__(
|
||||
invariant(i <= MLKEM_N / 8)
|
||||
invariant(array_bound(r->coeffs, 0, 8 * i, 0, MLKEM_Q))
|
||||
decreases(MLKEM_N / 8 - i))
|
||||
{
|
||||
unsigned j;
|
||||
uint8_t t[8];
|
||||
const unsigned offset = i * 5;
|
||||
/*
|
||||
* Explicitly truncate to avoid warning about
|
||||
* implicit truncation in CBMC and unwind loop for ease
|
||||
* of proof.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Decompress 5 8-bit bytes (so 40 bits) into
|
||||
* 8 5-bit values stored in t[]
|
||||
*/
|
||||
t[0] = 0x1F & (a[offset + 0] >> 0);
|
||||
t[1] = 0x1F & ((a[offset + 0] >> 5) | (a[offset + 1] << 3));
|
||||
t[2] = 0x1F & (a[offset + 1] >> 2);
|
||||
t[3] = 0x1F & ((a[offset + 1] >> 7) | (a[offset + 2] << 1));
|
||||
t[4] = 0x1F & ((a[offset + 2] >> 4) | (a[offset + 3] << 4));
|
||||
t[5] = 0x1F & (a[offset + 3] >> 1);
|
||||
t[6] = 0x1F & ((a[offset + 3] >> 6) | (a[offset + 4] << 2));
|
||||
t[7] = 0x1F & (a[offset + 4] >> 3);
|
||||
|
||||
/* and copy to the correct slice in r[] */
|
||||
for (j = 0; j < 8; j++)
|
||||
__loop__(
|
||||
invariant(j <= 8 && i <= MLKEM_N / 8)
|
||||
invariant(array_bound(r->coeffs, 0, 8 * i + j, 0, MLKEM_Q))
|
||||
decreases(8 - j))
|
||||
{
|
||||
r->coeffs[8 * i + j] = mlk_scalar_decompress_d5(t[j]);
|
||||
}
|
||||
}
|
||||
|
||||
mlk_assert_bound(r, MLKEM_N, 0, MLKEM_Q);
|
||||
}
|
||||
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_decompress_d5(mlk_poly *r,
|
||||
const uint8_t a[MLKEM_POLYCOMPRESSEDBYTES_D5])
|
||||
__contract__(
|
||||
requires(memory_no_alias(r, sizeof(mlk_poly)))
|
||||
requires(memory_no_alias(a, MLKEM_POLYCOMPRESSEDBYTES_D5))
|
||||
assigns(memory_slice(r, sizeof(mlk_poly)))
|
||||
ensures(array_bound(r->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
)
|
||||
{
|
||||
#if defined(MLK_USE_NATIVE_POLY_DECOMPRESS_D5)
|
||||
int ret;
|
||||
ret = mlk_poly_decompress_d5_native(r->coeffs, a);
|
||||
if (ret == MLK_NATIVE_FUNC_SUCCESS)
|
||||
{
|
||||
mlk_assert_bound(r, MLKEM_N, 0, MLKEM_Q);
|
||||
return;
|
||||
}
|
||||
#endif /* MLK_USE_NATIVE_POLY_DECOMPRESS_D5 */
|
||||
|
||||
mlk_poly_decompress_d5_c(r, a);
|
||||
}
|
||||
|
||||
/* Reference: Embedded into `polyvec_decompress()` in the
|
||||
* reference implementation, for ML-KEM-1024. */
|
||||
MLK_STATIC_TESTABLE void mlk_poly_decompress_d11_c(
|
||||
mlk_poly *r, const uint8_t a[MLKEM_POLYCOMPRESSEDBYTES_D11])
|
||||
__contract__(
|
||||
requires(memory_no_alias(r, sizeof(mlk_poly)))
|
||||
requires(memory_no_alias(a, MLKEM_POLYCOMPRESSEDBYTES_D11))
|
||||
assigns(memory_slice(r, sizeof(mlk_poly)))
|
||||
ensures(array_bound(r->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
)
|
||||
{
|
||||
unsigned j;
|
||||
for (j = 0; j < MLKEM_N / 8; j++)
|
||||
__loop__(
|
||||
invariant(j <= MLKEM_N / 8)
|
||||
invariant(array_bound(r->coeffs, 0, 8 * j, 0, MLKEM_Q))
|
||||
decreases(MLKEM_N / 8 - j))
|
||||
{
|
||||
unsigned k;
|
||||
uint16_t t[8];
|
||||
uint8_t const *base = &a[11 * j];
|
||||
t[0] = 0x7FF & ((base[0] >> 0) | ((uint16_t)base[1] << 8));
|
||||
t[1] = 0x7FF & ((base[1] >> 3) | ((uint16_t)base[2] << 5));
|
||||
t[2] = 0x7FF & ((base[2] >> 6) | ((uint16_t)base[3] << 2) |
|
||||
((uint16_t)base[4] << 10));
|
||||
t[3] = 0x7FF & ((base[4] >> 1) | ((uint16_t)base[5] << 7));
|
||||
t[4] = 0x7FF & ((base[5] >> 4) | ((uint16_t)base[6] << 4));
|
||||
t[5] = 0x7FF & ((base[6] >> 7) | ((uint16_t)base[7] << 1) |
|
||||
((uint16_t)base[8] << 9));
|
||||
t[6] = 0x7FF & ((base[8] >> 2) | ((uint16_t)base[9] << 6));
|
||||
t[7] = 0x7FF & ((base[9] >> 5) | ((uint16_t)base[10] << 3));
|
||||
|
||||
for (k = 0; k < 8; k++)
|
||||
__loop__(
|
||||
invariant(k <= 8)
|
||||
invariant(array_bound(r->coeffs, 0, 8 * j + k, 0, MLKEM_Q))
|
||||
decreases(8 - k))
|
||||
{
|
||||
r->coeffs[8 * j + k] = mlk_scalar_decompress_d11(t[k]);
|
||||
}
|
||||
}
|
||||
|
||||
mlk_assert_bound(r, MLKEM_N, 0, MLKEM_Q);
|
||||
}
|
||||
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_decompress_d11(mlk_poly *r,
|
||||
const uint8_t a[MLKEM_POLYCOMPRESSEDBYTES_D11])
|
||||
__contract__(
|
||||
requires(memory_no_alias(r, sizeof(mlk_poly)))
|
||||
requires(memory_no_alias(a, MLKEM_POLYCOMPRESSEDBYTES_D11))
|
||||
assigns(memory_slice(r, sizeof(mlk_poly)))
|
||||
ensures(array_bound(r->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
)
|
||||
{
|
||||
#if defined(MLK_USE_NATIVE_POLY_DECOMPRESS_D11)
|
||||
int ret;
|
||||
ret = mlk_poly_decompress_d11_native(r->coeffs, a);
|
||||
if (ret == MLK_NATIVE_FUNC_SUCCESS)
|
||||
{
|
||||
mlk_assert_bound(r, MLKEM_N, 0, MLKEM_Q);
|
||||
return;
|
||||
}
|
||||
#endif /* MLK_USE_NATIVE_POLY_DECOMPRESS_D11 */
|
||||
|
||||
mlk_poly_decompress_d11_c(r, a);
|
||||
}
|
||||
|
||||
#endif /* MLK_CONFIG_MULTILEVEL_WITH_SHARED || MLKEM_K == 4 */
|
||||
|
||||
/* Reference: `poly_tobytes()` in the reference implementation @[REF].
|
||||
* - In contrast to the reference implementation, we assume
|
||||
* unsigned canonical coefficients here.
|
||||
* The reference implementation works with coefficients
|
||||
* in the range [-(MLKEM_Q-1), MLKEM_Q-1]. */
|
||||
MLK_STATIC_TESTABLE void mlk_poly_tobytes_c(uint8_t r[MLKEM_POLYBYTES],
|
||||
const mlk_poly *a)
|
||||
__contract__(
|
||||
requires(memory_no_alias(r, MLKEM_POLYBYTES))
|
||||
requires(memory_no_alias(a, sizeof(mlk_poly)))
|
||||
requires(array_bound(a->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
assigns(memory_slice(r, MLKEM_POLYBYTES))
|
||||
)
|
||||
{
|
||||
unsigned i;
|
||||
mlk_assert_bound(a, MLKEM_N, 0, MLKEM_Q);
|
||||
|
||||
for (i = 0; i < MLKEM_N / 2; i++)
|
||||
__loop__(invariant(i <= MLKEM_N / 2)
|
||||
decreases(MLKEM_N / 2 - i))
|
||||
{
|
||||
/* The conversion to uint16_t is safe since we assume that
|
||||
* the coefficients of `a` are non-negative. */
|
||||
const uint16_t t0 = (uint16_t)a->coeffs[2 * i];
|
||||
const uint16_t t1 = (uint16_t)a->coeffs[2 * i + 1];
|
||||
/*
|
||||
* t0 and t1 are both < MLKEM_Q, so contain at most 12 bits each of
|
||||
* significant data, so these can be packed into 24 bits or exactly
|
||||
* 3 bytes, as follows.
|
||||
*/
|
||||
|
||||
/* Least significant bits 0 - 7 of t0. */
|
||||
r[3 * i + 0] = (uint8_t)(t0 & 0xFF);
|
||||
|
||||
/*
|
||||
* Most significant bits 8 - 11 of t0 become the least significant
|
||||
* nibble of the second byte. The least significant 4 bits
|
||||
* of t1 become the upper nibble of the second byte.
|
||||
*
|
||||
* The conversion to uint8_t does not alter the value.
|
||||
*/
|
||||
r[3 * i + 1] = (uint8_t)((t0 >> 8) | ((t1 << 4) & 0xF0));
|
||||
|
||||
/* Bits 4 - 11 of t1 become the third byte. The conversion to uint8_t
|
||||
* does not alter the value because t1 is 12-bit wide. */
|
||||
r[3 * i + 2] = (uint8_t)(t1 >> 4);
|
||||
}
|
||||
}
|
||||
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_tobytes(uint8_t r[MLKEM_POLYBYTES], const mlk_poly *a)
|
||||
{
|
||||
#if defined(MLK_USE_NATIVE_POLY_TOBYTES)
|
||||
int ret;
|
||||
mlk_assert_bound(a, MLKEM_N, 0, MLKEM_Q);
|
||||
ret = mlk_poly_tobytes_native(r, a->coeffs);
|
||||
if (ret == MLK_NATIVE_FUNC_SUCCESS)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif /* MLK_USE_NATIVE_POLY_TOBYTES */
|
||||
|
||||
mlk_poly_tobytes_c(r, a);
|
||||
}
|
||||
|
||||
/* Reference: `poly_frombytes()` in the reference implementation @[REF]. */
|
||||
MLK_STATIC_TESTABLE void mlk_poly_frombytes_c(mlk_poly *r,
|
||||
const uint8_t a[MLKEM_POLYBYTES])
|
||||
__contract__(
|
||||
requires(memory_no_alias(a, MLKEM_POLYBYTES))
|
||||
requires(memory_no_alias(r, sizeof(mlk_poly)))
|
||||
assigns(memory_slice(r, sizeof(mlk_poly)))
|
||||
ensures(array_bound(r->coeffs, 0, MLKEM_N, 0, MLKEM_UINT12_LIMIT))
|
||||
)
|
||||
{
|
||||
unsigned i;
|
||||
for (i = 0; i < MLKEM_N / 2; i++)
|
||||
__loop__(
|
||||
invariant(i <= MLKEM_N / 2)
|
||||
invariant(array_bound(r->coeffs, 0, 2 * i, 0, MLKEM_UINT12_LIMIT))
|
||||
decreases(MLKEM_N / 2 - i))
|
||||
{
|
||||
const uint8_t t0 = a[3 * i + 0];
|
||||
const uint8_t t1 = a[3 * i + 1];
|
||||
const uint8_t t2 = a[3 * i + 2];
|
||||
/* Safety:
|
||||
* - The explicit cast to uint16_t ensures that << 8 does
|
||||
* not signed-overflow even on a 16-bit system.
|
||||
* - The cast to int16_t is safe due to the explicit 0xFFF truncation.
|
||||
*/
|
||||
r->coeffs[2 * i + 0] = (int16_t)(t0 | (((uint16_t)t1 << 8) & 0xFFF));
|
||||
r->coeffs[2 * i + 1] = (int16_t)((t1 >> 4) | (t2 << 4));
|
||||
}
|
||||
|
||||
/* Note that the coefficients are not canonical */
|
||||
mlk_assert_bound(r, MLKEM_N, 0, MLKEM_UINT12_LIMIT);
|
||||
}
|
||||
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_frombytes(mlk_poly *r, const uint8_t a[MLKEM_POLYBYTES])
|
||||
{
|
||||
#if defined(MLK_USE_NATIVE_POLY_FROMBYTES)
|
||||
int ret;
|
||||
ret = mlk_poly_frombytes_native(r->coeffs, a);
|
||||
if (ret == MLK_NATIVE_FUNC_SUCCESS)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif /* MLK_USE_NATIVE_POLY_FROMBYTES */
|
||||
|
||||
mlk_poly_frombytes_c(r, a);
|
||||
}
|
||||
|
||||
/* Reference: `poly_frommsg()` in the reference implementation @[REF].
|
||||
* - We use a value barrier around the bit-selection mask to
|
||||
* reduce the risk of compiler-introduced branches.
|
||||
* The reference implementation contains the expression
|
||||
* `(msg[i] >> j) & 1` which the compiler can reason must
|
||||
* be either 0 or 1. */
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_frommsg(mlk_poly *r, const uint8_t msg[MLKEM_INDCPA_MSGBYTES])
|
||||
{
|
||||
unsigned i;
|
||||
#if (MLKEM_INDCPA_MSGBYTES != MLKEM_N / 8)
|
||||
#error "MLKEM_INDCPA_MSGBYTES must be equal to MLKEM_N/8 bytes!"
|
||||
#endif
|
||||
|
||||
for (i = 0; i < MLKEM_N / 8; i++)
|
||||
__loop__(
|
||||
invariant(i <= MLKEM_N / 8)
|
||||
invariant(array_bound(r->coeffs, 0, 8 * i, 0, MLKEM_Q))
|
||||
decreases(MLKEM_N / 8 - i))
|
||||
{
|
||||
unsigned j;
|
||||
for (j = 0; j < 8; j++)
|
||||
__loop__(
|
||||
invariant(i < MLKEM_N / 8 && j <= 8)
|
||||
invariant(array_bound(r->coeffs, 0, 8 * i + j, 0, MLKEM_Q))
|
||||
decreases(8 - j))
|
||||
{
|
||||
/* mlk_ct_sel_int16(MLKEM_Q_HALF, 0, b) is `Decompress_1(b != 0)`
|
||||
* as per @[FIPS203, Eq (4.8)]. */
|
||||
|
||||
/* Prevent the compiler from recognizing this as a bit selection */
|
||||
uint8_t mask = mlk_value_barrier_u8((uint8_t)(1u << j));
|
||||
r->coeffs[8 * i + j] = mlk_ct_sel_int16(MLKEM_Q_HALF, 0, msg[i] & mask);
|
||||
}
|
||||
}
|
||||
mlk_assert_abs_bound(r, MLKEM_N, MLKEM_Q);
|
||||
}
|
||||
|
||||
/* Reference: `poly_tomsg()` in the reference implementation @[REF].
|
||||
* - In contrast to the reference implementation, we assume
|
||||
* unsigned canonical coefficients here.
|
||||
* The reference implementation works with coefficients
|
||||
* in the range [-(MLKEM_Q-1), MLKEM_Q-1].
|
||||
*/
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_tomsg(uint8_t msg[MLKEM_INDCPA_MSGBYTES], const mlk_poly *r)
|
||||
{
|
||||
unsigned i;
|
||||
mlk_assert_bound(r, MLKEM_N, 0, MLKEM_Q);
|
||||
|
||||
for (i = 0; i < MLKEM_N / 8; i++)
|
||||
__loop__(invariant(i <= MLKEM_N / 8)
|
||||
decreases(MLKEM_N / 8 - i))
|
||||
{
|
||||
unsigned j;
|
||||
msg[i] = 0;
|
||||
for (j = 0; j < 8; j++)
|
||||
__loop__(
|
||||
invariant(i <= MLKEM_N / 8 && j <= 8)
|
||||
decreases(8 - j))
|
||||
{
|
||||
uint32_t t = mlk_scalar_compress_d1(r->coeffs[8 * i + j]);
|
||||
msg[i] |= (uint8_t)(t << j);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#else /* !MLK_CONFIG_MULTILEVEL_NO_SHARED */
|
||||
|
||||
MLK_EMPTY_CU(compress)
|
||||
|
||||
#endif /* MLK_CONFIG_MULTILEVEL_NO_SHARED */
|
||||
@@ -1,599 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
|
||||
/* References
|
||||
* ==========
|
||||
*
|
||||
* - [FIPS203]
|
||||
* FIPS 203 Module-Lattice-Based Key-Encapsulation Mechanism Standard
|
||||
* National Institute of Standards and Technology
|
||||
* https://csrc.nist.gov/pubs/fips/203/final
|
||||
*
|
||||
* - [REF]
|
||||
* CRYSTALS-Kyber C reference implementation
|
||||
* Bos, Ducas, Kiltz, Lepoint, Lyubashevsky, Schanck, Schwabe, Seiler, Stehlé
|
||||
* https://github.com/pq-crystals/kyber/tree/main/ref
|
||||
*/
|
||||
|
||||
#ifndef MLK_COMPRESS_H
|
||||
#define MLK_COMPRESS_H
|
||||
|
||||
|
||||
#include "cbmc.h"
|
||||
#include "common.h"
|
||||
#include "debug.h"
|
||||
#include "poly.h"
|
||||
#include "verify.h"
|
||||
|
||||
/*
|
||||
* The multiplication in this routine will exceed UINT32_MAX
|
||||
* and wrap around for large values of u. This is expected and required.
|
||||
*/
|
||||
#ifdef CBMC
|
||||
#pragma CPROVER check push
|
||||
#pragma CPROVER check disable "unsigned-overflow"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Compute round(u * 2 / MLKEM_Q).
|
||||
*
|
||||
* @spec{Compress_1 from @[FIPS203, Eq (4.7)].}
|
||||
*
|
||||
* @reference{Part of poly_tomsg() in the reference implementation @[REF].}
|
||||
*
|
||||
* @param u Unsigned canonical modulus modulo MLKEM_Q to be compressed.
|
||||
*
|
||||
* @return Compressed value.
|
||||
*/
|
||||
static MLK_INLINE uint8_t mlk_scalar_compress_d1(int16_t u)
|
||||
__contract__(
|
||||
requires(0 <= u && u <= MLKEM_Q - 1)
|
||||
ensures(return_value < 2)
|
||||
ensures(return_value == (((uint32_t)u * 2 + MLKEM_Q / 2) / MLKEM_Q) % 2) )
|
||||
{
|
||||
/* Compute as follows:
|
||||
* ```
|
||||
* round(u * 2 / MLKEM_Q)
|
||||
* = round(u * 2 * (2^31 / MLKEM_Q) / 2^31)
|
||||
* ~= round(u * 2 * round(2^31 / MLKEM_Q) / 2^31)
|
||||
* ```
|
||||
*/
|
||||
/* check-magic: 1290168 == 2*round(2^31 / MLKEM_Q) */
|
||||
uint32_t d0 = (uint32_t)u * 1290168;
|
||||
/* Unsigned shifting by 31 positions leaves only the top bit. */
|
||||
return (uint8_t)((d0 + ((uint32_t)1u << 30)) >> 31);
|
||||
}
|
||||
#ifdef CBMC
|
||||
#pragma CPROVER check pop
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The multiplication in this routine will exceed UINT32_MAX
|
||||
* and wrap around for large values of u. This is expected and required.
|
||||
*/
|
||||
#ifdef CBMC
|
||||
#pragma CPROVER check push
|
||||
#pragma CPROVER check disable "unsigned-overflow"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Compute round(u * 16 / MLKEM_Q) % 16.
|
||||
*
|
||||
* @spec{Compress_4 from @[FIPS203, Eq (4.7)].}
|
||||
*
|
||||
* @reference{Embedded into `poly_compress()` in the reference
|
||||
* implementation @[REF].}
|
||||
*
|
||||
* @param u Unsigned canonical modulus modulo MLKEM_Q to be compressed.
|
||||
*
|
||||
* @return Compressed value.
|
||||
*/
|
||||
static MLK_INLINE uint8_t mlk_scalar_compress_d4(int16_t u)
|
||||
__contract__(
|
||||
requires(0 <= u && u <= MLKEM_Q - 1)
|
||||
ensures(return_value < 16)
|
||||
ensures(return_value == (((uint32_t)u * 16 + MLKEM_Q / 2) / MLKEM_Q) % 16))
|
||||
{
|
||||
/* Compute as follows:
|
||||
* ```
|
||||
* round(u * 16 / MLKEM_Q)
|
||||
* = round(u * 16 * (2^28 / MLKEM_Q) / 2^28)
|
||||
* ~= round(u * 16 * round(2^28 / MLKEM_Q) / 2^28)
|
||||
* ```
|
||||
*/
|
||||
/* check-magic: 1290160 == 16 * round(2^28 / MLKEM_Q) */
|
||||
uint32_t d0 = (uint32_t)u * 1290160;
|
||||
/* The return value is < 16, so not altered by the conversion to uint8_t. */
|
||||
return (uint8_t)((d0 + ((uint32_t)1u << 27)) >> 28); /* round(d0/2^28) */
|
||||
}
|
||||
#ifdef CBMC
|
||||
#pragma CPROVER check pop
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Compute round(u * MLKEM_Q / 16).
|
||||
*
|
||||
* @spec{Decompress_4 from @[FIPS203, Eq (4.8)].}
|
||||
*
|
||||
* @reference{Embedded into `poly_decompress()` in the reference
|
||||
* implementation @[REF].}
|
||||
*
|
||||
* @param u Unsigned canonical modulus modulo 16 to be decompressed.
|
||||
*
|
||||
* @return Decompressed value.
|
||||
*/
|
||||
static MLK_INLINE int16_t mlk_scalar_decompress_d4(uint8_t u)
|
||||
__contract__(
|
||||
requires(0 <= u && u < 16)
|
||||
ensures(return_value <= (MLKEM_Q - 1))
|
||||
)
|
||||
{
|
||||
/* The return value is in 0..MLKEM_Q-1, hence not altered by the
|
||||
* conversion to int16_t. */
|
||||
return (int16_t)((((uint32_t)u * MLKEM_Q) + 8) >> 4);
|
||||
}
|
||||
|
||||
/*
|
||||
* The multiplication in this routine will exceed UINT32_MAX
|
||||
* and wrap around for large values of u. This is expected and required.
|
||||
*/
|
||||
#ifdef CBMC
|
||||
#pragma CPROVER check push
|
||||
#pragma CPROVER check disable "unsigned-overflow"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Compute round(u * 32 / MLKEM_Q) % 32.
|
||||
*
|
||||
* @spec{Compress_5 from @[FIPS203, Eq (4.7)].}
|
||||
*
|
||||
* @reference{Embedded into `poly_compress()` in the reference
|
||||
* implementation @[REF].}
|
||||
*
|
||||
* @param u Unsigned canonical modulus modulo MLKEM_Q to be compressed.
|
||||
*
|
||||
* @return Compressed value.
|
||||
*/
|
||||
static MLK_INLINE uint8_t mlk_scalar_compress_d5(int16_t u)
|
||||
__contract__(
|
||||
requires(0 <= u && u <= MLKEM_Q - 1)
|
||||
ensures(return_value < 32)
|
||||
ensures(return_value == (((uint32_t)u * 32 + MLKEM_Q / 2) / MLKEM_Q) % 32) )
|
||||
{
|
||||
/* Compute as follows:
|
||||
* ```
|
||||
* round(u * 32 / MLKEM_Q)
|
||||
* = round(u * 32 * (2^27 / MLKEM_Q) / 2^27)
|
||||
* ~= round(u * 32 * round(2^27 / MLKEM_Q) / 2^27)
|
||||
* ```
|
||||
*/
|
||||
/* check-magic: 1290176 == 2^5 * round(2^27 / MLKEM_Q) */
|
||||
uint32_t d0 = (uint32_t)u * 1290176;
|
||||
/* The return value is < 32, so not altered by the conversion to uint8_t. */
|
||||
return (uint8_t)((d0 + ((uint32_t)1u << 26)) >> 27); /* round(d0/2^27) */
|
||||
}
|
||||
#ifdef CBMC
|
||||
#pragma CPROVER check pop
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Compute round(u * MLKEM_Q / 32).
|
||||
*
|
||||
* @spec{Decompress_5 from @[FIPS203, Eq (4.8)].}
|
||||
*
|
||||
* @reference{Embedded into `poly_decompress()` in the reference
|
||||
* implementation @[REF].}
|
||||
*
|
||||
* @param u Unsigned canonical modulus modulo 32 to be decompressed.
|
||||
*
|
||||
* @return Decompressed value.
|
||||
*/
|
||||
static MLK_INLINE int16_t mlk_scalar_decompress_d5(uint8_t u)
|
||||
__contract__(
|
||||
requires(0 <= u && u < 32)
|
||||
ensures(0 <= return_value && return_value <= MLKEM_Q - 1)
|
||||
)
|
||||
{
|
||||
/* The return value is in 0..MLKEM_Q-1, hence not altered by the
|
||||
* conversion to int16_t. */
|
||||
return (int16_t)((((uint32_t)u * MLKEM_Q) + 16) >> 5);
|
||||
}
|
||||
|
||||
/*
|
||||
* The multiplication in this routine will exceed UINT32_MAX
|
||||
* and wrap around for large values of u. This is expected and required.
|
||||
*/
|
||||
#ifdef CBMC
|
||||
#pragma CPROVER check push
|
||||
#pragma CPROVER check disable "unsigned-overflow"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Compute round(u * 2**10 / MLKEM_Q) % 2**10.
|
||||
*
|
||||
* @spec{Compress_10 from @[FIPS203, Eq (4.7)].}
|
||||
*
|
||||
* @reference{Embedded into `polyvec_compress()` in the reference
|
||||
* implementation @[REF].}
|
||||
*
|
||||
* @param u Unsigned canonical modulus modulo MLKEM_Q to be compressed.
|
||||
*
|
||||
* @return Compressed value.
|
||||
*/
|
||||
static MLK_INLINE uint16_t mlk_scalar_compress_d10(int16_t u)
|
||||
__contract__(
|
||||
requires(0 <= u && u <= MLKEM_Q - 1)
|
||||
ensures(return_value < (1u << 10))
|
||||
ensures(return_value == (((uint32_t)u * (1u << 10) + MLKEM_Q / 2) / MLKEM_Q) % (1 << 10)))
|
||||
{
|
||||
/* Compute as follows:
|
||||
* ```
|
||||
* round(u * 1024 / MLKEM_Q)
|
||||
* = round(u * 1024 * (2^33 / MLKEM_Q) / 2^33)
|
||||
* ~= round(u * 1024 * round(2^33 / MLKEM_Q) / 2^33)
|
||||
* ```
|
||||
*/
|
||||
/* check-magic: 2642263040 == 2^10 * round(2^33 / MLKEM_Q) */
|
||||
uint64_t d0 = (uint64_t)u * 2642263040;
|
||||
d0 = (d0 + ((uint64_t)1u << 32)) >> 33; /* round(d0/2^33) */
|
||||
return (d0 & 0x3FF);
|
||||
}
|
||||
#ifdef CBMC
|
||||
#pragma CPROVER check pop
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Compute round(u * MLKEM_Q / 1024).
|
||||
*
|
||||
* @spec{Decompress_10 from @[FIPS203, Eq (4.8)].}
|
||||
*
|
||||
* @reference{Embedded into `polyvec_decompress()` in the reference
|
||||
* implementation @[REF].}
|
||||
*
|
||||
* @param u Unsigned canonical modulus modulo 1024 to be decompressed.
|
||||
*
|
||||
* @return Decompressed value.
|
||||
*/
|
||||
static MLK_INLINE int16_t mlk_scalar_decompress_d10(uint16_t u)
|
||||
__contract__(
|
||||
requires(0 <= u && u < 1024)
|
||||
ensures(0 <= return_value && return_value <= (MLKEM_Q - 1))
|
||||
)
|
||||
{
|
||||
/* The return value is in 0..MLKEM_Q-1, hence not altered by the
|
||||
* conversion to int16_t. */
|
||||
return (int16_t)((((uint32_t)u * MLKEM_Q) + 512) >> 10);
|
||||
}
|
||||
|
||||
/*
|
||||
* The multiplication in this routine will exceed UINT32_MAX
|
||||
* and wrap around for large values of u. This is expected and required.
|
||||
*/
|
||||
#ifdef CBMC
|
||||
#pragma CPROVER check push
|
||||
#pragma CPROVER check disable "unsigned-overflow"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Compute round(u * 2**11 / MLKEM_Q) % 2**11.
|
||||
*
|
||||
* @spec{Compress_11 from @[FIPS203, Eq (4.7)].}
|
||||
*
|
||||
* @reference{Embedded into `polyvec_compress()` in the reference
|
||||
* implementation @[REF].}
|
||||
*
|
||||
* @param u Unsigned canonical modulus modulo MLKEM_Q to be compressed.
|
||||
*
|
||||
* @return Compressed value.
|
||||
*/
|
||||
static MLK_INLINE uint16_t mlk_scalar_compress_d11(int16_t u)
|
||||
__contract__(
|
||||
requires(0 <= u && u <= MLKEM_Q - 1)
|
||||
ensures(return_value < (1u << 11))
|
||||
ensures(return_value == (((uint32_t)u * (1u << 11) + MLKEM_Q / 2) / MLKEM_Q) % (1 << 11)))
|
||||
{
|
||||
/* Compute as follows:
|
||||
* ```
|
||||
* round(u * 2048 / MLKEM_Q)
|
||||
* = round(u * 2048 * (2^33 / MLKEM_Q) / 2^33)
|
||||
* ~= round(u * 2048 * round(2^33 / MLKEM_Q) / 2^33)
|
||||
* ```
|
||||
*/
|
||||
/* check-magic: 5284526080 == 2^11 * round(2^33 / MLKEM_Q) */
|
||||
uint64_t d0 = (uint64_t)u * 5284526080;
|
||||
d0 = (d0 + ((uint64_t)1u << 32)) >> 33; /* round(d0/2^33) */
|
||||
return (d0 & 0x7FF);
|
||||
}
|
||||
#ifdef CBMC
|
||||
#pragma CPROVER check pop
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Compute round(u * MLKEM_Q / 2048).
|
||||
*
|
||||
* @spec{Decompress_11 from @[FIPS203, Eq (4.8)].}
|
||||
*
|
||||
* @reference{Embedded into `polyvec_decompress()` in the reference
|
||||
* implementation @[REF].}
|
||||
*
|
||||
* @param u Unsigned canonical modulus modulo 2048 to be decompressed.
|
||||
*
|
||||
* @return Decompressed value.
|
||||
*/
|
||||
static MLK_INLINE int16_t mlk_scalar_decompress_d11(uint16_t u)
|
||||
__contract__(
|
||||
requires(0 <= u && u < 2048)
|
||||
ensures(0 <= return_value && return_value <= (MLKEM_Q - 1))
|
||||
)
|
||||
{
|
||||
/* The return value is in 0..MLKEM_Q-1, hence not altered by the
|
||||
* conversion to int16_t. */
|
||||
return (int16_t)((((uint32_t)u * MLKEM_Q) + 1024) >> 11);
|
||||
}
|
||||
|
||||
#if defined(MLK_CONFIG_MULTILEVEL_WITH_SHARED) || (MLKEM_K == 2 || MLKEM_K == 3)
|
||||
#define mlk_poly_compress_d4 MLK_NAMESPACE(poly_compress_d4)
|
||||
/**
|
||||
* Compression (4 bits) and subsequent serialization of a polynomial.
|
||||
*
|
||||
* @spec{Implements `ByteEncode_4 (Compress_4 (a))`: ByteEncode_d
|
||||
* @[FIPS203, Algorithm 5], Compress_d @[FIPS203, Eq (4.7)], extended to
|
||||
* vectors as per @[FIPS203, 2.4.8 Applying Algorithms to Arrays].
|
||||
* `ByteEncode_{d_v} (Compress_{d_v} (v))` appears in @[FIPS203, Algorithm
|
||||
* 14 (K-PKE.Encrypt), L23], where `d_v=4` for ML-KEM-{512,768} @[FIPS203,
|
||||
* Table 2].}
|
||||
*
|
||||
* @param[out] r Output byte array (of length MLKEM_POLYCOMPRESSEDBYTES_D4
|
||||
* bytes).
|
||||
* @param[in] a Input polynomial. Coefficients must be unsigned canonical,
|
||||
* i.e. in [0,1,..,MLKEM_Q-1].
|
||||
*/
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_compress_d4(uint8_t r[MLKEM_POLYCOMPRESSEDBYTES_D4],
|
||||
const mlk_poly *a);
|
||||
|
||||
#define mlk_poly_compress_d10 MLK_NAMESPACE(poly_compress_d10)
|
||||
/**
|
||||
* Compression (10 bits) and subsequent serialization of a polynomial.
|
||||
*
|
||||
* @spec{Implements `ByteEncode_10 (Compress_10 (a))`: ByteEncode_d
|
||||
* @[FIPS203, Algorithm 5], Compress_d @[FIPS203, Eq (4.7)], extended to
|
||||
* vectors as per @[FIPS203, 2.4.8 Applying Algorithms to Arrays].
|
||||
* `ByteEncode_{d_u} (Compress_{d_u} (u))` appears in @[FIPS203, Algorithm
|
||||
* 14 (K-PKE.Encrypt), L22], where `d_u=10` for ML-KEM-{512,768} @[FIPS203,
|
||||
* Table 2].}
|
||||
*
|
||||
* @param[out] r Output byte array (of length MLKEM_POLYCOMPRESSEDBYTES_D10
|
||||
* bytes).
|
||||
* @param[in] a Input polynomial. Coefficients must be unsigned canonical,
|
||||
* i.e. in [0,1,..,MLKEM_Q-1].
|
||||
*/
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_compress_d10(uint8_t r[MLKEM_POLYCOMPRESSEDBYTES_D10],
|
||||
const mlk_poly *a);
|
||||
|
||||
#define mlk_poly_decompress_d4 MLK_NAMESPACE(poly_decompress_d4)
|
||||
/**
|
||||
* De-serialization and subsequent decompression (4 bits) of a polynomial;
|
||||
* approximate inverse of mlk_poly_compress_d4.
|
||||
*
|
||||
* Upon return, the coefficients of the output polynomial are
|
||||
* unsigned-canonical (non-negative and smaller than MLKEM_Q).
|
||||
*
|
||||
* @spec{Implements `Decompress_4 (ByteDecode_4 (a))`: ByteDecode_d
|
||||
* @[FIPS203, Algorithm 6], Decompress_d @[FIPS203, Eq (4.8)], extended to
|
||||
* vectors as per @[FIPS203, 2.4.8 Applying Algorithms to Arrays].
|
||||
* `Decompress_{d_v} (ByteDecode_{d_v} (v))` appears in @[FIPS203, Algorithm
|
||||
* 15 (K-PKE.Decrypt), L4], where `d_v=4` for ML-KEM-{512,768} @[FIPS203,
|
||||
* Table 2].}
|
||||
*
|
||||
* @param[out] r Output polynomial.
|
||||
* @param[in] a Input byte array (of length MLKEM_POLYCOMPRESSEDBYTES_D4
|
||||
* bytes).
|
||||
*/
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_decompress_d4(mlk_poly *r,
|
||||
const uint8_t a[MLKEM_POLYCOMPRESSEDBYTES_D4]);
|
||||
|
||||
#define mlk_poly_decompress_d10 MLK_NAMESPACE(poly_decompress_d10)
|
||||
/**
|
||||
* De-serialization and subsequent decompression (10 bits) of a polynomial;
|
||||
* approximate inverse of mlk_poly_compress_d10.
|
||||
*
|
||||
* Upon return, the coefficients of the output polynomial are
|
||||
* unsigned-canonical (non-negative and smaller than MLKEM_Q).
|
||||
*
|
||||
* @spec{Implements `Decompress_10 (ByteDecode_10 (a))`: ByteDecode_d
|
||||
* @[FIPS203, Algorithm 6], Decompress_d @[FIPS203, Eq (4.8)], extended to
|
||||
* vectors as per @[FIPS203, 2.4.8 Applying Algorithms to Arrays].
|
||||
* `Decompress_{d_u} (ByteDecode_{d_u} (u))` appears in @[FIPS203, Algorithm
|
||||
* 15 (K-PKE.Decrypt), L3], where `d_u=10` for ML-KEM-{512,768} @[FIPS203,
|
||||
* Table 2].}
|
||||
*
|
||||
* @param[out] r Output polynomial.
|
||||
* @param[in] a Input byte array (of length MLKEM_POLYCOMPRESSEDBYTES_D10
|
||||
* bytes).
|
||||
*/
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_decompress_d10(mlk_poly *r,
|
||||
const uint8_t a[MLKEM_POLYCOMPRESSEDBYTES_D10]);
|
||||
#endif /* MLK_CONFIG_MULTILEVEL_WITH_SHARED || MLKEM_K == 2 || MLKEM_K == 3 */
|
||||
|
||||
#if defined(MLK_CONFIG_MULTILEVEL_WITH_SHARED) || MLKEM_K == 4
|
||||
#define mlk_poly_compress_d5 MLK_NAMESPACE(poly_compress_d5)
|
||||
/**
|
||||
* Compression (5 bits) and subsequent serialization of a polynomial.
|
||||
*
|
||||
* @spec{Implements `ByteEncode_5 (Compress_5 (a))`: ByteEncode_d
|
||||
* @[FIPS203, Algorithm 5], Compress_d @[FIPS203, Eq (4.7)], extended to
|
||||
* vectors as per @[FIPS203, 2.4.8 Applying Algorithms to Arrays].
|
||||
* `ByteEncode_{d_v} (Compress_{d_v} (v))` appears in @[FIPS203, Algorithm
|
||||
* 14 (K-PKE.Encrypt), L23], where `d_v=5` for ML-KEM-1024 @[FIPS203,
|
||||
* Table 2].}
|
||||
*
|
||||
* @param[out] r Output byte array (of length MLKEM_POLYCOMPRESSEDBYTES_D5
|
||||
* bytes).
|
||||
* @param[in] a Input polynomial. Coefficients must be unsigned canonical,
|
||||
* i.e. in [0,1,..,MLKEM_Q-1].
|
||||
*/
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_compress_d5(uint8_t r[MLKEM_POLYCOMPRESSEDBYTES_D5],
|
||||
const mlk_poly *a);
|
||||
|
||||
#define mlk_poly_compress_d11 MLK_NAMESPACE(poly_compress_d11)
|
||||
/**
|
||||
* Compression (11 bits) and subsequent serialization of a polynomial.
|
||||
*
|
||||
* @spec{`ByteEncode_11 (Compress_11 (a))`: ByteEncode_d @[FIPS203,
|
||||
* Algorithm 5], Compress_d @[FIPS203, Eq (4.7)], extended to vectors as
|
||||
* per @[FIPS203, 2.4.8 Applying Algorithms to Arrays].
|
||||
* `ByteEncode_{d_u} (Compress_{d_u} (u))` appears in @[FIPS203, Algorithm
|
||||
* 14 (K-PKE.Encrypt), L22], where `d_u=11` for ML-KEM-1024 @[FIPS203,
|
||||
* Table 2].}
|
||||
*
|
||||
* @param[out] r Output byte array (of length MLKEM_POLYCOMPRESSEDBYTES_D11
|
||||
* bytes).
|
||||
* @param[in] a Input polynomial. Coefficients must be unsigned canonical,
|
||||
* i.e. in [0,1,..,MLKEM_Q-1].
|
||||
*/
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_compress_d11(uint8_t r[MLKEM_POLYCOMPRESSEDBYTES_D11],
|
||||
const mlk_poly *a);
|
||||
|
||||
#define mlk_poly_decompress_d5 MLK_NAMESPACE(poly_decompress_d5)
|
||||
/**
|
||||
* De-serialization and subsequent decompression (5 bits) of a polynomial;
|
||||
* approximate inverse of mlk_poly_compress_d5.
|
||||
*
|
||||
* Upon return, the coefficients of the output polynomial are
|
||||
* unsigned-canonical (non-negative and smaller than MLKEM_Q).
|
||||
*
|
||||
* @spec{Implements `Decompress_5 (ByteDecode_5 (a))`: ByteDecode_d
|
||||
* @[FIPS203, Algorithm 6], Decompress_d @[FIPS203, Eq (4.8)], extended to
|
||||
* vectors as per @[FIPS203, 2.4.8 Applying Algorithms to Arrays].
|
||||
* `Decompress_{d_v} (ByteDecode_{d_v} (v))` appears in @[FIPS203, Algorithm
|
||||
* 15 (K-PKE.Decrypt), L4], where `d_v=5` for ML-KEM-1024 @[FIPS203,
|
||||
* Table 2].}
|
||||
*
|
||||
* @param[out] r Output polynomial.
|
||||
* @param[in] a Input byte array (of length MLKEM_POLYCOMPRESSEDBYTES_D5
|
||||
* bytes).
|
||||
*/
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_decompress_d5(mlk_poly *r,
|
||||
const uint8_t a[MLKEM_POLYCOMPRESSEDBYTES_D5]);
|
||||
|
||||
#define mlk_poly_decompress_d11 MLK_NAMESPACE(poly_decompress_d11)
|
||||
/**
|
||||
* De-serialization and subsequent decompression (11 bits) of a polynomial;
|
||||
* approximate inverse of mlk_poly_compress_d11.
|
||||
*
|
||||
* Upon return, the coefficients of the output polynomial are
|
||||
* unsigned-canonical (non-negative and smaller than MLKEM_Q).
|
||||
*
|
||||
* @spec{Implements `Decompress_11 (ByteDecode_11 (a))`: ByteDecode_d
|
||||
* @[FIPS203, Algorithm 6], Decompress_d @[FIPS203, Eq (4.8)], extended to
|
||||
* vectors as per @[FIPS203, 2.4.8 Applying Algorithms to Arrays].
|
||||
* `Decompress_{d_u} (ByteDecode_{d_u} (u))` appears in @[FIPS203, Algorithm
|
||||
* 15 (K-PKE.Decrypt), L3], where `d_u=11` for ML-KEM-1024 @[FIPS203,
|
||||
* Table 2].}
|
||||
*
|
||||
* @param[out] r Output polynomial.
|
||||
* @param[in] a Input byte array (of length MLKEM_POLYCOMPRESSEDBYTES_D11
|
||||
* bytes).
|
||||
*/
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_decompress_d11(mlk_poly *r,
|
||||
const uint8_t a[MLKEM_POLYCOMPRESSEDBYTES_D11]);
|
||||
#endif /* MLK_CONFIG_MULTILEVEL_WITH_SHARED || MLKEM_K == 4 */
|
||||
|
||||
#define mlk_poly_tobytes MLK_NAMESPACE(poly_tobytes)
|
||||
/**
|
||||
* Serialization of a polynomial. Signed coefficients are converted to
|
||||
* unsigned form before serialization.
|
||||
*
|
||||
* @spec{Implements ByteEncode_12 @[FIPS203, Algorithm 5]. Extended to
|
||||
* vectors as per @[FIPS203, 2.4.8 Applying Algorithms to Arrays].}
|
||||
*
|
||||
* @param[out] r Output byte array (of MLKEM_POLYBYTES bytes).
|
||||
* @param[in] a Input polynomial, with each coefficient in the range
|
||||
* [0,1,..,MLKEM_Q-1].
|
||||
*/
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_tobytes(uint8_t r[MLKEM_POLYBYTES], const mlk_poly *a)
|
||||
__contract__(
|
||||
requires(memory_no_alias(r, MLKEM_POLYBYTES))
|
||||
requires(memory_no_alias(a, sizeof(mlk_poly)))
|
||||
requires(array_bound(a->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
assigns(memory_slice(r, MLKEM_POLYBYTES))
|
||||
);
|
||||
|
||||
|
||||
#define mlk_poly_frombytes MLK_NAMESPACE(poly_frombytes)
|
||||
/**
|
||||
* De-serialization of a polynomial.
|
||||
*
|
||||
* @spec{Implements ByteDecode_12 @[FIPS203, Algorithm 6]. Extended to
|
||||
* vectors as per @[FIPS203, 2.4.8 Applying Algorithms to Arrays].}
|
||||
*
|
||||
* @param[out] r Output polynomial, with each coefficient unsigned and in
|
||||
* the range 0..4095.
|
||||
* @param[in] a Input byte array (of MLKEM_POLYBYTES bytes).
|
||||
*/
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_frombytes(mlk_poly *r, const uint8_t a[MLKEM_POLYBYTES])
|
||||
__contract__(
|
||||
requires(memory_no_alias(a, MLKEM_POLYBYTES))
|
||||
requires(memory_no_alias(r, sizeof(mlk_poly)))
|
||||
assigns(memory_slice(r, sizeof(mlk_poly)))
|
||||
ensures(array_bound(r->coeffs, 0, MLKEM_N, 0, MLKEM_UINT12_LIMIT))
|
||||
);
|
||||
|
||||
|
||||
#define mlk_poly_frommsg MLK_NAMESPACE(poly_frommsg)
|
||||
/**
|
||||
* Convert a 32-byte message to a polynomial.
|
||||
*
|
||||
* @spec{Implements `Decompress_1 (ByteDecode_1 (a))`: ByteDecode_d
|
||||
* @[FIPS203, Algorithm 6], Decompress_d @[FIPS203, Eq (4.8)], extended to
|
||||
* vectors as per @[FIPS203, 2.4.8 Applying Algorithms to Arrays].
|
||||
* `Decompress_1 (ByteDecode_1 (w))` appears in @[FIPS203, Algorithm 15
|
||||
* (K-PKE.Encrypt), L20].}
|
||||
*
|
||||
* @param[out] r Output polynomial.
|
||||
* @param[in] msg Input message.
|
||||
*/
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_frommsg(mlk_poly *r, const uint8_t msg[MLKEM_INDCPA_MSGBYTES])
|
||||
__contract__(
|
||||
requires(memory_no_alias(msg, MLKEM_INDCPA_MSGBYTES))
|
||||
requires(memory_no_alias(r, sizeof(mlk_poly)))
|
||||
assigns(memory_slice(r, sizeof(mlk_poly)))
|
||||
ensures(array_bound(r->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
);
|
||||
|
||||
#define mlk_poly_tomsg MLK_NAMESPACE(poly_tomsg)
|
||||
/**
|
||||
* Convert a polynomial to a 32-byte message.
|
||||
*
|
||||
* @spec{Implements `ByteEncode_1 (Compress_1 (a))`: ByteEncode_d
|
||||
* @[FIPS203, Algorithm 5], Compress_d @[FIPS203, Eq (4.7)], extended to
|
||||
* vectors as per @[FIPS203, 2.4.8 Applying Algorithms to Arrays].
|
||||
* `ByteEncode_1 (Compress_1 (w))` appears in @[FIPS203, Algorithm 14
|
||||
* (K-PKE.Decrypt), L7].}
|
||||
*
|
||||
* @param[out] msg Output message.
|
||||
* @param[in] r Input polynomial. Coefficients must be unsigned canonical.
|
||||
*/
|
||||
MLK_INTERNAL_API
|
||||
void mlk_poly_tomsg(uint8_t msg[MLKEM_INDCPA_MSGBYTES], const mlk_poly *r)
|
||||
__contract__(
|
||||
requires(memory_no_alias(msg, MLKEM_INDCPA_MSGBYTES))
|
||||
requires(memory_no_alias(r, sizeof(mlk_poly)))
|
||||
requires(array_bound(r->coeffs, 0, MLKEM_N, 0, MLKEM_Q))
|
||||
assigns(memory_slice(msg, MLKEM_INDCPA_MSGBYTES))
|
||||
);
|
||||
|
||||
#endif /* !MLK_COMPRESS_H */
|
||||
@@ -1,64 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
|
||||
/* NOTE: You can remove this file unless you compile with MLKEM_DEBUG. */
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#if !defined(MLK_CONFIG_MULTILEVEL_NO_SHARED) && defined(MLKEM_DEBUG)
|
||||
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include "debug.h"
|
||||
|
||||
#define MLK_DEBUG_ERROR_HEADER "[ERROR:%s:%04d] "
|
||||
|
||||
void mlk_debug_check_assert(const char *file, int line, const int val)
|
||||
{
|
||||
if (val == 0)
|
||||
{
|
||||
fprintf(stderr, MLK_DEBUG_ERROR_HEADER "Assertion failed (value %d)\n",
|
||||
file, line, val);
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
void mlk_debug_check_bounds(const char *file, int line, const int16_t *ptr,
|
||||
unsigned len, int lower_bound_exclusive,
|
||||
int upper_bound_exclusive)
|
||||
{
|
||||
int err = 0;
|
||||
unsigned i;
|
||||
for (i = 0; i < len; i++)
|
||||
{
|
||||
int16_t val = ptr[i];
|
||||
if (!(val > lower_bound_exclusive && val < upper_bound_exclusive))
|
||||
{
|
||||
fprintf(
|
||||
stderr,
|
||||
MLK_DEBUG_ERROR_HEADER
|
||||
"Bounds assertion failed: Index %u, value %d out of bounds (%d,%d)\n",
|
||||
file, line, i, (int)val, lower_bound_exclusive,
|
||||
upper_bound_exclusive);
|
||||
err = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (err == 1)
|
||||
{
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
#else /* !MLK_CONFIG_MULTILEVEL_NO_SHARED && MLKEM_DEBUG */
|
||||
|
||||
MLK_EMPTY_CU(debug)
|
||||
|
||||
#endif /* !(!MLK_CONFIG_MULTILEVEL_NO_SHARED && MLKEM_DEBUG) */
|
||||
|
||||
/* To facilitate single-compilation-unit (SCU) builds, undefine all macros.
|
||||
* Don't modify by hand -- this is auto-generated by scripts/autogen. */
|
||||
#undef MLK_DEBUG_ERROR_HEADER
|
||||
@@ -1,121 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
#ifndef MLK_DEBUG_H
|
||||
#define MLK_DEBUG_H
|
||||
#include "common.h"
|
||||
|
||||
#if defined(MLKEM_DEBUG)
|
||||
|
||||
/**
|
||||
* Check debug assertion.
|
||||
*
|
||||
* Prints an error message to stderr and calls exit(1) on failure.
|
||||
*
|
||||
* @param[in] file Filename.
|
||||
* @param line Line number.
|
||||
* @param val Value asserted to be non-zero.
|
||||
*/
|
||||
#define mlk_debug_check_assert MLK_NAMESPACE(mlkem_debug_assert)
|
||||
void mlk_debug_check_assert(const char *file, int line, const int val);
|
||||
|
||||
/**
|
||||
* Check whether values in an array of int16_t are within specified bounds.
|
||||
*
|
||||
* Prints an error message to stderr and calls exit(1) on failure.
|
||||
*
|
||||
* @param[in] file Filename.
|
||||
* @param line Line number.
|
||||
* @param[in] ptr Base of array to be checked.
|
||||
* @param len Number of int16_t in @p ptr.
|
||||
* @param lower_bound_exclusive Exclusive lower bound.
|
||||
* @param upper_bound_exclusive Exclusive upper bound.
|
||||
*/
|
||||
#define mlk_debug_check_bounds MLK_NAMESPACE(mlkem_debug_check_bounds)
|
||||
void mlk_debug_check_bounds(const char *file, int line, const int16_t *ptr,
|
||||
unsigned len, int lower_bound_exclusive,
|
||||
int upper_bound_exclusive);
|
||||
|
||||
/* Check assertion, calling exit() upon failure
|
||||
*
|
||||
* val: Value that's asserted to be non-zero
|
||||
*/
|
||||
#define mlk_assert(val) mlk_debug_check_assert(__FILE__, __LINE__, (val))
|
||||
|
||||
/* Check bounds in array of int16_t's
|
||||
* ptr: Base of int16_t array; will be explicitly cast to int16_t*,
|
||||
* so you may pass a byte-compatible type such as mlk_poly or mlk_polyvec.
|
||||
* len: Number of int16_t in array
|
||||
* value_lb: Inclusive lower value bound
|
||||
* value_ub: Exclusive upper value bound */
|
||||
#define mlk_assert_bound(ptr, len, value_lb, value_ub) \
|
||||
mlk_debug_check_bounds(__FILE__, __LINE__, (const int16_t *)(ptr), (len), \
|
||||
(value_lb) - 1, (value_ub))
|
||||
|
||||
/* Check absolute bounds in array of int16_t's
|
||||
* ptr: Base of array, expression of type int16_t*
|
||||
* len: Number of int16_t in array
|
||||
* value_abs_bd: Exclusive absolute upper bound */
|
||||
#define mlk_assert_abs_bound(ptr, len, value_abs_bd) \
|
||||
mlk_assert_bound((ptr), (len), (-(value_abs_bd) + 1), (value_abs_bd))
|
||||
|
||||
/* Version of bounds assertions for 2-dimensional arrays */
|
||||
#define mlk_assert_bound_2d(ptr, len0, len1, value_lb, value_ub) \
|
||||
mlk_assert_bound((ptr), ((len0) * (len1)), (value_lb), (value_ub))
|
||||
|
||||
#define mlk_assert_abs_bound_2d(ptr, len0, len1, value_abs_bd) \
|
||||
mlk_assert_abs_bound((ptr), ((len0) * (len1)), (value_abs_bd))
|
||||
|
||||
/* When running CBMC, convert debug assertions into proof obligations */
|
||||
#elif defined(CBMC)
|
||||
#include "cbmc.h"
|
||||
|
||||
#define mlk_assert(val) cassert(val)
|
||||
|
||||
#define mlk_assert_bound(ptr, len, value_lb, value_ub) \
|
||||
cassert(array_bound(((int16_t *)(ptr)), 0, (len), (value_lb), (value_ub)))
|
||||
|
||||
#define mlk_assert_abs_bound(ptr, len, value_abs_bd) \
|
||||
cassert(array_abs_bound(((int16_t *)(ptr)), 0, (len), (value_abs_bd)))
|
||||
|
||||
/* Because of https://github.com/diffblue/cbmc/issues/8570, we can't
|
||||
* just use a single flattened array_bound(...) here. */
|
||||
#define mlk_assert_bound_2d(ptr, M, N, value_lb, value_ub) \
|
||||
cassert(forall(kN, 0, (M), \
|
||||
array_bound(&((int16_t (*)[(N)])(ptr))[kN][0], 0, (N), \
|
||||
(value_lb), (value_ub))))
|
||||
|
||||
#define mlk_assert_abs_bound_2d(ptr, M, N, value_abs_bd) \
|
||||
cassert(forall(kN, 0, (M), \
|
||||
array_abs_bound(&((int16_t (*)[(N)])(ptr))[kN][0], 0, (N), \
|
||||
(value_abs_bd))))
|
||||
|
||||
#else /* !MLKEM_DEBUG && CBMC */
|
||||
|
||||
#define mlk_assert(val) \
|
||||
do \
|
||||
{ \
|
||||
} while (0)
|
||||
#define mlk_assert_bound(ptr, len, value_lb, value_ub) \
|
||||
do \
|
||||
{ \
|
||||
} while (0)
|
||||
#define mlk_assert_abs_bound(ptr, len, value_abs_bd) \
|
||||
do \
|
||||
{ \
|
||||
} while (0)
|
||||
|
||||
#define mlk_assert_bound_2d(ptr, len0, len1, value_lb, value_ub) \
|
||||
do \
|
||||
{ \
|
||||
} while (0)
|
||||
|
||||
#define mlk_assert_abs_bound_2d(ptr, len0, len1, value_abs_bd) \
|
||||
do \
|
||||
{ \
|
||||
} while (0)
|
||||
|
||||
|
||||
#endif /* !MLKEM_DEBUG && !CBMC */
|
||||
#endif /* !MLK_DEBUG_H */
|
||||
@@ -1,249 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
|
||||
/* References
|
||||
* ==========
|
||||
*
|
||||
* - [FIPS203]
|
||||
* FIPS 203 Module-Lattice-Based Key-Encapsulation Mechanism Standard
|
||||
* National Institute of Standards and Technology
|
||||
* https://csrc.nist.gov/pubs/fips/203/final
|
||||
*
|
||||
* - [mupq]
|
||||
* Common files for pqm4, pqm3, pqriscv
|
||||
* Kannwischer, Petri, Rijneveld, Schwabe, Stoffelen
|
||||
* https://github.com/mupq/mupq
|
||||
*
|
||||
* - [supercop]
|
||||
* SUPERCOP benchmarking framework
|
||||
* Daniel J. Bernstein
|
||||
* http://bench.cr.yp.to/supercop.html
|
||||
*
|
||||
* - [tweetfips]
|
||||
* 'tweetfips202' FIPS202 implementation
|
||||
* Van Assche, Bernstein, Schwabe
|
||||
* https://keccak.team/2015/tweetfips202.html
|
||||
*/
|
||||
|
||||
/* Based on the CC0 implementation from @[mupq] and the public domain
|
||||
* implementation @[supercop, crypto_hash/keccakc512/simple/]
|
||||
* by Ronny Van Keer, and the public domain @[tweetfips] implementation. */
|
||||
|
||||
#include "../common.h"
|
||||
#if !defined(MLK_CONFIG_MULTILEVEL_NO_SHARED)
|
||||
|
||||
|
||||
#include "../verify.h"
|
||||
#include "fips202.h"
|
||||
#include "keccakf1600.h"
|
||||
|
||||
/**
|
||||
* Absorb step of Keccak; non-incremental, starts by zeroeing the state.
|
||||
*
|
||||
* @warning Must only be called once.
|
||||
*
|
||||
* @param[out] s Pointer to (uninitialized) output Keccak state.
|
||||
* @param r Rate in bytes (e.g., 168 for SHAKE128).
|
||||
* @param[in] m Input to be absorbed into @p s.
|
||||
* @param mlen Length of input in bytes.
|
||||
* @param p Domain-separation byte for different Keccak-derived
|
||||
* functions.
|
||||
*/
|
||||
static void mlk_keccak_absorb_once(uint64_t *s, unsigned r, const uint8_t *m,
|
||||
size_t mlen, uint8_t p)
|
||||
__contract__(
|
||||
requires(mlen <= MLK_MAX_BUFFER_SIZE)
|
||||
requires(r > 0)
|
||||
requires(r <= sizeof(uint64_t) * MLK_KECCAK_LANES)
|
||||
requires(memory_no_alias(s, sizeof(uint64_t) * MLK_KECCAK_LANES))
|
||||
requires(memory_no_alias(m, mlen))
|
||||
assigns(memory_slice(s, sizeof(uint64_t) * MLK_KECCAK_LANES)))
|
||||
{
|
||||
/* Initialize state */
|
||||
size_t i;
|
||||
for (i = 0; i < 25; ++i)
|
||||
__loop__(invariant(i <= 25)
|
||||
decreases(25 - i))
|
||||
{
|
||||
s[i] = 0;
|
||||
}
|
||||
|
||||
while (mlen >= r)
|
||||
__loop__(
|
||||
assigns(mlen, m, memory_slice(s, sizeof(uint64_t) * MLK_KECCAK_LANES))
|
||||
invariant(mlen <= loop_entry(mlen))
|
||||
invariant(m == loop_entry(m) + (loop_entry(mlen) - mlen))
|
||||
decreases(mlen))
|
||||
{
|
||||
mlk_keccakf1600_xor_bytes(s, m, 0, r);
|
||||
mlk_keccakf1600_permute(s);
|
||||
mlen -= r;
|
||||
m += r;
|
||||
}
|
||||
|
||||
/* At this point, mlen < r, so the truncations to unsigned are safe below. */
|
||||
|
||||
if (mlen > 0)
|
||||
{
|
||||
mlk_keccakf1600_xor_bytes(s, m, 0, (unsigned int)mlen);
|
||||
}
|
||||
|
||||
if (mlen == r - 1)
|
||||
{
|
||||
p |= 128;
|
||||
mlk_keccakf1600_xor_bytes(s, &p, (unsigned int)mlen, 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
mlk_keccakf1600_xor_bytes(s, &p, (unsigned int)mlen, 1);
|
||||
p = 128;
|
||||
mlk_keccakf1600_xor_bytes(s, &p, r - 1, 1);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Block-level Keccak squeeze.
|
||||
*
|
||||
* @param[out] h Output bytes.
|
||||
* @param nblocks Number of blocks to be squeezed.
|
||||
* @param[in,out] s Input/output state.
|
||||
* @param r Rate in bytes (e.g., 168 for SHAKE128).
|
||||
*/
|
||||
static void mlk_keccak_squeezeblocks(uint8_t *h, size_t nblocks, uint64_t *s,
|
||||
unsigned r)
|
||||
__contract__(
|
||||
requires(r <= sizeof(uint64_t) * MLK_KECCAK_LANES)
|
||||
requires(nblocks <= 8 /* somewhat arbitrary bound */)
|
||||
requires(memory_no_alias(s, sizeof(uint64_t) * MLK_KECCAK_LANES))
|
||||
requires(memory_no_alias(h, nblocks * r))
|
||||
assigns(memory_slice(s, sizeof(uint64_t) * MLK_KECCAK_LANES))
|
||||
assigns(memory_slice(h, nblocks * r)))
|
||||
{
|
||||
while (nblocks > 0)
|
||||
__loop__(
|
||||
assigns(h, nblocks,
|
||||
memory_slice(s, sizeof(uint64_t) * MLK_KECCAK_LANES),
|
||||
memory_slice(h, nblocks * r))
|
||||
invariant(nblocks <= loop_entry(nblocks) &&
|
||||
h == loop_entry(h) + r * (loop_entry(nblocks) - nblocks))
|
||||
decreases(nblocks))
|
||||
{
|
||||
mlk_keccakf1600_permute(s);
|
||||
mlk_keccakf1600_extract_bytes(s, h, 0, r);
|
||||
h += r;
|
||||
nblocks--;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Keccak squeeze; can be called on byte-level.
|
||||
*
|
||||
* @warning Must only be called once.
|
||||
*
|
||||
* @param[out] h Output bytes.
|
||||
* @param outlen Number of bytes to be squeezed.
|
||||
* @param[in,out] s Keccak state.
|
||||
* @param r Rate in bytes (e.g., 168 for SHAKE128).
|
||||
*/
|
||||
static void mlk_keccak_squeeze_once(uint8_t *h, size_t outlen, uint64_t *s,
|
||||
unsigned r)
|
||||
__contract__(
|
||||
requires(outlen <= MLK_MAX_BUFFER_SIZE)
|
||||
requires(r > 0)
|
||||
requires(r <= sizeof(uint64_t) * MLK_KECCAK_LANES)
|
||||
requires(memory_no_alias(s, sizeof(uint64_t) * MLK_KECCAK_LANES))
|
||||
requires(memory_no_alias(h, outlen))
|
||||
assigns(memory_slice(s, sizeof(uint64_t) * MLK_KECCAK_LANES))
|
||||
assigns(memory_slice(h, outlen)))
|
||||
{
|
||||
size_t len;
|
||||
while (outlen > 0)
|
||||
__loop__(
|
||||
assigns(len, h, outlen,
|
||||
memory_slice(s, sizeof(uint64_t) * MLK_KECCAK_LANES),
|
||||
memory_slice(h, outlen))
|
||||
invariant(outlen <= loop_entry(outlen) &&
|
||||
h == loop_entry(h) + (loop_entry(outlen) - outlen))
|
||||
decreases(outlen))
|
||||
{
|
||||
mlk_keccakf1600_permute(s);
|
||||
|
||||
if (outlen < r)
|
||||
{
|
||||
len = outlen;
|
||||
}
|
||||
else
|
||||
{
|
||||
len = r;
|
||||
}
|
||||
mlk_keccakf1600_extract_bytes(s, h, 0, (unsigned int)len);
|
||||
h += len;
|
||||
outlen -= len;
|
||||
}
|
||||
}
|
||||
|
||||
void mlk_shake128_absorb_once(mlk_shake128ctx *state, const uint8_t *input,
|
||||
size_t inlen)
|
||||
{
|
||||
mlk_keccak_absorb_once(state->ctx, SHAKE128_RATE, input, inlen, 0x1F);
|
||||
}
|
||||
|
||||
void mlk_shake128_squeezeblocks(uint8_t *output, size_t nblocks,
|
||||
mlk_shake128ctx *state)
|
||||
{
|
||||
mlk_keccak_squeezeblocks(output, nblocks, state->ctx, SHAKE128_RATE);
|
||||
}
|
||||
|
||||
void mlk_shake128_init(mlk_shake128ctx *state) { (void)state; }
|
||||
void mlk_shake128_release(mlk_shake128ctx *state)
|
||||
{
|
||||
/* Specification: Partially implements
|
||||
* @[FIPS203, Section 3.3, Destruction of intermediate values] */
|
||||
mlk_zeroize(state, sizeof(mlk_shake128ctx));
|
||||
}
|
||||
|
||||
typedef mlk_shake128ctx mlk_shake256ctx;
|
||||
void mlk_shake256(uint8_t *output, size_t outlen, const uint8_t *input,
|
||||
size_t inlen)
|
||||
{
|
||||
mlk_shake256ctx state;
|
||||
/* Absorb input */
|
||||
mlk_keccak_absorb_once(state.ctx, SHAKE256_RATE, input, inlen, 0x1F);
|
||||
/* Squeeze output */
|
||||
mlk_keccak_squeeze_once(output, outlen, state.ctx, SHAKE256_RATE);
|
||||
/* Specification: Partially implements
|
||||
* @[FIPS203, Section 3.3, Destruction of intermediate values] */
|
||||
mlk_zeroize(&state, sizeof(state));
|
||||
}
|
||||
|
||||
void mlk_sha3_256(uint8_t *output, const uint8_t *input, size_t inlen)
|
||||
{
|
||||
uint64_t ctx[25];
|
||||
/* Absorb input */
|
||||
mlk_keccak_absorb_once(ctx, SHA3_256_RATE, input, inlen, 0x06);
|
||||
/* Squeeze output */
|
||||
mlk_keccak_squeeze_once(output, 32, ctx, SHA3_256_RATE);
|
||||
/* Specification: Partially implements
|
||||
* @[FIPS203, Section 3.3, Destruction of intermediate values] */
|
||||
mlk_zeroize(ctx, sizeof(ctx));
|
||||
}
|
||||
|
||||
void mlk_sha3_512(uint8_t *output, const uint8_t *input, size_t inlen)
|
||||
{
|
||||
uint64_t ctx[25];
|
||||
/* Absorb input */
|
||||
mlk_keccak_absorb_once(ctx, SHA3_512_RATE, input, inlen, 0x06);
|
||||
/* Squeeze output */
|
||||
mlk_keccak_squeeze_once(output, 64, ctx, SHA3_512_RATE);
|
||||
/* Specification: Partially implements
|
||||
* @[FIPS203, Section 3.3, Destruction of intermediate values] */
|
||||
mlk_zeroize(ctx, sizeof(ctx));
|
||||
}
|
||||
|
||||
#else /* !MLK_CONFIG_MULTILEVEL_NO_SHARED */
|
||||
|
||||
MLK_EMPTY_CU(fips202)
|
||||
|
||||
#endif /* MLK_CONFIG_MULTILEVEL_NO_SHARED */
|
||||
@@ -1,144 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
#ifndef MLK_FIPS202_FIPS202_H
|
||||
#define MLK_FIPS202_FIPS202_H
|
||||
|
||||
#include "../cbmc.h"
|
||||
#include "../common.h"
|
||||
|
||||
#define SHAKE128_RATE 168
|
||||
#define SHAKE256_RATE 136
|
||||
#define SHA3_256_RATE 136
|
||||
#define SHA3_384_RATE 104
|
||||
#define SHA3_512_RATE 72
|
||||
|
||||
/** Context for the non-incremental SHAKE128 API. */
|
||||
typedef struct
|
||||
{
|
||||
uint64_t ctx[25]; /**< Keccak state. */
|
||||
} MLK_ALIGN mlk_shake128ctx;
|
||||
|
||||
#define mlk_shake128_absorb_once MLK_NAMESPACE(shake128_absorb_once)
|
||||
/**
|
||||
* One-shot absorb step of the SHAKE128 XOF.
|
||||
*
|
||||
* For call-sites (in mlkem-native):
|
||||
* - This function MUST ONLY be called straight after mlk_shake128_init().
|
||||
* - This function MUST ONLY be called once.
|
||||
*
|
||||
* Consequently, for providers of custom FIPS202 code to be used with
|
||||
* mlkem-native:
|
||||
* - You may assume that the input context is freshly initialized via
|
||||
* mlk_shake128_init().
|
||||
* - You may assume that this function is called exactly once.
|
||||
*
|
||||
* @param[in,out] state SHAKE128 context.
|
||||
* @param[in] input Input to be absorbed into the state.
|
||||
* @param inlen Length of input in bytes.
|
||||
*/
|
||||
void mlk_shake128_absorb_once(mlk_shake128ctx *state, const uint8_t *input,
|
||||
size_t inlen)
|
||||
__contract__(
|
||||
requires(inlen <= MLK_MAX_BUFFER_SIZE)
|
||||
requires(memory_no_alias(state, sizeof(mlk_shake128ctx)))
|
||||
requires(memory_no_alias(input, inlen))
|
||||
assigns(memory_slice(state, sizeof(mlk_shake128ctx)))
|
||||
);
|
||||
|
||||
#define mlk_shake128_squeezeblocks MLK_NAMESPACE(shake128_squeezeblocks)
|
||||
/**
|
||||
* Squeeze step of SHAKE128 XOF. Squeezes full blocks of SHAKE128_RATE bytes
|
||||
* each. Modifies the state. Can be called multiple times to keep squeezing,
|
||||
* i.e., is incremental.
|
||||
*
|
||||
* @param[out] output Output blocks.
|
||||
* @param nblocks Number of blocks to be squeezed (written to output).
|
||||
* @param[in,out] state Keccak state.
|
||||
*/
|
||||
void mlk_shake128_squeezeblocks(uint8_t *output, size_t nblocks,
|
||||
mlk_shake128ctx *state)
|
||||
__contract__(
|
||||
requires(nblocks <= 8 /* somewhat arbitrary bound */)
|
||||
requires(memory_no_alias(state, sizeof(mlk_shake128ctx)))
|
||||
requires(memory_no_alias(output, nblocks * SHAKE128_RATE))
|
||||
assigns(memory_slice(output, nblocks * SHAKE128_RATE), memory_slice(state, sizeof(mlk_shake128ctx)))
|
||||
);
|
||||
|
||||
#define mlk_shake128_init MLK_NAMESPACE(shake128_init)
|
||||
void mlk_shake128_init(mlk_shake128ctx *state);
|
||||
|
||||
#define mlk_shake128_release MLK_NAMESPACE(shake128_release)
|
||||
void mlk_shake128_release(mlk_shake128ctx *state);
|
||||
|
||||
/* One-stop SHAKE256 call. Aliasing between input and
|
||||
* output is not permitted */
|
||||
#define mlk_shake256 MLK_NAMESPACE(shake256)
|
||||
/**
|
||||
* SHAKE256 XOF with non-incremental API.
|
||||
*
|
||||
* @param[out] output Output buffer.
|
||||
* @param outlen Requested output length in bytes.
|
||||
* @param[in] input Input buffer.
|
||||
* @param inlen Length of input in bytes.
|
||||
*/
|
||||
void mlk_shake256(uint8_t *output, size_t outlen, const uint8_t *input,
|
||||
size_t inlen)
|
||||
__contract__(
|
||||
requires(inlen <= MLK_MAX_BUFFER_SIZE)
|
||||
requires(outlen <= MLK_MAX_BUFFER_SIZE)
|
||||
requires(memory_no_alias(input, inlen))
|
||||
requires(memory_no_alias(output, outlen))
|
||||
assigns(memory_slice(output, outlen))
|
||||
);
|
||||
|
||||
/* One-stop SHA3_256 call. Aliasing between input and
|
||||
* output is not permitted */
|
||||
#define SHA3_256_HASHBYTES 32
|
||||
#define mlk_sha3_256 MLK_NAMESPACE(sha3_256)
|
||||
/**
|
||||
* SHA3-256 with non-incremental API.
|
||||
*
|
||||
* @param[out] output Output buffer.
|
||||
* @param[in] input Input buffer.
|
||||
* @param inlen Length of input in bytes.
|
||||
*/
|
||||
void mlk_sha3_256(uint8_t *output, const uint8_t *input, size_t inlen)
|
||||
__contract__(
|
||||
requires(inlen <= MLK_MAX_BUFFER_SIZE)
|
||||
requires(memory_no_alias(input, inlen))
|
||||
requires(memory_no_alias(output, SHA3_256_HASHBYTES))
|
||||
assigns(memory_slice(output, SHA3_256_HASHBYTES))
|
||||
);
|
||||
|
||||
/* One-stop SHA3_512 call. Aliasing between input and
|
||||
* output is not permitted */
|
||||
#define SHA3_512_HASHBYTES 64
|
||||
#define mlk_sha3_512 MLK_NAMESPACE(sha3_512)
|
||||
/**
|
||||
* SHA3-512 with non-incremental API.
|
||||
*
|
||||
* @param[out] output Output buffer.
|
||||
* @param[in] input Input buffer.
|
||||
* @param inlen Length of input in bytes.
|
||||
*/
|
||||
void mlk_sha3_512(uint8_t *output, const uint8_t *input, size_t inlen)
|
||||
__contract__(
|
||||
requires(inlen <= MLK_MAX_BUFFER_SIZE)
|
||||
requires(memory_no_alias(input, inlen))
|
||||
requires(memory_no_alias(output, SHA3_512_HASHBYTES))
|
||||
assigns(memory_slice(output, SHA3_512_HASHBYTES))
|
||||
);
|
||||
|
||||
#if !defined(MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202) || \
|
||||
!defined(MLK_USE_FIPS202_X4_NATIVE)
|
||||
/* If you provide your own FIPS-202 implementation where the x4-
|
||||
* Keccak-f1600-x4 implementation falls back to 4-fold Keccak-f1600,
|
||||
* set this to gain a small speedup. */
|
||||
#define FIPS202_X4_DEFAULT_IMPLEMENTATION
|
||||
#endif /* !MLK_CONFIG_USE_NATIVE_BACKEND_FIPS202 || !MLK_USE_FIPS202_X4_NATIVE \
|
||||
*/
|
||||
|
||||
|
||||
#endif /* !MLK_FIPS202_FIPS202_H */
|
||||
@@ -1,207 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
|
||||
/* References
|
||||
* ==========
|
||||
*
|
||||
* - [FIPS203]
|
||||
* FIPS 203 Module-Lattice-Based Key-Encapsulation Mechanism Standard
|
||||
* National Institute of Standards and Technology
|
||||
* https://csrc.nist.gov/pubs/fips/203/final
|
||||
*/
|
||||
|
||||
#include "../common.h"
|
||||
#if !defined(MLK_CONFIG_MULTILEVEL_NO_SHARED)
|
||||
|
||||
#include "../verify.h"
|
||||
#include "fips202.h"
|
||||
#include "fips202x4.h"
|
||||
#include "keccakf1600.h"
|
||||
|
||||
typedef mlk_shake128x4ctx mlk_shake256x4_ctx;
|
||||
|
||||
static void mlk_keccak_absorb_once_x4(uint64_t *s, unsigned r,
|
||||
const uint8_t *in0, const uint8_t *in1,
|
||||
const uint8_t *in2, const uint8_t *in3,
|
||||
size_t inlen, uint8_t p)
|
||||
__contract__(
|
||||
requires(inlen <= MLK_MAX_BUFFER_SIZE)
|
||||
requires(memory_no_alias(s, sizeof(uint64_t) * MLK_KECCAK_LANES * MLK_KECCAK_WAY))
|
||||
requires(r > 0)
|
||||
requires(r <= sizeof(uint64_t) * MLK_KECCAK_LANES)
|
||||
requires(memory_no_alias(in0, inlen))
|
||||
requires(memory_no_alias(in1, inlen))
|
||||
requires(memory_no_alias(in2, inlen))
|
||||
requires(memory_no_alias(in3, inlen))
|
||||
assigns(memory_slice(s, sizeof(uint64_t) * MLK_KECCAK_LANES * MLK_KECCAK_WAY)))
|
||||
{
|
||||
while (inlen >= r)
|
||||
__loop__(
|
||||
assigns(inlen, in0, in1, in2, in3, memory_slice(s, sizeof(uint64_t) * MLK_KECCAK_LANES * MLK_KECCAK_WAY))
|
||||
invariant(inlen <= loop_entry(inlen))
|
||||
invariant(in0 == loop_entry(in0) + (loop_entry(inlen) - inlen))
|
||||
invariant(in1 == loop_entry(in1) + (loop_entry(inlen) - inlen))
|
||||
invariant(in2 == loop_entry(in2) + (loop_entry(inlen) - inlen))
|
||||
invariant(in3 == loop_entry(in3) + (loop_entry(inlen) - inlen))
|
||||
decreases(inlen))
|
||||
{
|
||||
mlk_keccakf1600x4_xor_bytes(s, in0, in1, in2, in3, 0, r);
|
||||
mlk_keccakf1600x4_permute(s);
|
||||
|
||||
in0 += r;
|
||||
in1 += r;
|
||||
in2 += r;
|
||||
in3 += r;
|
||||
inlen -= r;
|
||||
}
|
||||
|
||||
/* At this point, inlen < r, so the truncations to unsigned are safe below. */
|
||||
|
||||
if (inlen > 0)
|
||||
{
|
||||
mlk_keccakf1600x4_xor_bytes(s, in0, in1, in2, in3, 0, (unsigned int)inlen);
|
||||
}
|
||||
|
||||
if (inlen == r - 1)
|
||||
{
|
||||
p |= 128;
|
||||
mlk_keccakf1600x4_xor_bytes(s, &p, &p, &p, &p, (unsigned int)inlen, 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
mlk_keccakf1600x4_xor_bytes(s, &p, &p, &p, &p, (unsigned int)inlen, 1);
|
||||
p = 128;
|
||||
mlk_keccakf1600x4_xor_bytes(s, &p, &p, &p, &p, r - 1, 1);
|
||||
}
|
||||
}
|
||||
|
||||
static void mlk_keccak_squeezeblocks_x4(uint8_t *out0, uint8_t *out1,
|
||||
uint8_t *out2, uint8_t *out3,
|
||||
size_t nblocks, uint64_t *s, unsigned r)
|
||||
__contract__(
|
||||
requires(r <= sizeof(uint64_t) * MLK_KECCAK_LANES)
|
||||
requires(r == SHAKE128_RATE || r == SHAKE256_RATE)
|
||||
requires(nblocks <= (MLK_MAX_BUFFER_SIZE / SHAKE256_RATE))
|
||||
requires(memory_no_alias(s, sizeof(uint64_t) * MLK_KECCAK_LANES * MLK_KECCAK_WAY))
|
||||
requires(memory_no_alias(out0, nblocks * r))
|
||||
requires(memory_no_alias(out1, nblocks * r))
|
||||
requires(memory_no_alias(out2, nblocks * r))
|
||||
requires(memory_no_alias(out3, nblocks * r))
|
||||
assigns(memory_slice(s, sizeof(uint64_t) * MLK_KECCAK_LANES * MLK_KECCAK_WAY))
|
||||
assigns(memory_slice(out0, nblocks * r))
|
||||
assigns(memory_slice(out1, nblocks * r))
|
||||
assigns(memory_slice(out2, nblocks * r))
|
||||
assigns(memory_slice(out3, nblocks * r)))
|
||||
{
|
||||
size_t current_offset = 0;
|
||||
while (nblocks > 0)
|
||||
__loop__(
|
||||
assigns(nblocks, current_offset,
|
||||
memory_slice(s, sizeof(uint64_t) * MLK_KECCAK_LANES * MLK_KECCAK_WAY),
|
||||
memory_slice(out0, nblocks * r),
|
||||
memory_slice(out1, nblocks * r),
|
||||
memory_slice(out2, nblocks * r),
|
||||
memory_slice(out3, nblocks * r))
|
||||
invariant(nblocks <= loop_entry(nblocks))
|
||||
invariant(current_offset == (loop_entry(nblocks) - nblocks) * r)
|
||||
decreases(nblocks))
|
||||
{
|
||||
mlk_keccakf1600x4_permute(s);
|
||||
mlk_keccakf1600x4_extract_bytes(
|
||||
s, &out0[current_offset], &out1[current_offset], &out2[current_offset],
|
||||
&out3[current_offset], 0, r);
|
||||
current_offset += r;
|
||||
nblocks--;
|
||||
}
|
||||
}
|
||||
|
||||
void mlk_shake128x4_absorb_once(mlk_shake128x4ctx *state, const uint8_t *in0,
|
||||
const uint8_t *in1, const uint8_t *in2,
|
||||
const uint8_t *in3, size_t inlen)
|
||||
{
|
||||
mlk_memset(state, 0, sizeof(mlk_shake128x4ctx));
|
||||
mlk_keccak_absorb_once_x4(state->ctx, SHAKE128_RATE, in0, in1, in2, in3,
|
||||
inlen, 0x1F);
|
||||
}
|
||||
|
||||
void mlk_shake128x4_squeezeblocks(uint8_t *out0, uint8_t *out1, uint8_t *out2,
|
||||
uint8_t *out3, size_t nblocks,
|
||||
mlk_shake128x4ctx *state)
|
||||
{
|
||||
mlk_keccak_squeezeblocks_x4(out0, out1, out2, out3, nblocks, state->ctx,
|
||||
SHAKE128_RATE);
|
||||
}
|
||||
|
||||
void mlk_shake128x4_init(mlk_shake128x4ctx *state) { (void)state; }
|
||||
void mlk_shake128x4_release(mlk_shake128x4ctx *state)
|
||||
{
|
||||
/* Specification: Partially implements
|
||||
* @[FIPS203, Section 3.3, Destruction of intermediate values] */
|
||||
mlk_zeroize(state, sizeof(mlk_shake128x4ctx));
|
||||
}
|
||||
|
||||
static void mlk_shake256x4_absorb_once(mlk_shake256x4_ctx *state,
|
||||
const uint8_t *in0, const uint8_t *in1,
|
||||
const uint8_t *in2, const uint8_t *in3,
|
||||
size_t inlen)
|
||||
{
|
||||
mlk_memset(state, 0, sizeof(mlk_shake128x4ctx));
|
||||
mlk_keccak_absorb_once_x4(state->ctx, SHAKE256_RATE, in0, in1, in2, in3,
|
||||
inlen, 0x1F);
|
||||
}
|
||||
|
||||
static void mlk_shake256x4_squeezeblocks(uint8_t *out0, uint8_t *out1,
|
||||
uint8_t *out2, uint8_t *out3,
|
||||
size_t nblocks,
|
||||
mlk_shake256x4_ctx *state)
|
||||
{
|
||||
mlk_keccak_squeezeblocks_x4(out0, out1, out2, out3, nblocks, state->ctx,
|
||||
SHAKE256_RATE);
|
||||
}
|
||||
|
||||
void mlk_shake256x4(uint8_t *out0, uint8_t *out1, uint8_t *out2, uint8_t *out3,
|
||||
size_t outlen, const uint8_t *in0, const uint8_t *in1,
|
||||
const uint8_t *in2, const uint8_t *in3, size_t inlen)
|
||||
{
|
||||
mlk_shake256x4_ctx statex;
|
||||
size_t nblocks = outlen / SHAKE256_RATE;
|
||||
uint8_t tmp0[SHAKE256_RATE];
|
||||
uint8_t tmp1[SHAKE256_RATE];
|
||||
uint8_t tmp2[SHAKE256_RATE];
|
||||
uint8_t tmp3[SHAKE256_RATE];
|
||||
|
||||
mlk_shake256x4_absorb_once(&statex, in0, in1, in2, in3, inlen);
|
||||
mlk_shake256x4_squeezeblocks(out0, out1, out2, out3, nblocks, &statex);
|
||||
|
||||
out0 += nblocks * SHAKE256_RATE;
|
||||
out1 += nblocks * SHAKE256_RATE;
|
||||
out2 += nblocks * SHAKE256_RATE;
|
||||
out3 += nblocks * SHAKE256_RATE;
|
||||
|
||||
outlen -= nblocks * SHAKE256_RATE;
|
||||
|
||||
if (outlen)
|
||||
{
|
||||
mlk_shake256x4_squeezeblocks(tmp0, tmp1, tmp2, tmp3, 1, &statex);
|
||||
mlk_memcpy(out0, tmp0, outlen);
|
||||
mlk_memcpy(out1, tmp1, outlen);
|
||||
mlk_memcpy(out2, tmp2, outlen);
|
||||
mlk_memcpy(out3, tmp3, outlen);
|
||||
}
|
||||
|
||||
/* Specification: Partially implements
|
||||
* @[FIPS203, Section 3.3, Destruction of intermediate values] */
|
||||
mlk_zeroize(&statex, sizeof(statex));
|
||||
mlk_zeroize(tmp0, sizeof(tmp0));
|
||||
mlk_zeroize(tmp1, sizeof(tmp1));
|
||||
mlk_zeroize(tmp2, sizeof(tmp2));
|
||||
mlk_zeroize(tmp3, sizeof(tmp3));
|
||||
}
|
||||
|
||||
#else /* !MLK_CONFIG_MULTILEVEL_NO_SHARED */
|
||||
|
||||
MLK_EMPTY_CU(fips202x4)
|
||||
|
||||
#endif /* MLK_CONFIG_MULTILEVEL_NO_SHARED */
|
||||
@@ -1,81 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
#ifndef MLK_FIPS202_FIPS202X4_H
|
||||
#define MLK_FIPS202_FIPS202X4_H
|
||||
|
||||
|
||||
#include "../cbmc.h"
|
||||
#include "../common.h"
|
||||
|
||||
#include "fips202.h"
|
||||
#include "keccakf1600.h"
|
||||
|
||||
/** Context for the non-incremental 4-way SHAKE128 API. */
|
||||
typedef struct
|
||||
{
|
||||
uint64_t ctx[MLK_KECCAK_LANES *
|
||||
MLK_KECCAK_WAY]; /**< 4-way Keccak state, stored sequentially. */
|
||||
} MLK_ALIGN mlk_shake128x4ctx;
|
||||
|
||||
#define mlk_shake128x4_absorb_once MLK_NAMESPACE(shake128x4_absorb_once)
|
||||
void mlk_shake128x4_absorb_once(mlk_shake128x4ctx *state, const uint8_t *in0,
|
||||
const uint8_t *in1, const uint8_t *in2,
|
||||
const uint8_t *in3, size_t inlen)
|
||||
__contract__(
|
||||
requires(inlen <= MLK_MAX_BUFFER_SIZE)
|
||||
requires(memory_no_alias(state, sizeof(mlk_shake128x4ctx)))
|
||||
requires(memory_no_alias(in0, inlen))
|
||||
requires(memory_no_alias(in1, inlen))
|
||||
requires(memory_no_alias(in2, inlen))
|
||||
requires(memory_no_alias(in3, inlen))
|
||||
assigns(memory_slice(state, sizeof(mlk_shake128x4ctx)))
|
||||
);
|
||||
|
||||
#define mlk_shake128x4_squeezeblocks MLK_NAMESPACE(shake128x4_squeezeblocks)
|
||||
void mlk_shake128x4_squeezeblocks(uint8_t *out0, uint8_t *out1, uint8_t *out2,
|
||||
uint8_t *out3, size_t nblocks,
|
||||
mlk_shake128x4ctx *state)
|
||||
__contract__(
|
||||
requires(nblocks <= 8 /* somewhat arbitrary bound */)
|
||||
requires(memory_no_alias(state, sizeof(mlk_shake128x4ctx)))
|
||||
requires(memory_no_alias(out0, nblocks * SHAKE128_RATE))
|
||||
requires(memory_no_alias(out1, nblocks * SHAKE128_RATE))
|
||||
requires(memory_no_alias(out2, nblocks * SHAKE128_RATE))
|
||||
requires(memory_no_alias(out3, nblocks * SHAKE128_RATE))
|
||||
assigns(memory_slice(out0, nblocks * SHAKE128_RATE),
|
||||
memory_slice(out1, nblocks * SHAKE128_RATE),
|
||||
memory_slice(out2, nblocks * SHAKE128_RATE),
|
||||
memory_slice(out3, nblocks * SHAKE128_RATE),
|
||||
memory_slice(state, sizeof(mlk_shake128x4ctx)))
|
||||
);
|
||||
|
||||
#define mlk_shake128x4_init MLK_NAMESPACE(shake128x4_init)
|
||||
void mlk_shake128x4_init(mlk_shake128x4ctx *state);
|
||||
|
||||
#define mlk_shake128x4_release MLK_NAMESPACE(shake128x4_release)
|
||||
void mlk_shake128x4_release(mlk_shake128x4ctx *state);
|
||||
|
||||
#define mlk_shake256x4 MLK_NAMESPACE(shake256x4)
|
||||
void mlk_shake256x4(uint8_t *out0, uint8_t *out1, uint8_t *out2, uint8_t *out3,
|
||||
size_t outlen, const uint8_t *in0, const uint8_t *in1,
|
||||
const uint8_t *in2, const uint8_t *in3, size_t inlen)
|
||||
__contract__(
|
||||
requires(inlen <= MLK_MAX_BUFFER_SIZE)
|
||||
requires(outlen <= MLK_MAX_BUFFER_SIZE)
|
||||
requires(memory_no_alias(in0, inlen))
|
||||
requires(memory_no_alias(in1, inlen))
|
||||
requires(memory_no_alias(in2, inlen))
|
||||
requires(memory_no_alias(in3, inlen))
|
||||
requires(memory_no_alias(out0, outlen))
|
||||
requires(memory_no_alias(out1, outlen))
|
||||
requires(memory_no_alias(out2, outlen))
|
||||
requires(memory_no_alias(out3, outlen))
|
||||
assigns(memory_slice(out0, outlen))
|
||||
assigns(memory_slice(out1, outlen))
|
||||
assigns(memory_slice(out2, outlen))
|
||||
assigns(memory_slice(out3, outlen))
|
||||
);
|
||||
|
||||
#endif /* !MLK_FIPS202_FIPS202X4_H */
|
||||
@@ -1,499 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
|
||||
/* References
|
||||
* ==========
|
||||
*
|
||||
* - [mupq]
|
||||
* Common files for pqm4, pqm3, pqriscv
|
||||
* Kannwischer, Petri, Rijneveld, Schwabe, Stoffelen
|
||||
* https://github.com/mupq/mupq
|
||||
*
|
||||
* - [supercop]
|
||||
* SUPERCOP benchmarking framework
|
||||
* Daniel J. Bernstein
|
||||
* http://bench.cr.yp.to/supercop.html
|
||||
*
|
||||
* - [tweetfips]
|
||||
* 'tweetfips202' FIPS202 implementation
|
||||
* Van Assche, Bernstein, Schwabe
|
||||
* https://keccak.team/2015/tweetfips202.html
|
||||
*/
|
||||
|
||||
/* Based on the CC0 implementation from @[mupq] and the public domain
|
||||
* implementation @[supercop, crypto_hash/keccakc512/simple/]
|
||||
* by Ronny Van Keer, and the public domain @[tweetfips] implementation. */
|
||||
|
||||
|
||||
#include "keccakf1600.h"
|
||||
#if !defined(MLK_CONFIG_MULTILEVEL_NO_SHARED)
|
||||
|
||||
#define MLK_KECCAK_NROUNDS 24
|
||||
#define MLK_KECCAK_ROL(a, offset) (((a) << (offset)) ^ ((a) >> (64 - (offset))))
|
||||
|
||||
void mlk_keccakf1600_extract_bytes(uint64_t *state, unsigned char *data,
|
||||
unsigned offset, unsigned length)
|
||||
{
|
||||
unsigned i;
|
||||
#if defined(MLK_SYS_LITTLE_ENDIAN)
|
||||
uint8_t *state_ptr = (uint8_t *)state + offset;
|
||||
for (i = 0; i < length; i++)
|
||||
__loop__(invariant(i <= length)
|
||||
decreases(length - i))
|
||||
{
|
||||
data[i] = state_ptr[i];
|
||||
}
|
||||
#else /* MLK_SYS_LITTLE_ENDIAN */
|
||||
/* Portable version */
|
||||
for (i = 0; i < length; i++)
|
||||
__loop__(invariant(i <= length)
|
||||
decreases(length - i))
|
||||
{
|
||||
data[i] = (state[(offset + i) >> 3] >> (8 * ((offset + i) & 0x07))) & 0xFF;
|
||||
}
|
||||
#endif /* !MLK_SYS_LITTLE_ENDIAN */
|
||||
}
|
||||
|
||||
void mlk_keccakf1600_xor_bytes(uint64_t *state, const unsigned char *data,
|
||||
unsigned offset, unsigned length)
|
||||
{
|
||||
unsigned i;
|
||||
#if defined(MLK_SYS_LITTLE_ENDIAN)
|
||||
uint8_t *state_ptr = (uint8_t *)state + offset;
|
||||
for (i = 0; i < length; i++)
|
||||
__loop__(invariant(i <= length)
|
||||
decreases(length - i))
|
||||
{
|
||||
state_ptr[i] ^= data[i];
|
||||
}
|
||||
#else /* MLK_SYS_LITTLE_ENDIAN */
|
||||
/* Portable version */
|
||||
for (i = 0; i < length; i++)
|
||||
__loop__(invariant(i <= length)
|
||||
decreases(length - i))
|
||||
{
|
||||
state[(offset + i) >> 3] ^= (uint64_t)data[i]
|
||||
<< (8 * ((offset + i) & 0x07));
|
||||
}
|
||||
#endif /* !MLK_SYS_LITTLE_ENDIAN */
|
||||
}
|
||||
|
||||
static void mlk_keccakf1600x4_extract_bytes_c(uint64_t *state,
|
||||
unsigned char *data0,
|
||||
unsigned char *data1,
|
||||
unsigned char *data2,
|
||||
unsigned char *data3,
|
||||
unsigned offset, unsigned length)
|
||||
__contract__(
|
||||
requires(0 <= offset && offset <= MLK_KECCAK_LANES * sizeof(uint64_t) &&
|
||||
0 <= length && length <= MLK_KECCAK_LANES * sizeof(uint64_t) - offset)
|
||||
requires(memory_no_alias(state, sizeof(uint64_t) * MLK_KECCAK_LANES * MLK_KECCAK_WAY))
|
||||
requires(memory_no_alias(data0, length))
|
||||
requires(memory_no_alias(data1, length))
|
||||
requires(memory_no_alias(data2, length))
|
||||
requires(memory_no_alias(data3, length))
|
||||
assigns(memory_slice(data0, length))
|
||||
assigns(memory_slice(data1, length))
|
||||
assigns(memory_slice(data2, length))
|
||||
assigns(memory_slice(data3, length))
|
||||
)
|
||||
{
|
||||
mlk_keccakf1600_extract_bytes(state + MLK_KECCAK_LANES * 0, data0, offset,
|
||||
length);
|
||||
mlk_keccakf1600_extract_bytes(state + MLK_KECCAK_LANES * 1, data1, offset,
|
||||
length);
|
||||
mlk_keccakf1600_extract_bytes(state + MLK_KECCAK_LANES * 2, data2, offset,
|
||||
length);
|
||||
mlk_keccakf1600_extract_bytes(state + MLK_KECCAK_LANES * 3, data3, offset,
|
||||
length);
|
||||
}
|
||||
|
||||
void mlk_keccakf1600x4_extract_bytes(uint64_t *state, unsigned char *data0,
|
||||
unsigned char *data1, unsigned char *data2,
|
||||
unsigned char *data3, unsigned offset,
|
||||
unsigned length)
|
||||
{
|
||||
#if defined(MLK_USE_FIPS202_X4_EXTRACT_BYTES_NATIVE)
|
||||
if (mlk_keccakf1600_extract_bytes_x4_native(state, data0, data1, data2, data3,
|
||||
offset, length) ==
|
||||
MLK_NATIVE_FUNC_SUCCESS)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif /* MLK_USE_FIPS202_X4_EXTRACT_BYTES_NATIVE */
|
||||
mlk_keccakf1600x4_extract_bytes_c(state, data0, data1, data2, data3, offset,
|
||||
length);
|
||||
}
|
||||
|
||||
static void mlk_keccakf1600x4_xor_bytes_c(uint64_t *state,
|
||||
const unsigned char *data0,
|
||||
const unsigned char *data1,
|
||||
const unsigned char *data2,
|
||||
const unsigned char *data3,
|
||||
unsigned offset, unsigned length)
|
||||
__contract__(
|
||||
requires(0 <= offset && offset <= MLK_KECCAK_LANES * sizeof(uint64_t) &&
|
||||
0 <= length && length <= MLK_KECCAK_LANES * sizeof(uint64_t) - offset)
|
||||
requires(memory_no_alias(state, sizeof(uint64_t) * MLK_KECCAK_LANES * MLK_KECCAK_WAY))
|
||||
requires(memory_no_alias(data0, length))
|
||||
/* Case 1: all input buffers are distinct; Case 2: All input buffers are the same */
|
||||
requires((data0 == data1 &&
|
||||
data0 == data2 &&
|
||||
data0 == data3) ||
|
||||
(memory_no_alias(data1, length) &&
|
||||
memory_no_alias(data2, length) &&
|
||||
memory_no_alias(data3, length)))
|
||||
assigns(memory_slice(state, sizeof(uint64_t) * MLK_KECCAK_LANES * MLK_KECCAK_WAY))
|
||||
)
|
||||
{
|
||||
mlk_keccakf1600_xor_bytes(state + MLK_KECCAK_LANES * 0, data0, offset,
|
||||
length);
|
||||
mlk_keccakf1600_xor_bytes(state + MLK_KECCAK_LANES * 1, data1, offset,
|
||||
length);
|
||||
mlk_keccakf1600_xor_bytes(state + MLK_KECCAK_LANES * 2, data2, offset,
|
||||
length);
|
||||
mlk_keccakf1600_xor_bytes(state + MLK_KECCAK_LANES * 3, data3, offset,
|
||||
length);
|
||||
}
|
||||
|
||||
void mlk_keccakf1600x4_xor_bytes(uint64_t *state, const unsigned char *data0,
|
||||
const unsigned char *data1,
|
||||
const unsigned char *data2,
|
||||
const unsigned char *data3, unsigned offset,
|
||||
unsigned length)
|
||||
{
|
||||
#if defined(MLK_USE_FIPS202_X4_XOR_BYTES_NATIVE)
|
||||
if (mlk_keccakf1600_xor_bytes_x4_native(state, data0, data1, data2, data3,
|
||||
offset,
|
||||
length) == MLK_NATIVE_FUNC_SUCCESS)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif /* MLK_USE_FIPS202_X4_XOR_BYTES_NATIVE */
|
||||
mlk_keccakf1600x4_xor_bytes_c(state, data0, data1, data2, data3, offset,
|
||||
length);
|
||||
}
|
||||
|
||||
void mlk_keccakf1600x4_permute(uint64_t *state)
|
||||
{
|
||||
#if defined(MLK_USE_FIPS202_X4_NATIVE)
|
||||
if (mlk_keccak_f1600_x4_native(state) == MLK_NATIVE_FUNC_SUCCESS)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif /* MLK_USE_FIPS202_X4_NATIVE */
|
||||
mlk_keccakf1600_permute(state + MLK_KECCAK_LANES * 0);
|
||||
mlk_keccakf1600_permute(state + MLK_KECCAK_LANES * 1);
|
||||
mlk_keccakf1600_permute(state + MLK_KECCAK_LANES * 2);
|
||||
mlk_keccakf1600_permute(state + MLK_KECCAK_LANES * 3);
|
||||
}
|
||||
|
||||
static const uint64_t mlk_KeccakF_RoundConstants[MLK_KECCAK_NROUNDS] = {
|
||||
(uint64_t)0x0000000000000001ULL, (uint64_t)0x0000000000008082ULL,
|
||||
(uint64_t)0x800000000000808aULL, (uint64_t)0x8000000080008000ULL,
|
||||
(uint64_t)0x000000000000808bULL, (uint64_t)0x0000000080000001ULL,
|
||||
(uint64_t)0x8000000080008081ULL, (uint64_t)0x8000000000008009ULL,
|
||||
(uint64_t)0x000000000000008aULL, (uint64_t)0x0000000000000088ULL,
|
||||
(uint64_t)0x0000000080008009ULL, (uint64_t)0x000000008000000aULL,
|
||||
(uint64_t)0x000000008000808bULL, (uint64_t)0x800000000000008bULL,
|
||||
(uint64_t)0x8000000000008089ULL, (uint64_t)0x8000000000008003ULL,
|
||||
(uint64_t)0x8000000000008002ULL, (uint64_t)0x8000000000000080ULL,
|
||||
(uint64_t)0x000000000000800aULL, (uint64_t)0x800000008000000aULL,
|
||||
(uint64_t)0x8000000080008081ULL, (uint64_t)0x8000000000008080ULL,
|
||||
(uint64_t)0x0000000080000001ULL, (uint64_t)0x8000000080008008ULL};
|
||||
|
||||
MLK_STATIC_TESTABLE
|
||||
void mlk_keccakf1600_permute_c(uint64_t *state)
|
||||
__contract__(
|
||||
requires(memory_no_alias(state, sizeof(uint64_t) * MLK_KECCAK_LANES))
|
||||
assigns(memory_slice(state, sizeof(uint64_t) * MLK_KECCAK_LANES))
|
||||
)
|
||||
{
|
||||
unsigned round;
|
||||
|
||||
uint64_t Aba, Abe, Abi, Abo, Abu;
|
||||
uint64_t Aga, Age, Agi, Ago, Agu;
|
||||
uint64_t Aka, Ake, Aki, Ako, Aku;
|
||||
uint64_t Ama, Ame, Ami, Amo, Amu;
|
||||
uint64_t Asa, Ase, Asi, Aso, Asu;
|
||||
uint64_t BCa, BCe, BCi, BCo, BCu;
|
||||
uint64_t Da, De, Di, Do, Du;
|
||||
uint64_t Eba, Ebe, Ebi, Ebo, Ebu;
|
||||
uint64_t Ega, Ege, Egi, Ego, Egu;
|
||||
uint64_t Eka, Eke, Eki, Eko, Eku;
|
||||
uint64_t Ema, Eme, Emi, Emo, Emu;
|
||||
uint64_t Esa, Ese, Esi, Eso, Esu;
|
||||
|
||||
/* copyFromState(A, state) */
|
||||
Aba = state[0];
|
||||
Abe = state[1];
|
||||
Abi = state[2];
|
||||
Abo = state[3];
|
||||
Abu = state[4];
|
||||
Aga = state[5];
|
||||
Age = state[6];
|
||||
Agi = state[7];
|
||||
Ago = state[8];
|
||||
Agu = state[9];
|
||||
Aka = state[10];
|
||||
Ake = state[11];
|
||||
Aki = state[12];
|
||||
Ako = state[13];
|
||||
Aku = state[14];
|
||||
Ama = state[15];
|
||||
Ame = state[16];
|
||||
Ami = state[17];
|
||||
Amo = state[18];
|
||||
Amu = state[19];
|
||||
Asa = state[20];
|
||||
Ase = state[21];
|
||||
Asi = state[22];
|
||||
Aso = state[23];
|
||||
Asu = state[24];
|
||||
|
||||
for (round = 0; round < MLK_KECCAK_NROUNDS; round += 2)
|
||||
__loop__(invariant(round <= MLK_KECCAK_NROUNDS && round % 2 == 0)
|
||||
decreases(MLK_KECCAK_NROUNDS - round))
|
||||
{
|
||||
/* prepareTheta */
|
||||
BCa = Aba ^ Aga ^ Aka ^ Ama ^ Asa;
|
||||
BCe = Abe ^ Age ^ Ake ^ Ame ^ Ase;
|
||||
BCi = Abi ^ Agi ^ Aki ^ Ami ^ Asi;
|
||||
BCo = Abo ^ Ago ^ Ako ^ Amo ^ Aso;
|
||||
BCu = Abu ^ Agu ^ Aku ^ Amu ^ Asu;
|
||||
|
||||
/* thetaRhoPiChiIotaPrepareTheta(round, A, E) */
|
||||
Da = BCu ^ MLK_KECCAK_ROL(BCe, 1);
|
||||
De = BCa ^ MLK_KECCAK_ROL(BCi, 1);
|
||||
Di = BCe ^ MLK_KECCAK_ROL(BCo, 1);
|
||||
Do = BCi ^ MLK_KECCAK_ROL(BCu, 1);
|
||||
Du = BCo ^ MLK_KECCAK_ROL(BCa, 1);
|
||||
|
||||
Aba ^= Da;
|
||||
BCa = Aba;
|
||||
Age ^= De;
|
||||
BCe = MLK_KECCAK_ROL(Age, 44);
|
||||
Aki ^= Di;
|
||||
BCi = MLK_KECCAK_ROL(Aki, 43);
|
||||
Amo ^= Do;
|
||||
BCo = MLK_KECCAK_ROL(Amo, 21);
|
||||
Asu ^= Du;
|
||||
BCu = MLK_KECCAK_ROL(Asu, 14);
|
||||
Eba = BCa ^ ((~BCe) & BCi);
|
||||
Eba ^= (uint64_t)mlk_KeccakF_RoundConstants[round];
|
||||
Ebe = BCe ^ ((~BCi) & BCo);
|
||||
Ebi = BCi ^ ((~BCo) & BCu);
|
||||
Ebo = BCo ^ ((~BCu) & BCa);
|
||||
Ebu = BCu ^ ((~BCa) & BCe);
|
||||
|
||||
Abo ^= Do;
|
||||
BCa = MLK_KECCAK_ROL(Abo, 28);
|
||||
Agu ^= Du;
|
||||
BCe = MLK_KECCAK_ROL(Agu, 20);
|
||||
Aka ^= Da;
|
||||
BCi = MLK_KECCAK_ROL(Aka, 3);
|
||||
Ame ^= De;
|
||||
BCo = MLK_KECCAK_ROL(Ame, 45);
|
||||
Asi ^= Di;
|
||||
BCu = MLK_KECCAK_ROL(Asi, 61);
|
||||
Ega = BCa ^ ((~BCe) & BCi);
|
||||
Ege = BCe ^ ((~BCi) & BCo);
|
||||
Egi = BCi ^ ((~BCo) & BCu);
|
||||
Ego = BCo ^ ((~BCu) & BCa);
|
||||
Egu = BCu ^ ((~BCa) & BCe);
|
||||
|
||||
Abe ^= De;
|
||||
BCa = MLK_KECCAK_ROL(Abe, 1);
|
||||
Agi ^= Di;
|
||||
BCe = MLK_KECCAK_ROL(Agi, 6);
|
||||
Ako ^= Do;
|
||||
BCi = MLK_KECCAK_ROL(Ako, 25);
|
||||
Amu ^= Du;
|
||||
BCo = MLK_KECCAK_ROL(Amu, 8);
|
||||
Asa ^= Da;
|
||||
BCu = MLK_KECCAK_ROL(Asa, 18);
|
||||
Eka = BCa ^ ((~BCe) & BCi);
|
||||
Eke = BCe ^ ((~BCi) & BCo);
|
||||
Eki = BCi ^ ((~BCo) & BCu);
|
||||
Eko = BCo ^ ((~BCu) & BCa);
|
||||
Eku = BCu ^ ((~BCa) & BCe);
|
||||
|
||||
Abu ^= Du;
|
||||
BCa = MLK_KECCAK_ROL(Abu, 27);
|
||||
Aga ^= Da;
|
||||
BCe = MLK_KECCAK_ROL(Aga, 36);
|
||||
Ake ^= De;
|
||||
BCi = MLK_KECCAK_ROL(Ake, 10);
|
||||
Ami ^= Di;
|
||||
BCo = MLK_KECCAK_ROL(Ami, 15);
|
||||
Aso ^= Do;
|
||||
BCu = MLK_KECCAK_ROL(Aso, 56);
|
||||
Ema = BCa ^ ((~BCe) & BCi);
|
||||
Eme = BCe ^ ((~BCi) & BCo);
|
||||
Emi = BCi ^ ((~BCo) & BCu);
|
||||
Emo = BCo ^ ((~BCu) & BCa);
|
||||
Emu = BCu ^ ((~BCa) & BCe);
|
||||
|
||||
Abi ^= Di;
|
||||
BCa = MLK_KECCAK_ROL(Abi, 62);
|
||||
Ago ^= Do;
|
||||
BCe = MLK_KECCAK_ROL(Ago, 55);
|
||||
Aku ^= Du;
|
||||
BCi = MLK_KECCAK_ROL(Aku, 39);
|
||||
Ama ^= Da;
|
||||
BCo = MLK_KECCAK_ROL(Ama, 41);
|
||||
Ase ^= De;
|
||||
BCu = MLK_KECCAK_ROL(Ase, 2);
|
||||
Esa = BCa ^ ((~BCe) & BCi);
|
||||
Ese = BCe ^ ((~BCi) & BCo);
|
||||
Esi = BCi ^ ((~BCo) & BCu);
|
||||
Eso = BCo ^ ((~BCu) & BCa);
|
||||
Esu = BCu ^ ((~BCa) & BCe);
|
||||
|
||||
/* prepareTheta */
|
||||
BCa = Eba ^ Ega ^ Eka ^ Ema ^ Esa;
|
||||
BCe = Ebe ^ Ege ^ Eke ^ Eme ^ Ese;
|
||||
BCi = Ebi ^ Egi ^ Eki ^ Emi ^ Esi;
|
||||
BCo = Ebo ^ Ego ^ Eko ^ Emo ^ Eso;
|
||||
BCu = Ebu ^ Egu ^ Eku ^ Emu ^ Esu;
|
||||
|
||||
/* thetaRhoPiChiIotaPrepareTheta(round+1, E, A) */
|
||||
Da = BCu ^ MLK_KECCAK_ROL(BCe, 1);
|
||||
De = BCa ^ MLK_KECCAK_ROL(BCi, 1);
|
||||
Di = BCe ^ MLK_KECCAK_ROL(BCo, 1);
|
||||
Do = BCi ^ MLK_KECCAK_ROL(BCu, 1);
|
||||
Du = BCo ^ MLK_KECCAK_ROL(BCa, 1);
|
||||
|
||||
Eba ^= Da;
|
||||
BCa = Eba;
|
||||
Ege ^= De;
|
||||
BCe = MLK_KECCAK_ROL(Ege, 44);
|
||||
Eki ^= Di;
|
||||
BCi = MLK_KECCAK_ROL(Eki, 43);
|
||||
Emo ^= Do;
|
||||
BCo = MLK_KECCAK_ROL(Emo, 21);
|
||||
Esu ^= Du;
|
||||
BCu = MLK_KECCAK_ROL(Esu, 14);
|
||||
Aba = BCa ^ ((~BCe) & BCi);
|
||||
Aba ^= (uint64_t)mlk_KeccakF_RoundConstants[round + 1];
|
||||
Abe = BCe ^ ((~BCi) & BCo);
|
||||
Abi = BCi ^ ((~BCo) & BCu);
|
||||
Abo = BCo ^ ((~BCu) & BCa);
|
||||
Abu = BCu ^ ((~BCa) & BCe);
|
||||
|
||||
Ebo ^= Do;
|
||||
BCa = MLK_KECCAK_ROL(Ebo, 28);
|
||||
Egu ^= Du;
|
||||
BCe = MLK_KECCAK_ROL(Egu, 20);
|
||||
Eka ^= Da;
|
||||
BCi = MLK_KECCAK_ROL(Eka, 3);
|
||||
Eme ^= De;
|
||||
BCo = MLK_KECCAK_ROL(Eme, 45);
|
||||
Esi ^= Di;
|
||||
BCu = MLK_KECCAK_ROL(Esi, 61);
|
||||
Aga = BCa ^ ((~BCe) & BCi);
|
||||
Age = BCe ^ ((~BCi) & BCo);
|
||||
Agi = BCi ^ ((~BCo) & BCu);
|
||||
Ago = BCo ^ ((~BCu) & BCa);
|
||||
Agu = BCu ^ ((~BCa) & BCe);
|
||||
|
||||
Ebe ^= De;
|
||||
BCa = MLK_KECCAK_ROL(Ebe, 1);
|
||||
Egi ^= Di;
|
||||
BCe = MLK_KECCAK_ROL(Egi, 6);
|
||||
Eko ^= Do;
|
||||
BCi = MLK_KECCAK_ROL(Eko, 25);
|
||||
Emu ^= Du;
|
||||
BCo = MLK_KECCAK_ROL(Emu, 8);
|
||||
Esa ^= Da;
|
||||
BCu = MLK_KECCAK_ROL(Esa, 18);
|
||||
Aka = BCa ^ ((~BCe) & BCi);
|
||||
Ake = BCe ^ ((~BCi) & BCo);
|
||||
Aki = BCi ^ ((~BCo) & BCu);
|
||||
Ako = BCo ^ ((~BCu) & BCa);
|
||||
Aku = BCu ^ ((~BCa) & BCe);
|
||||
|
||||
Ebu ^= Du;
|
||||
BCa = MLK_KECCAK_ROL(Ebu, 27);
|
||||
Ega ^= Da;
|
||||
BCe = MLK_KECCAK_ROL(Ega, 36);
|
||||
Eke ^= De;
|
||||
BCi = MLK_KECCAK_ROL(Eke, 10);
|
||||
Emi ^= Di;
|
||||
BCo = MLK_KECCAK_ROL(Emi, 15);
|
||||
Eso ^= Do;
|
||||
BCu = MLK_KECCAK_ROL(Eso, 56);
|
||||
Ama = BCa ^ ((~BCe) & BCi);
|
||||
Ame = BCe ^ ((~BCi) & BCo);
|
||||
Ami = BCi ^ ((~BCo) & BCu);
|
||||
Amo = BCo ^ ((~BCu) & BCa);
|
||||
Amu = BCu ^ ((~BCa) & BCe);
|
||||
|
||||
Ebi ^= Di;
|
||||
BCa = MLK_KECCAK_ROL(Ebi, 62);
|
||||
Ego ^= Do;
|
||||
BCe = MLK_KECCAK_ROL(Ego, 55);
|
||||
Eku ^= Du;
|
||||
BCi = MLK_KECCAK_ROL(Eku, 39);
|
||||
Ema ^= Da;
|
||||
BCo = MLK_KECCAK_ROL(Ema, 41);
|
||||
Ese ^= De;
|
||||
BCu = MLK_KECCAK_ROL(Ese, 2);
|
||||
Asa = BCa ^ ((~BCe) & BCi);
|
||||
Ase = BCe ^ ((~BCi) & BCo);
|
||||
Asi = BCi ^ ((~BCo) & BCu);
|
||||
Aso = BCo ^ ((~BCu) & BCa);
|
||||
Asu = BCu ^ ((~BCa) & BCe);
|
||||
}
|
||||
|
||||
/* copyToState(state, A) */
|
||||
state[0] = Aba;
|
||||
state[1] = Abe;
|
||||
state[2] = Abi;
|
||||
state[3] = Abo;
|
||||
state[4] = Abu;
|
||||
state[5] = Aga;
|
||||
state[6] = Age;
|
||||
state[7] = Agi;
|
||||
state[8] = Ago;
|
||||
state[9] = Agu;
|
||||
state[10] = Aka;
|
||||
state[11] = Ake;
|
||||
state[12] = Aki;
|
||||
state[13] = Ako;
|
||||
state[14] = Aku;
|
||||
state[15] = Ama;
|
||||
state[16] = Ame;
|
||||
state[17] = Ami;
|
||||
state[18] = Amo;
|
||||
state[19] = Amu;
|
||||
state[20] = Asa;
|
||||
state[21] = Ase;
|
||||
state[22] = Asi;
|
||||
state[23] = Aso;
|
||||
state[24] = Asu;
|
||||
}
|
||||
|
||||
void mlk_keccakf1600_permute(uint64_t *state)
|
||||
{
|
||||
#if defined(MLK_USE_FIPS202_X1_NATIVE)
|
||||
if (mlk_keccak_f1600_x1_native(state) == MLK_NATIVE_FUNC_SUCCESS)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif /* MLK_USE_FIPS202_X1_NATIVE */
|
||||
mlk_keccakf1600_permute_c(state);
|
||||
}
|
||||
|
||||
#else /* !MLK_CONFIG_MULTILEVEL_NO_SHARED */
|
||||
|
||||
MLK_EMPTY_CU(keccakf1600)
|
||||
|
||||
#endif /* MLK_CONFIG_MULTILEVEL_NO_SHARED */
|
||||
|
||||
/* To facilitate single-compilation-unit (SCU) builds, undefine all macros.
|
||||
* Don't modify by hand -- this is auto-generated by scripts/autogen. */
|
||||
#undef MLK_KECCAK_NROUNDS
|
||||
#undef MLK_KECCAK_ROL
|
||||
@@ -1,98 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
#ifndef MLK_FIPS202_KECCAKF1600_H
|
||||
#define MLK_FIPS202_KECCAKF1600_H
|
||||
#include "../cbmc.h"
|
||||
#include "../common.h"
|
||||
|
||||
#define MLK_KECCAK_LANES 25
|
||||
#define MLK_KECCAK_WAY 4
|
||||
|
||||
/*
|
||||
* WARNING:
|
||||
* The contents of this structure, including the placement
|
||||
* and interleaving of Keccak lanes, are IMPLEMENTATION-DEFINED.
|
||||
* The struct is only exposed here to allow its construction on the stack.
|
||||
*/
|
||||
|
||||
#define mlk_keccakf1600_extract_bytes MLK_NAMESPACE(keccakf1600_extract_bytes)
|
||||
void mlk_keccakf1600_extract_bytes(uint64_t *state, unsigned char *data,
|
||||
unsigned offset, unsigned length)
|
||||
__contract__(
|
||||
requires(0 <= offset && offset <= MLK_KECCAK_LANES * sizeof(uint64_t) &&
|
||||
0 <= length && length <= MLK_KECCAK_LANES * sizeof(uint64_t) - offset)
|
||||
requires(memory_no_alias(state, sizeof(uint64_t) * MLK_KECCAK_LANES))
|
||||
requires(memory_no_alias(data, length))
|
||||
assigns(memory_slice(data, length))
|
||||
);
|
||||
|
||||
#define mlk_keccakf1600_xor_bytes MLK_NAMESPACE(keccakf1600_xor_bytes)
|
||||
void mlk_keccakf1600_xor_bytes(uint64_t *state, const unsigned char *data,
|
||||
unsigned offset, unsigned length)
|
||||
__contract__(
|
||||
requires(0 <= offset && offset <= MLK_KECCAK_LANES * sizeof(uint64_t) &&
|
||||
0 <= length && length <= MLK_KECCAK_LANES * sizeof(uint64_t) - offset)
|
||||
requires(memory_no_alias(state, sizeof(uint64_t) * MLK_KECCAK_LANES))
|
||||
requires(memory_no_alias(data, length))
|
||||
assigns(memory_slice(state, sizeof(uint64_t) * MLK_KECCAK_LANES))
|
||||
);
|
||||
|
||||
#define mlk_keccakf1600x4_extract_bytes \
|
||||
MLK_NAMESPACE(keccakf1600x4_extract_bytes)
|
||||
void mlk_keccakf1600x4_extract_bytes(uint64_t *state, unsigned char *data0,
|
||||
unsigned char *data1, unsigned char *data2,
|
||||
unsigned char *data3, unsigned offset,
|
||||
unsigned length)
|
||||
__contract__(
|
||||
requires(0 <= offset && offset <= MLK_KECCAK_LANES * sizeof(uint64_t) &&
|
||||
0 <= length && length <= MLK_KECCAK_LANES * sizeof(uint64_t) - offset)
|
||||
requires(memory_no_alias(state, sizeof(uint64_t) * MLK_KECCAK_LANES * MLK_KECCAK_WAY))
|
||||
requires(memory_no_alias(data0, length))
|
||||
requires(memory_no_alias(data1, length))
|
||||
requires(memory_no_alias(data2, length))
|
||||
requires(memory_no_alias(data3, length))
|
||||
assigns(memory_slice(data0, length))
|
||||
assigns(memory_slice(data1, length))
|
||||
assigns(memory_slice(data2, length))
|
||||
assigns(memory_slice(data3, length))
|
||||
);
|
||||
|
||||
#define mlk_keccakf1600x4_xor_bytes MLK_NAMESPACE(keccakf1600x4_xor_bytes)
|
||||
void mlk_keccakf1600x4_xor_bytes(uint64_t *state, const unsigned char *data0,
|
||||
const unsigned char *data1,
|
||||
const unsigned char *data2,
|
||||
const unsigned char *data3, unsigned offset,
|
||||
unsigned length)
|
||||
__contract__(
|
||||
requires(0 <= offset && offset <= MLK_KECCAK_LANES * sizeof(uint64_t) &&
|
||||
0 <= length && length <= MLK_KECCAK_LANES * sizeof(uint64_t) - offset)
|
||||
requires(memory_no_alias(state, sizeof(uint64_t) * MLK_KECCAK_LANES * MLK_KECCAK_WAY))
|
||||
requires(memory_no_alias(data0, length))
|
||||
/* Case 1: all input buffers are distinct; Case 2: All input buffers are the same */
|
||||
requires((data0 == data1 &&
|
||||
data0 == data2 &&
|
||||
data0 == data3) ||
|
||||
(memory_no_alias(data1, length) &&
|
||||
memory_no_alias(data2, length) &&
|
||||
memory_no_alias(data3, length)))
|
||||
assigns(memory_slice(state, sizeof(uint64_t) * MLK_KECCAK_LANES * MLK_KECCAK_WAY))
|
||||
);
|
||||
|
||||
|
||||
#define mlk_keccakf1600x4_permute MLK_NAMESPACE(keccakf1600x4_permute)
|
||||
void mlk_keccakf1600x4_permute(uint64_t *state)
|
||||
__contract__(
|
||||
requires(memory_no_alias(state, sizeof(uint64_t) * MLK_KECCAK_LANES * MLK_KECCAK_WAY))
|
||||
assigns(memory_slice(state, sizeof(uint64_t) * MLK_KECCAK_LANES * MLK_KECCAK_WAY))
|
||||
);
|
||||
|
||||
#define mlk_keccakf1600_permute MLK_NAMESPACE(keccakf1600_permute)
|
||||
void mlk_keccakf1600_permute(uint64_t *state)
|
||||
__contract__(
|
||||
requires(memory_no_alias(state, sizeof(uint64_t) * MLK_KECCAK_LANES))
|
||||
assigns(memory_slice(state, sizeof(uint64_t) * MLK_KECCAK_LANES))
|
||||
);
|
||||
|
||||
#endif /* !MLK_FIPS202_KECCAKF1600_H */
|
||||
@@ -1,70 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
|
||||
/* References
|
||||
* ==========
|
||||
*
|
||||
* - [HYBRID]
|
||||
* Hybrid scalar/vector implementations of Keccak and SPHINCS+ on AArch64
|
||||
* Becker, Kannwischer
|
||||
* https://eprint.iacr.org/2022/1243
|
||||
*/
|
||||
|
||||
#ifndef MLK_FIPS202_NATIVE_AARCH64_AUTO_H
|
||||
#define MLK_FIPS202_NATIVE_AARCH64_AUTO_H
|
||||
/* Default FIPS202 assembly profile for AArch64 systems */
|
||||
|
||||
/*
|
||||
* Default logic to decide which implementation to use.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Keccak-f1600
|
||||
*
|
||||
* - On Arm-based Apple CPUs, we pick a pure Neon implementation.
|
||||
* - Otherwise, unless MLK_SYS_AARCH64_SLOW_BARREL_SHIFTER is set,
|
||||
* we use lazy-rotation scalar assembly from @[HYBRID].
|
||||
* - Otherwise, if MLK_SYS_AARCH64_SLOW_BARREL_SHIFTER is set, we
|
||||
* fall back to the standard C implementation.
|
||||
*/
|
||||
#if defined(__ARM_FEATURE_SHA3) && defined(__APPLE__)
|
||||
#include "x1_v84a.h"
|
||||
#elif !defined(MLK_SYS_AARCH64_SLOW_BARREL_SHIFTER)
|
||||
#include "x1_scalar.h"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Keccak-f1600x2/x4
|
||||
*
|
||||
* The optimal implementation is highly CPU-specific; see @[HYBRID].
|
||||
*
|
||||
* For now, if v8.4-A is not implemented, we fall back to Keccak-f1600.
|
||||
* If v8.4-A is implemented and we are on an Apple CPU, we use a plain
|
||||
* Neon-based implementation.
|
||||
* If v8.4-A is implemented and we are not on an Apple CPU, we use a
|
||||
* scalar/Neon/Neon hybrid.
|
||||
* The reason for this distinction is that Apple CPUs appear to implement
|
||||
* the SHA3 instructions on all SIMD units, while Arm CPUs prior to Cortex-X4
|
||||
* don't, and ordinary Neon instructions are still needed.
|
||||
*/
|
||||
#if defined(__ARM_FEATURE_SHA3)
|
||||
/*
|
||||
* For Apple-M cores, we use a plain implementation leveraging SHA3
|
||||
* instructions only.
|
||||
*/
|
||||
#if defined(__APPLE__)
|
||||
#include "x2_v84a.h"
|
||||
#else
|
||||
#include "x4_v8a_v84a_scalar.h"
|
||||
#endif
|
||||
|
||||
#else /* __ARM_FEATURE_SHA3 */
|
||||
|
||||
#include "x4_v8a_scalar.h"
|
||||
|
||||
#endif /* !__ARM_FEATURE_SHA3 */
|
||||
|
||||
#endif /* !MLK_FIPS202_NATIVE_AARCH64_AUTO_H */
|
||||
@@ -1,80 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
#ifndef MLK_FIPS202_NATIVE_AARCH64_SRC_FIPS202_NATIVE_AARCH64_H
|
||||
#define MLK_FIPS202_NATIVE_AARCH64_SRC_FIPS202_NATIVE_AARCH64_H
|
||||
|
||||
#include "../../../../cbmc.h"
|
||||
#include "../../../../common.h"
|
||||
|
||||
#define mlk_keccakf1600_round_constants \
|
||||
MLK_NAMESPACE(keccakf1600_round_constants)
|
||||
MLK_INTERNAL_DATA_DECLARATION const uint64_t
|
||||
mlk_keccakf1600_round_constants[24];
|
||||
|
||||
#define mlk_keccak_f1600_x1_scalar_aarch64_asm \
|
||||
MLK_NAMESPACE(keccak_f1600_x1_scalar_aarch64_asm)
|
||||
void mlk_keccak_f1600_x1_scalar_aarch64_asm(uint64_t state[25],
|
||||
const uint64_t rc[24])
|
||||
/* This must be kept in sync with the HOL-Light specification
|
||||
* in proofs/hol_light/aarch64/proofs/keccak_f1600_x1_scalar_aarch64_asm.ml */
|
||||
__contract__(
|
||||
requires(memory_no_alias(state, sizeof(uint64_t) * 25 * 1))
|
||||
requires(rc == mlk_keccakf1600_round_constants)
|
||||
assigns(memory_slice(state, sizeof(uint64_t) * 25 * 1))
|
||||
);
|
||||
|
||||
#define mlk_keccak_f1600_x1_v84a_aarch64_asm \
|
||||
MLK_NAMESPACE(keccak_f1600_x1_v84a_aarch64_asm)
|
||||
void mlk_keccak_f1600_x1_v84a_aarch64_asm(uint64_t state[25],
|
||||
const uint64_t rc[24])
|
||||
/* This must be kept in sync with the HOL-Light specification
|
||||
* in proofs/hol_light/aarch64/proofs/keccak_f1600_x1_v84a_aarch64_asm.ml */
|
||||
__contract__(
|
||||
requires(memory_no_alias(state, sizeof(uint64_t) * 25 * 1))
|
||||
requires(rc == mlk_keccakf1600_round_constants)
|
||||
assigns(memory_slice(state, sizeof(uint64_t) * 25 * 1))
|
||||
);
|
||||
|
||||
#define mlk_keccak_f1600_x2_v84a_aarch64_asm \
|
||||
MLK_NAMESPACE(keccak_f1600_x2_v84a_aarch64_asm)
|
||||
void mlk_keccak_f1600_x2_v84a_aarch64_asm(uint64_t state[50],
|
||||
const uint64_t rc[24])
|
||||
/* This must be kept in sync with the HOL-Light specification
|
||||
* in proofs/hol_light/aarch64/proofs/keccak_f1600_x2_v84a_aarch64_asm.ml */
|
||||
__contract__(
|
||||
requires(memory_no_alias(state, sizeof(uint64_t) * 25 * 2))
|
||||
requires(rc == mlk_keccakf1600_round_constants)
|
||||
assigns(memory_slice(state, sizeof(uint64_t) * 25 * 2))
|
||||
);
|
||||
|
||||
#define mlk_keccak_f1600_x4_v8a_scalar_hybrid_aarch64_asm \
|
||||
MLK_NAMESPACE(keccak_f1600_x4_v8a_scalar_hybrid_aarch64_asm)
|
||||
void mlk_keccak_f1600_x4_v8a_scalar_hybrid_aarch64_asm(uint64_t state[100],
|
||||
const uint64_t rc[24])
|
||||
/* This must be kept in sync with the HOL-Light specification
|
||||
* in
|
||||
* proofs/hol_light/aarch64/proofs/keccak_f1600_x4_v8a_scalar_hybrid_aarch64_asm.ml
|
||||
*/
|
||||
__contract__(
|
||||
requires(memory_no_alias(state, sizeof(uint64_t) * 25 * 4))
|
||||
requires(rc == mlk_keccakf1600_round_constants)
|
||||
assigns(memory_slice(state, sizeof(uint64_t) * 25 * 4))
|
||||
);
|
||||
|
||||
#define mlk_keccak_f1600_x4_v8a_v84a_scalar_hybrid_aarch64_asm \
|
||||
MLK_NAMESPACE(keccak_f1600_x4_v8a_v84a_scalar_hybrid_aarch64_asm)
|
||||
void mlk_keccak_f1600_x4_v8a_v84a_scalar_hybrid_aarch64_asm(
|
||||
uint64_t state[100], const uint64_t rc[24])
|
||||
/* This must be kept in sync with the HOL-Light specification
|
||||
* in
|
||||
* proofs/hol_light/aarch64/proofs/keccak_f1600_x4_v8a_v84a_scalar_hybrid_aarch64_asm.ml
|
||||
*/
|
||||
__contract__(
|
||||
requires(memory_no_alias(state, sizeof(uint64_t) * 25 * 4))
|
||||
requires(rc == mlk_keccakf1600_round_constants)
|
||||
assigns(memory_slice(state, sizeof(uint64_t) * 25 * 4))
|
||||
);
|
||||
|
||||
#endif /* !MLK_FIPS202_NATIVE_AARCH64_SRC_FIPS202_NATIVE_AARCH64_H */
|
||||
@@ -1,377 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* Copyright (c) 2021-2022 Arm Limited
|
||||
* Copyright (c) 2022 Matthias Kannwischer
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
|
||||
// Author: Hanno Becker <hanno.becker@arm.com>
|
||||
// Author: Matthias Kannwischer <matthias@kannwischer.eu>
|
||||
|
||||
/*yaml
|
||||
Name: keccak_f1600_x1_scalar_aarch64_asm
|
||||
Description: AArch64 scalar implementation of Keccak-f[1600] permutation for single state
|
||||
Signature: void mlk_keccak_f1600_x1_scalar_aarch64_asm(uint64_t state[25], const uint64_t rc[24])
|
||||
ABI:
|
||||
Architecture: aarch64
|
||||
CallingConvention: AAPCS64
|
||||
x0:
|
||||
type: buffer
|
||||
size_bytes: 200
|
||||
permissions: read/write
|
||||
c_parameter: uint64_t state[25]
|
||||
description: Keccak state (25 x uint64_t)
|
||||
x1:
|
||||
type: buffer
|
||||
size_bytes: 192
|
||||
permissions: read-only
|
||||
c_parameter: uint64_t const *rc
|
||||
description: Round constants (24 x uint64_t)
|
||||
Stack:
|
||||
bytes: 128
|
||||
description: register preservation and temporary storage
|
||||
*/
|
||||
|
||||
#include "../../../../common.h"
|
||||
#if defined(MLK_FIPS202_AARCH64_NEED_X1_SCALAR) && \
|
||||
!defined(MLK_CONFIG_MULTILEVEL_NO_SHARED)
|
||||
|
||||
/*
|
||||
* WARNING: This file is auto-derived from the mlkem-native source file
|
||||
* dev/fips202/aarch64/src/keccak_f1600_x1_scalar_aarch64_asm.S using scripts/simpasm. Do not modify it directly.
|
||||
*/
|
||||
|
||||
.text
|
||||
.balign 4
|
||||
.global MLK_ASM_NAMESPACE(keccak_f1600_x1_scalar_aarch64_asm)
|
||||
MLK_ASM_FN_SYMBOL(keccak_f1600_x1_scalar_aarch64_asm)
|
||||
|
||||
.cfi_startproc
|
||||
sub sp, sp, #0x80
|
||||
.cfi_adjust_cfa_offset 0x80
|
||||
stp x19, x20, [sp, #0x20]
|
||||
.cfi_rel_offset x19, 0x20
|
||||
.cfi_rel_offset x20, 0x28
|
||||
stp x21, x22, [sp, #0x30]
|
||||
.cfi_rel_offset x21, 0x30
|
||||
.cfi_rel_offset x22, 0x38
|
||||
stp x23, x24, [sp, #0x40]
|
||||
.cfi_rel_offset x23, 0x40
|
||||
.cfi_rel_offset x24, 0x48
|
||||
stp x25, x26, [sp, #0x50]
|
||||
.cfi_rel_offset x25, 0x50
|
||||
.cfi_rel_offset x26, 0x58
|
||||
stp x27, x28, [sp, #0x60]
|
||||
.cfi_rel_offset x27, 0x60
|
||||
.cfi_rel_offset x28, 0x68
|
||||
stp x29, x30, [sp, #0x70]
|
||||
.cfi_rel_offset x29, 0x70
|
||||
.cfi_rel_offset x30, 0x78
|
||||
|
||||
Lkeccak_f1600_x1_scalar_initial:
|
||||
mov x26, x1
|
||||
str x1, [sp, #0x8]
|
||||
ldp x1, x6, [x0]
|
||||
ldp x11, x16, [x0, #0x10]
|
||||
ldp x21, x2, [x0, #0x20]
|
||||
ldp x7, x12, [x0, #0x30]
|
||||
ldp x17, x22, [x0, #0x40]
|
||||
ldp x3, x8, [x0, #0x50]
|
||||
ldp x13, x28, [x0, #0x60]
|
||||
ldp x23, x4, [x0, #0x70]
|
||||
ldp x9, x14, [x0, #0x80]
|
||||
ldp x19, x24, [x0, #0x90]
|
||||
ldp x5, x10, [x0, #0xa0]
|
||||
ldp x15, x20, [x0, #0xb0]
|
||||
ldr x25, [x0, #0xc0]
|
||||
str x0, [sp]
|
||||
eor x30, x24, x25
|
||||
eor x27, x9, x10
|
||||
eor x0, x30, x21
|
||||
eor x26, x27, x6
|
||||
eor x27, x26, x7
|
||||
eor x29, x0, x22
|
||||
eor x26, x29, x23
|
||||
eor x29, x4, x5
|
||||
eor x30, x29, x1
|
||||
eor x0, x27, x8
|
||||
eor x29, x30, x2
|
||||
eor x30, x19, x20
|
||||
eor x30, x30, x16
|
||||
eor x27, x26, x0, ror #63
|
||||
eor x4, x4, x27
|
||||
eor x30, x30, x17
|
||||
eor x30, x30, x28
|
||||
eor x29, x29, x3
|
||||
eor x0, x0, x30, ror #63
|
||||
eor x30, x30, x29, ror #63
|
||||
eor x22, x22, x30
|
||||
eor x23, x23, x30
|
||||
str x23, [sp, #0x18]
|
||||
eor x23, x14, x15
|
||||
eor x14, x14, x0
|
||||
eor x23, x23, x11
|
||||
eor x15, x15, x0
|
||||
eor x1, x1, x27
|
||||
eor x23, x23, x12
|
||||
eor x23, x23, x13
|
||||
eor x11, x11, x0
|
||||
eor x29, x29, x23, ror #63
|
||||
eor x23, x23, x26, ror #63
|
||||
eor x26, x13, x0
|
||||
eor x13, x28, x23
|
||||
eor x28, x24, x30
|
||||
eor x24, x16, x23
|
||||
eor x16, x21, x30
|
||||
eor x21, x25, x30
|
||||
eor x30, x19, x23
|
||||
eor x19, x20, x23
|
||||
eor x20, x17, x23
|
||||
eor x17, x12, x0
|
||||
eor x0, x2, x27
|
||||
eor x2, x6, x29
|
||||
eor x6, x8, x29
|
||||
bic x8, x28, x13, ror #47
|
||||
eor x12, x3, x27
|
||||
bic x3, x13, x17, ror #19
|
||||
eor x5, x5, x27
|
||||
ldr x27, [sp, #0x18]
|
||||
bic x25, x17, x2, ror #5
|
||||
eor x9, x9, x29
|
||||
eor x23, x25, x5, ror #52
|
||||
eor x3, x3, x2, ror #24
|
||||
eor x8, x8, x17, ror #2
|
||||
eor x17, x10, x29
|
||||
bic x25, x12, x22, ror #47
|
||||
eor x29, x7, x29
|
||||
bic x10, x4, x27, ror #2
|
||||
bic x7, x5, x28, ror #10
|
||||
eor x10, x10, x20, ror #50
|
||||
eor x13, x7, x13, ror #57
|
||||
bic x7, x2, x5, ror #47
|
||||
eor x2, x25, x24, ror #39
|
||||
bic x25, x20, x11, ror #57
|
||||
bic x5, x17, x4, ror #25
|
||||
eor x25, x25, x17, ror #53
|
||||
bic x17, x11, x17, ror #60
|
||||
eor x28, x7, x28, ror #57
|
||||
bic x7, x9, x12, ror #42
|
||||
eor x7, x7, x22, ror #25
|
||||
bic x22, x22, x24, ror #56
|
||||
bic x24, x24, x15, ror #31
|
||||
eor x22, x22, x15, ror #23
|
||||
bic x20, x27, x20, ror #48
|
||||
bic x15, x15, x9, ror #16
|
||||
eor x12, x15, x12, ror #58
|
||||
eor x15, x5, x27, ror #27
|
||||
eor x5, x20, x11, ror #41
|
||||
ldr x11, [sp, #0x8]
|
||||
eor x20, x17, x4, ror #21
|
||||
eor x17, x24, x9, ror #47
|
||||
mov x24, #0x1 // =1
|
||||
bic x9, x0, x16, ror #9
|
||||
str x24, [sp, #0x10]
|
||||
bic x24, x29, x1, ror #44
|
||||
bic x27, x1, x21, ror #50
|
||||
bic x4, x26, x29, ror #63
|
||||
eor x1, x1, x4, ror #21
|
||||
ldr x11, [x11]
|
||||
bic x4, x21, x30, ror #57
|
||||
eor x21, x24, x21, ror #30
|
||||
eor x24, x9, x19, ror #44
|
||||
bic x9, x14, x6, ror #5
|
||||
eor x9, x9, x0, ror #43
|
||||
bic x0, x6, x0, ror #38
|
||||
eor x1, x1, x11
|
||||
eor x11, x4, x26, ror #35
|
||||
eor x4, x0, x16, ror #47
|
||||
bic x0, x16, x19, ror #35
|
||||
eor x16, x27, x30, ror #43
|
||||
bic x27, x30, x26, ror #42
|
||||
bic x26, x19, x14, ror #41
|
||||
eor x19, x0, x14, ror #12
|
||||
eor x14, x26, x6, ror #46
|
||||
eor x6, x27, x29, ror #41
|
||||
|
||||
Lkeccak_f1600_x1_scalar_loop:
|
||||
eor x0, x15, x11, ror #52
|
||||
eor x0, x0, x13, ror #48
|
||||
eor x26, x8, x9, ror #57
|
||||
eor x27, x0, x14, ror #10
|
||||
eor x29, x16, x28, ror #63
|
||||
eor x26, x26, x6, ror #51
|
||||
eor x30, x23, x22, ror #50
|
||||
eor x0, x26, x10, ror #31
|
||||
eor x29, x29, x19, ror #37
|
||||
eor x27, x27, x12, ror #5
|
||||
eor x30, x30, x24, ror #34
|
||||
eor x0, x0, x7, ror #27
|
||||
eor x26, x30, x21, ror #26
|
||||
eor x26, x26, x25, ror #15
|
||||
ror x30, x27, #0x3e
|
||||
eor x30, x30, x26, ror #57
|
||||
ror x26, x26, #0x3a
|
||||
eor x16, x30, x16
|
||||
eor x28, x30, x28, ror #63
|
||||
str x28, [sp, #0x18]
|
||||
eor x29, x29, x17, ror #36
|
||||
eor x28, x1, x2, ror #61
|
||||
eor x19, x30, x19, ror #37
|
||||
eor x29, x29, x20, ror #2
|
||||
eor x28, x28, x4, ror #54
|
||||
eor x26, x26, x0, ror #55
|
||||
eor x28, x28, x3, ror #39
|
||||
eor x28, x28, x5, ror #25
|
||||
ror x0, x0, #0x38
|
||||
eor x0, x0, x29, ror #63
|
||||
eor x27, x28, x27, ror #61
|
||||
eor x13, x0, x13, ror #46
|
||||
eor x28, x29, x28, ror #63
|
||||
eor x29, x30, x20, ror #2
|
||||
eor x20, x26, x3, ror #39
|
||||
eor x11, x0, x11, ror #50
|
||||
eor x25, x28, x25, ror #9
|
||||
eor x3, x28, x21, ror #20
|
||||
eor x21, x26, x1
|
||||
eor x9, x27, x9, ror #49
|
||||
eor x24, x28, x24, ror #28
|
||||
eor x1, x30, x17, ror #36
|
||||
eor x14, x0, x14, ror #8
|
||||
eor x22, x28, x22, ror #44
|
||||
eor x8, x27, x8, ror #56
|
||||
eor x17, x27, x7, ror #19
|
||||
eor x15, x0, x15, ror #62
|
||||
bic x7, x20, x22, ror #47
|
||||
eor x4, x26, x4, ror #54
|
||||
eor x0, x0, x12, ror #3
|
||||
eor x28, x28, x23, ror #58
|
||||
eor x23, x26, x2, ror #61
|
||||
eor x26, x26, x5, ror #25
|
||||
eor x2, x7, x16, ror #39
|
||||
bic x7, x9, x20, ror #42
|
||||
bic x30, x15, x9, ror #16
|
||||
eor x7, x7, x22, ror #25
|
||||
eor x12, x30, x20, ror #58
|
||||
bic x20, x22, x16, ror #56
|
||||
eor x30, x27, x6, ror #43
|
||||
eor x22, x20, x15, ror #23
|
||||
bic x6, x19, x13, ror #42
|
||||
eor x6, x6, x17, ror #41
|
||||
bic x5, x13, x17, ror #63
|
||||
eor x5, x21, x5, ror #21
|
||||
bic x17, x17, x21, ror #44
|
||||
eor x27, x27, x10, ror #23
|
||||
bic x21, x21, x25, ror #50
|
||||
bic x20, x27, x4, ror #25
|
||||
bic x10, x16, x15, ror #31
|
||||
eor x16, x21, x19, ror #43
|
||||
eor x21, x17, x25, ror #30
|
||||
bic x19, x25, x19, ror #57
|
||||
ldr x25, [sp, #0x10]
|
||||
eor x17, x10, x9, ror #47
|
||||
ldr x9, [sp, #0x8]
|
||||
eor x15, x20, x28, ror #27
|
||||
bic x20, x4, x28, ror #2
|
||||
eor x10, x20, x1, ror #50
|
||||
bic x20, x11, x27, ror #60
|
||||
eor x20, x20, x4, ror #21
|
||||
bic x4, x28, x1, ror #48
|
||||
bic x1, x1, x11, ror #57
|
||||
ldr x28, [x9, x25, lsl #3]
|
||||
ldr x9, [sp, #0x18]
|
||||
add x25, x25, #0x1
|
||||
str x25, [sp, #0x10]
|
||||
cmp x25, #0x17
|
||||
eor x25, x1, x27, ror #53
|
||||
bic x27, x30, x26, ror #47
|
||||
eor x1, x5, x28
|
||||
eor x5, x4, x11, ror #41
|
||||
eor x11, x19, x13, ror #35
|
||||
bic x13, x26, x24, ror #10
|
||||
eor x28, x27, x24, ror #57
|
||||
bic x27, x24, x9, ror #47
|
||||
bic x19, x23, x3, ror #9
|
||||
bic x4, x29, x14, ror #41
|
||||
eor x24, x19, x29, ror #44
|
||||
bic x29, x3, x29, ror #35
|
||||
eor x13, x13, x9, ror #57
|
||||
eor x19, x29, x14, ror #12
|
||||
bic x29, x9, x0, ror #19
|
||||
bic x14, x14, x8, ror #5
|
||||
eor x9, x14, x23, ror #43
|
||||
eor x14, x4, x8, ror #46
|
||||
bic x23, x8, x23, ror #38
|
||||
eor x8, x27, x0, ror #2
|
||||
eor x4, x23, x3, ror #47
|
||||
bic x3, x0, x30, ror #5
|
||||
eor x23, x3, x26, ror #52
|
||||
eor x3, x29, x30, ror #24
|
||||
b.le Lkeccak_f1600_x1_scalar_loop
|
||||
ror x6, x6, #0x2b
|
||||
ror x11, x11, #0x32
|
||||
ror x21, x21, #0x14
|
||||
ror x2, x2, #0x3d
|
||||
ror x7, x7, #0x13
|
||||
ror x12, x12, #0x3
|
||||
ror x17, x17, #0x24
|
||||
ror x22, x22, #0x2c
|
||||
ror x3, x3, #0x27
|
||||
ror x8, x8, #0x38
|
||||
ror x13, x13, #0x2e
|
||||
ror x28, x28, #0x3f
|
||||
ror x23, x23, #0x3a
|
||||
ror x4, x4, #0x36
|
||||
ror x9, x9, #0x31
|
||||
ror x14, x14, #0x8
|
||||
ror x19, x19, #0x25
|
||||
ror x24, x24, #0x1c
|
||||
ror x5, x5, #0x19
|
||||
ror x10, x10, #0x17
|
||||
ror x15, x15, #0x3e
|
||||
ror x20, x20, #0x2
|
||||
ror x25, x25, #0x9
|
||||
ldr x0, [sp]
|
||||
stp x1, x6, [x0]
|
||||
stp x11, x16, [x0, #0x10]
|
||||
stp x21, x2, [x0, #0x20]
|
||||
stp x7, x12, [x0, #0x30]
|
||||
stp x17, x22, [x0, #0x40]
|
||||
stp x3, x8, [x0, #0x50]
|
||||
stp x13, x28, [x0, #0x60]
|
||||
stp x23, x4, [x0, #0x70]
|
||||
stp x9, x14, [x0, #0x80]
|
||||
stp x19, x24, [x0, #0x90]
|
||||
stp x5, x10, [x0, #0xa0]
|
||||
stp x15, x20, [x0, #0xb0]
|
||||
str x25, [x0, #0xc0]
|
||||
ldp x19, x20, [sp, #0x20]
|
||||
.cfi_restore x19
|
||||
.cfi_restore x20
|
||||
ldp x21, x22, [sp, #0x30]
|
||||
.cfi_restore x21
|
||||
.cfi_restore x22
|
||||
ldp x23, x24, [sp, #0x40]
|
||||
.cfi_restore x23
|
||||
.cfi_restore x24
|
||||
ldp x25, x26, [sp, #0x50]
|
||||
.cfi_restore x25
|
||||
.cfi_restore x26
|
||||
ldp x27, x28, [sp, #0x60]
|
||||
.cfi_restore x27
|
||||
.cfi_restore x28
|
||||
ldp x29, x30, [sp, #0x70]
|
||||
.cfi_restore x29
|
||||
.cfi_restore x30
|
||||
add sp, sp, #0x80
|
||||
.cfi_adjust_cfa_offset -0x80
|
||||
ret
|
||||
.cfi_endproc
|
||||
|
||||
MLK_ASM_FN_SIZE(keccak_f1600_x1_scalar_aarch64_asm)
|
||||
|
||||
#endif /* MLK_FIPS202_AARCH64_NEED_X1_SCALAR && \
|
||||
!MLK_CONFIG_MULTILEVEL_NO_SHARED */
|
||||
|
||||
#if defined(__ELF__)
|
||||
.section .note.GNU-stack,"",%progbits
|
||||
#endif
|
||||
@@ -1,206 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* Copyright (c) 2021-2022 Arm Limited
|
||||
* Copyright (c) 2022 Matthias Kannwischer
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
|
||||
/* References
|
||||
* ==========
|
||||
*
|
||||
* - [HYBRID]
|
||||
* Hybrid scalar/vector implementations of Keccak and SPHINCS+ on AArch64
|
||||
* Becker, Kannwischer
|
||||
* https://eprint.iacr.org/2022/1243
|
||||
*/
|
||||
|
||||
/*yaml
|
||||
Name: keccak_f1600_x1_v84a_aarch64_asm
|
||||
Description: AArch64 ARMv8.4-A implementation of Keccak-f[1600] permutation for single state
|
||||
Signature: void mlk_keccak_f1600_x1_v84a_aarch64_asm(uint64_t state[25], const uint64_t rc[24])
|
||||
ABI:
|
||||
Architecture: aarch64
|
||||
CallingConvention: AAPCS64
|
||||
Features: [SHA3]
|
||||
x0:
|
||||
type: buffer
|
||||
size_bytes: 200
|
||||
permissions: read/write
|
||||
c_parameter: uint64_t state[25]
|
||||
description: Keccak state (25 x uint64_t)
|
||||
x1:
|
||||
type: buffer
|
||||
size_bytes: 192
|
||||
permissions: read-only
|
||||
c_parameter: const uint64_t rc[24]
|
||||
description: Round constants (24 x uint64_t)
|
||||
Stack:
|
||||
bytes: 64
|
||||
description: register preservation
|
||||
*/
|
||||
|
||||
//
|
||||
// Author: Hanno Becker <hanno.becker@arm.com>
|
||||
// Author: Matthias Kannwischer <matthias@kannwischer.eu>
|
||||
//
|
||||
// This implementation is essentially from the paper @[HYBRID].
|
||||
// The only difference is interleaving/deinterleaving of Keccak state
|
||||
// during load and store, so that the caller need not do this.
|
||||
//
|
||||
|
||||
#include "../../../../common.h"
|
||||
#if defined(MLK_FIPS202_AARCH64_NEED_X1_V84A) && \
|
||||
!defined(MLK_CONFIG_MULTILEVEL_NO_SHARED)
|
||||
|
||||
#if defined(__ARM_FEATURE_SHA3)
|
||||
|
||||
/*
|
||||
* WARNING: This file is auto-derived from the mlkem-native source file
|
||||
* dev/fips202/aarch64/src/keccak_f1600_x1_v84a_aarch64_asm.S using scripts/simpasm. Do not modify it directly.
|
||||
*/
|
||||
|
||||
.text
|
||||
.balign 4
|
||||
.global MLK_ASM_NAMESPACE(keccak_f1600_x1_v84a_aarch64_asm)
|
||||
MLK_ASM_FN_SYMBOL(keccak_f1600_x1_v84a_aarch64_asm)
|
||||
|
||||
.cfi_startproc
|
||||
sub sp, sp, #0x40
|
||||
.cfi_adjust_cfa_offset 0x40
|
||||
stp d8, d9, [sp]
|
||||
.cfi_rel_offset d8, 0x0
|
||||
.cfi_rel_offset d9, 0x8
|
||||
stp d10, d11, [sp, #0x10]
|
||||
.cfi_rel_offset d10, 0x10
|
||||
.cfi_rel_offset d11, 0x18
|
||||
stp d12, d13, [sp, #0x20]
|
||||
.cfi_rel_offset d12, 0x20
|
||||
.cfi_rel_offset d13, 0x28
|
||||
stp d14, d15, [sp, #0x30]
|
||||
.cfi_rel_offset d14, 0x30
|
||||
.cfi_rel_offset d15, 0x38
|
||||
ldp d0, d1, [x0]
|
||||
ldp d2, d3, [x0, #0x10]
|
||||
ldp d4, d5, [x0, #0x20]
|
||||
ldp d6, d7, [x0, #0x30]
|
||||
ldp d8, d9, [x0, #0x40]
|
||||
ldp d10, d11, [x0, #0x50]
|
||||
ldp d12, d13, [x0, #0x60]
|
||||
ldp d14, d15, [x0, #0x70]
|
||||
ldp d16, d17, [x0, #0x80]
|
||||
ldp d18, d19, [x0, #0x90]
|
||||
ldp d20, d21, [x0, #0xa0]
|
||||
ldp d22, d23, [x0, #0xb0]
|
||||
ldr d24, [x0, #0xc0]
|
||||
mov x2, #0x18 // =24
|
||||
|
||||
Lkeccak_f1600_x1_v84a_loop:
|
||||
eor3 v30.16b, v0.16b, v5.16b, v10.16b
|
||||
eor3 v29.16b, v1.16b, v6.16b, v11.16b
|
||||
eor3 v28.16b, v2.16b, v7.16b, v12.16b
|
||||
eor3 v27.16b, v3.16b, v8.16b, v13.16b
|
||||
eor3 v26.16b, v4.16b, v9.16b, v14.16b
|
||||
eor3 v30.16b, v30.16b, v15.16b, v20.16b
|
||||
eor3 v29.16b, v29.16b, v16.16b, v21.16b
|
||||
eor3 v28.16b, v28.16b, v17.16b, v22.16b
|
||||
eor3 v27.16b, v27.16b, v18.16b, v23.16b
|
||||
eor3 v26.16b, v26.16b, v19.16b, v24.16b
|
||||
rax1 v25.2d, v30.2d, v28.2d
|
||||
rax1 v28.2d, v28.2d, v26.2d
|
||||
rax1 v26.2d, v26.2d, v29.2d
|
||||
rax1 v29.2d, v29.2d, v27.2d
|
||||
rax1 v27.2d, v27.2d, v30.2d
|
||||
eor v30.16b, v0.16b, v26.16b
|
||||
xar v0.2d, v2.2d, v29.2d, #0x2
|
||||
xar v2.2d, v12.2d, v29.2d, #0x15
|
||||
xar v12.2d, v13.2d, v28.2d, #0x27
|
||||
xar v13.2d, v19.2d, v27.2d, #0x38
|
||||
xar v19.2d, v23.2d, v28.2d, #0x8
|
||||
xar v23.2d, v15.2d, v26.2d, #0x17
|
||||
xar v15.2d, v1.2d, v25.2d, #0x3f
|
||||
xar v1.2d, v8.2d, v28.2d, #0x9
|
||||
xar v8.2d, v16.2d, v25.2d, #0x13
|
||||
xar v16.2d, v7.2d, v29.2d, #0x3a
|
||||
xar v7.2d, v10.2d, v26.2d, #0x3d
|
||||
xar v10.2d, v3.2d, v28.2d, #0x24
|
||||
xar v3.2d, v18.2d, v28.2d, #0x2b
|
||||
xar v18.2d, v17.2d, v29.2d, #0x31
|
||||
xar v17.2d, v11.2d, v25.2d, #0x36
|
||||
xar v11.2d, v9.2d, v27.2d, #0x2c
|
||||
xar v9.2d, v22.2d, v29.2d, #0x3
|
||||
xar v22.2d, v14.2d, v27.2d, #0x19
|
||||
xar v14.2d, v20.2d, v26.2d, #0x2e
|
||||
xar v20.2d, v4.2d, v27.2d, #0x25
|
||||
xar v4.2d, v24.2d, v27.2d, #0x32
|
||||
xar v24.2d, v21.2d, v25.2d, #0x3e
|
||||
xar v21.2d, v5.2d, v26.2d, #0x1c
|
||||
xar v27.2d, v6.2d, v25.2d, #0x14
|
||||
ld1r { v31.2d }, [x1], #8
|
||||
bcax v5.16b, v10.16b, v7.16b, v11.16b
|
||||
bcax v6.16b, v11.16b, v8.16b, v7.16b
|
||||
bcax v7.16b, v7.16b, v9.16b, v8.16b
|
||||
bcax v8.16b, v8.16b, v10.16b, v9.16b
|
||||
bcax v9.16b, v9.16b, v11.16b, v10.16b
|
||||
bcax v10.16b, v15.16b, v12.16b, v16.16b
|
||||
bcax v11.16b, v16.16b, v13.16b, v12.16b
|
||||
bcax v12.16b, v12.16b, v14.16b, v13.16b
|
||||
bcax v13.16b, v13.16b, v15.16b, v14.16b
|
||||
bcax v14.16b, v14.16b, v16.16b, v15.16b
|
||||
bcax v15.16b, v20.16b, v17.16b, v21.16b
|
||||
bcax v16.16b, v21.16b, v18.16b, v17.16b
|
||||
bcax v17.16b, v17.16b, v19.16b, v18.16b
|
||||
bcax v18.16b, v18.16b, v20.16b, v19.16b
|
||||
bcax v19.16b, v19.16b, v21.16b, v20.16b
|
||||
bcax v20.16b, v0.16b, v22.16b, v1.16b
|
||||
bcax v21.16b, v1.16b, v23.16b, v22.16b
|
||||
bcax v22.16b, v22.16b, v24.16b, v23.16b
|
||||
bcax v23.16b, v23.16b, v0.16b, v24.16b
|
||||
bcax v24.16b, v24.16b, v1.16b, v0.16b
|
||||
bcax v0.16b, v30.16b, v2.16b, v27.16b
|
||||
bcax v1.16b, v27.16b, v3.16b, v2.16b
|
||||
bcax v2.16b, v2.16b, v4.16b, v3.16b
|
||||
bcax v3.16b, v3.16b, v30.16b, v4.16b
|
||||
bcax v4.16b, v4.16b, v27.16b, v30.16b
|
||||
eor v0.16b, v0.16b, v31.16b
|
||||
sub x2, x2, #0x1
|
||||
cbnz x2, Lkeccak_f1600_x1_v84a_loop
|
||||
stp d0, d1, [x0]
|
||||
stp d2, d3, [x0, #0x10]
|
||||
stp d4, d5, [x0, #0x20]
|
||||
stp d6, d7, [x0, #0x30]
|
||||
stp d8, d9, [x0, #0x40]
|
||||
stp d10, d11, [x0, #0x50]
|
||||
stp d12, d13, [x0, #0x60]
|
||||
stp d14, d15, [x0, #0x70]
|
||||
stp d16, d17, [x0, #0x80]
|
||||
stp d18, d19, [x0, #0x90]
|
||||
stp d20, d21, [x0, #0xa0]
|
||||
stp d22, d23, [x0, #0xb0]
|
||||
str d24, [x0, #0xc0]
|
||||
ldp d8, d9, [sp]
|
||||
.cfi_restore d8
|
||||
.cfi_restore d9
|
||||
ldp d10, d11, [sp, #0x10]
|
||||
.cfi_restore d10
|
||||
.cfi_restore d11
|
||||
ldp d12, d13, [sp, #0x20]
|
||||
.cfi_restore d12
|
||||
.cfi_restore d13
|
||||
ldp d14, d15, [sp, #0x30]
|
||||
.cfi_restore d14
|
||||
.cfi_restore d15
|
||||
add sp, sp, #0x40
|
||||
.cfi_adjust_cfa_offset -0x40
|
||||
ret
|
||||
.cfi_endproc
|
||||
|
||||
MLK_ASM_FN_SIZE(keccak_f1600_x1_v84a_aarch64_asm)
|
||||
|
||||
#endif /* __ARM_FEATURE_SHA3 */
|
||||
|
||||
#endif /* MLK_FIPS202_AARCH64_NEED_X1_V84A && !MLK_CONFIG_MULTILEVEL_NO_SHARED \
|
||||
*/
|
||||
|
||||
#if defined(__ELF__)
|
||||
.section .note.GNU-stack,"",%progbits
|
||||
#endif
|
||||
@@ -1,261 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) The mlkem-native project authors
|
||||
* Copyright (c) 2021-2022 Arm Limited
|
||||
* Copyright (c) 2022 Matthias Kannwischer
|
||||
* SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
|
||||
*/
|
||||
|
||||
/* References
|
||||
* ==========
|
||||
*
|
||||
* - [HYBRID]
|
||||
* Hybrid scalar/vector implementations of Keccak and SPHINCS+ on AArch64
|
||||
* Becker, Kannwischer
|
||||
* https://eprint.iacr.org/2022/1243
|
||||
*/
|
||||
|
||||
/*yaml
|
||||
Name: keccak_f1600_x2_v84a_aarch64_asm
|
||||
Description: AArch64 ARMv8.4-A implementation of Keccak-f[1600] permutation for two sequential states
|
||||
Signature: void mlk_keccak_f1600_x2_v84a_aarch64_asm(uint64_t state[50], const uint64_t rc[24])
|
||||
ABI:
|
||||
Architecture: aarch64
|
||||
CallingConvention: AAPCS64
|
||||
Features: [SHA3]
|
||||
x0:
|
||||
type: buffer
|
||||
size_bytes: 400
|
||||
permissions: read/write
|
||||
c_parameter: uint64_t state[50]
|
||||
description: Two sequential Keccak states (state0[25], state1[25])
|
||||
x1:
|
||||
type: buffer
|
||||
size_bytes: 192
|
||||
permissions: read-only
|
||||
c_parameter: const uint64_t rc[24]
|
||||
description: Round constants (24 x uint64_t)
|
||||
Stack:
|
||||
bytes: 64
|
||||
description: register preservation
|
||||
*/
|
||||
|
||||
//
|
||||
// Author: Hanno Becker <hanno.becker@arm.com>
|
||||
// Author: Matthias Kannwischer <matthias@kannwischer.eu>
|
||||
//
|
||||
// This implementation is essentially from the paper @[HYBRID].
|
||||
// The only difference is interleaving/deinterleaving of Keccak state
|
||||
// during load and store, so that the caller need not do this.
|
||||
//
|
||||
|
||||
#include "../../../../common.h"
|
||||
#if defined(MLK_FIPS202_AARCH64_NEED_X2_V84A) && \
|
||||
!defined(MLK_CONFIG_MULTILEVEL_NO_SHARED)
|
||||
|
||||
#if defined(__ARM_FEATURE_SHA3)
|
||||
|
||||
/*
|
||||
* WARNING: This file is auto-derived from the mlkem-native source file
|
||||
* dev/fips202/aarch64/src/keccak_f1600_x2_v84a_aarch64_asm.S using scripts/simpasm. Do not modify it directly.
|
||||
*/
|
||||
|
||||
.text
|
||||
.balign 4
|
||||
.global MLK_ASM_NAMESPACE(keccak_f1600_x2_v84a_aarch64_asm)
|
||||
MLK_ASM_FN_SYMBOL(keccak_f1600_x2_v84a_aarch64_asm)
|
||||
|
||||
.cfi_startproc
|
||||
sub sp, sp, #0x40
|
||||
.cfi_adjust_cfa_offset 0x40
|
||||
stp d8, d9, [sp]
|
||||
.cfi_rel_offset d8, 0x0
|
||||
.cfi_rel_offset d9, 0x8
|
||||
stp d10, d11, [sp, #0x10]
|
||||
.cfi_rel_offset d10, 0x10
|
||||
.cfi_rel_offset d11, 0x18
|
||||
stp d12, d13, [sp, #0x20]
|
||||
.cfi_rel_offset d12, 0x20
|
||||
.cfi_rel_offset d13, 0x28
|
||||
stp d14, d15, [sp, #0x30]
|
||||
.cfi_rel_offset d14, 0x30
|
||||
.cfi_rel_offset d15, 0x38
|
||||
add x2, x0, #0xc8
|
||||
ldp q25, q26, [x0], #0x20
|
||||
ld1 { v27.2d, v28.2d }, [x2], #32
|
||||
trn1 v0.2d, v25.2d, v27.2d
|
||||
trn2 v1.2d, v25.2d, v27.2d
|
||||
trn1 v2.2d, v26.2d, v28.2d
|
||||
trn2 v3.2d, v26.2d, v28.2d
|
||||
ldp q25, q26, [x0], #0x20
|
||||
ld1 { v27.2d, v28.2d }, [x2], #32
|
||||
trn1 v4.2d, v25.2d, v27.2d
|
||||
trn2 v5.2d, v25.2d, v27.2d
|
||||
trn1 v6.2d, v26.2d, v28.2d
|
||||
trn2 v7.2d, v26.2d, v28.2d
|
||||
ldp q25, q26, [x0], #0x20
|
||||
ld1 { v27.2d, v28.2d }, [x2], #32
|
||||
trn1 v8.2d, v25.2d, v27.2d
|
||||
trn2 v9.2d, v25.2d, v27.2d
|
||||
trn1 v10.2d, v26.2d, v28.2d
|
||||
trn2 v11.2d, v26.2d, v28.2d
|
||||
ldp q25, q26, [x0], #0x20
|
||||
ld1 { v27.2d, v28.2d }, [x2], #32
|
||||
trn1 v12.2d, v25.2d, v27.2d
|
||||
trn2 v13.2d, v25.2d, v27.2d
|
||||
trn1 v14.2d, v26.2d, v28.2d
|
||||
trn2 v15.2d, v26.2d, v28.2d
|
||||
ldp q25, q26, [x0], #0x20
|
||||
ld1 { v27.2d, v28.2d }, [x2], #32
|
||||
trn1 v16.2d, v25.2d, v27.2d
|
||||
trn2 v17.2d, v25.2d, v27.2d
|
||||
trn1 v18.2d, v26.2d, v28.2d
|
||||
trn2 v19.2d, v26.2d, v28.2d
|
||||
ldp q25, q26, [x0], #0x20
|
||||
ld1 { v27.2d, v28.2d }, [x2], #32
|
||||
trn1 v20.2d, v25.2d, v27.2d
|
||||
trn2 v21.2d, v25.2d, v27.2d
|
||||
trn1 v22.2d, v26.2d, v28.2d
|
||||
trn2 v23.2d, v26.2d, v28.2d
|
||||
ldr d25, [x0]
|
||||
ldr d27, [x2]
|
||||
trn1 v24.2d, v25.2d, v27.2d
|
||||
mov x2, #0x18 // =24
|
||||
|
||||
Lkeccak_f1600_x2_v84a_loop:
|
||||
eor3 v30.16b, v0.16b, v5.16b, v10.16b
|
||||
eor3 v29.16b, v1.16b, v6.16b, v11.16b
|
||||
eor3 v28.16b, v2.16b, v7.16b, v12.16b
|
||||
eor3 v27.16b, v3.16b, v8.16b, v13.16b
|
||||
eor3 v26.16b, v4.16b, v9.16b, v14.16b
|
||||
eor3 v30.16b, v30.16b, v15.16b, v20.16b
|
||||
eor3 v29.16b, v29.16b, v16.16b, v21.16b
|
||||
eor3 v28.16b, v28.16b, v17.16b, v22.16b
|
||||
eor3 v27.16b, v27.16b, v18.16b, v23.16b
|
||||
eor3 v26.16b, v26.16b, v19.16b, v24.16b
|
||||
rax1 v25.2d, v30.2d, v28.2d
|
||||
rax1 v28.2d, v28.2d, v26.2d
|
||||
rax1 v26.2d, v26.2d, v29.2d
|
||||
rax1 v29.2d, v29.2d, v27.2d
|
||||
rax1 v27.2d, v27.2d, v30.2d
|
||||
eor v30.16b, v0.16b, v26.16b
|
||||
xar v0.2d, v2.2d, v29.2d, #0x2
|
||||
xar v2.2d, v12.2d, v29.2d, #0x15
|
||||
xar v12.2d, v13.2d, v28.2d, #0x27
|
||||
xar v13.2d, v19.2d, v27.2d, #0x38
|
||||
xar v19.2d, v23.2d, v28.2d, #0x8
|
||||
xar v23.2d, v15.2d, v26.2d, #0x17
|
||||
xar v15.2d, v1.2d, v25.2d, #0x3f
|
||||
xar v1.2d, v8.2d, v28.2d, #0x9
|
||||
xar v8.2d, v16.2d, v25.2d, #0x13
|
||||
xar v16.2d, v7.2d, v29.2d, #0x3a
|
||||
xar v7.2d, v10.2d, v26.2d, #0x3d
|
||||
xar v10.2d, v3.2d, v28.2d, #0x24
|
||||
xar v3.2d, v18.2d, v28.2d, #0x2b
|
||||
xar v18.2d, v17.2d, v29.2d, #0x31
|
||||
xar v17.2d, v11.2d, v25.2d, #0x36
|
||||
xar v11.2d, v9.2d, v27.2d, #0x2c
|
||||
xar v9.2d, v22.2d, v29.2d, #0x3
|
||||
xar v22.2d, v14.2d, v27.2d, #0x19
|
||||
xar v14.2d, v20.2d, v26.2d, #0x2e
|
||||
xar v20.2d, v4.2d, v27.2d, #0x25
|
||||
xar v4.2d, v24.2d, v27.2d, #0x32
|
||||
xar v24.2d, v21.2d, v25.2d, #0x3e
|
||||
xar v21.2d, v5.2d, v26.2d, #0x1c
|
||||
xar v27.2d, v6.2d, v25.2d, #0x14
|
||||
ld1r { v31.2d }, [x1], #8
|
||||
bcax v5.16b, v10.16b, v7.16b, v11.16b
|
||||
bcax v6.16b, v11.16b, v8.16b, v7.16b
|
||||
bcax v7.16b, v7.16b, v9.16b, v8.16b
|
||||
bcax v8.16b, v8.16b, v10.16b, v9.16b
|
||||
bcax v9.16b, v9.16b, v11.16b, v10.16b
|
||||
bcax v10.16b, v15.16b, v12.16b, v16.16b
|
||||
bcax v11.16b, v16.16b, v13.16b, v12.16b
|
||||
bcax v12.16b, v12.16b, v14.16b, v13.16b
|
||||
bcax v13.16b, v13.16b, v15.16b, v14.16b
|
||||
bcax v14.16b, v14.16b, v16.16b, v15.16b
|
||||
bcax v15.16b, v20.16b, v17.16b, v21.16b
|
||||
bcax v16.16b, v21.16b, v18.16b, v17.16b
|
||||
bcax v17.16b, v17.16b, v19.16b, v18.16b
|
||||
bcax v18.16b, v18.16b, v20.16b, v19.16b
|
||||
bcax v19.16b, v19.16b, v21.16b, v20.16b
|
||||
bcax v20.16b, v0.16b, v22.16b, v1.16b
|
||||
bcax v21.16b, v1.16b, v23.16b, v22.16b
|
||||
bcax v22.16b, v22.16b, v24.16b, v23.16b
|
||||
bcax v23.16b, v23.16b, v0.16b, v24.16b
|
||||
bcax v24.16b, v24.16b, v1.16b, v0.16b
|
||||
bcax v0.16b, v30.16b, v2.16b, v27.16b
|
||||
bcax v1.16b, v27.16b, v3.16b, v2.16b
|
||||
bcax v2.16b, v2.16b, v4.16b, v3.16b
|
||||
bcax v3.16b, v3.16b, v30.16b, v4.16b
|
||||
bcax v4.16b, v4.16b, v27.16b, v30.16b
|
||||
eor v0.16b, v0.16b, v31.16b
|
||||
sub x2, x2, #0x1
|
||||
cbnz x2, Lkeccak_f1600_x2_v84a_loop
|
||||
sub x0, x0, #0xc0
|
||||
add x2, x0, #0xc8
|
||||
trn1 v25.2d, v0.2d, v1.2d
|
||||
trn1 v26.2d, v2.2d, v3.2d
|
||||
stp q25, q26, [x0], #0x20
|
||||
trn2 v27.2d, v0.2d, v1.2d
|
||||
trn2 v28.2d, v2.2d, v3.2d
|
||||
st1 { v27.2d, v28.2d }, [x2], #32
|
||||
trn1 v25.2d, v4.2d, v5.2d
|
||||
trn1 v26.2d, v6.2d, v7.2d
|
||||
stp q25, q26, [x0], #0x20
|
||||
trn2 v27.2d, v4.2d, v5.2d
|
||||
trn2 v28.2d, v6.2d, v7.2d
|
||||
st1 { v27.2d, v28.2d }, [x2], #32
|
||||
trn1 v25.2d, v8.2d, v9.2d
|
||||
trn1 v26.2d, v10.2d, v11.2d
|
||||
stp q25, q26, [x0], #0x20
|
||||
trn2 v27.2d, v8.2d, v9.2d
|
||||
trn2 v28.2d, v10.2d, v11.2d
|
||||
st1 { v27.2d, v28.2d }, [x2], #32
|
||||
trn1 v25.2d, v12.2d, v13.2d
|
||||
trn1 v26.2d, v14.2d, v15.2d
|
||||
stp q25, q26, [x0], #0x20
|
||||
trn2 v27.2d, v12.2d, v13.2d
|
||||
trn2 v28.2d, v14.2d, v15.2d
|
||||
st1 { v27.2d, v28.2d }, [x2], #32
|
||||
trn1 v25.2d, v16.2d, v17.2d
|
||||
trn1 v26.2d, v18.2d, v19.2d
|
||||
stp q25, q26, [x0], #0x20
|
||||
trn2 v27.2d, v16.2d, v17.2d
|
||||
trn2 v28.2d, v18.2d, v19.2d
|
||||
st1 { v27.2d, v28.2d }, [x2], #32
|
||||
trn1 v25.2d, v20.2d, v21.2d
|
||||
trn1 v26.2d, v22.2d, v23.2d
|
||||
stp q25, q26, [x0], #0x20
|
||||
trn2 v27.2d, v20.2d, v21.2d
|
||||
trn2 v28.2d, v22.2d, v23.2d
|
||||
st1 { v27.2d, v28.2d }, [x2], #32
|
||||
str d24, [x0]
|
||||
trn2 v25.2d, v24.2d, v24.2d
|
||||
str d25, [x2]
|
||||
ldp d8, d9, [sp]
|
||||
.cfi_restore d8
|
||||
.cfi_restore d9
|
||||
ldp d10, d11, [sp, #0x10]
|
||||
.cfi_restore d10
|
||||
.cfi_restore d11
|
||||
ldp d12, d13, [sp, #0x20]
|
||||
.cfi_restore d12
|
||||
.cfi_restore d13
|
||||
ldp d14, d15, [sp, #0x30]
|
||||
.cfi_restore d14
|
||||
.cfi_restore d15
|
||||
add sp, sp, #0x40
|
||||
.cfi_adjust_cfa_offset -0x40
|
||||
ret
|
||||
.cfi_endproc
|
||||
|
||||
MLK_ASM_FN_SIZE(keccak_f1600_x2_v84a_aarch64_asm)
|
||||
|
||||
#endif /* __ARM_FEATURE_SHA3 */
|
||||
|
||||
#endif /* MLK_FIPS202_AARCH64_NEED_X2_V84A && !MLK_CONFIG_MULTILEVEL_NO_SHARED \
|
||||
*/
|
||||
|
||||
#if defined(__ELF__)
|
||||
.section .note.GNU-stack,"",%progbits
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user