This repository has been archived on 2026-08-21 . You can view files and clone it. You cannot open issues or pull requests or push a commit.
38f2051f04411d762da159a5d6de5d9254a8084e
Description
No description provided
Languages
Verilog
46.5%
C
27.8%
Assembly
20.5%
SystemVerilog
3.3%
Python
0.7%
Other
1.2%