5981 lines
508 KiB
Plaintext
5981 lines
508 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Sun Jul 5 23:35:18 2026
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| Host : fedora running 64-bit unknown
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| Command : report_timing -delay_type min -max_paths 100 -sort_by slack -path_type full_clock_expanded -input_pins -file ./vivado_reports/impl_worst_hold_paths.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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Timing Report
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Slack (MET) : 0.011ns (arrival time - required time)
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Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
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Logic Levels: 0
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Clock Path Skew: 0.145ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.555ns
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Source Clock Delay (SCD): -0.882ns
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Clock Pessimism Removal (CPR): 0.183ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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K21 0.000 0.000 r clk (IN)
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net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
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K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
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K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
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net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
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r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
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-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
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net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
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r pll_clk.u_clk_pll/inst/clkout2_buf/I
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BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
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net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
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FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
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------------------------------------------------------------------- -------------------
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FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
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net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0]
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FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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K21 0.000 0.000 r clk (IN)
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net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
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K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
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K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
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net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
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r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
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-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
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net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
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r pll_clk.u_clk_pll/inst/clkout2_buf/I
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BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
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net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
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FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
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clock pessimism -0.183 -0.737
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FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]
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-------------------------------------------------------------------
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required time 0.667
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arrival time -0.657
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-------------------------------------------------------------------
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slack 0.011
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Slack (MET) : 0.011ns (arrival time - required time)
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Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
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Logic Levels: 0
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Clock Path Skew: 0.145ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.555ns
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Source Clock Delay (SCD): -0.882ns
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Clock Pessimism Removal (CPR): 0.183ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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K21 0.000 0.000 r clk (IN)
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net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
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K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
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K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
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net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
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r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
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-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
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net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
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r pll_clk.u_clk_pll/inst/clkout2_buf/I
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BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
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net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
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FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
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------------------------------------------------------------------- -------------------
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FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q
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net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[1]
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FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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K21 0.000 0.000 r clk (IN)
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net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
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K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
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K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
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net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
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r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
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-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
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net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
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r pll_clk.u_clk_pll/inst/clkout2_buf/I
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BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
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net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
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FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
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clock pessimism -0.183 -0.737
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FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]
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-------------------------------------------------------------------
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required time 0.667
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arrival time -0.657
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-------------------------------------------------------------------
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slack 0.011
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Slack (MET) : 0.011ns (arrival time - required time)
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Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
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Logic Levels: 0
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Clock Path Skew: 0.145ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.555ns
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Source Clock Delay (SCD): -0.882ns
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Clock Pessimism Removal (CPR): 0.183ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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K21 0.000 0.000 r clk (IN)
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net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
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K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
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K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
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net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
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r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
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-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
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net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
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r pll_clk.u_clk_pll/inst/clkout2_buf/I
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BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
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net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
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FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
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------------------------------------------------------------------- -------------------
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FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
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net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[2]
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FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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K21 0.000 0.000 r clk (IN)
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net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
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K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
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K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
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net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
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r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
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-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
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net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
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r pll_clk.u_clk_pll/inst/clkout2_buf/I
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BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
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net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
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FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
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clock pessimism -0.183 -0.737
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FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]
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-------------------------------------------------------------------
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required time 0.667
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arrival time -0.657
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-------------------------------------------------------------------
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slack 0.011
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Slack (MET) : 0.011ns (arrival time - required time)
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Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
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Logic Levels: 0
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Clock Path Skew: 0.145ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.555ns
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Source Clock Delay (SCD): -0.882ns
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Clock Pessimism Removal (CPR): 0.183ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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K21 0.000 0.000 r clk (IN)
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net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
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K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
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K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
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net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
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r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
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-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
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net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
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r pll_clk.u_clk_pll/inst/clkout2_buf/I
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BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
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net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
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FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C
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------------------------------------------------------------------- -------------------
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FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/Q
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net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/awFifo/bufferCC_12/buffers_0
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FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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K21 0.000 0.000 r clk (IN)
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net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
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K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
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K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
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net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
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r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
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-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
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net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
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r pll_clk.u_clk_pll/inst/clkout2_buf/I
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BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
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net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
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FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
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clock pessimism -0.183 -0.737
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FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg
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-------------------------------------------------------------------
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required time 0.667
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arrival time -0.657
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-------------------------------------------------------------------
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slack 0.011
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Slack (MET) : 0.011ns (arrival time - required time)
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Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
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Logic Levels: 0
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Clock Path Skew: 0.145ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.555ns
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Source Clock Delay (SCD): -0.882ns
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Clock Pessimism Removal (CPR): 0.183ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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K21 0.000 0.000 r clk (IN)
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net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
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K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
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K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
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net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
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r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[0]
|
|
FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.183 -0.737
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.667
|
|
arrival time -0.657
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.555ns
|
|
Source Clock Delay (SCD): -0.882ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[1]
|
|
FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.183 -0.737
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.667
|
|
arrival time -0.657
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.555ns
|
|
Source Clock Delay (SCD): -0.882ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.183 -0.737
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.667
|
|
arrival time -0.657
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.555ns
|
|
Source Clock Delay (SCD): -0.882ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[0]
|
|
FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.183 -0.737
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.667
|
|
arrival time -0.657
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.555ns
|
|
Source Clock Delay (SCD): -0.882ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[1]
|
|
FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.183 -0.737
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.667
|
|
arrival time -0.657
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.555ns
|
|
Source Clock Delay (SCD): -0.882ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[2]
|
|
FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.183 -0.737
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.667
|
|
arrival time -0.657
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.555ns
|
|
Source Clock Delay (SCD): -0.882ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0[0]
|
|
FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.183 -0.737
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.667
|
|
arrival time -0.657
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.555ns
|
|
Source Clock Delay (SCD): -0.882ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0[1]
|
|
FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.183 -0.737
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.667
|
|
arrival time -0.657
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.555ns
|
|
Source Clock Delay (SCD): -0.882ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0[2]
|
|
FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.183 -0.737
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.667
|
|
arrival time -0.657
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_1_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.555ns
|
|
Source Clock Delay (SCD): -0.882ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/Q
|
|
net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0[3]
|
|
FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_1_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_1_reg[3]/C
|
|
clock pessimism -0.183 -0.737
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_1_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.667
|
|
arrival time -0.657
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.555ns
|
|
Source Clock Delay (SCD): -0.882ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0[0]
|
|
FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.183 -0.737
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.667
|
|
arrival time -0.657
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.555ns
|
|
Source Clock Delay (SCD): -0.882ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0[1]
|
|
FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.183 -0.737
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.667
|
|
arrival time -0.657
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.555ns
|
|
Source Clock Delay (SCD): -0.882ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.183 -0.737
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.667
|
|
arrival time -0.657
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.555ns
|
|
Source Clock Delay (SCD): -0.882ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q
|
|
net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0[3]
|
|
FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C
|
|
clock pessimism -0.183 -0.737
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.667
|
|
arrival time -0.657
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0[0]
|
|
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.183 -0.833
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.763
|
|
arrival time -0.752
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0[1]
|
|
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.183 -0.833
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.763
|
|
arrival time -0.752
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0[2]
|
|
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.183 -0.833
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.763
|
|
arrival time -0.752
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[0]
|
|
FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.183 -0.833
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.763
|
|
arrival time -0.752
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[1]
|
|
FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.183 -0.833
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.763
|
|
arrival time -0.752
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[2]
|
|
FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.183 -0.833
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.763
|
|
arrival time -0.752
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/Q
|
|
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/bFifo/bufferCC_12/buffers_0
|
|
FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
clock pessimism -0.183 -0.833
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.763
|
|
arrival time -0.752
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[0]
|
|
FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.183 -0.833
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.763
|
|
arrival time -0.752
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[1]
|
|
FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.183 -0.833
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.763
|
|
arrival time -0.752
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.183 -0.833
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.763
|
|
arrival time -0.752
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[0]
|
|
FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.183 -0.833
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.763
|
|
arrival time -0.752
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[1]
|
|
FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.183 -0.833
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.763
|
|
arrival time -0.752
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.183 -0.833
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.763
|
|
arrival time -0.752
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q
|
|
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[3]
|
|
FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C
|
|
clock pessimism -0.183 -0.833
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.763
|
|
arrival time -0.752
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[0]
|
|
FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.183 -0.833
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.763
|
|
arrival time -0.752
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[1]
|
|
FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.183 -0.833
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.763
|
|
arrival time -0.752
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[2]
|
|
FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.183 -0.833
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.763
|
|
arrival time -0.752
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/Q
|
|
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[3]
|
|
FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/C
|
|
clock pessimism -0.183 -0.833
|
|
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.763
|
|
arrival time -0.752
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.555ns
|
|
Source Clock Delay (SCD): -0.882ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.210 -0.882 u_axi_uart_controller/uart0/regs/receiver/sys_clk
|
|
FDRE r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.741 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/Q
|
|
net (fo=1, unplaced) 0.141 -0.600 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIA0
|
|
RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.355 -0.555 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/WCLK
|
|
RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/CLK
|
|
clock pessimism -0.183 -0.737
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.643 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.643
|
|
arrival time -0.600
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[9]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.555ns
|
|
Source Clock Delay (SCD): -0.882ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.210 -0.882 u_axi_uart_controller/uart0/regs/receiver/sys_clk
|
|
FDRE r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[9]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.741 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[9]/Q
|
|
net (fo=1, unplaced) 0.141 -0.600 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/DIA0
|
|
RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.355 -0.555 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/WCLK
|
|
RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/RAMA/CLK
|
|
clock pessimism -0.183 -0.737
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.643 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.643
|
|
arrival time -0.600
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/araddr_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/araddr_reg[0]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIA0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[12]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/araddr_reg[12]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/araddr_reg[12]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/DIA0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[18]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/araddr_reg[18]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/araddr_reg[18]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/DIA0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[24]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/araddr_reg[24]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/araddr_reg[24]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/DIA0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[30]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/araddr_reg[30]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/araddr_reg[30]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/DIA0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/araddr_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/araddr_reg[6]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIA0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/awaddr_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/awaddr_reg[0]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA0
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[12]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/awaddr_reg[12]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/awaddr_reg[12]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/DIA0
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[18]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/awaddr_reg[18]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/awaddr_reg[18]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/DIA0
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[24]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/awaddr_reg[24]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/awaddr_reg[24]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/DIA0
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[30]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/awaddr_reg[30]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/awaddr_reg[30]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/DIA0
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/awaddr_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/awaddr_reg[6]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIA0
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/wdata_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/wdata_reg[0]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA0
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[12]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/wdata_reg[12]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/wdata_reg[12]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIA0
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[18]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/wdata_reg[18]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/wdata_reg[18]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/DIA0
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[24]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/wdata_reg[24]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/wdata_reg[24]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/DIA0
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[30]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/wdata_reg[30]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/wdata_reg[30]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIA0
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.043ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/wdata_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/wdata_reg[6]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/DIA0
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.043
|
|
|
|
Slack (MET) : 0.044ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.555ns
|
|
Source Clock Delay (SCD): -0.882ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.210 -0.882 u_axi_uart_controller/uart0/regs/receiver/sys_clk
|
|
FDRE r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.741 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/Q
|
|
net (fo=1, unplaced) 0.141 -0.600 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIB0
|
|
RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.355 -0.555 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/WCLK
|
|
RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/CLK
|
|
clock pessimism -0.183 -0.737
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.644 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.644
|
|
arrival time -0.600
|
|
-------------------------------------------------------------------
|
|
slack 0.044
|
|
|
|
Slack (MET) : 0.044ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/araddr_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/araddr_reg[2]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIB0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.044
|
|
|
|
Slack (MET) : 0.044ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/araddr_reg[14]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/araddr_reg[14]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/DIB0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.044
|
|
|
|
Slack (MET) : 0.044ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[20]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/araddr_reg[20]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/araddr_reg[20]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/DIB0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.044
|
|
|
|
Slack (MET) : 0.044ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[26]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/araddr_reg[26]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/araddr_reg[26]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/DIB0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.044
|
|
|
|
Slack (MET) : 0.044ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[8]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/araddr_reg[8]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/araddr_reg[8]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIB0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.044
|
|
|
|
Slack (MET) : 0.044ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/awaddr_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/awaddr_reg[2]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIB0
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.044
|
|
|
|
Slack (MET) : 0.044ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/awaddr_reg[14]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/awaddr_reg[14]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/DIB0
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.044
|
|
|
|
Slack (MET) : 0.044ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[20]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/awaddr_reg[20]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/awaddr_reg[20]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/DIB0
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.044
|
|
|
|
Slack (MET) : 0.044ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[26]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/awaddr_reg[26]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/awaddr_reg[26]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/DIB0
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.044
|
|
|
|
Slack (MET) : 0.044ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[8]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/awaddr_reg[8]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/awaddr_reg[8]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIB0
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.044
|
|
|
|
Slack (MET) : 0.044ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/wdata_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/wdata_reg[2]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIB0
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.044
|
|
|
|
Slack (MET) : 0.044ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/wdata_reg[14]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/wdata_reg[14]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB0
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.044
|
|
|
|
Slack (MET) : 0.044ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[20]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/wdata_reg[20]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/wdata_reg[20]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/DIB0
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.044
|
|
|
|
Slack (MET) : 0.044ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[26]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/wdata_reg[26]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/wdata_reg[26]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/DIB0
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.044
|
|
|
|
Slack (MET) : 0.044ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wstrb_reg[0]/C
|
|
(rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDSE r u_cpu/axi_bridge/wstrb_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDSE (Prop_fdse_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/wstrb_reg[0]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIB0
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.044
|
|
|
|
Slack (MET) : 0.044ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[8]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/wdata_reg[8]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/wdata_reg[8]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/DIB0
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.044
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.555ns
|
|
Source Clock Delay (SCD): -0.882ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.210 -0.882 u_axi_uart_controller/uart0/regs/receiver/sys_clk
|
|
FDRE r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.741 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[7]/Q
|
|
net (fo=1, unplaced) 0.141 -0.600 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIC0
|
|
RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.355 -0.555 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/WCLK
|
|
RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMC/CLK
|
|
clock pessimism -0.183 -0.737
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.646 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.646
|
|
arrival time -0.600
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[4]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/araddr_reg[4]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/araddr_reg[4]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIC0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.742 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.742
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[16]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/araddr_reg[16]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/araddr_reg[16]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/DIC0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.742 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.742
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[22]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/araddr_reg[22]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/araddr_reg[22]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/DIC0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.742 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.742
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[28]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/araddr_reg[28]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/araddr_reg[28]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/DIC0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.742 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.742
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/arsize_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/arsize_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/arsize_reg[1]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/DIC0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.742 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.742
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[10]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/araddr_reg[10]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/araddr_reg[10]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.742 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.742
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[4]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/awaddr_reg[4]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/awaddr_reg[4]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIC0
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.742 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.742
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[16]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/awaddr_reg[16]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/awaddr_reg[16]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/DIC0
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.742 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.742
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[22]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/awaddr_reg[22]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/awaddr_reg[22]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/DIC0
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.742 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.742
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[28]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/awaddr_reg[28]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/awaddr_reg[28]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/DIC0
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.742 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.742
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awsize_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/awsize_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/awsize_reg[1]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/DIC0
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.742 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.742
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[10]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/awaddr_reg[10]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/awaddr_reg[10]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.742 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.742
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[4]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/wdata_reg[4]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/wdata_reg[4]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIC0
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.742 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.742
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[16]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/wdata_reg[16]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/wdata_reg[16]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIC0
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.742 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.742
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[22]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/wdata_reg[22]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/wdata_reg[22]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/DIC0
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.742 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.742
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[28]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/wdata_reg[28]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/wdata_reg[28]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/DIC0
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.742 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.742
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wstrb_reg[2]/C
|
|
(rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDSE r u_cpu/axi_bridge/wstrb_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDSE (Prop_fdse_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/wstrb_reg[2]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIC0
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.742 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.742
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.046ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[10]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.282ns (logic 0.141ns (50.038%) route 0.141ns (49.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/wdata_reg[10]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/wdata_reg[10]/Q
|
|
net (fo=1, unplaced) 0.141 -0.696 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/DIC0
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK
|
|
RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.091 -0.742 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.742
|
|
arrival time -0.696
|
|
-------------------------------------------------------------------
|
|
slack 0.046
|
|
|
|
Slack (MET) : 0.048ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/arid_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.286ns (logic 0.141ns (49.228%) route 0.145ns (50.772%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/arid_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/arid_reg[0]/Q
|
|
net (fo=2, unplaced) 0.145 -0.692 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/DIB0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.692
|
|
-------------------------------------------------------------------
|
|
slack 0.048
|
|
|
|
Slack (MET) : 0.048ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/arlen_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.286ns (logic 0.141ns (49.228%) route 0.145ns (50.772%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/arlen_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/arlen_reg[1]/Q
|
|
net (fo=2, unplaced) 0.145 -0.692 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/DIB0
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK
|
|
RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.692
|
|
-------------------------------------------------------------------
|
|
slack 0.048
|
|
|
|
Slack (MET) : 0.048ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awlen_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.286ns (logic 0.141ns (49.228%) route 0.145ns (50.772%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/axi_bridge/cpu_clk
|
|
FDRE r u_cpu/axi_bridge/awlen_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/axi_bridge/awlen_reg[1]/Q
|
|
net (fo=2, unplaced) 0.145 -0.692 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/DIB0
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK
|
|
RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.093 -0.740 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time -0.692
|
|
-------------------------------------------------------------------
|
|
slack 0.048
|
|
|
|
Slack (MET) : 0.053ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[8]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.292ns (logic 0.141ns (48.304%) route 0.151ns (51.696%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/u_csr/cpu_clk
|
|
FDRE r u_cpu/u_csr/csr_tlbelo0_reg[8]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/u_csr/csr_tlbelo0_reg[8]/Q
|
|
net (fo=4, unplaced) 0.151 -0.686 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/DIA0
|
|
RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/WCLK
|
|
RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.686
|
|
-------------------------------------------------------------------
|
|
slack 0.053
|
|
|
|
Slack (MET) : 0.053ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[20]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_12_17/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.292ns (logic 0.141ns (48.304%) route 0.151ns (51.696%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/u_csr/cpu_clk
|
|
FDRE r u_cpu/u_csr/csr_tlbelo0_reg[20]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/u_csr/csr_tlbelo0_reg[20]/Q
|
|
net (fo=4, unplaced) 0.151 -0.686 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_12_17/DIA0
|
|
RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_12_17/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_12_17/WCLK
|
|
RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_12_17/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_12_17/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.686
|
|
-------------------------------------------------------------------
|
|
slack 0.053
|
|
|
|
Slack (MET) : 0.053ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[26]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_18_19/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.292ns (logic 0.141ns (48.304%) route 0.151ns (51.696%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/u_csr/cpu_clk
|
|
FDRE r u_cpu/u_csr/csr_tlbelo0_reg[26]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/u_csr/csr_tlbelo0_reg[26]/Q
|
|
net (fo=4, unplaced) 0.151 -0.686 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_18_19/DIA0
|
|
RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_18_19/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_18_19/WCLK
|
|
RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_18_19/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_18_19/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.686
|
|
-------------------------------------------------------------------
|
|
slack 0.053
|
|
|
|
Slack (MET) : 0.053ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_6_11/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.292ns (logic 0.141ns (48.304%) route 0.151ns (51.696%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/u_csr/cpu_clk
|
|
FDRE r u_cpu/u_csr/csr_tlbelo0_reg[14]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/u_csr/csr_tlbelo0_reg[14]/Q
|
|
net (fo=4, unplaced) 0.151 -0.686 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_6_11/DIA0
|
|
RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_6_11/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_6_11/WCLK
|
|
RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_6_11/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_6_11/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.739
|
|
arrival time -0.686
|
|
-------------------------------------------------------------------
|
|
slack 0.053
|
|
|
|
Slack (MET) : 0.053ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[8]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r2_0_31_0_5/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.292ns (logic 0.141ns (48.304%) route 0.151ns (51.696%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.650ns
|
|
Source Clock Delay (SCD): -0.978ns
|
|
Clock Pessimism Removal (CPR): 0.183ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.114 -0.978 u_cpu/u_csr/cpu_clk
|
|
FDRE r u_cpu/u_csr/csr_tlbelo0_reg[8]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 -0.837 r u_cpu/u_csr/csr_tlbelo0_reg[8]/Q
|
|
net (fo=4, unplaced) 0.151 -0.686 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r2_0_31_0_5/DIA0
|
|
RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r2_0_31_0_5/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout1_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, unplaced) 0.259 -0.650 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r2_0_31_0_5/WCLK
|
|
RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r2_0_31_0_5/RAMA/CLK
|
|
clock pessimism -0.183 -0.833
|
|
RAMD32 (Hold_ramd32_CLK_I)
|
|
0.094 -0.739 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r2_0_31_0_5/RAMA
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-------------------------------------------------------------------
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required time 0.739
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arrival time -0.686
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-------------------------------------------------------------------
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slack 0.053
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